Dual gate ldmos device for a gate-all-around process flow

Abstract

The present disclosure relates to dual gate LDMOS devices for a gate-all-around process flow. In an embodiment, a transistor has a semiconductor layer with a first type region and a second type region adjacent to the first type region. An insulating structure extends into the second type region. A first conductor is on the first type region. A second conductor is on the second type region. A first gate structure is on the semiconductor layer, between the first and second conductors. The first gate structure includes semiconductive layers vertically spaced apart from each other and a first gate metal contacting the semiconductive layers. A second gate structure is on the semiconductor layer, between the first gate structure and the second conductor. The second gate structure includes semiconductive layers vertically spaced apart from each other. The second gate structure further includes a second gate metal contacting the semiconductive layers of the second gate structure.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more particularly to dual-gate LDMOS devices for gate-around process flows. Background Technology

[0002] The increasing scaling down of integrated circuit devices necessitates the adoption of different field-effect transistor (FET) device designs. While initial complementary metal-oxide-semiconductor (CMOS) transistors featured planar gate designs, smaller device design nodes shifted towards so-called "FinFET" designs, where the gate electrode is fabricated to surround a three-dimensional fin-like semiconductor channel structure for improved control and performance. However, for device design nodes below 3 to 5 nm, even FinFET designs face control and performance challenges. In response to these issues, several companies have developed novel device designs (known as gate-all-around (GAA) designs) for smaller nodes. In a GAA design, the gate electrode is fabricated to surround individual stacked semiconductor sheets (nanosheets) or lines (nanowires) on all sides (at least in cross-section). The nanosheets or nanowires then serve as a controllable / switchable channel for current flow. The number and size of the stacked nanosheets / nanowires can be customized to meet the device design requirements. However, there are usually limitations on the length of nanosheets / nanowires that can be extended between support structures without collapsing during manufacturing. This is because current methods use a removal / replacement approach, in which a “sacrificial” layer is initially formed between adjacent stacked sheets / wires, followed by the sacrificial layer, which temporarily leaves an open gap / space between the sheets / wires, which is then filled with gate electrode material.

[0003] These GAA designs have many uses and applications, but some devices and applications may be better addressed by dissimilar transistor designs, such as lateral drain metal-oxide-semiconductor (LDMOS) transistor designs. For example, some high-voltage applications may require long channel lengths that are not easily provided by GAA designs due to wafer / wire collapse issues during manufacturing. Additionally, some integrated circuit designs may require mixing GAA-type transistors and LDMOS-type transistors within the same die / chip. In any case, it would be useful to be able to provide LDMOS transistors via a process flow substantially similar to that currently used for GAA designs, as GAA-related processes are typically state-of-the-art in current manufacturing facilities. Summary of the Invention

[0004] In one embodiment, a transistor includes a first type region of a semiconductor layer and a second type region of the semiconductor layer. The second type region is adjacent to the first type region in a first direction. An insulating structure extends from the surface of the semiconductor layer into the second type region in a second direction orthogonal to or substantially orthogonal to the surface of the semiconductor layer. A first conductor is located on the surface of the semiconductor layer in the first type region. A second conductor is located on the surface of the semiconductor layer in the second type region. A first gate structure is located on the surface of the semiconductor layer between the first conductor and the second conductor along the first direction. The first gate structure includes a first plurality of semiconducting layers spaced apart from each other in the second direction. The first gate structure further includes a first gate metal contacting the first plurality of semiconducting layers. A second gate structure is located on the surface of the semiconductor layer between the first gate structure and the second conductor along the first direction. The second gate structure includes a second plurality of semiconducting layers spaced apart from each other in the second direction. The second gate structure further includes a second gate metal contacting the second plurality of semiconducting layers.

[0005] In another embodiment, a lateral drain metal-oxide-semiconductor transistor includes a p-type region and an n-type region of a semiconductor layer. The n-type region is adjacent to the p-type region in a first direction. A shallow trench insulating structure extends from the surface of the semiconductor layer into the n-type region in a second direction orthogonal to or substantially orthogonal to the surface of the semiconductor layer. A source electrode is located on the surface of the semiconductor layer in the p-type region. A drain electrode is located on the surface of the semiconductor layer in the n-type region. A first gate structure is located on the surface of the semiconductor layer between the source electrode and the drain electrode along the first direction. The first gate structure includes a first plurality of semiconducting layers spaced apart from each other in the second direction and a first gate metal contacting the first plurality of semiconducting layers. A second gate structure is located on the surface of the semiconductor layer between the first gate structure and the drain electrode along the first direction. The second gate structure includes a second plurality of semiconducting layers spaced apart from each other in the second direction and a second gate metal contacting the second plurality of semiconducting layers. The second gate metal is located along the second direction between each pair of other adjacent semiconducting layers in the second plurality of semiconducting layers.

[0006] In one embodiment, a transistor includes a semiconductor layer having a first type region and a second type region adjacent to the first type region in a first direction. An insulating structure extends from the surface of the semiconductor layer into the second type region in a second direction orthogonal to or substantially orthogonal to the surface of the semiconductor layer. A first electrode is located on the surface of the semiconductor layer in the first type region. A second electrode is located on the surface of the semiconductor layer in the second type region. A first gate structure is located on the surface of the semiconductor layer between the first electrode and the second electrode along the first direction. The first gate structure has a first plurality of semiconducting layers and a first gate metal. The first plurality of semiconducting layers are spaced apart from each other in the second direction. Each of the first plurality of semiconducting layers contacts the first electrode. A second gate structure is located on the surface of the semiconductor layer between the first gate structure and the second electrode along the first direction. The second gate structure has a second plurality of semiconducting layers spaced apart from each other in the second direction and a second gate metal surrounding each of the second plurality of semiconducting layers.

[0007] As used herein, when used in a manner such as component X having / having / including component Y, terms such as “having,” “having,” “including,” or “comprising” are non-exclusive and open-ended to indicate that component X includes component Y, such that other aspects, components, or elements besides component Y may also be part of component X. Similarly, when an element is referred to herein as “connected” or “coupled” to another element, it should be understood that an element may be directly connected to the other element, or that there may be an intermediary element between the elements. In contrast, when an element is specifically referred to herein as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in the “direct” connection or coupling between the elements. However, the presence of a direct connection does not preclude the possibility of other connections in which intermediary elements may be present. Likewise, when an element is referred herein as “placed on another element” or “on another element,” it should be understood that this element may be directly engaged to, mounted on, placed on, or on another element (without any intermediary element), or that there may be an intermediary element between the engaged, mounted, or placed elements. Similarly, when an element is said to "contact another element," "be in contact with another element," or "be connected to another element," an intermediary element may be present therein or similar. In contrast, when an element is described as "directly on another element," "directly connected to another element," "directly placed on another element," or "directly in contact with another element," it should be understood that no intermediary element exists. The reference to "electrical connection" or "electrical connection" of an assembly encompasses both direct physical / electrical connections between assemblies and indirect electrical connections via other conductive components. For example, an electrical connection between two assemblies may be provided individually or in combination by wiring, wires, conductive paths (whether temporary or permanent), electrodes, conductors, leads, through-holes, terminals, or contacts.

[0008] Generally, the drawings are schematic and therefore the dimensions, relative dimensions, component ratios, specific positioning of components relative to each other, and the like may be chosen for ease of description and / or clarity of representation and should not be considered limiting unless specifically stated otherwise. Similarly, aspects may be omitted from the description for the same or similar reasons related to ease of description and / or clarity of representation. Such additional aspects may exist in actual embodiments without departing from this disclosure. Attached Figure Description

[0009] Figure 1A A schematic cross-sectional view depicting a portion of the manufacturing structure at a point in a GAA-type manufacturing process.

[0010] Figure 1B A schematic cross-sectional view depicting a portion of the manufacturing structure at another point in the GAA-type manufacturing process.

[0011] Figure 2A A schematic cross-sectional view depicting a portion of the dual-gate LDMOS transistor design of the first embodiment.

[0012] Figure 2B A schematic depiction of current flow in the dual-gate LDMOS transistor design of the first embodiment is shown.

[0013] Figure 3A A schematic cross-sectional view depicting a portion of the dual-gate LDMOS transistor design of the second embodiment.

[0014] Figure 3B A schematic depiction of current flow in the dual-gate LDMOS transistor design of the second embodiment is shown.

[0015] Figure 4 A schematic cross-sectional view depicting the dual-gate LDMOS transistor of the third embodiment.

[0016] Figure 5 A schematic cross-sectional view depicting the dual-gate LDMOS transistor of the fourth embodiment. Detailed Implementation

[0017] Ring-type process flow and structure

[0018] Figure 1A and Figure 1B Aspects of the process flow for manufacturing GAA transistors are described. The process flow for manufacturing GAA devices involves several steps, of which only those steps particularly relevant to this disclosure are described. At one point in the GAA process flow, semiconductor wafers 20 (“wafers 20”) are stacked one after another, with spacer layers 30 (“spacers 30”) interspersed. That is, within the stack, wafers 20 and spacers 30 alternate. Figure 1A In this diagram, the stack is shown to be formed on a substrate 15, which is on a substrate 10. A dummy gate 50 is formed on top of the stack. Figure 1A As depicted, the topmost layer (in the z-axis direction) of the stack is spacer 30, on which a dummy gate 50 is formed. In other instances, the topmost layer of the stack may be chip 20.

[0019] In the depicted xz plane, the outer spacer 40 surrounds the stack and the dummy gate 50. A portion of the outer spacer 40 is also present at the outer end of the spacer 30, which is slightly recessed from the outermost end of the wafer 20 in the x-axis direction. That is, a portion of the outer spacer 40 is located between the end portions of other adjacent wafers 20. Similarly, a portion of the outer spacer 40 is located between the end portion of the uppermost wafer 20 of the stack and the dummy gate 50, and another portion of the outer spacer 40 is located between the end portion of the lowermost wafer of the stack and the substrate 15.

[0020] In this example, wafer 20 is a semiconducting material, such as silicon (Si) or more specifically, monocrystalline silicon. Wafer 20 may be a silicon layer, i.e., a layer formed of silicon material. In some contexts, wafer 20 may be referred to as a semiconducting layer. Spacer 30 is a different material from wafer 20. For example, when wafer 20 is a silicon layer, spacer 30 may be silicon-germanium (SiGe), i.e., a layer formed of silicon-germanium material. In some instances, wafer 20 may be a SiGe layer with a different germanium content than spacer 30 (e.g., less than spacer 30). In some contexts, the stacking of wafer 20 and spacer 30 may be referred to as a superlattice structure.

[0021] The substrate 10 and the base layer 15 may be formed of the same material as the wafer 20, such as silicon; however, the substrate 10 and the base layer 15 may be made of a different material than the wafer 20. In some instances, the substrate 10 and the base layer 15 may be made of different materials from each other. Furthermore, as mentioned above, because the figures are merely illustrative, the dimensions of the substrate 10 relative to the base layer 15 may differ from... Figure 1A The dimensions depicted in the original text are significantly different.

[0022] For example, when spacer 30 is SiGe and wafer 20 is silicon, outer spacer 40 may be made of, for example, silicon nitride (SiN). When spacer 30 is SiGe and wafer 20 is monocrystalline silicon, dummy gate 50 may be made of polycrystalline silicon (polycrystalline Si). Generally, other materials may be used for these components as appropriate, considering factors such as the nature of the final device and / or manufacturability.

[0023] Figure 1A The GAA-type device is shown at the manufacturing stage, which can be referred to as the "pre-release" stage. Figure 1A Pre-release structure 80 is shown. Figure 1B The GAA-type device is displayed at the manufacturing stage, which can be referred to as the "post-release" stage. Figure 1B Release structure 85 after display. Figure 1B In the middle, it has been further processed in the manner of forming and releasing structure 85. Figure 1AThe pre-release structure 80. In the post-release structure 85, the outer spacer 40 has been opened at a location above the stack and elsewhere. During or subsequently in this opening process, the dummy gate 50 may also be removed. After opening, the spacer 30 is removed by exposure to an etchant or etching process that preferentially removes material from the spacer 30 compared to the material of the wafer 20 (and the outer spacer 40). This removal of the spacer 30 may be referred to as a “channel release” process.

[0024] After the spacer 30 is removed, a gap 35 (also referred to as a “void” or “space”) is left between the stacked sheets 20. Eventually, a gate electrode material (sometimes referred to as “gate metal”) is formed to fill the gap 35, but before this occurs, the sheets 20 are supported only at their outer ends by the remaining portion of the outer spacer 40. Therefore, the structural stability / integrity of the individual sheets 20 limits the achievable channel size (channel length) in a GAA-type device. For example, when the length of the sheet 20 along the depicted x-axis becomes excessive, the sheet 20 may sag, bend, or break. That is, as the maximum unsupported dimension of the sheet 20 increases, the likelihood of sheet deformation, collapse, breakage, or the like increases, potentially leading to manufacturing errors that could cause the final device to malfunction. This limitation on the maximum channel length in a GAA-type device is one aspect addressed by certain embodiments of this disclosure.

[0025] Dual-gate LDMOS design

[0026] Figure 2A A schematic cross-sectional view depicting a portion of a dual-gate LDMOS transistor design according to a first embodiment. This design employs certain structural aspects associated with the fabrication of GAA-type devices, but transistor 400 operates as an LDMOS-type transistor, wherein at least a portion of the transistor channel is within the N-well region 102 and / or the P-well region 101 on substrate 100, rather than being entirely or primarily contained within chip 20 as in conventional GAA-type devices. See also Figure 2B Depicts the current flow (channel formation) in transistor 400.

[0027] Transistor 400 includes various structures that can be formed via a GAA-type process flow or through relatively minor variations thereof. For example, in transistor 400, a first gate structure 261 (“first gate 261”) contacted by gate contact 201 includes both spacer 30 and sheet 20 together with a portion of gate metal 60. This structure can be formed without processing superlattice stacking (see...). Figure 1A This is formed by removing spacer 30. For example, during the spacer removal process (see...) Figure 1BPreviously, simply leaving the spacer 30 in its proper place in the GAA process flow without opening the outer spacer 40 at the location corresponding to the first gate 261 was not an option. The second gate structure 262 (“second gate 262”), contacted by the gate contact 202, comprises a sheet 20 surrounded by a portion of the gate metal 60 in a manner structurally similar to a conventional GAA-type device (however, it should be noted that the ends of the sheet 20 in the second gate 262 are not directly connected to the source / drain structure and the second gate 262 operates more along the lines of a planar gate). Therefore, the second gate sheet 262 is processed in a more standard GAA-type process, in which the initially present spacer 30 is removed, and the gap left by this removal is then filled with the gate metal 60 (see [link to GAA process]). Figure 1B In some instances, a gate oxide or dielectric material may be present between the second gate 262 and the underlying semiconductor layer (e.g., N-well 102).

[0028] In transistor 400, the first gate 261 and the second gate 262 are electrically connected via gate connector 200, and therefore, the gate voltage of each gate in the dual-gate structure is controlled to be substantially the same. Thus, when a sufficient gate voltage is applied to gate connector 200, a conductive channel is formed within transistor 400 that allows current to flow between drain electrode 225 and source electrode 215 (see [link to transistor 400]). Figure 2B In other words, when transistor 400 is in the "on state," current is allowed to flow between drain contact 220 (electrical contact drain electrode 225) and source contact 210 (electrical contact source electrode 215). In the "off state," this current flow is essentially cut off because no channel is provided.

[0029] Transistor 400 includes shallow trench insulators (STIs) 105. These structures are insulating materials (such as silicon oxide or the like) formed in the semiconductor material of P-well 101 and N-well 102. In some contexts or instances, such STI structures may also be referred to as “shallow trench isolation” structures. The depth, location, and shape of the depicted STI 105 are merely descriptive examples and are not limiting. Generally, the STI 105 may be located beyond the outermost plane of the drain electrode 225 and source electrode 215 to provide electrical isolation from adjacent transistors and other components formed together with transistor 400 on the same substrate 100. Although depicted as two separate components in cross-section, the outermost STI 105 may be a portion of the same structure surrounding transistor 400 when viewed from above, such as a ring, frame, grid pattern, or the like. The STI 105, positioned in the N-well 102 between the second gate 262 and the drain electrode 225, is provided to limit "push-through" and the like during transistor operation. For example, this STI 105 increases the voltage drop path, allowing the LDMOS drain side to maintain a higher voltage without compromising the gate high-k dielectric or gate oxide material. STI 105s can vary from one another in various aspects, such as depth, shape, lateral width, material, or other dimensions.

[0030] Figure 2B A schematic depiction of current flow in the dual-gate LDMOS transistor design of the first embodiment is shown. Specifically, Figure 2B The conduction state of transistor 400 is shown. In the conduction state, in this description, the first gate 261 can be considered to provide a current channel (channel 1) that travels from the P-well 101 through the chip 20 in both the vertical (z-axis) and horizontal (x-axis) directions to the source electrode 215 of the chip 20 connected within the first gate 261. In this description, the second gate 262 can be considered to primarily provide a current channel (channel 2) within the N-well 102 in the horizontal (lateral) direction from the drain electrode 225 to channel 1, but the presence of the internal STI 105 restricts current flow in the direct horizontal direction between the second gate 262 and the drain electrode 225.

[0031] As mentioned, although the second gate 262 structurally includes the sheet 20 (semiconductor material), the source / drain current channel does not pass through these sheets 20 and the second gate 262 operates similarly to a planar gate to provide a current channel within the lower N-well 102.

[0032] Figure 3AA schematic cross-sectional view depicting a portion of a dual-gate LDMOS transistor design according to a second embodiment. This design employs certain structural aspects associated with the fabrication of GAA-type devices, but transistor 500 operates as an LDMOS-type transistor, wherein at least a portion of the transistor channel is within the N-well region 102 and / or the P-well region 101, rather than being entirely or primarily contained within chip 20 as in conventional GAA-type devices. See also Figure 3B Depicts the current flow (channel formation) in transistor 500.

[0033] Transistor 500 includes various structures that can be formed via a GAA-type process or through minor variations thereof. In transistor 500, both the first gate structure 261a (“first gate 261a”) contacted by gate contact 201 and the second gate structure 262 (“second gate 262”) contacted by gate contact 202 include a sheet 20 surrounded by a portion of gate metal 60 in a manner structurally similar to a conventional GAA-type device. Unlike transistor 400 described above, the gate structures in transistor 500 do not include spacers 30. That is, each gate structure in transistor 500 is a post-release GAA-type structure in which the spacers 30 have been removed and replaced by gate metal 60.

[0034] While transistors 400 and 500 may each have certain comparative advantages in different applications, one consideration when choosing between them may involve the expected lateral (horizontal) size of the first gate 261 / 261a and manufacturing process limitations associated with the release process. As described, as the planar dimensions of wafer 20 increase, collapse, breakage, and the like are more likely to occur once spacer 30 is removed.

[0035] In transistor 500, the first gate 261a and the second gate 262 are electrically connected via gate connector 200, and thus the gate voltage of each of the gates in the dual-gate structure is controlled together. Therefore, when a sufficient gate drive voltage is applied to gate connector 200, a conductive channel is formed within transistor 500 that allows current to flow between drain electrode 225 and source electrode 215 (see [link to transistor 500]). Figure 3B In other words, when transistor 500 is in the "on state", current is allowed to flow between drain contact 220 (electrical contact drain electrode 225) and source contact 210 (electrical contact source electrode 215). In the "off state", since no conductive channel is formed, the current is essentially cut off.

[0036] Transistor 500 includes shallow trench insulators (STI) 105. As described, these structures are made of insulating materials, such as silicon oxide or the like. Figure 3AThe depth, positioning, and shape of the STI 105 depicted are merely descriptive examples and are not limiting. Generally, the STI 105 may be positioned beyond the outermost plane of the drain electrode 225 and source electrode 215 to provide electrical isolation from adjacent transistors and other components formed together with transistor 500 on the same substrate 100. Although depicted as two separate components in cross-section, the outermost STI 105 may be part of the same structure, such as a ring, frame, mesh pattern, or the like. The STI 105 shown positioned in the N-well 102 between the second gate 262 and the drain electrode 225 is provided to limit "punch-through" and the like. For example, this STI 105 increases the voltage drop path, allowing the LDMOS drain side to maintain a higher voltage without compromising the gate high-k dielectric or gate oxide material. STI 105s may differ from each other in various aspects, such as depth, lateral width, material, or other aspects.

[0037] Figure 3B A schematic depiction of current flow in the dual-gate LDMOS transistor design of the second embodiment is shown. Specifically, Figure 3B The conduction state of transistor 500 is shown. When in the conduction state, in this description, the first gate 261a can be considered to provide a current channel (channel 1) primarily within the P-well 101. Channel 1 is a horizontal (lateral) channel, and unlike transistor 400, channel 1 does not specifically incorporate or include any of the pieces 20 within the first gate 261a. In this description, the second gate 262 can be considered to provide a current channel (channel 2) primarily in the horizontal (lateral) direction from the drain electrode 225 to channel 1 within the N-well 102, but the presence of the internal STI 105 restricts current flow in the direct horizontal direction between the second gate 262 and the drain electrode 225, and current must flow around (below) this STI 105. The second gate 262 again operates as a planar gate to provide a current channel within the underlying N-well 102, and the pieces 20 within the second gate 262 are not incorporated as part of channel 2. In some instances, the gate oxide or dielectric material may be present between the first gate 261a and the underlying semiconductor layer (e.g., P-well 101). In some instances, the gate oxide or dielectric material may be present between the second gate 262 and the underlying semiconductor layer (e.g., N-well 102).

[0038] Figure 4 A schematic cross-sectional view depicting a dual-gate LDMOS transistor according to a third embodiment. Specifically, Figure 4Transistor 410 is depicted. Transistor 410 is similar to transistor 400 in several respects, but shows certain variations and / or modifications. For example, transistor 410 lacks gate connector 200, thus allowing independent control of the first gate 261 and the second gate 262. That is, in some instances, a different voltage can be applied to the first gate 261 compared to the second gate 262. Alternatively, the timing of the gate voltage application may differ for each gate. Therefore, the first gate 261 and the second gate 262 can be driven independently.

[0039] Also shown as a difference between transistor 410 and transistor 400 is the location of the conceptual boundary / edge between P-well 101 and N-well 102. In transistor 400, the boundary is located between the first gate 261 and the second gate 262. In transistor 410, the boundary is located below the first gate 261. However, it should be noted that typically P-well 101 and N-well 102 are regions within the same half-conductive material, where only the region doping differences (e.g., dopant type and / or implanted dopant concentration) are used to create different regions (wells). Therefore, the identification of a specific boundary between regions is somewhat arbitrary, given factors such as dopant diffusion, net concentration, measurement difficulties, and the like. However, boundary location can still be employed as one of several design variables that may affect the performance and behavior of transistor 410 or the like. Therefore, in other embodiments, the boundary location may differ from the boundary location depicted in these figures. For example, in transistors that are otherwise similar to transistor 400 or transistor 410, the boundary location may be below the second gate 262 (see example...). Figure 5 ).

[0040] Figure 5 A schematic cross-sectional view depicting a dual-gate LDMOS transistor according to a fourth embodiment. Specifically, Figure 5 Transistor 510 is depicted. Transistor 510 is similar to transistor 500 in several respects, but shows certain variations and / or modifications. For example, transistor 510 lacks gate connector 200, thus allowing independent control of the first gate 261a and the second gate 262. That is, in some instances, a different voltage can be applied to the first gate 261a compared to the second gate 262. Alternatively, the timing of the gate voltage application may differ for each gate. Therefore, the first gate 261a and the second gate 262 can be driven independently.

[0041] Also shown as a difference between transistor 510 and transistor 500 is the location of the conceptual boundary / edge between P-well 101 and N-well 102. In transistor 500, the boundary is located between the first gate 261a and the second gate 262. In transistor 510, the boundary is located below the first gate 261a. However, as discussed above, typically P-well 101 and N-well 102 are regions within the same half-conductive material, where only the region doping differences (e.g., dopant type and / or implanted dopant concentration) are used to create different regions (wells). Therefore, the identification of a specific boundary between regions is somewhat arbitrary, given factors such as dopant diffusion, net concentration, measurement difficulties, and the like. However, boundary location can still be employed as one of several design variables that may affect the performance and behavior of transistor 510 or the like. Therefore, in other embodiments, the boundary location may differ from the specific boundary location depicted in these figures. For example, in transistors that are otherwise similar to transistor 500 or transistor 510, the boundary location may be below the first gate 261a (see example...). Figure 4 ).

[0042] In some non-limiting examples, transistors 400, 410, 500, or 510 may have a first gate 261 (or first gate 261a) with a lateral dimension (x-axis dimension) of approximately 150 nm or less and a second gate 262 with a lateral dimension (x-axis dimension) of approximately 100 nm or less. In some examples, such transistors may be used as high-voltage LDMOS transistors with a source / drain difference of 0.75 V or greater. The process used to manufacture transistors 400, 410, 500, or 510 may be, for example, a sub-5 nm node process used in other ways to manufacture GAA-type transistors or devices, but is not limited thereto. In other non-limiting examples, the process employed may be a 2 nm node process used in other ways to manufacture GAA-type transistors or devices.

[0043] The integrated semiconductor circuit device may incorporate one or more transistors 400, one or more transistors 410, one or more transistors 500, and / or one or more transistors 510. That is, the described transistors can be used in combination with any other described transistors. Similarly, the described transistors can be used in combination with other types of transistors (e.g., GAA transistors) and / or other circuit components (e.g., resistors and capacitors). Connections between such transistors and circuit components can be made in any feasible manner, such as via wiring at or above the level of gate connector 200, or at or above the level where source contact 210 and drain contact 220 terminate.

[0044] Although the illustrated example shows that the source contact 210 and drain contact 220 terminate at a position lower than the first gate contact 201 and the second gate contact 202, this is not necessarily required and the levels may be the same, or the source contact 210 and / or drain contact 220 may terminate at a level higher than the gate contact.

[0045] Generally speaking, there are no restrictions on the materials, shapes, and / or sizes used for various contacts and connectors, as long as the material is sufficiently conductive and the shape and size allow sufficient current to flow without intolerable resistance.

[0046] Generally, although not specifically marked in the diagram, insulating material covers the depicted components and exists in the spaces between them. For example, interlayer dielectrics are typically present between the gate connector 200 and other components besides the connected gate contacts.

[0047] The source electrode 215 and drain electrode 225 can typically be fabricated in a manner similar to that used in GAA-type transistors. Similarly, various contacts can be fabricated in a manner similar to those in GAA-type transistors. As depicted, the drain electrode 225 travels through multiple plates 20, but these plates are not physically connected to the second gate 262. Electrical separation between the second gate 262 and the plates 20 associated with the drain electrode 225 can be provided in various ways, and the drain electrode 225 can be offset from the center or midpoint of the associated plate 20.

[0048] In the specific example depicted, the source electrode 215 directly contacts the chip 20 of the first gate 261. This contact is typically required in designs such as transistors 400 and 410 because the current channel travels laterally through these chips 20. However, in some variations, not all chips 20 of the first gate 261 need to contact the source electrode 215, and it may be sufficient for fewer than all such chips 20 to contact the source electrode 215, provided that the chips 20 that do contact the source electrode 215 provide a sufficient lateral current channel. In designs such as transistors 500 and 510, any chip 20 of the first gate 261a may not need to contact the source electrode 215 because the current channel travels laterally through the underlying semiconductor layer (e.g., P-well 101) to the source electrode 215, but not through any of the chips 20 of the first gate 261a.

[0049] While some described examples refer to source electrode 215 and drain electrode 225, this naming convention is generally used for ease of description. In various embodiments, without departing from the scope of this disclosure, source electrode 215 may electrically function as a "drain" and drain electrode 225 may electrically function as a "source" in a particular circuit design.

[0050] N-well 102 and P-well 101 may be sub-regions of substrate 100. For example, substrate 100 may be a silicon wafer (or a portion thereof), and N-well 102 and P-well 101 may be doped regions of substrate 100. In such cases, the discrete lower boundary between the wells and substrate 100 may not be readily apparent during inspection. In other instances, substrate 100 may be made of a material entirely different from N-well 102 and P-well 101. For example, substrate 100 may be or comprise an insulating material, and the semiconductor material of N-well 102 and P-well 101 may be deposited, grown, or otherwise formed on the surface of substrate 100.

[0051] Although one or more embodiments of this disclosure have been described in some detail for clarity of understanding, certain changes may be made and remain within the scope of the claims. Therefore, the described embodiments are to be considered illustrative rather than restrictive or limiting, and the scope of the claims should not be considered limited to the details given herein, but may be modified while remaining within the scope of the claims and their equivalents. Any recitation of elements and / or steps in the claims does not imply any particular order of operation or incorporation unless expressly stated in the claims.

[0052] The depicted boundaries between components, elements, devices, and units are to a certain extent arbitrary, and while specific boundaries have been described in the context of particular example configurations, other boundaries, divisions, and / or allocations of functions, components, elements, or aspects may be possible or available. Such other allocations of functionality and / or components are contemplated and should be considered to fall within the scope of this disclosure. Generally, structures and functionalities presented as individual components in exemplary configurations may be implemented as combined structures or components. Similarly, structures and functionalities presented as single components may be implemented as single components. These and other variations, additions, modifications, and improvements may fall within the scope of the appended claims.

Claims

1. A transistor comprising: The first type region of the semiconductor layer; The second type region of the semiconductor layer is adjacent to the first type region in a first direction; An insulating structure that extends from the surface into the second type region in a second direction orthogonal to the surface of the semiconductor layer; A first conductor, located on the surface of the semiconductor layer, is situated in the first type region; The second conductor is located in the second type region on the surface of the semiconductor layer; A first gate structure is located on the surface of the semiconductor layer, between the first conductor and the second conductor along the first direction, the first gate structure comprising a first plurality of semiconducting layers spaced apart from each other in the second direction and a first gate metal contacting the first plurality of semiconducting layers. and A second gate structure is located on the surface of the semiconductor layer, between the first gate structure and the second conductor along the first direction. The second gate structure includes a second plurality of semiconducting layers spaced apart from each other in the second direction and a second gate metal contacting the second plurality of semiconducting layers.

2. The transistor of claim 1, wherein the first gate structure comprises a plurality of spacer layers between the plurality of semiconducting layers.

3. The transistor of claim 2, wherein the second gate structure comprises a plurality of spacer layers between the second plurality of semiconducting layers.

4. The transistor of claim 1, wherein the first gate metal is located along the second direction between each pair of other adjacent semiconducting layers in the plurality of first semiconducting layers.

5. The transistor of claim 4, wherein the second gate metal is located along the second direction between each pair of other adjacent semiconducting layers in the second plurality of semiconducting layers.

6. The transistor of claim 5, wherein the first and second metals are electrically connected.

7. The transistor of claim 1, wherein the first and second gate structures are electrically connected.

8. The transistor of claim 1, wherein the first plurality of semiconducting layers are in contact with the first conductor.

9. The transistor of claim 1, wherein the boundary between the first type region and the second type region is located between the first gate structure and the second gate structure.

10. A lateral drain metal-oxide-semiconductor transistor, comprising: p-type region of the semiconductor layer; The n-type region of the semiconductor layer is adjacent to the p-type region in a first direction; A shallow trench insulating structure that extends from the surface of the semiconductor layer into the n-type region in a second direction orthogonal to the surface of the semiconductor layer; The source electrode is located in the p-type region on the surface of the semiconductor layer; The drain electrode is located on the surface of the semiconductor layer within the n-type region; A first gate structure is located on the surface of the semiconductor layer, between the source electrode and the drain electrode along the first direction, the first gate structure comprising a first plurality of semiconducting layers spaced apart from each other in the second direction and a first gate metal contacting the first plurality of semiconducting layers. and A second gate structure is located on the surface of the semiconductor layer, between the first gate structure and the drain electrode along the first direction. The second gate structure includes a second plurality of semiconducting layers spaced apart from each other in the second direction and a second gate metal that contacts the second plurality of semiconducting layers and is located between each pair of other adjacent semiconducting layers in the second plurality of semiconducting layers along the second direction.

11. The lateral drain metal-oxide-semiconductor transistor of claim 10, wherein the first gate structure comprises a plurality of spacer layers between the first plurality of semiconducting layers.

12. The lateral drain metal-oxide-semiconductor transistor of claim 11, wherein... Each half of the conductive layer is a silicon layer, and The plurality of spacer layers are silicon-germanium layers.

13. The lateral drain metal-oxide-semiconductor transistor of claim 12, wherein the boundary between the p-type region and the n-type region is located between the first gate structure and the second gate structure.

14. The lateral drain metal-oxide-semiconductor transistor of claim 13, wherein the first and second gate structures are electrically connected.

15. The lateral drain metal-oxide-semiconductor transistor of claim 10, wherein the first gate metal is located along the second direction between each pair of other adjacent semiconducting layers in the plurality of first semiconducting layers.

16. A transistor comprising: The first type region of the semiconductor layer; The second type region of the semiconductor layer is adjacent to the first type region in a first direction; An insulating structure that extends from the surface into the second type region in a second direction orthogonal to the surface of the semiconductor layer; The first electrode is located on the surface of the semiconductor layer in the first type region; The second electrode is located in the second type region on the surface of the semiconductor layer; A first gate structure is located on the surface of the semiconductor layer, between the first electrode and the second electrode along the first direction. The first gate structure has a first plurality of semiconducting layers and a first gate metal. The first plurality of semiconducting layers are spaced apart from each other in the second direction. Each of the first plurality of semiconducting layers contacts the first electrode. and A second gate structure is located on the surface of the semiconductor layer, between the first gate structure and the second electrode along the first direction. The second gate structure includes a second plurality of semiconducting layers spaced apart from each other in the second direction and a second gate metal surrounding each of the second plurality of semiconducting layers.

17. The transistor of claim 16, wherein the first gate structure comprises a silicon-germanium layer between each pair of adjacent semiconducting layers of the first plurality of semiconducting layers along the second direction.

18. The transistor of claim 16, wherein the first gate metal is located along the second direction between each pair of other adjacent semiconducting layers in the plurality of first semiconducting layers.

19. The transistor of claim 16, wherein the first gate structure and the second gate structure are electrically connected.

20. The transistor of claim 16, wherein the second electrode extends in the second direction through a third plurality of semiconducting layers spaced apart from each other in the second direction.

Images