SiC trench mosfet with trench bottom protection structure and method of manufacturing the same

Abstract

The present invention relates to a SiC trench MOSFET which simplifies a manufacturing process and provides a protective structure to prevent gate oxide bottom destruction caused by electric field concentration under the gate oxide. More particularly, the present invention relates to a SiC trench MOSFET including a semiconductor layer of a first conductivity type; gate trenches formed on an upper surface of the semiconductor layer; a source well structure of a second conductivity type formed at a predetermined distance apart from the upper surface of the semiconductor layer and the gate trenches; a body region of the second conductivity type formed on the upper surface of the semiconductor layer between the gate trenches and the source well structure; a source region of the first conductivity type formed on an upper surface of the body region; and a trench bottom protective structure provided at a lower portion of the gate trenches.

Description

Technical Field

[0001] This invention relates to SiC trench MOSFETs, and more specifically, to an invention that reduces the electric field of the gate oxide layer formed at the bottom of the trench by means of a trench bottom protection structure, thereby solving the problem of gate oxide damage. Background Technology

[0002] SiC (silicon carbide) is a wide-bandgap semiconductor with a higher bandgap than silicon, and its insulation breakdown electric field is 3 × 10⁻⁶. 6 Its voltage drop is approximately 10 times that of silicon (3.26 eV), its energy band gap is approximately 3 times that of silicon, and its thermal conductivity is 3.7 W / cmK, approximately 3 times that of silicon. Therefore, while possessing a higher breakdown voltage than silicon, it also exhibits lower losses and superior heat dissipation. Consequently, when manufacturing power semiconductor devices of the same level, not only can the cooling system be minimized, but the device size can also be reduced, thereby lowering production costs.

[0003] In particular, SiC is easy to substrate through single crystal growth, and the device manufacturing process is similar to that of existing silicon processes. Therefore, it is being extensively studied as a semiconductor material to replace silicon power devices.

[0004] Compared to silicon-based power semiconductor devices, this SiC power semiconductor device can increase power density by 3 to 10 times. Utilizing the excellent physical properties of SiC as a power switching device, it can be manufactured to 1 / 10 the size of silicon switching devices and significantly reduce power losses caused by switching devices.

[0005] Since the dielectric breakdown electric field of SiC is about 10 times higher than that of silicon, the thickness of the drift layer (drift region) required to withstand the same voltage can be made to be about 1 / 10 of that of silicon, thus significantly reducing the on-resistance at the same voltage.

[0006] Typically, in SiC semiconductors, a high electric field is formed beneath the gate oxide of the trench structure. This high electric field can lead to problems such as insulation breakdown of the gate oxide, becoming a factor that reduces reliability. To solve this problem, a deep P-well structure (hereinafter referred to as deep P-well structure) can be considered.

[0007] This deep P-type well structure is effective because the electric field is formed downwards as the depth increases. However, when the depth of the deep P-type well structure is greater than the trench depth, a narrower region is formed in the electron movement path, which leads to the problem of increased current congestion.

[0008] Therefore, it is urgent to study structural improvements that can reduce the electric field strength formed below the trench. Summary of the Invention

[0009] The problem the invention aims to solve The technical problem to be solved by the present invention is to provide a protective structure in SiC trench MOSFETs to prevent damage to the gate oxide layer at the bottom of the trench caused by a high electric field, thereby providing a technology to improve the stability of semiconductor devices.

[0010] Another technical problem to be solved by the present invention is to provide a structural technology that alleviates the current congestion problem that may occur when the depth of the deep P-type well is greater than the trench depth, so as to uniformize the current path and reduce power loss and thermal stress.

[0011] Another technical problem to be solved by the present invention is to provide a semiconductor device that simultaneously satisfies the effects of trench bottom oxide protection and current dispersion by combining the first and second bottom protection structures.

[0012] The technical problems to be solved by the present invention are not limited to those mentioned above. Other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0013] means for solving problems According to an embodiment of the present invention, a SiC trench MOSFET includes: a semiconductor layer of a first conductivity type; a gate trench formed on the upper surface of the semiconductor layer; a source-well structure of a second conductivity type formed on the upper surface of the semiconductor layer at a predetermined distance from the gate trench; a body region of the second conductivity type formed on the upper surface between the gate trench and the source-well structure; a source region of the first conductivity type formed on the upper surface of the body region; and a trench bottom protection structure disposed at the lower part of the gate trench.

[0014] The trench bottom protection structure includes: a first bottom protection structure forming a second conductive type region of a predetermined depth from the bottom of the trench downwards; and a second bottom protection structure forming the first conductive type region in a manner that surrounds the first bottom protection structure.

[0015] At the bottom of the trench, the second bottom protection structure is arranged in a hemispherical shape, and the first bottom protection structure is inserted into the interior of the hemispherical shape, so that the lower part and the sides of the first bottom protection structure are surrounded by the second bottom protection structure.

[0016] The second bottom protection structure is limited to the area directly below the bottom of the trench, contacts at least a portion of the area below the bottom of the trench, and does not extend upward along the outer sidewall of the trench.

[0017] The doping concentration of the second bottom protection structure can be higher than that of the semiconductor layer.

[0018] The first bottom protection structure may be a structure that forms a second conductivity type region in the lower part of the trench in order to reduce the electric field applied to the oxide at the bottom of the gate.

[0019] The second bottom protection structure can be a structure that forms a first conductivity type region in order to widely disperse current to reduce power loss and thermal stress by surrounding the first bottom protection structure.

[0020] The depth of the source well structure can be greater than the depth of the lower part of the gate trench.

[0021] A method for manufacturing a SiC trench MOSFET according to another aspect of the present invention includes the following steps.

[0022] A method for manufacturing a SiC trench MOSFET according to an embodiment of the present invention includes the steps of: forming a body region of a second conductivity type on the upper surface of a semiconductor layer of a first conductivity type; forming a source region of the first conductivity type on the upper surface of the body region; forming a gate trench on the upper surface of the semiconductor layer; forming a source well structure of the second conductivity type on the upper surface of the semiconductor layer at a predetermined distance from the gate trench; and forming a trench bottom protection structure at the lower part of the gate trench.

[0023] The steps of forming the trench bottom protection structure include: performing a first conductivity type implantation at the bottom of the trench to form a second bottom protection structure; filling the interior of the trench with polysilicon; etching the filled polysilicon to form spacers; performing a second conductivity type implantation at the bottom of the trench to form a first bottom protection structure; performing additional first conductivity type implantation to strengthen the second bottom protection structure; and removing the formed spacers.

[0024] The trench bottom protection structure includes: a first bottom protection structure forming a second conductivity type region of a predetermined depth from the bottom of the trench downwards; and a second bottom protection structure forming the first conductivity type region in a shape that surrounds the first bottom protection structure, wherein the doping concentration of the second bottom protection structure may be higher than the doping concentration of the semiconductor layer.

[0025] The first bottom protection structure may be a structure that forms a second conductivity type region in the lower part of the trench in order to reduce the electric field applied to the lower part of the gate oxide.

[0026] The second bottom protection structure can be a structure that forms a first conductivity type region in order to widely disperse current to reduce power loss and thermal stress by surrounding the first bottom protection structure.

[0027] The depth of the source well structure can be greater than the depth of the lower part of the gate trench.

[0028] Invention Effects The effects of the SiC trench MOSFET with trench bottom protection structure and its manufacturing method according to the present invention are explained below.

[0029] According to at least one embodiment of the present invention, a protective structure is provided in a SiC trench MOSFET to prevent damage to the trench bottom oxide caused by a high electric field, thereby having the advantage of improving the stability of the semiconductor device.

[0030] Furthermore, according to at least one embodiment of the present invention, when the depth of the deep P-type well is greater than the trench depth, it can alleviate the potential current congestion problem, homogenize the current path, and reduce power loss and thermal stress.

[0031] Furthermore, according to at least one embodiment of the present invention, by combining the first and second bottom protection structures, the effects of oxide protection and current dispersion at the bottom of the trench can be simultaneously achieved.

[0032] The further scope of the applicability of this invention will become clear from the following detailed description. However, since various changes and modifications within the spirit and scope of this invention will be clearly understood by those skilled in the art, the detailed description and specific embodiments, such as preferred embodiments of the invention, should be understood as being given by way of example only. Attached Figure Description

[0033] Figures 1 to 21 The process flow for manufacturing a trench structure according to an embodiment of the present invention is shown in sequence.

[0034] Figure 22 This is a drawing illustrating a SiC trench MOSFET structure with a trench bottom protection structure according to an embodiment of the present invention.

[0035] Figure 23 This is an attached diagram showing the doping distribution of general ion implantation and channel effect implantation (axial channel effect in the

[0001] direction).

[0036] Figure 24 This is a conceptual diagram illustrating the effect of a protective structure according to an embodiment of the present invention.

[0037] Figure 25 The accompanying drawing illustrates why the protective structure according to an embodiment of the present invention is more effective in a deep P-type well structure.

[0038] Figure 26 The accompanying drawing illustrates how a protection structure according to an embodiment of the present invention alters the current path.

[0039] Figure 27 The attached figure shows reference lines A and B that cross the first bottom protection structure 1410, the second bottom protection structure 1111, and the epitaxial layer 200 to illustrate the doping distribution. Figure 28 The attached figure shows the doping distribution along the reference lines A and B. Detailed Implementation

[0040] The embodiments disclosed in this specification are described in detail below with reference to the accompanying drawings. Identical or similar components are assigned the same reference numerals regardless of the reference numerals, and repeated descriptions are omitted. The suffixes "module" and "part" used in the following description are assigned or used interchangeably for ease of writing and do not inherently distinguish one another. Furthermore, when describing the embodiments disclosed in this specification, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions might obscure the essence of the embodiments disclosed in this specification. Moreover, the accompanying drawings are only for facilitating understanding of the embodiments disclosed in this specification. The technical concepts disclosed in this specification are not limited by the drawings and should be understood to include all modifications, equivalents, and substitutions within the scope of the present invention.

[0041] Terms including ordinal numbers such as first and second can be used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are merely used to distinguish one constituent element from other constituent elements.

[0042] It should be understood that when referring to certain constituent elements as being "connected" or "continuously connected" with other constituent elements, they may be directly connected or continuous with other constituent elements, or there may be another constituent element in between. On the other hand, it should be understood that when referring to certain constituent elements as being "directly connected" or "directly continuous" with other constituent elements, there is no other constituent element in between.

[0043] A singular expression may include multiple expressions if no other meaning is explicitly stated in the context.

[0044] The terminology used in this application is merely for illustrating specific embodiments and is not intended to limit the invention. A singular expression may include plural expressions unless the context clearly indicates otherwise. It should be understood that, in this application, terms such as "comprising" or "having" specify the presence of features, numbers, steps, actions, constituent elements, components, or combinations thereof as described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, actions, constituent elements, components, or combinations thereof.

[0045] According to an embodiment of the present invention, the first bottom protection structure refers to a structure in which a second conductivity type region is formed at the lower end of the trench structure in a semiconductor layer of the first conductivity type, so as to reduce the electric field applied to the oxide at the bottom of the trench and prevent oxide damage.

[0046] This structure helps reduce the risk of oxide damage caused by high electric fields and improves device reliability.

[0047] The first bottom protection structure is designed to improve the electrical characteristics of the lower part of the trench while optimizing current flow and channel resistance characteristics.

[0048] According to an embodiment of the present invention, the second bottom protection structure is a layer designed to alleviate current congestion in a specific area around the trench. The second bottom protection structure forms a first conductivity type region in a first conductivity type semiconductor layer in a manner that surrounds the first bottom protection structure.

[0049] This structure not only widely disperses current to reduce power loss and thermal stress, but also enhances the protection of oxides at the bottom of the trench.

[0050] The second bottom protection structure, combined with the first bottom protection structure, ensures the uniformity of current flow, thereby improving the electrical performance and stability of the device.

[0051] When using general random implantation for ion implantation, it is difficult to implant to a depth of more than 1.5 μm in SiC unless a high energy of more than 1 MeV is applied using special equipment.

[0052] In ion implantation, the channeling effect refers to the phenomenon where ions penetrate deeper than expected through the gaps between the aligned silicon atoms during ion implantation along a specific direction. Generally, because the channeling effect leads to implantation at depths greater than desired, it is a negative factor in ion implantation and needs to be minimized to prevent its occurrence.

[0053] Hereinafter, this invention describes a method for forming a source-well structure with a deep-well structure using this channel effect.

[0054] Figures 1 to 21 The process flow for manufacturing a trench structure according to an embodiment of the present invention is shown in sequence.

[0055] Reference Figure 1 An n+ type SiC semiconductor substrate 101 is prepared as the basis for an n+ type SiC semiconductor substrate. Hereinafter, the semiconductor layer, the first and second protective structures are doped with n-type or p-type as an example, but the present invention is not necessarily limited to this, and the opposite type can also be doped.

[0056] Next, refer to Figure 2 An epitaxial layer 200 is formed on the upper surface of the SiC semiconductor substrate 101. The epitaxial layer 200 is formed by growing SiC on the upper surface of the SiC semiconductor substrate 101 using an epitaxial growth method.

[0057] In this step, by adjusting the amount of n-type impurities introduced, an epitaxial layer 200 with a high-concentration region 201 and a low-concentration region 202 is formed. This forms a SiC semiconductor layer 210 comprising a SiC semiconductor substrate 101 and the epitaxial layer 200.

[0058] Next refer to Figure 3 A mask 301 with a predetermined pattern is formed on the SiC semiconductor layer 210. The mask 301 has selectively exposed openings 302. The openings 302 expose the region on the SiC semiconductor layer 210 where the source-well structure will be formed.

[0059] Next refer to Figure 4 A source-well structure 401 is formed in the SiC semiconductor layer 210. The term "source-well structure" as used in this specification is a general concept; in one embodiment, it can be a deep P-type well structure. The source-well structure 401 can be formed by introducing p-type impurities onto the upper surface of the SiC semiconductor layer 210. The p-type impurities are introduced onto the upper surface of the SiC semiconductor layer 210 through a mask 301.

[0060] According to an embodiment of the present invention, the source-well structure 401 is proposed to be formed by ion implantation utilizing the channel effect.

[0061] As mentioned above, the channeling effect refers to the phenomenon where, during ion implantation along a specific direction, ions penetrate deeper than expected through the gaps between the arranged silicon atoms. Generally, the channeling effect is a phenomenon that should be avoided in semiconductor processes.

[0062] However, in this invention, it is proposed to utilize this channel effect in order to form a source-well structure 401 with sufficient depth.

[0063] More specifically, in this invention, it is recommended to perform ion implantation (hereinafter referred to as channel effect implantation) with the SiC semiconductor substrate 101 tilted at a 4° angle. That is, according to an embodiment of the present invention, ion implantation is recommended to be performed with a tilt of 3 to 5°.

[0064] Figure 23 This is an attached diagram showing the doping distribution of general ion implantation and channel effect implantation (axial channel effect in the

[0001] direction).

[0065] In typical ion implantation, it can be confirmed that the peak value is reached around 1 μm and then drops sharply. That is, it can be known that typical ion implantation is difficult to penetrate to deeper depths.

[0066] However, in the case of channel effect implantation, it can be confirmed that there is still sufficient implantation up to about 3 μm. That is, it can be confirmed that under the same conditions, channel effect implantation can implant to a deeper depth than conventional ion implantation.

[0067] Furthermore, in one embodiment of the invention, it is recommended that the channel effect implantation be performed at room temperature. Unlike general ion implantation, which is performed at temperatures above room temperature, channel effect implantation is recommended to be performed at room temperature, i.e., between 20°C and 50°C. This is because as the temperature increases, atomic vibrations become more active, and the implantation depth may become shallower. Since the process is performed at room temperature, a photoresist mask can be used instead of a general oxide mask, thereby simplifying the process.

[0068] Reference Figure 5 Mask 301 was removed.

[0069] Reference Figure 6 A p-type body region 601 is formed on the upper surface of the SiC semiconductor layer 210. The body region 601 can be formed by introducing p-type impurities onto the upper surface of the SiC semiconductor layer 210.

[0070] Reference Figure 7 The mask 610 has selectively exposed openings 603. Openings 603 expose regions on the SiC semiconductor layer 210 where the n-type source region 602 will be formed. The n-type source region 602 is then formed on a surface layer portion of the body region 601. The source region 602 can be formed by introducing n-type impurities into the surface layer portion of the body region 601. The formation of the source region 602 is performed at high temperature using an oxide mask.

[0071] Reference Figure 8 Mask 610 was removed.

[0072] Reference Figure 9 A mask 901 with a predetermined pattern is formed on the upper surface of the SiC semiconductor layer 210. The mask 901 has a plurality of openings 903 that selectively expose the areas where the contact regions 902 will be formed.

[0073] Next, contact region 902 is formed on the surface layer portion of the upper surface of SiC semiconductor layer 210. Contact region 902 is formed by introducing p-type impurities onto the upper surface of SiC semiconductor layer 210. The p-type impurities are introduced onto the upper surface of SiC semiconductor layer 210 through mask 901, after which mask 901 is removed. The formation of contact region 902 is performed at high temperature using an oxide mask.

[0074] Reference Figure 10A mask 1001 with a predetermined pattern is formed on top. The mask 1001 has an opening 1002 that selectively exposes the area where the gate trench 1003 will be formed.

[0075] Next, unwanted portions of the SiC semiconductor layer 210 are removed using an etching method (e.g., dry etching) through a mask 1001. In this step, the gate trench 1003 is formed by removing unwanted portions of the epitaxial layer 200.

[0076] Reference Figure 11 Before the formation of the first bottom protective structure, a thin oxide film 1110 is formed.

[0077] Although thin, the thin oxide film 1110 forms a uniform layer, playing a crucial role in ensuring the electrical and physical stability of the gate trench 1003 structure during the process. The thin oxide film 1110 protects the internal surface of the gate trench 1003 structure to ensure that it is not damaged during subsequent processes (e.g., doping, deposition, etching, etc.).

[0078] In addition, the thin oxide film improves the interface characteristics between the first bottom protective structure or other structures to optimize electrical performance, and plays a role in reducing defects at the interface and minimizing electrical losses.

[0079] Next, a first N-type implantation is performed to form a second bottom protection structure 1111 at the bottom of the gate trench 1003. This is to minimize the effects caused by the first bottom protection structure. Furthermore, the doping concentration and depth are designed to optimize the oxide protection and electrical characteristics at the bottom of the trench.

[0080] Next refer to Figure 12 The gate trench 1003 is filled with polysilicon 1210. Then refer to... Figure 13 Etching polysilicon 1210 to form spacers 1310.

[0081] The spacer 1310 serves to expose only the desired area and protect the rest, forming the desired structure in subsequent processes such as etching or ion implantation. The spacer 1310 is formed after depositing polysilicon 1210 in the gate trench 1003 structure.

[0082] According to an embodiment of the present invention, when removing the polysilicon 1210 in the future, it is recommended to form (maintain) R-Tox (Remaining Oxide Thickness) to protect the shape of the lower part of the gate trench 1003. The residual oxide film plays a role in ensuring the stability of the lower part of the gate trench 1003 during the polysilicon 1210 removal process.

[0083] Next refer to Figure 14To form a first bottom protection structure 1410 at the bottom of the gate trench 1003, a P-type implantation is performed. A second N-type implantation is then performed to reinforce the previously formed second bottom protection structure 1111. This helps to disperse the current more evenly flowing in and around the bottom of the gate trench 1003.

[0084] Reference Figure 15 Spacer 1310 was removed. Then refer to... Figure 16 The oxide film 1210 and the mask 1001 are removed.

[0085] Reference Figure 17 A gate insulating layer 1201 is formed on the upper surface of the SiC semiconductor layer 210. The gate insulating layer 1201 may include silicon oxide. The gate insulating layer 1201 may be formed by CVD or thermal oxidation.

[0086] The gate insulating layer 1201 of this structure is formed by adjusting the conditions of the CVD method or the thermal oxidation process. For example, in the CVD method or the thermal oxidation process, it is necessary to adjust the specified conditions such as gas flow rate, gas type, gas ratio, gas supply time, and ambient temperature.

[0087] Reference Figure 18 The gate electrode 1301 fills the gate trench 1003. The gate electrode 1301 may comprise polysilicon. The gate electrode 1301 may be formed by a CVD method. The CVD method may be LP-CVD (low-voltage CVD).

[0088] Reference Figure 19 An insulating layer 1401 is formed on the upper surface of the SiC semiconductor layer 210. The insulating layer 1401 may include silicon oxide or silicon nitride. The insulating layer 1401 may be formed by a CVD method.

[0089] Reference Figure 20 A mask 1501 with a predetermined pattern is formed on the insulating layer 1401. Next, unwanted portions of the insulating layer 1401 and the gate insulating layer 1201 are removed. The unwanted portions of the insulating layer 1401 and the gate insulating layer 1201 can be removed by using an etching method (e.g., dry etching) through the mask 1501.

[0090] Next refer to Figure 21 Mask 1501 was removed.

[0091] Figure 22 This is a drawing illustrating a SiC trench MOSFET structure with a trench bottom protection structure according to an embodiment of the present invention.

[0092] Reference Figure 22The source electrode 1701 is formed above the insulating layer 1401. The drain electrode 1702 is formed on the lower surface of the SiC semiconductor layer 210.

[0093] Reference Figure 22 The structure of a SiC trench MOSFET according to an embodiment of the present invention is described.

[0094] The SiC semiconductor layer 210 has a stacked structure including a SiC semiconductor substrate 101 containing SiC single crystals and an n-type epitaxial layer 200 containing SiC single crystals.

[0095] Drain electrode 1702 is formed on the lower surface of SiC semiconductor layer 210. SiC semiconductor substrate 101 is formed as an n+ type drain region. SiC epitaxial layer 200 is formed as an n-type drain drift region.

[0096] The n-type impurity concentration of the SiC semiconductor substrate 101 can be as low as 1.0 × 10¹ 8 cm - ³ to a maximum of 1.0 × 10²¹ cm - ³. The n-type impurity concentration of the SiC epitaxial layer 200 can be as low as 1.0 × 10¹ 5 cm - ³ to a maximum of 1.0 × 10¹ 7 cm - ³. In this description, "impurity concentration" refers to the peak value of the impurity concentration.

[0097] The trench gate structure includes a gate trench 1003, a gate insulating layer 1201, a gate electrode 1301, a second bottom protection structure 1111, and a first bottom protection structure 1410.

[0098] The gate trench 1003 is formed by digging downwards from the upper surface of the SiC semiconductor layer 210.

[0099] The gate insulating layer 1201 is formed in the form of a thin film along the sidewalls and bottom surface of the gate trench 1003. The gate insulating layer 1201 forms a recessed space inside the gate trench 1003.

[0100] The gate insulating layer 1201 may include silicon oxide. In addition to silicon oxide, the gate insulating layer 1201 may also include one or more of undoped silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0101] The gate electrode 1301 is inserted into a recessed space formed by the gate insulating layer 1201. The gate electrode 1301 may include conductive polysilicon. In addition to conductive polysilicon, the gate electrode layer may also include one or more of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0102] The second bottom protection structure 1111 refers to a layer designed to alleviate current congestion in a specific area around the trench.

[0103] The first bottom protection structure 1410 refers to a structure in which a P-type region is formed at the bottom of the trench structure and in the region below it to reduce the electric field applied to the gate oxide layer at the bottom of the trench and prevent damage to it.

[0104] The following is for reference Figure 24 This illustrates the protective effect produced by the second bottom protective structure 1111 and the first bottom protective structure 1410.

[0105] Figure 24 This is a conceptual diagram illustrating the effect of a protective structure according to an embodiment of the present invention.

[0106] Figure 24 (a) shows the electron path without a protective structure. Figure 24 (b) shows the electronic pathway altered by the protective structure.

[0107] The protective structures, namely the second bottom protection structure 1111 and the first bottom protection structure 1410, comprehensively enhance the protection of the bottom oxide of the trench and the current diffusion function, thereby improving the stability and power efficiency of the device.

[0108] Figure 24 In (a), without a protective structure, electrons descend along the sidewall of the gate trench 1003 and then flow along the bottom surface of the gate trench 1003 at the lower corner of the gate trench 1003. However, as Figure 24 As shown in (b), when a protective structure is formed, it can be confirmed that the flow of electrons is impeded, which may be accompanied by an increase in resistance.

[0109] In particular, the source-well structure 401 according to an embodiment of the present invention is proposed to be formed as a deep P-type well structure. For this source-well structure 401, refer to... Figure 25 Explain the strengthening effect of the protective structure.

[0110] Figure 25 The accompanying drawing illustrates why the protective structure according to an embodiment of the present invention is more effective in a deep P-type well structure.

[0111] Reference Figure 25 (a) shows the narrowed channel caused by the deep P-type well structure.

[0112] As shown in the figure, when the source well structure 401 is formed as a deep P-type well structure, and the depth of the deep P-type well structure is greater than the depth of the gate trench 1003, a region of narrowed channel (i.e., narrowed current path) will be formed, which may aggravate current congestion.

[0113] Reference Figure 25(b) When the second bottom protection structure 1111 is formed, current congestion can be alleviated, and the protection of the bottom oxide of the trench can be satisfied.

[0114] The effect of the second bottom protection structure 1111 will be explained below by comparing the current flow in the case where only the first bottom protection structure 1410 is formed and the case where the first bottom protection structure 1410 and the second bottom protection structure 1111 are formed simultaneously.

[0115] Figure 26 The accompanying drawing illustrates how a protection structure according to an embodiment of the present invention alters the current path.

[0116] Figure 26 (a) shows the current flow when only the first bottom protection structure 1410 is formed. Figure 26 (b) shows the current flow when the first bottom protection structure 1410 and the second bottom protection structure 1111 are formed simultaneously.

[0117] In the attached diagram, denser current lines indicate more severe current congestion, while wider spacing between current lines indicates less congestion. This can be confirmed. Figure 26 (b) Current gap ratio Figure 26 (a) is less dense. Therefore, it can be seen that the simultaneous formation of the first bottom protection structure 1410 and the second bottom protection structure 1111 is more effective in suppressing current congestion than the case where only the first bottom protection structure 1410 is formed.

[0118] Return again Figure 22 Explain the structure. The p-type impurity concentration of the source-well structure 401 can be as low as 1.0 × 10¹. 7 cm - ³ to a maximum of 1.0 × 10¹ 9 cm - ³.

[0119] The p-type body region 601 is formed on the upper surface of the SiC semiconductor layer 210. The body region 601 is formed in the region between the gate trench 1003 and the source-well structure 401.

[0120] The body region 601 is exposed from the sidewalls of the gate trench 1003 and the source well structure 401.

[0121] The concentration of p-type impurities in the bulk region 601 can be as low as 1.0 × 10¹ 6 cm - ³ to a maximum of 1.0 × 10¹ 9 cm - ³. The p-type impurity concentration in the bulk region 601 can be substantially the same as the p-type impurity concentration in the source-well structure 401.

[0122] The n+ type source region 602 is formed on the surface layer portion of the body region 601. The source region 602 is formed on the surface layer portion of the body region 601 along the sidewall of the gate trench 1003.

[0123] Multiple p+ type contact regions 902 are formed on the surface layer portion of the body region 601. The contact regions 902 are formed along the sidewalls of the source-well structure 401 on the surface layer portion of the body region 601. The p-type impurity concentration of the contact regions 902 can be as low as 1.0 × 10¹. 8 cm - ³ to a maximum of 1.0 × 10²¹ cm - ³.

[0124] An insulating layer 1401 is formed on the upper surface of the SiC semiconductor layer 210. The insulating layer 1401 completely covers the trench gate structure.

[0125] The source electrode 1701 is formed on top of the insulating layer 1401.

[0126] Reference Figure 27 and Figure 28 This illustrates the doping distribution among the first bottom protection structure 1410, the second bottom protection structure 1111, and the epitaxial layer 200.

[0127] Figure 27 The attached figure shows reference lines A and B that cross the first bottom protection structure 1410, the second bottom protection structure 1111, and the epitaxial layer 200 to illustrate the doping distribution. Figure 28 The attached figure shows the doping distribution along the reference lines A and B.

[0128] First, look at baseline A. Along the depth direction (from top to bottom), it sequentially crosses the first bottom protection structure 1410, the second bottom protection structure 1111, and the epitaxial layer 200. Baseline B, along the horizontal direction (from left to right), sequentially crosses the first bottom protection structure 1410, the second bottom protection structure 1111, and the epitaxial layer 200.

[0129] According to an embodiment of the present invention, the first bottom protection structure 1410 is a P-shaped structure, forming a predetermined depth from the bottom of the trench downwards.

[0130] According to an embodiment of the present invention, the second bottom protective structure 1111 is an N-type structure, which is arranged to surround the P-type structure.

[0131] The P-type and N-type structures form a PN junction at the bottom of the trench to protect the lower part of the trench.

[0132] Regarding doping concentration, the first bottom protection structure 1410 is p-type, approximately 1.0 × 10¹. 7 cm- ³ to a maximum of 1.0 × 10¹ 9 cm - ³; The second bottom protective structure 1111 is of type N, approximately 5.0 × 10¹ 6 cm - ³ to a maximum of 1.0 × 10¹ 8 cm - ³; Epitaxial layer 200 is N-type, approximately 1.0 × 10¹ 5 cm - ³ to a maximum of 1.0 × 10¹ 7 cm - ³.

[0133] That is, the second bottom protection structure 1111 at the bottom of the trench is set in a hemispherical shape, the first bottom protection structure 1410 is inserted into the interior of the hemispherical shape, and the first bottom protection structure 1410 is surrounded by the second bottom protection structure 1111.

[0134] In addition, the first bottom protection structure 1410 and the second bottom protection structure 1111 form a PN junction at the bottom of the trench.

[0135] The above describes embodiments of the SiC trench MOSFET with a deep well structure and its manufacturing method according to the present invention. However, this is only illustrative as at least one embodiment, and the technical concept, structure, and function of the present invention are not limited thereto. The scope of the technical concept of the present invention is not limited / restricted by the accompanying drawings or the description with reference to the drawings. Furthermore, the concepts and embodiments of the invention presented in this invention can be used by those skilled in the art as a basis for modifications or designs to achieve other structures to achieve the same purpose of the invention. Equivalent structures of modifications or alterations by those skilled in the art are limited by the technical scope of the invention as described in the claims. Various changes, substitutions, and modifications can be made without departing from the spirit or scope of the invention as described in the claims.

Claims

1. A SiC trench MOSFET, wherein, include: Semiconductor layer of the first conductivity type; Gate trenches formed on the upper surface of the semiconductor layer; A source-well structure of the second conductivity type is formed on the upper surface of the semiconductor layer at a predetermined distance from the gate trench; a body region of the second conductivity type is formed on the upper surface between the gate trench and the source-well structure; A source region of the first conductivity type formed on the upper surface of the body region; And a trench bottom protection structure disposed at the lower part of the gate trench, the trench bottom protection structure comprising: a first bottom protection structure forming a second conductivity type region of a predetermined depth from the bottom of the trench downward; A second bottom protection structure is formed in a shape that surrounds the first bottom protection structure to form a first conductive type region. At the bottom of the trench, the second bottom protection structure is set in a hemispherical shape. The first bottom protection structure is inserted into the interior of the hemispherical shape, such that the lower part and the side of the first bottom protection structure are surrounded by the second bottom protection structure. The second bottom protection structure is limited to the region directly below the bottom of the trench, contacts at least a portion of the region below the bottom of the trench, and does not extend upward along the outer sidewall of the trench.

2. The SiC trench MOSFET according to claim 1, wherein, The doping concentration of the second bottom protective structure is higher than that of the semiconductor layer.

3. The SiC trench MOSFET according to claim 2, wherein, The first bottom protection structure is a structure in which a second conductivity type region is formed in the lower part of the trench in order to reduce the electric field of the gate oxide layer applied to the bottom of the trench.

4. The SiC trench MOSFET according to claim 2, wherein, The second bottom protection structure is a structure that forms a first conductivity type region in a shape that surrounds the first bottom protection structure in order to widely disperse the current and reduce power loss and thermal stress.

5. The SiC trench MOSFET according to claim 1, wherein, The depth of the source trap structure is greater than the depth of the lower part of the gate trench.

6. A method for manufacturing a SiC trench MOSFET, wherein, include: The step of forming a body region of a second conductivity type on the upper surface of a semiconductor layer of a first conductivity type; The step of forming a source region of the first conductivity type on the upper surface of the body region; The step of forming a gate trench on the upper surface of the semiconductor layer; the step of forming a source well structure of a second conductivity type on the upper surface of the semiconductor layer at a predetermined distance from the gate trench; The step of forming a trench bottom protection structure at the lower part of the gate trench includes: performing a first conductivity type implantation at the bottom of the trench to form a second bottom protection structure; filling the interior of the trench with polysilicon; etching the filled polysilicon to form a spacer; performing a second conductivity type implantation at the bottom of the trench to form a first bottom protection structure; performing additional first conductivity type implantation to strengthen the second bottom protection structure; and removing the formed spacer.

7. The method for manufacturing a SiC trench MOSFET according to claim 6, wherein, The trench bottom protection structure includes: a first bottom protection structure forming a second conductivity type region of a predetermined depth from the bottom of the trench downwards; and a second bottom protection structure forming the first conductivity type region in a shape that surrounds the first bottom protection structure, wherein the doping concentration of the second bottom protection structure is higher than the doping concentration of the semiconductor layer.

8. The method for manufacturing a SiC trench MOSFET according to claim 7, wherein, The first bottom protection structure is a structure in which a second conductivity type region is formed in the lower part of the trench in order to reduce the electric field of the gate oxide layer applied to the bottom of the trench.

9. The method for manufacturing a SiC trench MOSFET according to claim 7, wherein, The second bottom protection structure is a structure that forms a first conductivity type region in a shape that surrounds the first bottom protection structure in order to widely disperse the current and reduce power loss and thermal stress.

10. The method for manufacturing a SiC trench MOSFET according to claim 6, wherein, The depth of the source trap structure is greater than the depth of the lower part of the gate trench.

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