Trench gate semiconductor device and method of manufacturing the same

Abstract

The application discloses a trench gate semiconductor device, which comprises a first trench formed in a first epitaxial layer of a first conductive type, and a second epitaxial layer of a second conductive type filled in the first trench. A second trench is formed in the second epitaxial layer. A gate oxide layer is formed on the inner side surface of the second trench, and the second epitaxial layer on the bottom surface of the first trench is partially oxidized and is protected by a protective layer of the second epitaxial layer remaining as the bottom of the second trench. A gate conductive material layer is filled in the second trench. The application also discloses a manufacturing method of the trench gate semiconductor device. The application does not need to use ion implantation to form a protective layer with a doping type opposite to that of a drift region at the bottom of the trench gate, and can realize the reduction of the electric field in the bottom region of the trench gate while avoiding the lattice defects caused by ion implantation for forming the protective layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a trench gate semiconductor device. This invention also relates to a method for manufacturing a trench gate semiconductor device. Background Technology

[0002] The main method for protecting the bottom of the trench in existing trench gate SiC devices is to form a P-buried layer through ion implantation. When the device is reverse blocked, the P-buried layer and the drift region form a depletion region, which reduces the peak electric field at the bottom of the trench and thus improves the reliability of the device.

[0003] However, there are certain drawbacks to forming P buried layers through ion implantation, mainly that ion implantation can create severe lattice defects and cause irreversible damage to the surface. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a trench gate semiconductor device that can form a protective layer with the opposite doping type to the drift region at the bottom of the trench gate without ion implantation, thereby reducing the electric field in the bottom region of the trench gate while avoiding lattice defects caused by ion implantation to form the protective layer. To this end, the present invention also provides a method for manufacturing the trench gate semiconductor device.

[0005] To solve the above-mentioned technical problems, the trench gate semiconductor device provided by the present invention includes: A first trench is formed in a first epitaxial layer doped with a first conductivity type, and a second epitaxial layer doped with a second conductivity type is filled in the first trench.

[0006] A second trench is formed in the second epitaxial layer, wherein the width of the second trench is less than the width of the first trench and the depth of the second trench is less than the depth of the first trench.

[0007] A gate oxide layer is formed on the inner surface of the second trench. The gate oxide layer located on the side of the second trench is formed by oxidation of the second epitaxial layer between the side of the second trench and the side of the first trench. The gate oxide layer located on the bottom surface of the second trench is formed by oxidation of the second epitaxial layer between the bottom surface of the second trench and the bottom surface of the first trench. The second epitaxial layer retained on the bottom surface of the first trench serves as a protective layer for the bottom of the second trench.

[0008] A gate conductive material layer is filled in the second trench where the gate oxide layer is formed.

[0009] A further improvement is that the material of the first epitaxial layer includes Si or SiC, and the material of the second epitaxial layer includes Si or SiC.

[0010] A further improvement is that a body region doped with a second conductivity type is formed in the surface region of the first epitaxial layer outside the second trench, and a source region heavily doped with a first conductivity type and a body lead-out region heavily doped with a second conductivity type are formed on the top surface of the body region; the first side of the body region and the first side of the source region are aligned with the outer side of the gate oxide layer located on the side of the second trench; there is a gap between the first side of the body lead-out region and the outer side of the gate oxide layer located on the side of the second trench.

[0011] A further improvement includes: an interlayer film, contact holes through the interlayer film, and a source and gate composed of a front metal layer.

[0012] Both the body lead-out region and the source region are connected to the source electrode through the corresponding contact hole at the top.

[0013] The gate conductive material layer is connected to the gate through the corresponding contact hole at the top.

[0014] A further improvement is that a heavily doped drain region of a first conductivity type is formed on the back side of the first epitaxial layer; and a drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0015] A further improvement is that the material of the gate conductive material layer includes polycrystalline silicon.

[0016] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0017] To solve the above-mentioned technical problems, the manufacturing method of the trench gate semiconductor device provided by the present invention includes the following steps: A first epitaxial layer with a first conductivity type doped is provided, and a first trench is formed in the first epitaxial layer.

[0018] A second epitaxial layer doped with a second conductivity type is filled into the first trench.

[0019] A second trench is formed in the second epitaxial layer, wherein the width of the second trench is less than the width of the first trench and the depth of the second trench is less than the depth of the first trench.

[0020] Thermal oxidation is performed to form a gate oxide layer on the inner surface of the second trench. The second epitaxial layer located between the side surface of the second trench and the side surface of the first trench is completely oxidized, and a portion of the second epitaxial layer located between the bottom surface of the second trench and the bottom surface of the first trench is oxidized. The second epitaxial layer retained on the bottom surface of the first trench serves as a protective layer for the bottom of the second trench.

[0021] A gate conductive material layer is filled in the second trench where the gate oxide layer is formed.

[0022] A further improvement is that the material of the first epitaxial layer includes Si or SiC, and the material of the second epitaxial layer includes Si or SiC.

[0023] A further improvement is that, after filling the second epitaxial layer and before forming the second trench, the method further includes: A body region is formed by body implantation with a second conductivity type doping, the body region being located in the surface region of the first epitaxial layer outside the first trench and the surface region of the second epitaxial layer inside the first trench.

[0024] A source region is formed in the surface region of the body region by implanting a source with a first conductivity class of heavy doping.

[0025] Ions heavily doped with a second conductivity type are implanted to form a body exit region in a selected region of the body region, the bottom surface of which is in contact with the body region.

[0026] After the gate oxide layer is formed, the first side surface of the body region and the first side surface of the source region are aligned with the outer side surface of the gate oxide layer located on the side surface of the second trench; there is a gap between the first side surface of the body lead-out region and the outer side surface of the gate oxide layer located on the side surface of the second trench.

[0027] A further improvement is that, after the body implantation, the source implantation, and the ion implantation of the body extraction region are completed, annealing activation is also performed.

[0028] A further improvement is that, after the gate conductive material layer is formed, the following steps are also included: An interlayer film is formed, passing through the contact holes of the interlayer film and the source and gate composed of the front metal layer.

[0029] Both the body lead-out region and the source region are connected to the source electrode through the corresponding contact hole at the top.

[0030] The gate conductive material layer is connected to the gate through the corresponding contact hole at the top.

[0031] A further improvement is that, after the front-side process is completed, it also includes: A heavily doped drain region of the first conductivity type is formed on the back side of the first epitaxial layer.

[0032] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0033] A further improvement is that the material of the gate conductive material layer includes polycrystalline silicon.

[0034] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0035] In this invention, the second trench corresponding to the trench gate is not directly formed in the first epitaxial layer, which serves as the drift region, but rather in a second epitaxial layer doped with a second conductivity type that fills the first trench. Utilizing the characteristic that the width and depth of the second trench are smaller than those of the first trench, a second epitaxial layer is retained at the bottom of the second trench. The gate oxide layer of the trench gate is formed through a thermal oxidation process. This thermal oxidation process at least completely oxidizes the second epitaxial layer between the sides of the first and second trenches, ensuring that the gate oxide layer at the sides of the second trench is in direct contact with the first epitaxial layer. The thermal oxidation process oxidizes the second epitaxial layer between the bottom surface of the second trench and the bottom surface of the first trench. Thus, the second epitaxial layer remaining on the bottom surface of the first trench can serve as a protective layer at the bottom of the second trench. Therefore, the protective layer of the present invention is composed of an epitaxial layer and does not need to be formed by ion implantation. Thus, the present invention can form a protective layer with the opposite doping type to the drift region at the bottom of the trench gate without ion implantation. This can reduce the electric field in the bottom region of the trench gate while avoiding lattice defects caused by ion implantation to form the protective layer, thereby avoiding irreversible damage related to lattice defects.

[0036] In addition, the gate oxide layer of the present invention is formed by a thermal oxidation process and has good quality. Attached Figure Description

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the structure of a trench gate semiconductor device according to an embodiment of the present invention; Figures 2-7 This is a schematic diagram of the device structure in each step of the manufacturing method of the trench gate semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0038] like Figure 1 The diagram shown is a structural schematic of a trench gate semiconductor device according to an embodiment of the present invention; the trench gate semiconductor device according to an embodiment of the present invention includes: A first trench 102 is formed in a first epitaxial layer 101 doped with a first conductivity type, and a second epitaxial layer 103 doped with a second conductivity type is filled in the first trench 102.

[0039] In this embodiment of the invention, the material of the first epitaxial layer 101 includes Si or SiC, and the material of the second epitaxial layer 103 includes Si or SiC.

[0040] A second trench 104 is formed in the second epitaxial layer 103. The width of the second trench 104 is smaller than the width of the first trench 102, and the depth of the second trench 104 is smaller than the depth of the first trench 102.

[0041] A gate oxide layer 105 is formed on the inner surface of the second trench 104. The gate oxide layer 105 located on the side of the second trench 104 is formed by oxidation of the second epitaxial layer 103 between the side of the second trench 104 and the side of the first trench 102. The gate oxide layer 105 located on the bottom surface of the second trench 104 is formed by oxidation of the second epitaxial layer 103 between the bottom surface of the second trench 104 and the bottom surface of the first trench 102. The second epitaxial layer 103 retained on the bottom surface of the first trench 102 serves as a protective layer for the bottom of the second trench 104.

[0042] A gate conductive material layer 106 is filled in the second trench 104 where the gate oxide layer 105 is formed. In this embodiment of the invention, the material of the gate conductive material layer 106 includes polysilicon.

[0043] A body region 107 doped with a second conductivity type is formed in the surface region of the first epitaxial layer 101 outside the second trench 104. A source region 108 heavily doped with a first conductivity type and a body lead-out region 109 heavily doped with a second conductivity type are formed on the top surface of the body region 107. The first side surface of the body region 107 and the first side surface of the source region 108 are aligned with the outer side surface of the gate oxide layer 105 located on the side surface of the second trench 104. There is a gap between the first side surface of the body lead-out region 109 and the outer side surface of the gate oxide layer 105 located on the side surface of the second trench 104. The drift region is composed of the first epitaxial layer 101 located at the bottom of the body region 107.

[0044] In this embodiment of the invention, it further includes: an interlayer film 110, a contact hole through the interlayer film 110, and a source and a gate composed of a front metal layer (not shown). Figure 1 The image shows the opening 111 of the contact hole, which is formed by metal filling the opening 111.

[0045] Both the body lead-out region 109 and the source region 108 are connected to the source electrode through the corresponding contact hole at the top.

[0046] The gate conductive material layer 106 is connected to the gate through the corresponding contact hole at the top.

[0047] In this embodiment of the invention, the trench gate semiconductor device is a trench gate MOSFET, and a heavily doped drain region (not shown) of a first conductivity type is formed on the back side of the first epitaxial layer 101; a drain electrode composed of a back metal layer is formed on the back side of the drain region. In other embodiments, the trench gate semiconductor device may also be a trench gate IGBT, and a heavily doped collector region of a second conductivity type is formed on the back side of the first epitaxial layer 101.

[0048] In this embodiment of the invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0049] In this embodiment of the invention, the second trench 104 corresponding to the trench gate, i.e., the gate trench, is not directly formed in the first epitaxial layer 101, which serves as the drift region, but is formed in the second epitaxial layer 103 doped with the second conductivity type, which fills the first trench 102. Utilizing the characteristic that the width and depth of the second trench 104 are smaller than the width and depth of the first trench 102, the bottom of the second trench 104 retains the second epitaxial layer 103. The gate oxide layer 105 of the trench gate is formed by a thermal oxidation process. This thermal oxidation process at least oxidizes all of the second epitaxial layer 103 between the sides of the first trench 102 and the second trench 104, ensuring that the gate oxide layer 105 at the sides of the second trench 104 is directly oxidized. Contacting the first epitaxial layer 101; the thermal oxidation process of the gate oxide transistor will partially oxidize the second epitaxial layer 103 between the bottom surface of the second trench 104 and the bottom surface of the first trench 102. Thus, the second epitaxial layer 103 remaining on the bottom surface of the first trench 102 can serve as a protective layer at the bottom of the second trench 104. Therefore, the protective layer in this embodiment of the invention is composed of an epitaxial layer and does not need to be formed by ion implantation. Thus, this embodiment of the invention can form a protective layer with the opposite doping type to the drift region at the bottom of the trench gate without ion implantation. This can reduce the electric field in the bottom region of the trench gate while avoiding lattice defects caused by ion implantation to form the protective layer, thereby avoiding irreversible damage related to lattice defects.

[0050] In addition, the gate oxide layer 105 in this embodiment of the invention is formed by a thermal oxidation process and has good quality.

[0051] like Figures 2 to 7The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the trench gate semiconductor device according to an embodiment of the present invention. The manufacturing method of the trench gate semiconductor device according to an embodiment of the present invention includes the following steps: Step S101, as follows Figure 2 As shown, a first epitaxial layer 101 with a first conductivity type doped is provided, and a first trench 102 is formed in the first epitaxial layer 101.

[0052] In the method of this embodiment of the invention, the material of the first epitaxial layer 101 includes Si or SiC.

[0053] The steps for forming the first trench 102 include: The formation area of ​​the first trench 102 is defined using photolithography.

[0054] The first epitaxial layer 101 is etched to form the first trench 102. In some embodiments, a hard mask layer is formed before the photolithography process, and during etching, the hard mask layer is etched first, followed by the first epitaxial layer 101.

[0055] Step S102, as follows Figure 3 As shown, a second epitaxial layer 103 doped with a second conductivity type is filled in the first trench 102.

[0056] In the method of this embodiment of the invention, the second epitaxial layer 103 is formed by epitaxial growth. After the epitaxial growth is completed, the epitaxial layer can be etched back or CMP can be performed to remove the second epitaxial layer 103 outside the first trench 102.

[0057] In the method of this embodiment of the invention, the material of the second epitaxial layer 103 includes Si or SiC.

[0058] In the method of this embodiment of the invention, after filling the second epitaxial layer 103 and before subsequently forming the second trench 104, the method further includes: like Figure 4 As shown, a body region 107 is formed by body implantation to perform second conductivity type doping. The body region 107 is located in the surface region of the first epitaxial layer 101 outside the first trench 102 and in the surface region of the second epitaxial layer 103 inside the first trench 102.

[0059] A source region 108 is formed in the surface region of the body region 107 by performing a first type of heavy doping source implantation.

[0060] Ions of a second conductivity type are implanted to form a body exit region 109 in a selected region of the body region 107, and the bottom surface of the body exit region 109 is in contact with the body region 107.

[0061] This is followed by annealing activation.

[0062] Step S103, as follows Figure 5 As shown, a second trench 104 is formed in the second epitaxial layer 103. The width of the second trench 104 is smaller than the width of the first trench 102, and the depth of the second trench 104 is smaller than the depth of the first trench 102.

[0063] Step S104, as follows Figure 6 As shown, thermal oxidation is performed to form a gate oxide layer 105 on the inner surface of the second trench 104. The second epitaxial layer 103 located between the side surface of the second trench 104 and the side surface of the first trench 102 is completely oxidized, and the second epitaxial layer 103 located between the bottom surface of the second trench 104 and the bottom surface of the first trench 102 is partially oxidized. The second epitaxial layer 103 retained on the bottom surface of the first trench 102 serves as a protective layer for the bottom of the second trench 104.

[0064] In the method of this embodiment of the invention, after the gate oxide layer 105 is formed, the first side surface of the body region 107 and the first side surface of the source region 108 are aligned with the outer side surface of the gate oxide layer 105 located on the side surface of the second trench 104; there is a gap between the first side surface of the body lead-out region 109 and the outer side surface of the gate oxide layer 105 located on the side surface of the second trench 104.

[0065] Step S105, as follows Figure 7 As shown, a gate conductive material layer 106 is filled in the second trench 104 where the gate oxide layer 105 is formed.

[0066] In the method of this embodiment of the invention, the material of the gate conductive material layer 106 includes polycrystalline silicon.

[0067] like Figure 1 As shown, after the gate conductive material layer 106 is formed, the following steps are also included: An interlayer film 110 is formed, passing through the contact holes of the interlayer film 110 and the source and gate composed of the front metal layer.

[0068] Both the body lead-out region 109 and the source region 108 are connected to the source electrode through the corresponding contact hole at the top.

[0069] The gate conductive material layer 106 is connected to the gate through the corresponding contact hole at the top.

[0070] In the method of this embodiment of the invention, the trench gate semiconductor device is a trench gate MOSFET, and after the front-side process is completed, the method further includes: A heavily doped drain region of the first conductivity type is formed on the back side of the first epitaxial layer 101.

[0071] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0072] In other embodiments, the method may also include: the trench gate semiconductor device is a trench gate IGBT, and after the front-side process is completed, the method further includes: forming a heavily doped collector region of a second conductivity type on the back side of the first epitaxial layer 101. Then, a collector electrode composed of a back metal layer is formed on the back side of the collector region.

[0073] In the method of this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0074] In the method of this invention embodiment, in order to avoid lattice defects caused by ion implantation, a method of filling before etching is adopted, which has the following advantages: ① A P buried layer with a certain doping concentration can be obtained at the bottom, that is, a P buried layer composed of the second epitaxial layer, which avoids irreversible damage caused by ion implantation and optimizes the electric field at the bottom corner of the trench; ② A high-quality gate oxide film can also be obtained through thermal oxidation.

[0075] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A trench gate semiconductor device, characterized in that, include: A first trench is formed in a first epitaxial layer doped with a first conductivity type, and a second epitaxial layer doped with a second conductivity type is filled in the first trench; A second trench is formed in the second epitaxial layer, wherein the width of the second trench is less than the width of the first trench and the depth of the second trench is less than the depth of the first trench. A gate oxide layer is formed on the inner surface of the second trench. The gate oxide layer located on the side of the second trench is formed by oxidation of the second epitaxial layer between the side of the second trench and the side of the first trench. The gate oxide layer located on the bottom surface of the second trench is formed by oxidation of the second epitaxial layer between the bottom surface of the second trench and the bottom surface of the first trench. The second epitaxial layer retained on the bottom surface of the first trench serves as a protective layer for the bottom of the second trench. A gate conductive material layer is filled in the second trench where the gate oxide layer is formed.

2. The trench gate semiconductor device as described in claim 1, characterized in that: The material of the first epitaxial layer includes Si or SiC, and the material of the second epitaxial layer includes Si or SiC.

3. The trench gate semiconductor device as described in claim 1, characterized in that: A body region doped with a second conductivity type is formed in the surface region of the first epitaxial layer outside the second trench. A source region heavily doped with a first conductivity type and a body lead-out region heavily doped with a second conductivity type are formed on the top surface of the body region. The first side of the body region and the first side of the source region are aligned with the outer side of the gate oxide layer located on the side of the second trench. There is a gap between the first side of the body lead-out region and the outer side of the gate oxide layer located on the side of the second trench.

4. The trench gate semiconductor device as described in claim 3, characterized in that, Also includes: Interlayer film, through contact holes in the interlayer film, and source and gate composed of front metal layers; Both the body lead-out region and the source region are connected to the source electrode through the corresponding contact hole at the top; The gate conductive material layer is connected to the gate through the corresponding contact hole at the top.

5. The trench gate semiconductor device as described in claim 4, characterized in that: A heavily doped drain region of a first conductivity type is formed on the back side of the first epitaxial layer; a drain electrode composed of a back metal layer is formed on the back side of the drain region.

6. The trench gate semiconductor device as claimed in claim 1, characterized in that: The material of the gate conductive material layer includes polycrystalline silicon.

7. The trench gate semiconductor device according to any one of claims 1 to 6, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

8. A method for manufacturing a trench gate semiconductor device, characterized in that, Includes the following steps: A first epitaxial layer with doping of a first conductivity type is provided, and a first trench is formed in the first epitaxial layer; A second epitaxial layer doped with a second conductivity type is filled into the first trench; A second trench is formed in the second epitaxial layer, wherein the width of the second trench is less than the width of the first trench and the depth of the second trench is less than the depth of the first trench. Thermal oxidation is performed to form a gate oxide layer on the inner surface of the second trench. The second epitaxial layer located between the side surface of the second trench and the side surface of the first trench is completely oxidized, and a portion of the second epitaxial layer located between the bottom surface of the second trench and the bottom surface of the first trench is oxidized. The second epitaxial layer retained on the bottom surface of the first trench serves as a protective layer for the bottom of the second trench. A gate conductive material layer is filled in the second trench where the gate oxide layer is formed.

9. The method for manufacturing a trench gate semiconductor device as described in claim 8, characterized in that: The material of the first epitaxial layer includes Si or SiC, and the material of the second epitaxial layer includes Si or SiC.

10. The method for manufacturing a trench gate semiconductor device as described in claim 8, characterized in that: After filling the second epitaxial layer and before forming the second trench, the method further includes: A body region is formed by body implantation of a second conductivity type doping method, the body region being located in the surface region of the first epitaxial layer outside the first trench and the surface region of the second epitaxial layer inside the first trench; A source region is formed in the surface region of the bulk region by implanting a source with heavy doping of the first conductivity class. Ions heavily doped with a second conductivity type are implanted to form a body exit region in a selected region of the body region, and the bottom surface of the body exit region is in contact with the body region; After the gate oxide layer is formed, the first side surface of the body region and the first side surface of the source region are aligned with the outer side surface of the gate oxide layer located on the side surface of the second trench; there is a gap between the first side surface of the body lead-out region and the outer side surface of the gate oxide layer located on the side surface of the second trench.

11. The method for manufacturing a trench gate semiconductor device as described in claim 10, characterized in that: After the body implantation, the source implantation, and the ion implantation of the body extraction region are completed, the process further includes: performing annealing activation.

12. The method for manufacturing a trench gate semiconductor device as described in claim 10, characterized in that, After the gate conductive material layer is formed, the following steps are also included: An interlayer film is formed, passing through the contact holes of the interlayer film and the source and gate composed of the front metal layer; Both the body lead-out region and the source region are connected to the source electrode through the corresponding contact hole at the top; The gate conductive material layer is connected to the gate through the corresponding contact hole at the top.

13. The method for manufacturing a trench gate semiconductor device as described in claim 12, characterized in that: After the front-side process is completed, it also includes: A heavily doped drain region of the first conductivity type is formed on the back side of the first epitaxial layer; A drain electrode composed of a back metal layer is formed on the back side of the drain region.

14. The method for manufacturing a trench gate semiconductor device as described in claim 8, characterized in that: The material of the gate conductive material layer includes polycrystalline silicon.

15. The method for manufacturing a trench gate semiconductor device according to any one of claims 8 to 14, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

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