A trench gate silicon carbide MOSFET device and a method of manufacturing the same

Abstract

The application discloses a trench gate silicon carbide MOSFET device and a preparation method thereof. The device comprises a drain, a substrate, a first epitaxial layer, a P-type island, a second epitaxial layer, a P-type masking area, a gate oxide layer, a trench, a gate, an interlayer dielectric layer and a source from bottom to top. A P-type base region and a heavily doped N-type region are periodically arranged on the second epitaxial layer in sequence. A heavily doped P-type first region and a heavily doped P-type second region are periodically arranged on both sides of the second epitaxial layer, the P-type base region and the heavily doped N-type region in a longitudinal direction. The heavily doped P-type first region and the heavily doped P-type second region are periodically arranged along the Y-axis direction. The second epitaxial layer is arranged between the adjacent spaced heavily doped P-type second regions. A P-type connecting region is arranged between the adjacent spaced heavily doped P-type first regions. The application can protect the trench bottom oxide layer and improve the third quadrant performance of the device without sacrificing the forward conduction capability of the MOSFET device.

Description

Technical Field

[0001] This invention belongs to the field of silicon carbide MOSFET technology, and particularly relates to a trench gate silicon carbide MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide possesses excellent material properties such as a large bandgap, high critical breakdown electric field, high thermal conductivity, and high saturation drift velocity. These properties enable silicon carbide MOSFET devices to adapt to extreme application environments such as high voltage, high frequency, and high temperature, and can significantly improve the efficiency of power electronic systems.

[0003] Silicon carbide MOSFETs are among the most widely used silicon carbide power devices on the market. Silicon carbide MOSFETs have two typical gate structures: planar gate and trench gate. Because trench gate devices lack a JFET region and increase channel density, they significantly reduce the on-resistance of the device, making them a promising technology with great development potential.

[0004] However, improvements in the electrical performance and reliability of trench-gate silicon carbide MOSFET devices have encountered obstacles. For example... Figure 1 As shown, on the one hand, SiC MOSFET devices are often used in high-voltage environments with high internal electric fields. The electric field in the gate oxide layer of a silicon carbide MOSFET is approximately three times that of the silicon carbide material itself. Furthermore, in the blocking state, the electric field tends to accumulate near the trench corners. Therefore, under strong electric field impacts, trench-gate silicon carbide MOSFETs are prone to gate oxide breakdown. Existing technologies often utilize floating square P-type doped regions formed at the bottom of the trench to protect the gate oxide, but these floating P-type doped regions reduce the forward conduction capability. On the other hand, when a silicon carbide MOSFET operates in the third quadrant, its internal parasitic body diode turns on, but its turn-on voltage is as high as 2-3V. Therefore, the conduction of the silicon carbide MOSFET body diode introduces significant losses. In addition, the silicon carbide epitaxial layer contains plane dislocations. When the body diode conducts, the energy released by electron-hole recombination causes stacking faults to propagate at these plane dislocations, resulting in bipolar degradation. This leads to a degradation of the electrical performance of the silicon carbide MOSFET, such as increased on-resistance and increased leakage current. Summary of the Invention

[0005] Purpose of the invention: The present invention designs a trench-gate silicon carbide MOSFET device. The device structure can protect the oxide layer at the bottom of the trench and improve the performance of the device in the third quadrant without sacrificing the forward conduction capability.

[0006] In a first aspect, the present invention proposes a trench-gate silicon carbide MOSFET device, comprising, from bottom to top, a drain, a silicon carbide substrate, a first epitaxial layer, a P-type island, a second epitaxial layer, a P-type masking region, a gate oxide layer, a trench, a gate, an interlayer dielectric layer, and an uppermost source. A gate oxide layer is disposed at the bottom and sidewalls of the trench, a gate is disposed in the trench, a P-type masking region is disposed between the gate oxide layer at the bottom of the trench and the second epitaxial layer, and an interlayer dielectric layer is disposed above the trench. The device is characterized in that a P-type base region and a heavily doped N-type region are periodically disposed sequentially on the second epitaxial layer; a heavily doped P-type first region and a heavily doped P-type second region are periodically disposed longitudinally on both sides of the second epitaxial layer, the P-type base region, and the heavily doped N-type region, respectively. The heavily doped P-type first region and the heavily doped P-type second region are periodically arranged along the Y-axis direction, a second epitaxial layer is disposed between adjacent heavily doped P-type second regions, and a second epitaxial layer is disposed between adjacent heavily doped P-type islands. A P-type connection region is provided between the first regions; the trench is provided above the P-type island and in the middle of the second epitaxial layer, the P-type base region and the heavily doped N-type region; a Schottky contact metal is provided between adjacent heavily doped P-type second regions and above the second epitaxial layer.

[0007] Secondly, the present invention provides a method for fabricating a trench-gate silicon carbide MOSFET device as described in the first aspect of the present invention. The method includes:

[0008] S1: An N-type silicon carbide epitaxial layer is grown on a silicon carbide substrate wafer;

[0009] S2: On the N-type silicon carbide epitaxial layer, photolithography and boron ion implantation are performed using at least three windows of different sizes to form a stepped P-type island region.

[0010] S3: A second epitaxial layer with a higher doping concentration is formed on the N-type silicon carbide epitaxial layer by epitaxial growth;

[0011] S4: On the second epitaxial layer, periodic photolithography and boron ion implantation are performed to form a P-type base region; on the P-type base region, photolithography and phosphorus ion implantation are performed to form a heavily doped N-type region;

[0012] S5: Periodic photolithography and high-energy boron ion implantation are performed on the second epitaxial layer to form heavily doped P-type regions and P-type connection regions, respectively.

[0013] S6: A trench is formed above the P-type island and in the middle of the first epitaxial layer, the P-type base region and the heavily doped N-type region using a trench etching process, and then a P-type masking layer is formed by photolithography and boron ion implantation.

[0014] S7: A gate oxide layer is formed at the bottom and sides of the trench using a thermal oxidation process, and a gate polysilicon is formed in the trench using polysilicon deposition;

[0015] S8: The upper surface of the trench is fully covered by a silica deposition process to form an interlayer dielectric layer;

[0016] S9: On the interlayer dielectric layer between adjacent heavily doped P-type second regions, etch contact holes for Schottky contacts, deposit metal on the contact holes, and form Schottky contacts after alloying.

[0017] S10: Deposit metal at the top of the whole cell to form a metallized source, and deposit metal at the bottom of the whole cell to form a metallized drain.

[0018] The beneficial effects of this invention are:

[0019] First, in this invention, the P-type island is deeper than the P-type masking region, which can effectively shield the high drain voltage, thereby significantly reducing the gate oxide electric field at the bottom of the trench and improving device reliability. The P-type connection region can connect the P+ source region and the P-type island, enabling the P-type island to be periodically grounded. This can make the depletion region of the P-type island narrower during forward conduction, avoiding current path compression and thus improving conduction capability. The Schottky contact metal and the second epitaxial layer below form a Schottky barrier diode. This structure can be turned on when the silicon carbide MOSFET device is operating in the third quadrant, thereby avoiding bipolar degradation caused by hole injection. Moreover, the turn-on voltage of the Schottky barrier diode is significantly lower than that of the parasitic body diode, greatly reducing losses.

[0020] Secondly, the MOSFE device proposed in this invention features a periodic alternation of two structures in the cell direction, rather than the traditional structure where the cell directions are completely uniform. In the second periodic structure, the P-type connection region only needs to occupy half of the position to achieve a good grounding effect, while the other half integrates a Schottky barrier diode. The integrated Schottky barrier diode can avoid the adverse effects of all P-region doped regions on the third quadrant, thus improving the device's third quadrant capability. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the three-dimensional cell structure of a trench-gate silicon carbide MOSFET in the prior art;

[0022] Figure 2 This is a schematic diagram of the three-dimensional structure of a cell in Embodiment 1 of the present invention;

[0023] Figure 3 for Figure 2 Schematic diagram of the structure of section A;

[0024] Figure 4 for Figure 2Schematic diagram of the structure of section B;

[0025] Figure 5 This is a schematic diagram of the formation of a P-shaped island in Embodiment 2 of the present invention;

[0026] Figure 6 This is a schematic diagram illustrating the formation of a P-type base region (Pbase) and a heavily doped N-type region (N+) in Embodiment 2 of the present invention;

[0027] Figure 7 This is a schematic diagram of the formation of a heavily doped P-type region (P+) and a P-type connection region in Embodiment 2 of the present invention;

[0028] Figure 8 This is a schematic diagram of the trench formed in Embodiment 2 of the present invention;

[0029] Figure 9 This is a schematic diagram of oxidizing the trench and forming a gate oxide layer in Embodiment 2 of the present invention;

[0030] Figure 10 This is a schematic diagram of the formation of the interlayer medium in Embodiment 2 of the present invention;

[0031] Figure 11 This is a schematic diagram of the formation of a Schottky contact in Embodiment 2 of the present invention;

[0032] Figure 12 This is a schematic diagram of the formation of the metal drain and metal source in Embodiment 2 of the present invention;

[0033] In the attached diagram, 1 represents the metallized drain, 2 represents the N-type silicon carbide substrate, 3 represents the first N-type silicon carbide epitaxial layer, 4 represents the P-type island, 5, 51, and 52 represent the second epitaxial layer, 6, 61, and 62 represent the P-type base region, 7, 71, and 72 represent the heavily doped N-type region (N+), 81 represents the heavily doped first P-type region (P+), 82 represents the heavily doped second P-type region (P+), 9 represents the P-type masking region, 10 represents the gate, 111 represents the first oxide (gate oxide), 112 represents the second oxide (interlayer dielectric layer), 12 represents the source, 13 represents the Schottky contact metal, and 14 represents the P-type connection region. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] like Figure 1 As shown, a trench-gate silicon carbide MOSFET device exists in the prior art. This device includes, from bottom to top: a metallized drain 1, an N-type silicon carbide substrate 2, an N-type silicon carbide first epitaxial layer 3, a second epitaxial layer 5, a P-type base region 6, and a heavily doped N-type region (N+) 7. Heavily doped P-type first region (P+) 81 and heavily doped P-type second region (P+) 82 are vertically disposed on both sides of the second epitaxial layer 5, the P-type base region, and the heavily doped N-type region 7, respectively. A trench is formed in the middle of the second epitaxial layer 5, the P-type base region 6, and the heavily doped N-type region 7. A gate oxide layer 111 is disposed at the bottom and sidewalls of the trench. A gate 10 is disposed in the trench. A P-type gate oxide layer 10 is disposed at the bottom of the trench between the gate oxide layer 111 and the second epitaxial layer 5. The masking region 9 has an interlayer dielectric layer 112 at the top of the trench, which completely covers the metallized source 12. This trench-gate silicon carbide MOSFET device, on the one hand, forms a floating square P-type doped region at the bottom of the trench to protect the gate oxide; however, the floating P-type doped region reduces its forward conduction capability. On the other hand, when the silicon carbide MOSFET device operates in the third quadrant, its internal parasitic body diode turns on, but its turn-on voltage is as high as 2-3V, resulting in significant losses when the body diode is turned on. Furthermore, the silicon carbide epitaxial layer contains plane dislocations. When the body diode is turned on, the energy released by electron-hole recombination causes stacking faults to propagate at the plane dislocations, resulting in bipolar degradation and degrading the electrical performance of the silicon carbide MOSFET, such as increased on-resistance and increased leakage current.

[0036] Example 1

[0037] Reference Figure 1-4Embodiment 1 of the present invention proposes a trench gate silicon carbide MOSFET device. The trench-type silicon carbide MOSFET device includes, from bottom to top: a metallized drain 1, an N-type silicon carbide substrate 2, an N-type silicon carbide first epitaxial layer 3, a P-type island 4, and a second epitaxial layer 51. P-type base regions (Pbase) (61, 62) and heavily doped N-type regions (N+) (71, 72) are periodically arranged sequentially on the second epitaxial layer 51, specifically on both sides of the second epitaxial layer 51. Heavily doped P-type first regions (P+) 81 and heavily doped P-type second regions (P+) 82 are periodically arranged longitudinally on both sides of the second epitaxial layer 51, the P-type base regions, and the heavily doped N-type regions, specifically in the four corner regions at the top of the entire cell. The heavily doped P-type first regions (P+) 81 and heavily doped P-type second regions (P+) 82 are periodically arranged along the Y-axis, specifically distributed at both ends of the entire cell. Adjacent heavily doped P-type islands are arranged in a specific pattern. A second epitaxial layer 52 is provided between the second P+ regions 82, and a P-type connection region 14 is provided between adjacent heavily doped P-type first regions (P+) 81. A trench is provided above the P-type island 4 and in the middle of the second epitaxial layer 51, the P-type base region and the heavily doped N-type region 7. A gate oxide layer 111 is provided at the bottom and on both side walls of the trench, and a gate 10 is provided in the trench. A P-type masking region 9 is provided below the gate oxide layer 111 at the bottom of the trench and between the second epitaxial layer 5. A Schottky contact metal 13 is provided between adjacent heavily doped P-type second regions (P+) 82 and above the second epitaxial layer 52. An interlayer dielectric layer 112 is provided above the trench, and a metallized source 12 is fully covered above the interlayer dielectric layer 112.

[0038] Specifically, using N-type silicon carbide as the substrate, silicon carbide possesses excellent material properties such as a large bandgap, high critical breakdown electric field, high thermal conductivity, and high saturation drift velocity. An N-type silicon carbide first epitaxial layer is grown on the N-type silicon carbide substrate, forming the N-type drift region (N-drift). The thickness and doping concentration of this first epitaxial layer directly determine the breakdown voltage level of the MOSFET device. Next, a second epitaxial layer is grown on top of the first epitaxial layer. The doping concentration of the second epitaxial layer is higher than that of the first epitaxial layer, which serves to extend the current; this can also be called the current spreading layer (CSL).

[0039] In one embodiment, the cross-section of the P-shaped island 4 has a three-layered trapezoidal shape, such as... Figure 4 As shown.

[0040] Specifically, the P-type island is deeper than the P-type shielding region, which can effectively shield the high drain voltage, thereby significantly reducing the gate oxide electric field at the bottom of the trench and improving device reliability. The P-type connection region can connect the P+ source region and the P-type island, enabling the P-type island to be periodically grounded. This can make the P-type island depletion region narrower during forward conduction, avoiding current path compression and thus improving conduction capability. The Schottky contact metal 13 and the lower second epitaxial layer 52 form a Schottky barrier diode. This structure can turn on when the silicon carbide MOSFET device is operating in the third quadrant, thereby avoiding bipolar degradation caused by hole injection. Moreover, the turn-on voltage of the Schottky barrier diode is significantly lower than that of the parasitic body diode, greatly reducing losses.

[0041] Current enters from the bottom drain, passes through epitaxial layer 3 and the second epitaxial layer, then through the conductive channel formed at the interface between the P-base region and gate oxide 111, before entering N+ and flowing out from the source. This invention optimizes the device for both breakdown voltage and forward conduction states. For the blocking state, the main optimization is the electric field within the gate oxide at the bottom of the trench. This invention forms a stepped P-type island region below the trench and uses ion implantation to form periodic P-type connection regions. The P-type connection regions connect the P+ source region and the P-type islands, enabling periodic grounding of the P-type islands. In the blocking state, the P-type islands are deeper than the P-type masking regions. The P-type islands connected to ground below the trench can more effectively shield the high drain voltage, thereby significantly reducing the electric field within the gate oxide at the bottom of the trench and improving device reliability. For the forward conduction state, the main optimization is the current propagation within epitaxial layer 3 and the second epitaxial layer. The P-type island is a stepped shape, wider at the top and narrower at the bottom. This design avoids the narrowing of the current conduction path caused by an excessively wide bottom band in the square doped region. Furthermore, in traditional device structures, the P-type masking region is usually floating, resulting in a wider depletion region and a narrower current path during forward conduction. In this invention, the P-type island is connected to the source (low potential) through a P-type connection region. Compared to the floating case, the depletion region is narrower during forward conduction, further ensuring a sufficiently wide current conduction path and guaranteeing the device's forward conduction performance. In addition, when the device operates in the third quadrant, the P+ region and P-type connection region inject holes into the N-type doped region. The Schottky barrier diode integrated in this invention can turn on when the silicon carbide MOSFET device operates in the third quadrant, thus avoiding bipolar degradation caused by hole injection. Moreover, the Schottky barrier diode's turn-on voltage is significantly lower than that of the parasitic body diode, significantly improving the third quadrant performance of the MOSFET device and greatly reducing losses.

[0042] It should be noted that, as Figure 7 , Figure 8As shown, in this application, P-type base regions (Pbase) (61, 62) and heavily doped N-type regions (N+) (71, 72) are periodically and sequentially arranged on the second epitaxial layer 51. For a single cell, these regions are specifically located on the front and rear sides of the second epitaxial layer 51. Heavily doped P-type first regions (P+) 81 and heavily doped P-type second regions (P+) 82 are periodically arranged longitudinally on both sides of the second epitaxial layer 51, the P-type base regions, and the heavily doped N-type regions 7. For a single cell, these regions are specifically located in the four corner regions at the top of the entire cell. The formation process involves device patterning in the second stage of manufacturing. Different functional regions are formed at different positions within the cell using photolithography and ion implantation, including P-type base regions (Pbase) (61, 62), heavily doped N-type regions (N+) (71, 72), heavily doped P-type first regions (P+) 81, heavily doped P-type second regions (P+) 82, and P-type connection regions 14, etc. If multiple cells are arranged and combined, the characteristic of periodically setting functional areas will become more prominent.

[0043] The MOSFE device proposed in this invention features a periodic alternation of two structures in the cell direction, rather than the traditional structure where the cell directions are completely uniform. In the second periodic structure, the P-type connection region only needs to occupy half of the space to achieve a good grounding effect, while the other half integrates a Schottky barrier diode. The integrated Schottky barrier diode can avoid the adverse effects of all P-type doped regions on the third quadrant, thus improving the device's third quadrant capability.

[0044] Example 2

[0045] Embodiment 2 of this invention proposes a method for fabricating a trench-gate silicon carbide MOSFET device as described in Embodiment 1. (Refer to...) Figure 5-12 As shown, the method includes:

[0046] Phase 1: Preparing the silicon carbide substrate

[0047] S1: Grow a silicon carbide substrate and cut it into silicon carbide substrate wafers; grow an N-type silicon carbide epitaxial layer 3 on the silicon carbide substrate wafers. Perform defect scanning on the silicon carbide substrate 2 and its epitaxial layer 3, leaving the defect-free silicon carbide substrate 2 and its epitaxial layer 3, and proceed to S2.

[0048] Phase Two: Device Graphics

[0049] S2: On the N-type silicon carbide epitaxial layer 3, photolithography and boron ion implantation are performed using at least three windows of different sizes to form a stepped P-type island region 4, such as... Figure 5 As shown.

[0050] S3: On the N-type silicon carbide epitaxial layer 3, a second epitaxial layer 51 with a higher doping concentration (i.e., lower resistivity) is formed by epitaxial growth, such as... Figure 6 As shown. The second epitaxial layer serves to extend the current, and can also be called the Current Spreading Layer (CSL).

[0051] S4: On the second epitaxial layer 51, periodic photolithography and boron ion implantation are performed to form P-type base regions (61, 62); then, photolithography and phosphorus ion implantation are performed on the P-type base regions (61, 62) to form heavily doped N-type regions (N+) (71, 72); as shown Figure 6 As shown.

[0052] S5: Periodic photolithography and high-energy boron ion implantation are performed on the second epitaxial layer 51 to form heavily doped P-type regions (81,82) and P-type connection regions 14, respectively.

[0053] Specifically, periodic photolithography and high-energy boron ion implantation are performed on both sides of the second epitaxial layer 51 to form heavily doped P-type first region (P+) 81 and heavily doped P-type second region (P+) 82; photolithography and high-energy boron ion implantation are performed between adjacent heavily doped P-type first regions (P+) 81 to form P-type connection regions 14, and the second epitaxial layer 52 is formed between adjacent heavily doped P-type second regions (P+) 82, as shown below. Figure 7 As shown.

[0054] The semi-finished products obtained after steps S2-S5 are subjected to defect scanning, and the defect-free semi-finished products are kept to enter the next step.

[0055] Third stage: Formation of trench, gate, gate oxide layer and interlayer dielectric layer

[0056] S6: Above the P-type island 4 and in the middle of the first epitaxial layer 51, the P-type base region, and the heavily doped N-type region 7, trenches are formed using a trench etching process. Then, a P-type masking layer is formed through photolithography and boron ion implantation. Figure 8 As shown.

[0057] S7: A gate oxide layer 111 is formed at the bottom and sides of the trench using a thermal oxidation process, and a polycrystalline gate 10 is formed within the trench using polycrystalline deposition, such as... Figure 9 As shown.

[0058] S8: Using a silica deposition process, an interlayer dielectric layer 112 is formed by fully covering the upper surface of the trench, such as... Figure 10 As shown.

[0059] The semi-finished products obtained after steps S6-S8 are subjected to defect scanning, and the defect-free semi-finished products are kept to enter the next step.

[0060] Fourth stage: Formation of Schottky contacts and metallization

[0061] S9: Contact holes for Schottky contacts are etched on the interlayer dielectric layer 112 between adjacent heavily doped P-type second regions (P+) 82. Metal is deposited on the contact holes, and excess metal is removed using planarization techniques. After alloying, Schottky contacts are formed, such as... Figure 11 As shown.

[0062] S10: Deposit metal at the top of the whole cell to form a metallized source 12, and deposit metal at the bottom of the whole cell to form a metallized drain 1, as shown. Figure 12 As shown.

[0063] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A trench-gate silicon carbide MOSFET device, comprising, from bottom to top, a drain (1), a silicon carbide substrate (2), a first epitaxial layer (3), a P-type island (4), a second epitaxial layer (51), a P-type masking region (9), a gate oxide layer (111), a trench, a gate (10), an interlayer dielectric layer (112), and an uppermost source (12), wherein the gate oxide layer (111) is disposed at the bottom and on both sidewalls of the trench, the gate (10) is disposed in the trench, the P-type masking region (9) is disposed below the gate oxide layer (111) at the bottom of the trench and between the second epitaxial layer (51), and the interlayer dielectric layer (112) is disposed above the trench, characterized in that, P-type base regions (61, 62) and heavily doped N-type regions (71, 72) are periodically arranged sequentially on the second epitaxial layer (51); heavily doped P-type first region (81) and heavily doped P-type second region (82) are periodically arranged longitudinally on both sides of the second epitaxial layer, the P-type base region and the heavily doped N-type region, respectively. The heavily doped P-type first region (81) and the heavily doped P-type second region (82) are arranged periodically along the Y-axis direction. There is a second epitaxial layer (52) between adjacent heavily doped P-type second regions (82), and a P-type connection region (14) is arranged between adjacent heavily doped P-type first regions (81); the trench is arranged above the P-type island (4) and in the middle of the second epitaxial layer (51), the P-type base region and the heavily doped N-type region; a Schottky contact metal (13) is arranged between adjacent heavily doped P-type second regions (82) and above the second epitaxial layer (52).

2. The trench-gate silicon carbide MOSFET device according to claim 1, characterized in that, The cross-section of the P-shaped island (4) presents a three-layered trapezoidal shape.

3. The trench-gate silicon carbide MOSFET device according to claim 1, characterized in that, The silicon carbide substrate (2), the first epitaxial layer (3), and the second epitaxial layer (51, 52) are all N-type silicon carbide.

4. A method for fabricating a trench-gate silicon carbide MOSFET device as described in claim 1, the method comprising: S1: An N-type silicon carbide epitaxial layer (3) is epitaxially grown on a silicon carbide substrate (2) wafer. S2: On the N-type silicon carbide epitaxial layer (3), photolithography and boron ion implantation are performed using windows of different sizes at least three times to form a stepped P-type island region (4). S3: On the N-type silicon carbide epitaxial layer (3), a second epitaxial layer (51) with a higher doping concentration is formed by epitaxial growth. S4: On the second epitaxial layer (51), periodic photolithography and boron ion implantation are performed to form a P-type base region (61,62); on the P-type base region (61,62), photolithography and phosphorus ion implantation are performed to form a heavily doped N-type region (71,72). S5: Periodic photolithography and high-energy boron ion implantation are performed on the second epitaxial layer (51) to form heavily doped P-type regions (81,82) and P-type connection regions (14), respectively. S6: A trench is formed above the P-type island (4) and in the middle of the first epitaxial layer (51), the P-type base region and the heavily doped N-type region using a trench etching process, and then a P-type masking layer (9) is formed by photolithography and boron ion implantation. S7: A gate oxide layer (111) is formed at the bottom and sides of the trench using a thermal oxidation process, and a gate (10) polycrystalline is formed in the trench using polycrystalline deposition; S8: The upper surface of the trench is fully covered by the silica deposition process to form an interlayer dielectric layer (112). S9: On the interlayer dielectric layer (112) between adjacent heavily doped P-type second regions (82), a Schottky contact contact hole is etched, metal is deposited on the contact hole, and a Schottky contact (13) is formed after alloying. S10: Deposit metal at the top of the whole cell to form a metallized source (12), and deposit metal at the bottom of the whole cell to form a metallized drain (1).

Images