A silicon carbide mosfet

Abstract

The application relates to the technical field of silicon carbide MOSFETs, and discloses a silicon carbide MOSFET, wherein, in use, a first N+ source region and a first P body region of the application form a ring-shaped channel, the device simultaneously has a longitudinal channel of a ring gate groove sidewall and a ring-shaped transverse channel of a groove bottom, the channel density is increased, the on-current density of the device is greatly improved, and the on-resistance of the device is reduced; secondly, the second P body region, the second N+ source region on the top of an N-type epitaxial layer, the first P body region and the first N+ source region on the groove bottom are selectively short-circuited on a Z axis in a three-dimensional direction, the device preparation process complexity is simplified, and the production cost is reduced. The device structure can improve the reliability problems of gate oxide quality, thermal stability, avalanche capability and short-circuit capability of the device under the premise of effectively improving the static and dynamic performance of the device, and provides a feasible technical path for the localization and commercial application of the silicon carbide trench MOSFET device.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide MOSFET technology, and more specifically to a silicon carbide MOSFET. Background Technology

[0002] Currently, SiC MOSFETs are at a critical stage of development, transitioning from "high-end optional equipment" to "industry standard equipment." As a third-generation wide-bandgap semiconductor material, silicon carbide (SiC) has achieved large-scale application in fields such as new energy vehicles, photovoltaic energy storage, AI data centers, and smart grids due to its excellent characteristics such as high voltage, high frequency, and low conduction loss. In the new energy field, as the 800V high-voltage platform becomes standard equipment in mid-to-high-end vehicles, the value of SiC MOSFETs is shifting from performance upgrades to providing fundamental support for system efficiency and charging experience. In the photovoltaic and energy storage fields, it can improve inverter conversion efficiency to over 99% and reduce energy loss by less than 50%. In AI data centers, the explosive growth of AI computing power is driving the evolution of power supply architecture towards higher voltage and higher power density, making SiC MOSFETs a key foundation for infrastructure expansion.

[0003] While SiC MOSFETs are rapidly expanding in the application market, the three core issues of device performance, gate oxide reliability, and short-circuit capability remain technical bottlenecks that restrict their further popularization.

[0004] First, with the increasing demands for power density and efficiency in power electronic systems, the inherent contradiction between the on-resistance (Rds(on)) and blocking voltage (BV) of traditional silicon carbide devices has made their performance unable to meet current application requirements. This is especially true in medium- and high-voltage applications such as traction inverters for new energy vehicles, photovoltaics, energy storage, smart grids, and rail transit. How to further reduce the conduction loss of devices while maintaining high blocking voltage has become a key challenge for technological development.

[0005] Secondly, there are issues related to gate oxide quality and long-term reliability. The critical breakdown electric field strength of SiC is ten times that of silicon (Si), forcing the gate oxide to withstand a high electric field, which exponentially increases its lifetime stress. Furthermore, the inherent characteristics of SiC materials and processes result in a much higher defect density in its gate oxide layer than traditional silicon (Si) devices, making it more prone to breakdown under long-term high electric fields. This is a key bottleneck determining the device's lifetime and reliability. Therefore, in practical applications, SiC MOSFET drive circuits require more stringent control over gate voltage overshoot, negative voltage turn-off (to prevent false turn-on and release interface trap charges), and carefully designed gate resistors than silicon devices to balance switching losses and gate oxide stress, ensuring reliable lifetime.

[0006] Furthermore, regarding short-circuit capability, most SiC MOSFETs have a relatively short short-circuit withstand time (typically ≤3μs). This is due to the higher saturation current density of the device, which leads to severe short-circuit current surges. In addition, the pursuit of low on-resistance requires thinning the gate oxide, which makes the device more susceptible to gate oxide breakdown. The main short-circuit failure modes include thermal expansion stress causing cracking of the interlayer dielectric layer, which leads to gate-source short circuits, and hole current triggering the turn-on of parasitic NPN transistors, which leads to thermal runaway.

[0007] To address the aforementioned issues, existing silicon carbide MOSFETs employing a trench structure eliminate the junction field-effect transistor (JFET) region of planar MOSFETs, reducing on-resistance, cell size, and manufacturing costs. However, the gate oxide at the bottom corner of the trench experiences a higher electric field strength than in planar structures, which reduces the device's breakdown voltage and long-term gate oxide reliability. Another SiC MOSFET device structure uses a semi-enclosed structure on one side of the trench to shield the high electric field strength at the bottom corner and improve short-circuit withstand capability, but this also sacrifices conduction performance. Therefore, effectively addressing reliability issues such as gate oxide quality and short-circuit withstand capability while improving the superior performance of SiC MOSFET devices has become a key research focus and challenge. Summary of the Invention

[0008] In view of the shortcomings of the prior art, the present invention provides a silicon carbide MOSFET. The technical problem to be solved is that the existing silicon carbide MOSFETs cannot guarantee the gate oxide reliability and short-circuit reliability of the device while providing excellent device performance.

[0009] To solve the above technical problems, the present invention provides the following technical solution: a silicon carbide MOSFET, comprising an N-type substrate, wherein an N-type epitaxial layer is disposed on the N-type substrate; a trench is formed inward on the top surface of the N-type epitaxial layer; a gate oxide layer is deposited on the inner wall of the trench; and a polysilicon gate is deposited on the inner wall of the gate oxide layer. A first P-body region is provided on the N-type epitaxial layer below the trench; a first N+ source region is provided inward on the top surface of the first P-body region; On both sides of the trench, a second N+ source region and a second P-body region are respectively provided inward on the top surface of the N-type epitaxial layer; the bottom surface of the second P-body region on one side of the trench is connected to the first P-body region through the P-type region; the second N+ source region on one side of the trench is connected to the first N+ source region through the third N+ source region. On the N-type epitaxial layer, the P-type region, the second N+ source region, and the second P-body region on one side of the trench are connected through the first P+ source region; On the N-type epitaxial layer, the second N+ source region and the second P-body region on the other side of the trench are connected through the second P+ source region; An oxide layer is provided on the top surface of the N-type epitaxial layer, and the oxide layer is located above the polysilicon gate and the two second N+ source regions. The N-type epitaxial layer is further provided with a source metal, which covers the oxide layer, the second N+ source region, the first P+ source region and the second P+ source region. The bottom surface of the N-type substrate is provided with drain metal.

[0010] In one embodiment, the first P+ source region is located on the side of the second P body region away from the trench; the second P+ source region is located on the side of the second P body region away from the trench.

[0011] In one embodiment, along the length of the trench, a third P-body region and a fourth N+ source region are sequentially provided on one side of the trench from bottom to top on the N-type epitaxial layer. The oxide layer is located on the fourth N+ source region; the source metal covers the fourth N+ source region.

[0012] In one embodiment, two first P-body regions are spaced apart below the trench, and a first N+ source region is respectively provided inward on the top surface of each first P-body region; The bottom surface of the second P-body region on one side of the trench is connected to the corresponding first P-body region below it through a P-shaped region; the second N+ source region on one side of the trench is connected to the corresponding first N+ source region below it through a third N+ source region.

[0013] In one embodiment, two first P-body regions and two first N+ source regions are symmetrically arranged on the N-type epitaxial layer.

[0014] In one embodiment, the bottom surface of the second P-body region on the other side of the trench is connected to the corresponding lower first P-body region through another P-type region; the second P+ source region is connected to the other P-type region.

[0015] In one embodiment, two first P-body regions are provided below the trench, and the opposing sides of the two first P-body regions are partially connected through an intermediate P-body region. Each first P-body region has a first N+ source region on its top surface facing inwards, and the opposing sides of the two first N+ source regions are locally connected through the intermediate N+ source region.

[0016] In one embodiment, two first P-body regions, two first N+ source regions, an intermediate P-body region, and an intermediate N+ source region are symmetrically arranged on the N-type epitaxial layer.

[0017] In one embodiment, the two first P-body regions are L-shaped, including a first region parallel to the trench and a second region perpendicular to the trench, and the distance between the outer surfaces of the first regions of the two first P-body regions is greater than the width of the trench.

[0018] In one embodiment, the first P-body region and the second P-body region are simultaneously implanted with ions to form the first N+ source region and the second N+ source region are simultaneously implanted with ions to form the first N+ source region.

[0019] The beneficial effects of this invention compared to the prior art are: Firstly, the first N+ source region and the first P body region of the silicon carbide MOSFET of the present invention form an annular channel around the perimeter. The device simultaneously has a longitudinal channel on the sidewall of the trench and an annular transverse channel at the bottom of the trench. By increasing the channel density, the on-current density of the device can be greatly improved and the on-resistance of the device can be reduced. Secondly, the device of the present invention selectively shorts the second P-body region at the top of the N-type epitaxial layer and the first P-body region and the first N+ source region at the bottom of the trench on the Z-axis in the three-dimensional direction. This can simplify the device fabrication process and reduce production costs. It can also convert the gate-drain capacitance at the bottom of the device trench into a drain-source capacitance, reduce the Miller capacitance of the device, improve the switching speed of the device, and reduce the switching loss of the device. In addition, the device of the present invention can optimize the avalanche current path and improve the device's avalanche resistance. Finally, the first P-body region, which is shorted to the source metal at the bottom of the trench, can effectively suppress the high electric field intensity at the trench corners and bottom, thereby improving the long-term reliability of the device gate oxide. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the first 3D structure of the silicon carbide MOSFET device in Example 1; Figure 2 This is a schematic diagram of the second 3D structure of the silicon carbide MOSFET device in Example 1; Figure 3 This is a schematic diagram of the first 3D structure of the silicon carbide MOSFET device in Example 2; Figure 4 This is a schematic diagram of the second 3D structure of the silicon carbide MOSFET device in Example 2; Figure 5 This is a schematic diagram of the first 3D structure of the silicon carbide MOSFET device in Example 3; Figure 6 This is a schematic diagram of the second 3D structure of the silicon carbide MOSFET device in Example 3; Figure 7 This is a schematic diagram of the first 3D structure of the silicon carbide MOSFET device in Example 4; Figure 8 This is a schematic diagram of the second 3D structure of the silicon carbide MOSFET device in Example 4; Figure 9 This is a schematic diagram of the first 3D structure of the silicon carbide MOSFET device in Example 5; Figure 10 This is a schematic diagram of the second 3D structure of the silicon carbide MOSFET device in Example 5; Figure 11 This is a schematic diagram of the first 3D structure of the silicon carbide MOSFET device in Example 6; Figure 12 This is a schematic diagram of the second 3D structure of the silicon carbide MOSFET device in Example 6. Detailed Implementation

[0021] The illustrative embodiments of this application include, but are not limited to, a silicon carbide MOSFET.

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Words such as “comprising” or “including” mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. Words such as “connected” or “linked” are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0024] Example 1 like Figure 1-2 As shown, this embodiment provides a silicon carbide MOSFET, including an N-type substrate 1, an N-type epitaxial layer 2 on the N-type substrate 1; a trench is formed inward on the top surface of the N-type epitaxial layer 2; a gate oxide layer 3 is deposited on the inner wall of the trench; a polysilicon gate 4 is deposited on the inner wall of the gate oxide layer 3; it should be noted that, although attached Figure 1 and 2 The trenches are not labeled, but those skilled in the art can know their location based on the position of the gate oxide layer 3. A first P-body region 5 is provided below the trench on the N-type epitaxial layer 2; a first N+ source region 6 is provided inward on the top surface of the first P-body region 5; On both sides of the trench width direction, the top surface of the N-type epitaxial layer 2 is provided with a second N+ source region 7 and a second P-body region 8 respectively; the bottom surface of the second P-body region 8 on one side of the trench is connected to the first P-body region 5 through the P-type region 9; the second N+ source region 7 on one side of the trench is connected to the first N+ source region 6 through the third N+ source region 10. On the N-type epitaxial layer 2, the P-type region 9 and the second P-body region 8 on one side of the trench are connected through the first P+ source region 11. On the N-type epitaxial layer 2, the second P-body region 8 on the other side of the trench is connected to the second P+ source region 12; An oxide layer 13 is provided on the top surface of the N-type epitaxial layer 2, and the oxide layer 13 is located above the polysilicon gate 4 and the two second N+ source regions 7. The N-type epitaxial layer 2 is further provided with a source metal 14, which covers the oxide layer 13, the second N+ source region 7, the first P+ source region 11 and the second P+ source region 12. The bottom surface of the N-type substrate 1 is provided with drain metal 15.

[0025] Specifically, in this embodiment, the first P-body region 5 and the second P-body region 8 can be formed by simultaneous ion implantation; the first N+ source region 6 and the second N+ source region 7 can be formed by simultaneous ion implantation.

[0026] Additionally, it should be noted that, for the sake of displaying the internal structure of the device, Figure 1 and Figure 2 This is equivalent to showing two MOSFET structures.

[0027] In actual implementation, when multiple MOSFET structures are provided on the N-type epitaxial layer 2, the P-type regions 9 can be alternately arranged on the N-type epitaxial layer 2, that is, they can be staggered on both sides of the trench.

[0028] Specifically, in this embodiment, the polysilicon gate 4 can be a strip cell structure.

[0029] Specifically, in this embodiment, the first P+ source region 11 is located on the side of the second P body region 8 away from the trench; the second P+ source region 12 is located on the side of the second P body region 8 away from the trench.

[0030] for Figure 1 and Figure 2 The silicon carbide MOSFET structure shown has the following beneficial effects: Firstly, in this embodiment, the first N+ source region 6 and the first P body region 5 of the silicon carbide MOSFET form a ring-shaped channel around the perimeter, that is, a ring-shaped transverse channel is integrated below the trench gate. The device simultaneously has a longitudinal channel on the trench sidewall and a ring-shaped transverse channel at the bottom of the trench. By increasing the channel density, the device's on-current density can be greatly improved, the device's on-resistance can be reduced, and the device performance can be optimized.

[0031] Secondly, by selectively shorting the second P-body region 8 at the top of the N-type epitaxial layer 2 and the first P-body region 5 and the first N+ source region 6 at the bottom of the trench on the Z-axis of the three-dimensional direction of the device, it is possible to simplify the complexity of the device fabrication process and reduce production costs. Secondly, it is possible to convert the gate-drain capacitance at the bottom of the device trench into a drain-source capacitance, reduce the device Miller capacitance, improve the device switching speed, and reduce the device switching loss. Additionally, the avalanche current path of the device can be optimized to improve the device's avalanche resistance. Finally, the first P-body region 5, which is shorted to the source metal 14 at the bottom of the trench, can effectively suppress the high electric field intensity at the trench corners and bottom, and improve the long-term reliability of the device gate oxide.

[0032] Example 2 Based on the structure of Embodiment 1, in order to further increase the device communication density, such as Figure 3 and 4 As shown, this embodiment provides a second type of silicon carbide MOSFET, including an N-type substrate 1, an N-type epitaxial layer 2 on the N-type substrate 1; a trench is formed inward on the top surface of the N-type epitaxial layer 2; a gate oxide layer 3 is deposited on the inner wall of the trench; a polysilicon gate 4 is deposited on the inner wall of the gate oxide layer 3; it should be noted that, although attached Figure 1 and 2 The trenches are not labeled, but those skilled in the art can know their location based on the position of the gate oxide layer 3. A first P-body region 5 is provided below the trench on the N-type epitaxial layer 2; a first N+ source region 6 is provided inward on the top surface of the first P-body region 5; On both sides of the trench width direction, the top surface of the N-type epitaxial layer 2 is provided with a second N+ source region 7 and a second P-body region 8 respectively; the bottom surface of the second P-body region 8 on one side of the trench is connected to the first P-body region 5 through the P-type region 9; the second N+ source region 7 on one side of the trench is connected to the first N+ source region 6 through the third N+ source region 10. Along the length of the trench, the N-type epitaxial layer 2 has a third P-body region 17 and a fourth N+ source region 16 arranged sequentially from bottom to top on one side of the trench; On the N-type epitaxial layer 2, the P-type region 9 and the second P-body region 8 on one side of the trench are connected through the first P+ source region 11. On the N-type epitaxial layer 2, the second P-body region 8 on the other side of the trench is connected to the second P+ source region 12; An oxide layer 13 is provided on the top surface of the N-type epitaxial layer 2. The oxide layer 13 is located above the polysilicon gate 4, the two second N+ source regions 7 and the fourth N+ source region 16. The N-type epitaxial layer 2 is further provided with a source metal 14, which covers the oxide layer 13, the second N+ source region 7, the first P+ source region 11, the second P+ source region 12 and the fourth N+ source region 16. The bottom surface of the N-type substrate 1 is provided with drain metal 15.

[0033] Specifically, in this embodiment, the first P-body region 5 and the second P-body region 8 can be formed by simultaneous ion implantation; the first N+ source region 6 and the second N+ source region 7 can be formed by simultaneous ion implantation.

[0034] Additionally, it should be noted that, for the sake of displaying the internal structure of the device, Figure 1 and Figure 2 This is equivalent to showing two MOSFET structures.

[0035] In actual implementation, when multiple MOSFET structures are provided on the N-type epitaxial layer 2, the P-type regions 9 can be alternately arranged on the N-type epitaxial layer 2, that is, they can be staggered on both sides of the trench.

[0036] Specifically, in this embodiment, the polysilicon gate 4 has a square cell structure.

[0037] Specifically, in this embodiment, the first P+ source region 11 is located on the side of the second P body region 8 away from the trench; the second P+ source region 12 is located on the side of the second P body region 8 away from the trench.

[0038] Specifically, in this embodiment, the third P-body region 17 and the second P-body region 8 can be formed simultaneously. The third P-body region 17 is connected to the second P-body regions 8 on both sides of the trench and is arranged around the trench. The fourth N+ source region 16 and the second N+ source region 7 can be formed simultaneously. The fourth N+ source region 16 is adjacent to the second N+ source regions 16 on both sides of the trench and is arranged around the trench.

[0039] for Figure 3 and Figure 4 The silicon carbide MOSFET structure shown has the following beneficial effects: Firstly, in this embodiment, the first N+ source region 6 and the first P body region 5 of the silicon carbide MOSFET form a ring-shaped channel around the perimeter, that is, a ring-shaped transverse channel is integrated below the trench gate. The device simultaneously has a longitudinal channel on the trench sidewall and a ring-shaped transverse channel at the bottom of the trench. By increasing the channel density, the device's on-current density can be greatly improved, the device's on-resistance can be reduced, and the device performance can be optimized.

[0040] Secondly, by selectively shorting the second P-body region 8 at the top of the N-type epitaxial layer 2 and the first P-body region 5 and the first N+ source region 6 at the bottom of the trench on the Z-axis of the three-dimensional direction of the device, it is possible to simplify the complexity of the device fabrication process and reduce production costs. Secondly, it is possible to convert the gate-drain capacitance at the bottom of the device trench into a drain-source capacitance, reduce the device Miller capacitance, improve the device switching speed, and reduce the device switching loss. In addition, the avalanche current path of the device can be optimized to improve the device's avalanche resistance; the first P-body region 5, which is shorted to the source metal 14 at the bottom of the trench, can effectively suppress the high electric field intensity at the trench corners and bottom, and improve the long-term reliability of the device's gate oxide. Finally, by setting the polysilicon gate 4 of the strip cell to a square cell structure, the density of longitudinal channels on the trench sidewalls was further increased, and the on-resistance of the device was reduced.

[0041] Example 3 Based on the structure of Example 2, in order to further increase the device communication density, such as Figure 5 and 6 As shown, this embodiment provides a third type of silicon carbide MOSFET, including an N-type substrate 1, an N-type epitaxial layer 2 on the N-type substrate 1; a trench is formed inward on the top surface of the N-type epitaxial layer 2; a gate oxide layer 3 is deposited on the inner wall of the trench; a polysilicon gate 4 is deposited on the inner wall of the gate oxide layer 3; it should be noted that, although attached Figure 1 and 2 The trenches are not labeled, but those skilled in the art can know their location based on the position of the gate oxide layer 3. Two first P-body regions 5 are spaced apart below the trench on the N-type epitaxial layer 2; a first N+ source region 6 is provided inward on the top surface of each first P-body region 5; the two first N+ source regions 6 and the two first body regions 5 form two separate annular channels. On both sides of the trench width direction, the top surface of the N-type epitaxial layer 2 is provided with a second N+ source region 7 and a second P-body region 8 respectively; the bottom surface of the second P-body region 8 on one side of the trench is connected to the first P-body region 5 through a P-type region 9; the bottom surface of the second P-body region 8 on the other side of the trench is connected to the corresponding first P-body region 5 below through another P-type region 9. Along the length of the trench, the N-type epitaxial layer 2 has a third P-body region 17 and a fourth N+ source region 16 arranged sequentially from bottom to top on one side of the trench; The second N+ source region 7 on one side of the trench is connected to the first N+ source region 6 through the third N+ source region 10; On the N-type epitaxial layer 2, the P-type region 9 and the second P-body region 8 on one side of the trench are connected through the first P+ source region 11. On the N-type epitaxial layer 2, the second P-body region 8 on the other side of the trench is connected to the second P+ source region 12; the second P+ source region 12 is connected to another P-type region 9; An oxide layer 13 is provided on the top surface of the N-type epitaxial layer 2. The oxide layer 13 is located above the polysilicon gate 4, the two second N+ source regions 7 and the fourth N+ source region 16. The N-type epitaxial layer 2 is further provided with a source metal 14, which covers the oxide layer 13, the second N+ source region 7, the first P+ source region 11, the second P+ source region 12 and the fourth N+ source region 16. The bottom surface of the N-type substrate 1 is provided with drain metal 15.

[0042] Specifically, in this embodiment, the first P-body region 5 and the second P-body region 8 can be formed by simultaneous ion implantation; the first N+ source region 6 and the second N+ source region 7 can be formed by simultaneous ion implantation.

[0043] Additionally, it should be noted that, for the sake of displaying the internal structure of the device, Figure 1 and Figure 2 This is equivalent to showing two MOSFET structures.

[0044] Specifically, in this embodiment, the polysilicon gate 4 has a square cell structure.

[0045] Specifically, in this embodiment, the first P+ source region 11 is located on the side of the second P-body region 8 away from the trench; the second P+ source region 12 is located on the side of the second P-body region 8 away from the trench. The first P+ source region 11 and the second P+ source region 12 are symmetrically arranged on both sides of the trench. The two P-type regions 9 are symmetrically arranged on both sides of the trench.

[0046] for Figure 3 and Figure 4 The silicon carbide MOSFET structure shown has the following beneficial effects: Firstly, in this embodiment, the first N+ source region 6 and the first P-body region 5 of the silicon carbide MOSFET form a ring-shaped channel around the perimeter, i.e., a ring-shaped lateral channel is integrated below the trench gate. The device simultaneously possesses longitudinal channels on the trench sidewalls and a ring-shaped lateral channel at the bottom of the trench. By increasing the channel density, the device's on-current density can be greatly improved, the on-resistance can be reduced, and the device performance can be optimized. Furthermore, by selectively shorting the second P-body region 8 at the top of the N-type epitaxial layer 2 and the first P-body region 5 and the first N+ source region 6 at the bottom of the trench along the Z-axis in the three-dimensional direction of the device, firstly, the complexity of the device fabrication process can be simplified, and the production cost can be reduced; secondly, the gate-drain capacitance at the bottom of the device trench can be converted into a drain-source capacitance, reducing the device's Miller capacitance, improving the device's switching speed, and reducing the device's switching losses. Secondly, it can optimize the avalanche current path of the device and improve the device's avalanche resistance; the first P-body region 5, which is shorted to the source metal 14 at the bottom of the trench, can effectively suppress the high electric field intensity at the trench corner and bottom, and improve the long-term reliability of the device's gate oxide. In addition, by setting the polysilicon gate 4 of the bar cell to a square cell structure, the density of longitudinal channels on the trench sidewalls is further increased, and the on-resistance of the device is reduced. Finally, by integrating two separate annular lateral channels at the bottom of the trench, the density of the lateral channels at the bottom of the trench was further increased, and the on-resistance of the device was reduced.

[0047] Example 4 like Figure 7 and 8 As shown, this embodiment provides a fourth type of silicon carbide MOSFET, including an N-type substrate 1, an N-type epitaxial layer 2 on the N-type substrate 1; a trench is formed inward on the top surface of the N-type epitaxial layer 2; a gate oxide layer 3 is deposited on the inner wall of the trench; a polysilicon gate 4 is deposited on the inner wall of the gate oxide layer 3; it should be noted that, although attached Figure 1 and 2 The trenches are not labeled, but those skilled in the art can know their location based on the position of the gate oxide layer 3. Two first P-body regions 5 are provided below the trench on the N-type epitaxial layer 2; the opposing sides of the two first P-body regions 5 are partially connected through the intermediate P-body region 18. Each first P-body region 5 has a first N+ source region 6 facing inward on its top surface; the opposing sides of the two first N+ source regions 6 are partially connected through the intermediate N+ source region 19; the two first P-body regions 5 and the two first N+ source regions 6 form two partially connected annular channels; On both sides of the trench width direction, the top surface of the N-type epitaxial layer 2 is provided with a second N+ source region 7 and a second P-body region 8 respectively; the bottom surface of the second P-body region 8 on one side of the trench is connected to the first P-body region 5 through the P-type region 9; the second N+ source region 7 on one side of the trench is connected to the first N+ source region 6 through the third N+ source region 10. Along the length of the trench, the N-type epitaxial layer 2 has a third P-body region 17 and a fourth N+ source region 16 arranged sequentially from bottom to top on one side of the trench. On the N-type epitaxial layer 2, the P-type region 9 and the second P-body region 8 on one side of the trench are connected through the first P+ source region 11. On the N-type epitaxial layer 2, the second P-body region 8 on the other side of the trench is connected to the second P+ source region 12; An oxide layer 13 is provided on the top surface of the N-type epitaxial layer 2. The oxide layer 13 is located above the polysilicon gate 4, the two second N+ source regions 7 and the fourth N+ source region 16. The N-type epitaxial layer 2 is further provided with a source metal 14, which covers the oxide layer 13, the second N+ source region 7, the first P+ source region 11, the second P+ source region 12 and the fourth N+ source region 16. The bottom surface of the N-type substrate 1 is provided with drain metal 15.

[0048] Specifically, in this embodiment, the first P-body region 5 and the second P-body region 8 can be formed by simultaneous ion implantation; the first N+ source region 6 and the second N+ source region 7 can be formed by simultaneous ion implantation.

[0049] Additionally, it should be noted that, for the sake of displaying the internal structure of the device, Figure 1 and Figure 2 This is equivalent to showing two MOSFET structures.

[0050] In actual implementation, when multiple MOSFET structures are provided on the N-type epitaxial layer 2, the P-type regions 9 can be alternately arranged on the N-type epitaxial layer 2, that is, they can be staggered on both sides of the trench.

[0051] Specifically, in this embodiment, the polysilicon gate 4 has a square cell structure.

[0052] Specifically, in this embodiment, the first P+ source region 11 is located on the side of the second P body region 8 away from the trench; the second P+ source region 12 is located on the side of the second P body region 8 away from the trench.

[0053] In practical use, the silicon carbide MOSFET in this embodiment has the beneficial effects of the silicon carbide MOSFET in embodiments one to three. In addition, the silicon carbide MOSFET in this embodiment further increases the longitudinal channel density on both sides of the ring gate trench by integrating two locally connected annular lateral channels at the bottom of the trench, without sacrificing the lateral channel density at the bottom of the trench, thereby reducing the on-resistance of the device.

[0054] Example 5 like Figure 9 and 10 As shown, this embodiment provides a fifth type of silicon carbide MOSFET, including an N-type substrate 1, an N-type epitaxial layer 2 on the N-type substrate 1; a trench is formed inward on the top surface of the N-type epitaxial layer 2; a gate oxide layer 3 is deposited on the inner wall of the trench; a polysilicon gate 4 is deposited on the inner wall of the gate oxide layer 3; it should be noted that, although attached Figure 1 and 2 The trenches are not labeled, but those skilled in the art can know their location based on the position of the gate oxide layer 3. Two first P-body regions 5 are spaced apart below the trench on the N-type epitaxial layer 2; a first N+ source region 6 is provided inward on the top surface of each first P-body region 5; the two first N+ source regions 6 and the two first body regions 5 form two separate annular channels. Furthermore, the two first P-body regions 5 are L-shaped, including a first region parallel to the trench and a second region perpendicular to the trench, and the distance between the outer surfaces of the first regions of the two first P-body regions 5 is greater than the width of the trench. On both sides of the trench width direction, the top surface of the N-type epitaxial layer 2 is provided with a second N+ source region 7 and a second P-body region 8 respectively; the bottom surface of the second P-body region 8 on one side of the trench is connected to the first P-body region 5 through a P-type region 9; the bottom surface of the second P-body region 8 on the other side of the trench is connected to the corresponding first P-body region 5 below through another P-type region 9. Along the length of the trench, the N-type epitaxial layer 2 has a third P-body region 17 and a fourth N+ source region 16 arranged sequentially from bottom to top on one side of the trench; The second N+ source region 7 on one side of the trench is connected to the first N+ source region 6 through the third N+ source region 10; On the N-type epitaxial layer 2, the P-type region 9 and the second P-body region 8 on one side of the trench are connected through the first P+ source region 11. On the N-type epitaxial layer 2, the second P-body region 8 on the other side of the trench is connected to the second P+ source region 12; the second P+ source region 12 is connected to another P-type region 9; An oxide layer 13 is provided on the top surface of the N-type epitaxial layer 2. The oxide layer 13 is located above the polysilicon gate 4, the two second N+ source regions 7 and the fourth N+ source region 16. The N-type epitaxial layer 2 is further provided with a source metal 14, which covers the oxide layer 13, the second N+ source region 7, the first P+ source region 11, the second P+ source region 12 and the fourth N+ source region 16. The bottom surface of the N-type substrate 1 is provided with drain metal 15.

[0055] Specifically, in this embodiment, the first P-body region 5 and the second P-body region 8 can be formed by simultaneous ion implantation; the first N+ source region 6 and the second N+ source region 7 can be formed by simultaneous ion implantation.

[0056] Additionally, it should be noted that, for the sake of displaying the internal structure of the device, Figure 1 and Figure 2 This is equivalent to showing two MOSFET structures.

[0057] Specifically, in this embodiment, the polysilicon gate 4 has a square cell structure.

[0058] Specifically, in this embodiment, the first P+ source region 11 is located on the side of the second P-body region 8 away from the trench; the second P+ source region 12 is located on the side of the second P-body region 8 away from the trench. The first P+ source region 11 and the second P+ source region 12 are symmetrically arranged on both sides of the trench. The two P-type regions 9 are symmetrically arranged on both sides of the trench. The two first P-body regions 5 and the two first N+ source regions 6 are symmetrically arranged about the trench.

[0059] Based on the above, the silicon carbide MOSFET proposed in this embodiment is a high-reliability annular trench device with integrated separated annular lateral channels. The trench gate has a cubic cell structure, and the bottom of the trench consists of two separate annular lateral channels. Furthermore, the outer sides of the first regions of the two first P-body regions 5 are wider than the bottom of the trench. This structure also possesses the advantages of embodiments one through four, as it further improves the device's thermal stability and short-circuit withstand capability by making the outer sides of the first regions of the two first P-body regions 5 wider than the bottom of the trench.

[0060] Example 6 like Figure 11 and 12 As shown, this embodiment provides a sixth type of silicon carbide MOSFET, including an N-type substrate 1, an N-type epitaxial layer 2 on the N-type substrate 1; a trench is formed inward on the top surface of the N-type epitaxial layer 2; a gate oxide layer 3 is deposited on the inner wall of the trench; a polysilicon gate 4 is deposited on the inner wall of the gate oxide layer 3; it should be noted that, although attached Figure 1 and 2 The trenches are not labeled, but those skilled in the art can know their location based on the position of the gate oxide layer 3. Two first P-body regions 5 are provided below the trench on the N-type epitaxial layer 2; the opposing sides of the two first P-body regions 5 are partially connected through the intermediate P-body region 18. Each first P-body region 5 has a first N+ source region 6 facing inward on its top surface; the opposing sides of the two first N+ source regions 6 are partially connected through the intermediate N+ source region 19; the two first P-body regions 5 and the two first N+ source regions 6 form two partially connected annular channels; The two first P-body regions 5 are L-shaped, including a first region parallel to the trench and a second region perpendicular to the trench. The distance between the outer surfaces of the first regions of the two first P-body regions 5 is greater than the width of the trench. On both sides of the trench width direction, the top surface of the N-type epitaxial layer 2 is provided with a second N+ source region 7 and a second P-body region 8 respectively; the bottom surface of the second P-body region 8 on one side of the trench is connected to the first P-body region 5 through the P-type region 9; the second N+ source region 7 on one side of the trench is connected to the first N+ source region 6 through the third N+ source region 10. Along the length of the trench, the N-type epitaxial layer 2 has a third P-body region 17 and a fourth N+ source region 16 arranged sequentially from bottom to top on one side of the trench. On the N-type epitaxial layer 2, the P-type region 9 and the second P-body region 8 on one side of the trench are connected through the first P+ source region 11. On the N-type epitaxial layer 2, the second P-body region 8 on the other side of the trench is connected to the second P+ source region 12; An oxide layer 13 is provided on the top surface of the N-type epitaxial layer 2. The oxide layer 13 is located above the polysilicon gate 4, the two second N+ source regions 7 and the fourth N+ source region 16. The N-type epitaxial layer 2 is further provided with a source metal 14, which covers the oxide layer 13, the second N+ source region 7, the first P+ source region 11, the second P+ source region 12 and the fourth N+ source region 16. The bottom surface of the N-type substrate 1 is provided with drain metal 15.

[0061] Specifically, in this embodiment, the first P-body region 5 and the second P-body region 8 can be formed by simultaneous ion implantation; the first N+ source region 6 and the second N+ source region 7 can be formed by simultaneous ion implantation.

[0062] Additionally, it should be noted that, for the sake of displaying the internal structure of the device, Figure 1 and Figure 2 This is equivalent to showing two MOSFET structures.

[0063] In actual implementation, when multiple MOSFET structures are provided on the N-type epitaxial layer 2, the P-type regions 9 can be alternately arranged on the N-type epitaxial layer 2, that is, they can be staggered on both sides of the trench.

[0064] Specifically, in this embodiment, the polysilicon gate 4 has a square cell structure.

[0065] Specifically, in this embodiment, the first P+ source region 11 is located on the side of the second P body region 8 away from the trench; the second P+ source region 12 is located on the side of the second P body region 8 away from the trench.

[0066] In practical use, the silicon carbide MOSFET in this embodiment has the advantages of implementation cases one to five. In addition, by integrating two locally connected annular lateral channels at the bottom of the trench, the longitudinal channel density on both sides of the trench is further increased without sacrificing the lateral channel density at the bottom of the trench, thereby reducing the on-resistance of the device.

[0067] Combining all the above embodiments, this invention innovatively proposes a high-reliability trench silicon carbide MOSFET device with an integrated annular lateral channel. The new MOSFET integrates an annular lateral channel at the bottom of the trench, and the trench gate is configured as a cubic cell structure to form an annular longitudinal channel surrounding the gate. The current paths of the annular lateral channel and the longitudinal channel are independent, preventing current congestion and eliminating the high-resistance region at the bottom of the trench when the device is turned on, thus greatly optimizing device performance. Furthermore, two short-circuit structures are designed on the Z-axis of the device's three-dimensional direction, shorting the second P-body region 8 at the top of the N-type epitaxial layer 2 and the first P-body region 5 and the first N+ source region 6 at the bottom of the trench. This simplifies the device fabrication process and reduces production costs. Compared to existing trench silicon carbide MOSFETs, the new structure can effectively improve the static and dynamic performance of the device in the first and third quadrants while simultaneously improving reliability issues such as gate oxide quality, thermal stability, avalanche capability, and short-circuit capability, overcoming the technical problem of existing technologies where high performance and high reliability are mutually exclusive.

[0068] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A silicon carbide MOSFET, characterized in that, The system includes an N-type substrate (1), on which an N-type epitaxial layer (2) is provided; a trench is formed inward on the top surface of the N-type epitaxial layer (2); a gate oxide layer (3) is deposited on the inner wall of the trench; and a polysilicon gate (4) is deposited on the inner wall of the gate oxide layer (3). The N-type epitaxial layer (2) has a first P-body region (5) below the trench; the top surface of the first P-body region (5) has a first N+ source region (6) inward; On both sides of the trench width direction, the top surface of the N-type epitaxial layer (2) is provided with a second N+ source region (7) and a second P-body region (8) respectively; the bottom surface of the second P-body region (8) on one side of the trench is connected to the first P-body region (5) through a P-type region (9); the second N+ source region (7) on one side of the trench is connected to the first N+ source region (6) through a third N+ source region (10); On the N-type epitaxial layer (2), the P-type region (9) on one side of the trench and the second P-body region (8) are connected through the first P+ source region (11); On the N-type epitaxial layer (2), the second P-body region (8) on the other side of the trench is connected to the second P+ source region (12); An oxide layer (13) is provided on the top surface of the N-type epitaxial layer (2), and the oxide layer (13) is located above the polysilicon gate (4) and the two second N+ source regions (7); The N-type epitaxial layer (2) is further provided with a source metal (14), which covers the oxide layer (13), the second N+ source region (7), the first P+ source region (11), and the second P+ source region (12). The bottom surface of the N-type substrate (1) is provided with drain metal (15).

2. A silicon carbide MOSFET according to claim 1, characterized in that, The first P+ source region (11) is located on the side of the second P body region (8) away from the trench; the second P+ source region (12) is located on the side of the second P body region (8) away from the trench.

3. A silicon carbide MOSFET according to claim 1 or 2, characterized in that, Along the length of the trench, the N-type epitaxial layer (2) is provided with a third P-body region (17) and a fourth N+ source region (16) sequentially from bottom to top on one side of the trench. The oxide layer (13) is located on the fourth N+ source region (16); the source metal (14) covers the fourth N+ source region (16).

4. A silicon carbide MOSFET according to claim 3, characterized in that, Two first P-body regions (5) are spaced apart below the trench, and a first N+ source region (6) is provided inward on the top surface of each first P-body region (5). The bottom surface of the second P-body region (8) on one side of the trench is connected to the corresponding lower first P-body region (5) through a P-shaped region (9); the bottom surface of the second P-body region (8) on the other side of the trench is connected to the corresponding lower first P-body region (5) through another P-shaped region (9); the second P+ source region (12) is connected to the other P-shaped region (9). The second N+ source region (7) on one side of the trench is connected to the corresponding first N+ source region (6) below through the third N+ source region (10).

5. A silicon carbide MOSFET according to claim 4, characterized in that, Two first P-body regions (5) and two first N+ source regions (6) are symmetrically arranged on the N-type epitaxial layer (2).

6. A silicon carbide MOSFET according to claim 5, characterized in that, The two first P-body regions (5) are L-shaped, including a first region parallel to the trench and a second region perpendicular to the trench. The distance between the outer surfaces of the first regions of the two first P-body regions (5) is greater than the width of the trench.

7. A silicon carbide MOSFET according to claim 1 or 2, characterized in that, Two first P-body regions (5) are provided below the trench, and the opposing sides of the two first P-body regions (5) are partially connected through the intermediate P-body region (18). Each first P body region (5) has a first N+ source region (6) on its top surface facing inwards, and the opposing sides of the two first N+ source regions (6) are locally connected through the intermediate N+ source region (19).

8. A silicon carbide MOSFET according to claim 7, characterized in that, Two first P-body regions (5), two first N+ source regions (6), an intermediate P-body region (18), and an intermediate N+ source region (19) are symmetrically arranged on the N-type epitaxial layer (2).

9. A silicon carbide MOSFET according to claim 8, characterized in that, The two first P-body regions (5) are L-shaped, including a first region parallel to the trench and a second region perpendicular to the trench. The distance between the outer surfaces of the first regions of the two first P-body regions (5) is greater than the width of the trench.

10. A silicon carbide MOSFET according to claim 1, characterized in that, The first P-body region (5) and the second P-body region (8) are simultaneously implanted with ions to form the first N+ source region (6) and the second N+ source region (7) are simultaneously implanted with ions to form the first N+ source region (6) and the second N+ source region (7).

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