Thin film transistor, shift register unit, gate driving circuit and display panel

Abstract

A thin film transistor, a shift register unit, a gate driving circuit and a display panel, the thin film transistor, each source unit comprising M source branches, the source branches and the drain branches extending along a first direction and being arranged at intervals in a second direction intersecting the first direction; one source unit and a corresponding drain unit constitute a source-drain unit, the thin film transistor comprising P source-drain units, M source branches and N drain branches in each source-drain unit being arranged alternately, M being greater than or equal to N; a semiconductor layer being electrically connected with the M source branches and the N drain branches, the semiconductor layer comprising a plurality of sub-channel regions between adjacent drain branches and source branches; the sum of the widths of the plurality of sub-channel regions of the P source-drain units in the first direction being W, the average length of the plurality of sub-channel regions of the P source-drain units in a direction perpendicular to the first direction being L; 12≤W / L≤400, P, M and N are all integers greater than or equal to 1, and P×N≥4.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202280002073.7 entitled "Thin Film Transistor, Shift Register Unit, Gate Drive Circuit and Display Panel", which entered the Chinese national phase on June 30, 2022. Chinese Patent Application No. 202280002073.7 is a patent application that entered the Chinese national phase of PCT Application No. PCT / CN2022 / 102945, filed on June 30, 2022. Technical Field

[0002] This disclosure provides at least one embodiment of a thin-film transistor, a shift register unit, a gate drive circuit, and a display panel. Background Technology

[0003] In the field of display technology, switching elements play a crucial role in high-definition display devices. For example, the conductivity of the switching element, the thin-film transistor (TFT), directly affects the degree to which the TFT is turned on, the degree of deflection of liquid crystal molecules, and thus the displayed image.

[0004] Currently, the main requirement is to increase the charging current of TFTs. Generally, this is achieved by increasing the aspect ratio of the TFT channel. For example, the charging current requirement is particularly high for the gate row drive circuit (GOA circuit) fabricated in the non-display area of ​​the array substrate. Furthermore, the size requirements for TFTs fabricated in the non-display area of ​​the array substrate are smaller compared to designs in pixels. Therefore, TFTs with larger areas and higher charging currents have been designed.

[0005] The materials of TFT semiconductor layers mainly include amorphous silicon (a-Si) or oxides (such as IGZO, i.e., Indium Gallium Zinc Oxide). With the increasing demand for high PPI (Pixels Per Inch), high refresh rates, and narrow bezel products, traditional a-Si thin film transistor products can no longer meet the performance requirements of devices. Oxide technology, as the most likely new technology to replace a-Si thin film transistor products, has become the focus of current research. Summary of the Invention

[0006] At least one embodiment of this disclosure provides a thin-film transistor, which includes a source, a drain, a gate, and a semiconductor layer. The source includes a source trace and P source cells electrically connected to the source trace. Each of the P source cells includes M source branches, each of the M source branches extending along a first direction and spaced apart in a second direction intersecting the first direction. The drain includes a drain trace and P drain cells electrically connected to the drain trace and corresponding one-to-one with the P source cells. Each of the P drain cells includes N drain branches, each of the N drain branches extending along a first direction and spaced apart in a second direction; the thin-film transistor includes P source-drain cells, one source cell and one corresponding drain cell forming a source-drain cell; within each of the P source-drain cells, M source branches and N drain branches are alternately arranged, spaced apart from each other and insulated, M is greater than or equal to N; the gate is insulated from the source and drain; a semiconductor layer is electrically connected to the M source branches and N drain branches of each source-drain cell; the semiconductor layer includes multiple sub-channel regions located in each of the P source-drain cells, each of the multiple sub-channel regions located between adjacent drain branches and source branches; the sum of the widths of the multiple sub-channel regions of the P source-drain cells in the first direction is W, and the average length of the multiple sub-channel regions of the P source-drain cells in the direction perpendicular to the first direction is L; 12≤W / L≤400, P, M and N are all integers greater than or equal to 1, P×N≥4.

[0007] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, 112 ≤ W / L ≤ 400, and P×N ≥ 6.

[0008] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, P ≥ 3 and N ≥ 2.

[0009] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, P×N≥ 12.

[0010] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, P×N ≥ 16.

[0011] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, 235 ≤ W / L ≤ 400, P×N ≥ 32.

[0012] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, W / L < 180, and W ranges from 10 μm to 1600 μm.

[0013] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, W / L > 180, and L ranges from 4 μm to 15 μm.

[0014] For example, in a thin-film transistor provided in at least one embodiment of this disclosure, the plurality of source and drain cells are arranged in at least one cell row, and each cell row in the at least one cell row includes at least one source and drain cell; in the same cell row, the distance between adjacent source and drain cells is d, W≥500μm, and the range of d is 50μm~500μm.

[0015] For example, in a thin-film transistor provided in at least one embodiment of this disclosure, the plurality of source and drain cells are arranged in at least one cell row, and each cell row in the at least one cell row includes at least one source and drain cell; in the same cell row, the distance between adjacent source and drain cells is d, W < 500 μm, and the range of d is 20 μm to 300 μm.

[0016] For example, in a thin-film transistor provided in at least one embodiment of this disclosure, the plurality of source-drain cells are arranged in at least two cell rows, and each cell row in the at least one cell row includes at least one source-drain cell.

[0017] For example, in a thin-film transistor provided in at least one embodiment of this disclosure, the semiconductor layer includes a sub-region overlapping with each of the plurality of source / drain cells, the sub-region including Q semiconductor branches, the plurality of sub-channel regions including sub-channel cells of the Q semiconductor branches located between adjacent source and drain branches, where Q is an integer greater than or equal to 1; W is the sum of the widths of the sub-channel cells of the Q semiconductor branches of the P source / drain cells in the first direction, and L is the average length of the plurality of sub-channel cells of the P source / drain cells in a direction perpendicular to the first direction.

[0018] For example, in a thin-film transistor provided in at least one embodiment of this disclosure, the semiconductor layer includes a sub-section overlapping with each of the plurality of source / drain units, and the plurality of sub-sections overlapping with the source / drain units constitute a continuous integrated structure.

[0019] For example, in a thin-film transistor provided in at least one embodiment of this disclosure, the plurality of source-drain cells are disposed in the region between adjacent source lines and drain lines to arrange the plurality of source-drain cells into at least two cell rows, each of the at least two cell rows including at least one source-drain cell; the source branches of the at least one source-drain cell in each cell row are electrically connected to the same source line, and the drain branches of the at least one source-drain cell in each cell row are electrically connected to the same drain line.

[0020] At least one embodiment of this disclosure also provides a shift register unit, which includes any of the thin-film transistors provided in this disclosure.

[0021] For example, in at least one embodiment of the shift register unit provided in this disclosure, the gate row driving circuit includes an input circuit, an output circuit, and a first node reset circuit; the input circuit is connected to the first node and configured to charge the first node in response to an input signal; the output circuit is connected to the first node and configured to output an output signal at an output terminal under the control of a level signal of the first node; the first node reset circuit is connected to the first node and configured to reset the first node in response to a reset signal; the output circuit, the input circuit, and the first node reset circuit all include any thin-film transistor provided in the embodiments of this disclosure.

[0022] For example, in at least one embodiment of the shift register unit provided in this disclosure, the output terminal includes a shift output terminal and a scan signal output terminal; the output circuit includes a first output transistor and a second output transistor; the gate of the first output transistor is connected to the first node, the first electrode of the first output transistor is connected to a clock signal terminal to receive a clock signal, and the second electrode of the first output transistor is connected to the shift output terminal; the gate of the second output transistor is connected to the first node, the first electrode of the second output transistor is connected to the clock signal terminal to receive the clock signal, and the second electrode of the second output transistor is connected to the scan signal output terminal; the clock signal is transmitted to the output terminal as the output signal; the first output transistor and the second output transistor are both any thin-film transistors provided in the embodiments of this disclosure; the first output transistor and the second output transistor both satisfy P ≥ 3 and N ≥ 2, or, the first output transistor and the second output transistor both satisfy P × N ≥ 12, or, the first output transistor and the second output transistor both satisfy P × N ≥ 16.

[0023] For example, in the shift register unit provided in at least one embodiment of this disclosure, the first output transistor satisfies 235 ≤ W / L ≤ 400 and P×N ≥ 32.

[0024] At least one embodiment of this disclosure also provides a gate driving circuit, which includes any of the shift register units provided in the embodiments of this disclosure. The gate driving circuit includes multiple cascaded shift register units; except for the first to s-th level shift register units, the precharge control terminal of each of the remaining shift register units is connected to the output terminal of the upper-level shift register unit at least s levels away; except for the first to s-th level shift register units, the input terminal of each of the remaining shift register units is connected to the output terminal of the upper-level shift register unit at s-1 levels away; except for the last s-th level shift register unit, the reset terminal of each of the remaining shift register units is connected to the output terminal of the lower-level shift register unit at s-1 levels away; wherein s is an integer greater than 2.

[0025] At least one embodiment of this disclosure also provides a display panel, including any of the gate driving circuits provided in the embodiments of this disclosure.

[0026] For example, in a display panel provided in at least one embodiment of this disclosure, the display panel includes a display area and a non-display area at least partially surrounding the display area; the non-display area includes a gate driving circuit area and a circuit lead area. The gate driving circuit area extends longitudinally and is provided with the gate driving circuit, wherein the plurality of cascaded shift register units are arranged along the longitudinal direction; the circuit lead area is provided with circuit leads extending laterally intersecting the longitudinal direction and adjacent to the gate driving circuit area, the circuit leads including a first lead connected to the gate driving circuit and a second lead connected to the display area; the plurality of cascaded shift register units include an end shift register unit located at one end of the circuit area near the circuit lead area; in each shift register, the output terminal includes a shift output terminal and a scan signal output terminal; the output circuit includes a first output transistor and a second output transistor; the gate of the first output transistor is connected to the first node, and the first electrode of the first output transistor is connected to a clock signal terminal to receive a clock signal. The second terminal of the first output transistor is connected to the shift output terminal; the gate of the second output transistor is connected to the first node, the first terminal of the second output transistor is connected to the clock signal terminal to receive the clock signal, and the second terminal of the second output transistor is connected to the scan signal output terminal; the clock signal is transmitted to the output terminal as the output signal; the first output transistor and the second output transistor are both any thin-film transistors provided in the embodiments of this disclosure; the P×N value of the first output transistor in the end shift register unit and the P×N value of the second output transistor in the end shift register unit are respectively greater than the P×N values ​​of the first output transistors in other shift register units in the plurality of cascaded shift register units and the P×N value of the second output transistor in the end shift register unit. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1 This is a schematic diagram of the structure of a thin-film transistor provided in at least one embodiment of the present disclosure;

[0029] Figure 2 yes Figure 1 A partially enlarged schematic diagram of a source / drain cell of a thin-film transistor shown;

[0030] Figure 3A This is a schematic diagram of the structure of two transistors in a shift register unit provided in at least one embodiment of the present disclosure;

[0031] Figure 3B This is a schematic diagram of the structure of two transistors in another shift register unit provided in at least one embodiment of the present disclosure;

[0032] Figure 4A This is the relationship between the total width W of the channel region of the thin-film transistor provided in at least one embodiment of the present disclosure and the threshold voltage drift Δth of the thin-film transistor;

[0033] Figure 4B This is the relationship between the average length L of the sub-channel region of the thin-film transistor provided in at least one embodiment of the present disclosure and the threshold voltage drift Δth of the thin-film transistor;

[0034] Figure 4C This is the relationship between the ratio of the total width W of the channel region to the average length L of the sub-channel region of the thin-film transistor provided in at least one embodiment of the present disclosure, W / L, and the threshold voltage drift Δth of the thin-film transistor.

[0035] Figure 5A This is the relationship between the number of source / drain branches of a source / drain cell of a thin-film transistor provided in at least one embodiment of the present disclosure and the threshold voltage drift Δth of the thin-film transistor;

[0036] Figure 5B This is the relationship between the number of source / drain cells of the thin-film transistor provided in at least one embodiment of the present disclosure and the threshold voltage drift Δth of the thin-film transistor;

[0037] Figure 5C This describes the relationship between the distance between adjacent source and drain cells of a thin-film transistor provided in at least one embodiment of the present disclosure and the threshold voltage drift Δth of the thin-film transistor.

[0038] Figure 6A This is a schematic diagram of the structure of another thin-film transistor provided in at least one embodiment of the present disclosure;

[0039] Figure 6B This is a schematic diagram of the structure of another thin-film transistor provided in at least one embodiment of the present disclosure;

[0040] Figure 7 This is an exemplary circuit diagram of a shift register unit provided in at least one embodiment of the present disclosure;

[0041] Figure 8 This is an exemplary circuit diagram of another shift register unit provided in at least one embodiment of the present disclosure;

[0042] Figure 9 This is a schematic diagram of a display panel provided in at least one embodiment of the present disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The embodiments described below are some, but not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0045] In related technologies, GOA (Gate Driver on Array) technology refers to integrating the gate driver onto the array substrate to form a scanning driver for the panel. Compared to traditional chip-on-flex / film (COF) and chip-on-glass (COG) processes, the main feature of GOA technology is that it relies on the continuous triggering of the GOA driving unit integrated on the array substrate to achieve its shift register function. This replaces the bonding area and fan-out wiring space of the original gate driver IC, allowing for a symmetrical and aesthetically pleasing panel design on both sides, enabling a narrow bezel design, reducing costs, and also improving production capacity and yield.

[0046] In GOA circuits, the materials of the TFT semiconductor layer mainly include amorphous silicon (a-Si) or oxides (such as IGZO, i.e., Indium Gallium Zinc Oxide). With the increasing demand for high PPI (Pixels Per Inch), high refresh rates, and narrow bezel products, traditional a-Si thin film transistor products can no longer meet the performance requirements of devices. Oxide technology, as the most likely new technology to replace aSi thin film transistor products, has become the focus of research for various display manufacturers.

[0047] Typically, a GOA circuit includes multiple thin-film transistors, each of which includes multiple source branches, multiple drain branches, multiple semiconductor branches, source traces, and drain traces. Multiple source branches are connected to source traces, multiple drain branches are connected to drain traces, and the multiple source branches and multiple drain branches are divided into multiple units (TFT units).

[0048] Since the current magnitude on the source and drain branches is closely related to the amount of heat generated, increasing the number of branches to reduce the current on each branch, and thus the heat generated on each branch, is the most direct and effective way to solve the heat generation problem in GOA circuits. However, this method is suitable for amorphous silicon thin-film transistors (a-Si TFTs) with low mobility. For large-size oxide thin-film transistors (Oxide TFTs), the high ion mobility of Oxide TFTs makes them prone to heat generation, and the heat generation problem is more serious. The main reasons are: first, the excessive number of source and drain branches, arranged in a highly concentrated manner, easily leads to heat accumulation, which cannot be dissipated; second, the contact points between the oxide semiconductor layer and the source and drain branches experience the most severe heat generation. At the same time, since the contact parts between the source and drain branches and the semiconductor layer are all on the current-converging wires, the current-converging wires are also prone to high heat generation, further aggravating the heat accumulation. The accumulated heat reduces the reliability of the display panel. Furthermore, an excessively wide channel region or an inappropriate number of source and drain branches can increase the threshold voltage offset of the thin-film transistor, affecting the stability of its performance and the reliability of its operation.

[0049] Currently, conventional oxide transistors, such as IGZO TFTs, have a mobility of less than 10. However, for products with higher resolution and higher refresh rates, high mobility oxides have significant issues with unstable device characteristics. In particular, a large aspect ratio leads to a significant increase in on-state current (Ion), resulting in prominent device heat generation and increased drift of the threshold voltage. Ultimately, this leads to poor reliability of display devices and affects the display performance of GOA display panels.

[0050] At least one embodiment of this disclosure provides a thin-film transistor, which includes a source, a drain, a gate, and a semiconductor layer. The source includes a source trace and P source cells electrically connected to the source trace. Each of the P source cells includes M source branches, each of the M source branches extending along a first direction and spaced apart in a second direction intersecting the first direction. The drain includes a drain trace and P drain cells electrically connected to the drain trace and corresponding one-to-one with the P source cells. Each of the P drain cells includes N drain branches, each of the N drain branches extending along a first direction and spaced apart in a second direction; the thin-film transistor includes P source-drain cells, one source cell and one corresponding drain cell forming a source-drain cell; within each of the P source-drain cells, M source branches and N drain branches are alternately arranged, spaced apart from each other and insulated, M is greater than or equal to N; the gate is insulated from the source and drain; a semiconductor layer is electrically connected to the M source branches and N drain branches of each source-drain cell; the semiconductor layer includes multiple sub-channel regions located in each of the P source-drain cells, each of the multiple sub-channel regions located between adjacent drain branches and source branches; the sum of the widths of the multiple sub-channel regions of the P source-drain cells in the first direction is W, and the average length of the multiple sub-channel regions of the P source-drain cells in the direction perpendicular to the first direction is L; 12≤W / L≤400, P, M and N are all integers greater than or equal to 1, P×N≥4.

[0051] At least one embodiment of this disclosure also provides a shift register unit, which includes any of the thin-film transistors provided in this disclosure.

[0052] At least one embodiment of this disclosure also provides a gate driving circuit, which includes any of the shift register units provided in the embodiments of this disclosure. The gate driving circuit includes multiple cascaded shift register units; except for the first to s-th level shift register units, the precharge control terminal of each of the remaining shift register units is connected to the output terminal of the upper-level shift register unit at least s levels away; except for the first to s-th level shift register units, the input terminal of each of the remaining shift register units is connected to the output terminal of the upper-level shift register unit at s-1 levels away; except for the last s-th level shift register unit, the reset terminal of each of the remaining shift register units is connected to the output terminal of the lower-level shift register unit at s-1 levels away; wherein s is an integer greater than 2.

[0053] At least one embodiment of this disclosure also provides a display panel, including any of the gate driving circuits provided in the embodiments of this disclosure.

[0054] For example, Figure 1 This is a schematic diagram of the structure of a thin-film transistor provided in at least one embodiment of this disclosure. For example... Figure 1As shown, the thin-film transistor includes: a source 100, a drain 200, a gate 300, and a semiconductor layer 400. The source 100 includes a source trace 110 and P source cells electrically connected to the source trace 110. Each of the P source cells includes N source branches 120, each of the N source branches 120 extending along a first direction D1 and spaced apart along a second direction D2 intersecting the first direction D1. The drain 200 includes a drain trace 210 and P drain cells electrically connected to the drain trace 210 and corresponding one-to-one with the P source cells. Each of the P drain cells includes M drain branches 220, each of the M drain branches 220 extending along the first direction D1 and spaced apart along the second direction D2. The thin-film transistor includes P source-drain cells 10, where one source cell and one corresponding drain cell constitute one source-drain cell 10. Within each of the P source-drain cells 10, N source cells... Branch 120 is alternately arranged with M drain branches 220, spaced apart from each other and insulated from each other, where M is greater than or equal to N; gate 300 is insulated from source 100 and drain 200; semiconductor layer 400 is electrically connected to N source branches 120 and M drain branches 220 of each source-drain unit 10, semiconductor layer 400 includes a plurality of sub-channel regions 40 located in each of P source-drain units 10, each of the plurality of sub-channel regions 40 being located between adjacent drain branches 220 and source branches 120; the sum of the widths of the plurality of sub-channel regions 40 of P source-drain units 10 in the first direction D1 is W (hereinafter referred to as the total width of the channel region), and the average length of the plurality of sub-channel regions 40 of P source-drain units 10 in the direction perpendicular to the first direction D1 is L (the average length of the sub-channel region); 12≤W / L≤400, P, M and N are all integers greater than or equal to 1, P×N≥4.

[0055] refer to Figure 4A , Figure 4A The total width W of the channel region of the thin-film transistor is shown when it is 500 μm, 800 μm, 1000 μm, 2100 μm and 3000 μm. It can be seen that the offset Δth of the threshold voltage of the thin-film transistor is positively correlated with W.

[0056] refer to Figure 4B , Figure 4B The results show the cases where the average length L of the sub-channel region of the thin-film transistor is 4.5 μm, 5.5 μm, 6.5 μm, 7.5 μm and 8.5 μm, respectively. It can be seen that the offset Δth of the threshold voltage of the thin-film transistor is negatively correlated with L.

[0057] Reducing the threshold voltage offset Δth improves the charging rate of thin-film transistors (TFTs), leading to better TFT performance. However, increasing the on-state current Ion causes significant heat generation in TFTs. We aim for a smaller threshold voltage offset Δth while avoiding excessively high on-state current Ion, as a high on-state current also contributes to a larger threshold voltage offset Δth during TFT operation. Therefore, exploring the design boundaries of TFTs is crucial.

[0058] Through research, the inventors established a relationship between W / L and P×N in the thin-film transistor provided in this disclosure embodiment. When 12 ≤ W / L ≤ 400, satisfying P×N ≥ 4 effectively reduces the heat generation of the thin-film transistor, reduces the threshold voltage offset Δth, improves the charging rate, and maintains stable performance during operation. This improves the display effect of the display panel using the GOA driving circuit including this thin-film transistor, and avoids excessively high on-state current Ion. It also avoids simply increasing the number of source / drain cells, source branches, and drain branches, which could lead to a highly concentrated arrangement of source and drain branches, thus preventing heat accumulation. Finding the appropriate product of the number of source / drain cells P and the number of source branches N in a single source / drain cell within a specific W / L range achieves a better effect in reducing the heat generation of the thin-film transistor, which is of great significance for the rational design of transistors. Especially for transistors with a large W (e.g., W greater than 100 μm), the effect of reducing the heat generation of thin-film transistors is more obvious.

[0059] By basing the design on the relationship between W / L and P and N, the design limits for the number of P and N can be controlled, making the design rules clearer. This allows for the reasonable arrangement of thin-film transistors (TFTs) in the circuit (e.g., GOA driving circuit) of a display panel using multiple TFTs, based on the foreseeable improvement in heat dissipation. It also facilitates the reasonable arrangement of multiple TFTs in the limited GOA area (non-display area, e.g., at least partially surrounding the display area) of the display panel, setting up more shift register units to drive more rows of pixels in the display area of ​​the display panel. This is beneficial for driving high PPI display panels. Furthermore, in the GOA area of ​​a high PPI display panel, the arrangement of TFTs in the GOA driving circuit is more dense. In this case, it is particularly necessary to improve the heat dissipation of the TFTs. Designing according to the relationship between W / L and the product of P and N in this application can effectively obtain the design boundary, solve the problem of improving the heat dissipation of TFTs, and prevent the threshold voltage offset Δth of TFTs from being too large.

[0060] For example, the lengths of multiple subchannel regions 40 are all equal, and all are... Figure 1 The length L' of one of the sub-channel regions 40 in the first direction D1 is given by L=L'. Of course, in other embodiments, the lengths of the multiple sub-channel regions 40 may not all be equal. In summary, L is the sum of the widths of the multiple sub-channel regions 40 of the P source / drain units 10 in the first direction D1, which is W, and the average length of the multiple sub-channel regions 40 of the P source / drain units 10 in the direction perpendicular to the first direction D1.

[0061] To clearly explain the meanings of P, M, and N mentioned above, the following will use... Figure 1 The thin-film transistor shown is used as an example to illustrate this. For example, in Figure 1 In the thin-film transistor shown, the number of source / drain units 10 is P=8, which is also the number of source units. N source branches 120 in one source / drain unit 10 constitute one source unit, and M drain branches 220 in one source / drain unit 10 constitute one drain unit. For example, in... Figure 1 In the thin-film transistor shown, M=5, N=4, and M=N+1. Of course, in other embodiments, M=N is also possible.

[0062] It should be noted that "alternating arrangement" here refers to the arrangement according to the pattern of one source branch 120, one drain branch 220, one source branch 120, one drain branch 220... or the arrangement according to the pattern of one drain branch 220, one source branch 120, one drain branch 220, one source branch 120...

[0063] For example, when 112 ≤ W / L ≤ 400, P×N ≥ 6. Further experimental research shows that, when 112 ≤ W / L ≤ 400, i.e., for relatively larger W / L values ​​(at least 112), satisfying P×N ≥ 6 can more effectively reduce the heat generation of the thin-film transistor (TFT), reduce the threshold voltage offset Δth of the TFT, maintain the stability of the TFT's performance during operation, and thus improve the display effect of the display panel using the GOA driving circuit including this TFT. For example, especially for transistors with larger W values, such as W ≥ 950 μm, when 112 ≤ W / L ≤ 400 and P×N ≥ 6, the reduction in TFT heat generation is significant.

[0064] For example, in the case of 112 ≤ W / L ≤ 400, P×N ≥ 6, P ≥ 3 and N ≥ 2. Figure 3A As shown, Figure 3A A structure of thin-film transistors M13 and M3 is shown. Figure 3AIn the thin-film transistor M13, 112 ≤ W / L ≤ 400 is satisfied. In the thin-film transistor M13, P=3 and N=2.

[0065] For example, further, when 112 ≤ W / L ≤ 400, P×N ≥ 12, to further effectively reduce the heat generation of thin-film transistors.

[0066] For example, further, P ≥ 4 and N ≥ 3. Figure 3A As shown, the thin-film transistor M3 also satisfies 112≤ W / L≤400. In the thin-film transistor M3, P=4 and N=3. After experimental verification, the heat generation problem of the thin-film transistor M3 is significantly improved, and the design limits of the number of P and N can be controlled, making the design rules clearer.

[0067] For example, further, P×N≥ 16, to further effectively reduce the heat generation of thin-film transistors.

[0068] For example, further, P ≥ 4 and N ≥ 4. Figure 3B As shown, Figure 3B Another structure for thin-film transistors M13 and M3 is shown. Figure 3B In the thin-film transistor M13, 112 ≤ W / L ≤ 400 is satisfied. In the thin-film transistor M13, P=4 and N=4.

[0069] For example, further, 235 ≤ W / L ≤ 400, P×N ≥ 32. That is, for a relatively large W / L value (at least 235), through experimental exploration, satisfying 235 ≤ W / L ≤ 400 and P×N ≥ 32 can significantly reduce the heat generation of the thin-film transistor, reduce the threshold voltage offset Δth of the thin-film transistor, maintain the stability of the thin-film transistor's performance during operation, thereby improving the display effect of the display panel using the GOA driving circuit including this thin-film transistor.

[0070] For example, further, P ≥ 8 and N ≥ 4, to further effectively reduce the heat generation of thin-film transistors. Figure 3B In the thin-film transistor M3, 112 ≤ W / L ≤ 400 is satisfied. In the thin-film transistor M3, P=8 and N=4.

[0071] like Figure 5A As shown, when the total width W of the channel region and the average length L of the sub-channel region are the same, within a certain range, the threshold voltage offset Δth is negatively correlated with the number of source / drain branches, and increasing the number of source / drain branches also helps to reduce the heat generation of the thin-film transistor. For example... Figure 5AThe diagram illustrates cases where W is 1200 μm, L is 4.5 μm, and the number of source branches N (where N represents the number of source / drain branches) is 9 and 39 respectively; cases where W is 1200 μm, L is 6 μm, and the number of source branches N is 9 and 39 respectively; and cases where W is 1200 μm, L is 8.5 μm, and the number of source branches N is 9 and 39 respectively. Therefore, appropriately increasing the number of source / drain branches is beneficial for reducing the threshold voltage offset Δth and reducing the heat generation of the thin-film transistor.

[0072] like Figure 5B As shown, Figure 5B The results show the cases where the number of source / drain cells P is 2, 12, and 16, respectively. It can be seen that, within a certain range, the offset of the threshold voltage Δth is negatively correlated with the number of source / drain cells P. Furthermore, increasing the number of source / drain branches is also beneficial to reducing the heat generation of thin-film transistors.

[0073] The proposed scheme explores the W / L relationship with P and N for each thin-film transistor, which is an optimized design that can provide design boundaries for the design of thin-film transistors in the gate drive circuit and achieve better working results.

[0074] For example, in the thin-film transistor provided in at least one embodiment, W / L < 180, and W ranges from 10 μm to 1600 μm. This was obtained through experimental research. Figure 4C ,refer to Figure 4C , Figure 4C This demonstrates the case where the W / L value of thin-film transistors is between 50 and 400, based on... Figure 4C It can be seen that when W / L < 180 (in Figure 4C At the intersection of the two lines (W / L = 180), the average length L of the sub-channel region has a relatively small impact on the threshold voltage offset Δth. However, the total width W of the channel region has a greater impact on the threshold voltage offset Δth than the average length L. Therefore, when W / L < 180, adjusting the total width W of the channel region can more effectively adjust the threshold voltage offset Δth and improve the operating performance of the thin-film transistor. Experimental studies have shown that when W / L < 180, a W range of 10 μm to 1600 μm can effectively reduce the threshold voltage offset Δth, improve the heat dissipation problem of thin-film transistors, and provide guidance for the design of the channel region size of thin-film transistors.

[0075] For example, in the thin-film transistor provided in at least one embodiment, W / L > 180, and L ranges from 4 μm to 15 μm. (Reference) Figure 4CWhen W / L > 180, the total width W of the channel region has a relatively small impact on the threshold voltage offset Δth. However, the average length L of the sub-channel region has a greater impact on the offset Δth than the total width W. Therefore, when W / L > 180, adjusting the average length L of the sub-channel region can more effectively adjust the threshold voltage offset Δth and improve the operating performance of the thin-film transistor. Experimental studies have shown that when W / L > 180, a range of L of 4μm to 15μm can effectively reduce the threshold voltage offset Δth, improve the heat dissipation problem of the thin-film transistor, and provide guidance for the design of the channel region size of the thin-film transistor.

[0076] For example, in the thin-film transistor provided in at least one embodiment of this disclosure, L = 6 μm ~ 8.5 μm, so that it is easier to control the value of W / L and to easily achieve a suitable transistor size design.

[0077] For example, multiple source / drain cells 10 are arranged in at least one cell row 1, and each cell row 1 includes at least one source / drain cell 10; within the same cell row 1, the distance between adjacent source / drain cells 10 is d. (Reference) Figure 5C , Figure 5C The diagram shows the threshold voltage offset Δth and on-state current Ion when the distance d between adjacent source / drain cells 10 in the same cell row 1 is 50 μm, 100 μm, 150 μm, 200 μm, and 250 μm, respectively. According to... Figure 5C It is known that the threshold voltage offset Δth of a thin-film transistor (TFT) is negatively correlated with the distance d between adjacent source-drain cells 10. A larger distance d between adjacent cells 10 within each row 1 results in stronger heat dissipation and a smaller threshold voltage offset Δth, which is beneficial for improving the charging rate of the TFT and thus its performance. However, as the distance d increases, the on-state current Ion increases. We desire a smaller threshold voltage offset Δth, but we also do not want an excessively high on-state current Ion, as a high on-state current Ion will also cause a larger threshold voltage offset Δth during the operation of the TFT. Therefore, exploring the design boundaries is crucial.

[0078] For example, in the thin-film transistor provided in at least one embodiment, such as Figure 1As shown, W ≥ 500 μm, and the distance d between adjacent source / drain cells 10 in row 1 of the same cell ranges from 50 μm to 500 μm. Experimental studies have shown that, under the conditions of 12 ≤ W / L ≤ 400 and P × N ≥ 4, combining the conditions of W ≥ 500 μm and d ranging from 50 μm to 500 μm with the conditions of 12 ≤ W / L ≤ 400 and P × N ≥ 4 can effectively reduce the threshold voltage offset Δth of the thin-film transistor (TFT) when the total width W of the channel region is large, thus reducing the TFT's heat generation. For TFTs satisfying W ≥ 500 μm, this provides a design boundary for TFT designs aimed at effectively reducing the threshold voltage offset Δth and lowering the TFT's heat generation.

[0079] For example, in another embodiment, W < 500 μm, and the distance between adjacent source / drain cells 10 in the same cell row 1 is d, where d ranges from 20 μm to 300 μm. Experimental studies have shown that, under the conditions of 12 ≤ W / L ≤ 400 and P × N ≥ 4, combining the conditions of W < 500 μm and d ranging from 20 μm to 300 μm with the conditions of 12 ≤ W / L ≤ 400 and P × N ≥ 4 can achieve a better reduction in the threshold voltage offset Δth of the thin-film transistor (TFT) when the total width W of the channel region is large, thus reducing the TFT's heat generation. For TFTs satisfying W < 500 μm, this provides a design boundary for TFT designs aimed at effectively reducing the threshold voltage offset Δth and lowering the TFT's heat generation.

[0080] Of course, the above is just a specific example. In practical applications, the distance d between adjacent source and drain cells 10 in the same cell row 1 is not limited to this.

[0081] For example, such as Figure 1As shown, multiple source / drain cells 10 are arranged in at least two cell rows 1, and each cell row 1 in at least one cell row 1 includes at least one source / drain cell 10. For example, multiple source / drain cells 10 are disposed in the region between adjacent source traces 110 and drain traces 210 to arrange multiple source / drain cells 10 into at least two cell rows 1. For example, the first source trace 110a, the first drain trace 210a, and the second drain trace 210b are arranged parallel and spaced apart; and the first source trace 110a is located between the first drain trace 210a and the second drain trace 210b. Multiple source / drain cells 10 are spaced apart between the first source trace 110a and the first drain trace 210a to form a first cell row 11; multiple source / drain cells 10 are spaced apart between the first source trace 110a and the second drain trace 210b to form a second cell row 12. The drain branches 220 of each cell 10 in the first cell row 11 are all connected to the first drain line 210a, and the drain branches 220 of each cell 10 in the second cell row 12 are all connected to the second drain line 210b; that is, the source branches 120 of at least one source-drain cell 10 in each cell row 1 are electrically connected to the same source line 110, and the drain branches 220 of at least one source-drain cell 10 in each cell row 1 are electrically connected to the same drain line 210. The source branches 120 of each source-drain cell 10 in the first cell row 11 are all connected to one side of the first source line 110a, and the source branches 120 of each source-drain cell 10 in the second cell row 12 are all connected to the other side of the first source line 110a. In other words, the source branches 120 in the first cell row 11 and the source branches 120 in the second cell row 12 share the same first source line 110a.

[0082] Of course, in other embodiments, the source and drain cells 10 of the thin-film transistor may also be arranged in only one cell row.

[0083] For example, Figure 1 In the example thin-film transistor, the number of source / drain units 10 in the first unit row 11 is 4, and the number of units 10 q in the second unit row 12 is 4, for a total of 8 units 10 in the thin-film transistor. Of course, the number of source / drain units 10 q in each unit row 1 is not limited to this. For example, the number of source / drain units 10 in each unit row 1 can also be only 2. In this way, the total number of source / drain units 10 in the two unit rows 1 in the thin-film transistor is still greater than 3, so as to improve the heat dissipation performance of the thin-film transistor. Alternatively, depending on the actual needs, the number of source / drain units 10 in the thin-film transistor can also be less than or equal to 3.

[0084] For example, combining Figure 1 and Figure 2The semiconductor layer 400 includes a sub-section overlapping with each of the plurality of source / drain cells 10, i.e., the sub-section overlaps with the orthographic projection of each drain cell 10 onto a plane defined by a first direction D1 and a second direction D2. Each sub-section includes Q semiconductor branches 410. The plurality of sub-channel regions 40 include sub-channel cells 401 of the Q semiconductor branches 410 located between adjacent source branches 120 and drain branches 220, as shown in... Figure 2 The small rectangle shown is a schematic of a sub-channel unit 401, where Q is an integer greater than or equal to 1. In this case, the total width W of the channel region is the sum of the widths of the sub-channel units 401 of the Q semiconductor branches 410 of the P source / drain units 10 in the first direction D1. The width of a sub-channel unit 401 in the first direction D1 is W1, that is, W = W1 × Q × P; L is the average length of the multiple sub-channel units 401 of the P source / drain units 10 in the direction perpendicular to the first direction D1. For example, if the second direction D2 is perpendicular to the first direction D1, L = the sum of the lengths of the multiple sub-channel units 401 of the P source / drain units 10 in the second direction D2 / the total number of sub-channel units 401. For example, if the lengths of the multiple sub-channel regions 40 are all equal, L = L'.

[0085] In addition, Figure 1 In the embodiment shown, the orthogonal projection of the gate 300 on the substrate does not overlap with the orthogonal projection of the source line 110 on the substrate, and the orthogonal projection of the gate 300 on the substrate overlaps with the orthogonal projection of the drain line 210 on the substrate.

[0086] In the above embodiments, the orthogonal projection of the gate 300 on the substrate does not overlap with the orthogonal projection of the first source line 110a on the substrate. For example... Figure 1 As illustrated, the gate 300 is hollowed out at the location where the first source trace 110a is arranged. This reduces the overlap area between the gate 300 and the first source trace 110a, thereby reducing the CGS capacitance, i.e., reducing the capacitance between the gate 300 and the first source trace 110a, to reduce signal delay. Furthermore, the orthographic projection of the gate 300 on the substrate overlaps with the orthographic projections of the first drain trace 210a and the second drain trace 210b on the substrate. For example... Figure 1 As shown, the source branch 120 and drain branch 220 in each unit 10 of the thin film transistor, as well as the orthogonal projections of the first drain line 210a and the second drain line 210b on the substrate, all fall on the orthogonal projection of the gate 300 on the substrate. In this way, the CGD capacitance, that is, the capacitance between the drain 200 and the gate 300, can be increased to reduce signal noise.

[0087] In addition, Figure 1 In the illustrated embodiment, in the thin-film transistor application, for example, when applied in a GOA circuit, the first end of the first source trace 110a is connected to the clock pulse signal trace 600 in the GOA circuit. The orthographic projection of the gate 300 on the substrate does not overlap with the orthographic projection of the clock pulse signal trace 600 on the substrate. Furthermore, a gate trace 310 is connected to the gate 300, and the orthographic projection of the gate trace 310 on the substrate intersects and overlaps with the orthographic projection of the clock pulse signal trace 600 on the substrate.

[0088] In the above embodiments, on the one hand, reducing the overlap area between the gate 300 and the clock pulse signal trace 600 can further reduce the CGS capacitance, that is, reducing the capacitance between the gate 300 and the clock pulse signal trace 600, thereby reducing signal delay; on the other hand, as Figure 1 As shown, when the GOA circuit includes multiple thin-film transistors, in order to Figure 1 Taking the thin-film transistor shown as an example, the gate 300 of this thin-film transistor is connected to the gate of other thin-film transistors through a gate trace 310. The gate trace 310 is located on the side of the gate 300 close to the clock pulse signal trace 600. The gate 300 has a cutout pattern on the side where the clock pulse signal trace 600 is located so that it does not overlap with the clock pulse signal trace 600. Only the gate trace 310 crosses and overlaps with the clock pulse signal trace 600. In this way, the spacing between the gates 300 of adjacent thin-film transistors can be increased at the cutout pattern, thereby reducing the heat generation problem of the gate 300.

[0089] also, Figure 1 In the embodiment shown, a drain electrode block 230 formed by a metal layer of drain 200 is provided between two adjacent units 10. The drain electrode block 230 overlaps with the orthographic projection of the gate 300 on the substrate. In this way, the CGD capacitance, that is, the capacitance between the metal layer of drain 200 and gate 300, can be increased to further reduce signal noise.

[0090] It is understandable that, in other embodiments, depending on actual needs, the drain electrode block 230 may not be provided between two adjacent units 10.

[0091] In addition, Figure 1In the illustrated embodiment, one end of the drain line 210 is connected to the signal output terminal 500. A first gate metal pattern 320 formed by the metal layer of the gate 300 is also provided on the substrate. The first gate metal pattern 320 is located on one side of the signal output terminal 500 and is independent and insulated from the gate 300. The signal output terminal 500 is provided with a plurality of first vias 510, and the first gate metal pattern 320 is provided with a plurality of second vias 321. The signal output terminal 500 is connected to an ITO layer (indium tin oxide) 330 through the first vias 510, and the first gate metal pattern 320 is connected to the ITO layer 330 through the second vias 321, so as to realize the electrical connection between the signal output terminal 500 and the first gate metal pattern 320. The first gate metal pattern 320 is also electrically connected to the pixel electrode of the display device through the second vias 321.

[0092] In addition, such as Figure 1 As shown, one end of the first source trace 110a is connected to the clock pulse signal trace 600, and the trace direction of the clock pulse signal trace 600 is perpendicular to the first source trace 110a. The signal output terminal 500 is connected to the same end of the first drain trace 210a and the second drain trace 210b, and is perpendicular to the first drain trace 210a. The clock pulse signal trace 600 and the signal output terminal 500 are located on opposite sides of the thin-film transistor. Of course, the positions of the clock pulse signal trace and the signal output terminal 500 are not limited to this situation.

[0093] Figure 6A This is a schematic diagram of another thin-film transistor structure provided in at least one embodiment of the present disclosure. Figure 6A The thin-film transistor shown is Figure 1 The thin-film transistors shown have the following differences. Figure 6A In the illustrated embodiment, within each source / drain cell 10, at least one semiconductor branch 410 is designed as a compensation semiconductor branch 411, the total channel length of which is less than the channel length of the other semiconductor branches 410 in the second direction D2. Figure 6A Other features and corresponding technical effects of the illustrated embodiments are similar to Figure 1 The same applies, please refer to the previous description, and will not be repeated here.

[0094] Figure 6B This is a schematic diagram of the structure of another thin-film transistor provided in at least one embodiment of the present disclosure. Figure 6B The thin-film transistor shown is Figure 1 The thin-film transistors shown have the following differences. Figure 6BIn the illustrated embodiment, the semiconductor layer 400 includes a sub-section overlapping with each of the plurality of source / drain cells 10. Specifically, the sub-section overlaps with the orthographic projection of each drain cell 10 onto a plane defined by a first direction D1 and a second direction D2. The overlapping sub-sections with the plurality of source / drain cells 10 constitute a continuous, integrated structure. In this case, for example, the plurality of sub-sections constitute a continuous, integrated structure, W = W2 × P. As long as there is no contradiction, Figure 6B Other features and corresponding technical effects of the illustrated embodiments are similar to Figure 1 The same applies, please refer to the previous description, and will not be repeated here.

[0095] In the embodiments of this disclosure, the thin-film transistor can be a P-type thin-film transistor or an N-type thin-film transistor, and the structure can be bottom-gate, top-gate, or dual-gate. The embodiments of this disclosure do not limit the specific type of thin-film transistor.

[0096] At least one embodiment of this disclosure also provides a shift register unit, which includes any of the thin-film transistors provided in this disclosure.

[0097] Figure 7 This is an exemplary circuit diagram of a shift register unit provided in at least one embodiment of the present disclosure. Figure 7 As shown, in the shift register unit 01, the gate row driving circuit includes an input circuit 101, an output circuit 102 / 103, and a first node reset circuit 104. The input circuit 101 is connected to the first node PU and configured to charge the first node PU in response to an input signal. The output circuit 102 / 103 is connected to the first node PU and configured to output an output signal at the output terminal Output1 under the control of the level signal of the first node PU. The first node reset circuit 104 is connected to the first node PU and configured to reset the first node PU in response to a reset signal. The output circuit 102 / 103, the input circuit 101, and the first node reset circuit 104 all include any of the thin-film transistors provided in this disclosure.

[0098] like Figure 7As shown, the output terminal Output1 includes a scan signal output terminal, i.e., the first output terminal Output1, and a shift output terminal, i.e., the second output terminal Output2; the output circuit includes a first output sub-circuit 102 and a second output sub-circuit 103. For example, the shift register unit 01 also includes a monitoring sub-circuit 105. Input circuit 101 is configured to precharge pull-up node PU (i.e., the first node PU mentioned above) in response to an input signal; pull-up node PU is the connection node between input circuit 101, first output sub-circuit 102, second output sub-circuit 103 and reset sub-circuit 104; first output sub-circuit 102 is configured to output a clock signal through first output terminal Output1 in response to the potential of pull-up node PU; second output sub-circuit 103 is configured to output a synchronization signal with the first output terminal Output1 through second output terminal Output2 in response to the potential of pull-up node PU; reset sub-circuit 104 is configured to reset the potential of pull-up node PU through second power supply voltage in response to a reset signal; monitoring sub-circuit 104 is configured to monitor second output terminal Output2 and output the monitoring result through third output terminal Output3.

[0099] Therefore, in the aforementioned shift register unit, the first output sub-circuit 102 can output a GOA signal, such as a clock signal, through the first output terminal Output1. The second output sub-circuit 103 can output the synchronization signal output by the first output terminal Output1 through the second output terminal Output2. The monitoring sub-circuit 104 can monitor the second output terminal Output2 and output the monitoring result through the third output terminal Output3. In this way, the GOA signal output by the second output terminal Output2 can be monitored to determine whether the GOA signal output by the shift register is abnormal. Therefore, real-time monitoring of the GOA signal can be realized, thereby monitoring the changes in the GOA working state during the product reliability process and detecting the point where the GOA signal is abnormal at the first time.

[0100] For example, in some examples, such as Figure 7As shown, the first shift register may further include at least one pull-down control sub-circuit 106, at least one pull-down sub-circuit 107, at least one first noise reduction sub-circuit 108, at least one second noise reduction sub-circuit 109, and at least one third noise reduction sub-circuit 110. The pull-down control sub-circuit 106 is configured to control the potential of the pull-down node PD in response to a first power supply voltage; the pull-down node PD is the connection node between the pull-down control sub-circuit 106 and the pull-down sub-circuit 107; the pull-down sub-circuit 107 is configured to pull down the potential of the pull-up node PD in response to the potential of the pull-up node PU in response to a second power supply voltage; the first noise reduction sub-circuit 108 is configured to reduce noise at the first output terminal Output1 in response to the potential of the pull-down node PD in response to a second power supply voltage; the second noise reduction sub-circuit 109 is configured to reduce noise at the second output terminal Output2 in response to the potential of the pull-down node PD in response to a second power supply voltage; and the third noise reduction sub-circuit 110 is configured to reduce noise at the pull-up node PU in response to the potential of the pull-down node PD in response to a second power supply voltage.

[0101] For example, in some embodiments, such as Figure 7 As shown, the first shift register unit may further include an initialization sub-circuit 111; the initialization sub-circuit 111 is configured to initialize the potential of the pull-up node PU by means of a second power supply voltage in response to an initialization signal.

[0102] Specifically, such as Figure 7 As shown, the input circuit 101 includes a first transistor M1 (input transistor), whose gate and source are both connected to the input signal terminal Input, and whose drain is connected to the pull-up node PU. The reset sub-circuit 104 includes a second transistor M2 (i.e., the aforementioned reset transistor), whose gate is connected to the reset control signal terminal Reset, whose source is connected to the second power supply voltage terminal VSS, and whose drain is connected to the pull-up node PU. The first output sub-circuit 102 includes a third transistor M3 (i.e., the aforementioned output transistor) and a storage capacitor C. The gate of the third transistor M3 is connected to the pull-up node PU, its source is connected to the clock signal terminal CLK, and its drain is connected to the first output terminal Output1; one end of the storage capacitor C is connected to the pull-up node PU, and its drain is connected to the first output terminal Output1. The second output sub-circuit 103 includes a thirteenth transistor M13 (this transistor is also an output transistor); the gate of the thirteenth transistor M13 is connected to the pull-up node PU, its source is connected to the clock signal terminal CLK, and its drain is connected to the second output terminal Output2.

[0103] During the input phase, a high-level signal is written to the Input terminal, turning on the first transistor M1. This high-level signal pre-charges the pull-up node PU through the first transistor M1. During the output phase, the potential of the pull-up node PU is pulled high due to pre-charging and stored in the storage capacitor C. In this phase, the first transistor M1 is turned off, and the storage capacitor C discharges, further pulling the potential of the pull-up node PU high. The third transistor M3 and the thirteenth transistor M13 are both turned on. The first output terminal Output1 outputs the high-level signal written to the clock signal terminal CLK, and the second output terminal Output2 outputs the synchronization signal output from the first output terminal Output1. During the reset phase, a high-level signal is written to the Reset control signal terminal, turning on the second transistor M2. The low power supply voltage written to the second power supply voltage terminal VSS resets the potential of the pull-up node PU.

[0104] For example, the monitoring sub-circuit 105 includes a fourth transistor M4, the gate and source of which are both connected to the second output terminal Output2, and the drain is connected to the third output terminal Output3.

[0105] It should be noted that the gate and source of the fourth transistor M4 are connected to the second output terminal Output2, and the drain is connected to the third output terminal Output3. When the GOA signal output from the second output terminal Output2 is a high-level signal, the fourth transistor M4 can be turned on under the control of the high-level signal, and this high-level signal is output through the third output terminal Output3. By comparing the high-level signal output from the third output terminal Output3 with a reference high-level signal, if the signal output from the third output terminal Output3 is the same as the reference high-level signal, it indicates that the GOA signal output from the second output terminal Output2 is normal; if the signal output from the third output terminal Output3 is different from the reference high-level signal or there is no output signal from the third output terminal Output3, it indicates that the GOA signal output from the second output terminal Output2 is abnormal. Therefore, real-time monitoring of the GOA signal can be achieved, thereby monitoring changes in the GOA operating state during product reliability testing, and detecting points where GOA signal abnormalities occur at the first time, avoiding defects such as AD.

[0106] For example, the pull-down control sub-circuit 106 includes a ninth transistor M9 and a fifth transistor M5. The gate and source of the ninth transistor M9 are both connected to the first power supply voltage terminal VDD, and its drain is connected to the gate of the fifth transistor M5. The gate of the fifth transistor M5 is connected to the drain of the ninth transistor M9, its source is connected to the first power supply voltage terminal VDD, and its drain is connected to the pull-down node PD. The pull-down sub-circuit 107 includes a sixth transistor M6 and an eighth transistor M8. The gate of the sixth transistor M6 is connected to the pull-up node PU, its source is connected to the pull-down node PD, and its drain is connected to the second power supply voltage terminal VSS. The gate of the eighth transistor M8 is connected to the pull-up node PU, its source is connected to the drain of the ninth transistor M9, and its drain is connected to the second power supply voltage terminal VSS. The first noise reduction sub-circuit 108 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is connected to the pull-down node PD, its source is connected to the first output terminal Output1, and its drain is connected to the second power supply voltage terminal VSS. The second noise reduction sub-circuit 109 includes a twelfth transistor M12. The gate of the twelfth transistor M12 is connected to the pull-down node PD, the source is connected to the second output terminal Output2, and the drain is connected to the second power supply voltage terminal VSS. The third noise reduction sub-circuit 110 includes a tenth transistor M10. The gate of the tenth transistor M10 is connected to the pull-down node PD, the source is connected to the pull-up node PU, and the drain is connected to the second power supply voltage terminal VSS.

[0107] It should be noted that, in Figure 7 The example shown uses two pull-down control sub-circuits 106, two pull-down sub-circuits 107, two first noise reduction sub-circuits 108, two second noise reduction sub-circuits 109, and two third noise reduction sub-circuits 110 for illustration. It is understood that the number of each of the above sub-circuits can be one or other numbers, but the implementation principle is the same, and will not be elaborated further here.

[0108] For example, in Figure 7In the first and second pull-down control sub-circuits 106, the fifth transistors are represented by M5 and M5′, respectively, and the ninth transistors are represented by M9 and M9′, respectively; the sixth transistors in the first and second pull-down circuits 5 are represented by M6 and M6′, respectively, and the eighth transistor M8 is represented by M8 and M8′, respectively; the eleventh transistors in the first and second first noise reduction circuits 108 are represented by M11 and M11′, respectively; the twelfth transistors in the first and second second noise reduction circuits 109 are represented by M12 and M12′, respectively; the tenth transistors in the first and second third noise reduction circuits 110 are represented by M10 and M10′, respectively; and the first power supply voltage terminals connected to the first and second pull-down control sub-circuits 106 are represented by VDD1 and VDD2, respectively. In addition, the first pull-down control sub-circuit 106 and the first pull-down circuit 107 are connected, and the connection node between them is represented by the pull-down node PD1; the second pull-down control sub-circuit 106 and the second pull-down circuit 107 are connected, and the connection node between them is represented by the pull-down node PD2; the first first noise reduction circuit 108 is connected to PD1, and the second first noise reduction circuit 108 is connected to PD2; the first second noise reduction circuit 109 is connected to PD1, and the second second noise reduction circuit 109 is connected to PD2; the first third noise reduction circuit 110 is connected to PD1, and the second third noise reduction circuit 110 is connected to PD2.

[0109] For example, during the scanning of one frame of an image, the first pull-down control sub-circuit 106, the first first pull-down circuit 107, the first first noise reduction circuit 108, the first second noise reduction circuit 109, and the first third noise reduction circuit 110 may operate, or the second pull-down control sub-circuit 106, the second first pull-down circuit 107, the second first noise reduction circuit 108, the second second noise reduction circuit 109, and the second third noise reduction circuit 110 may operate. That is, there can be multiple pull-down control sub-circuits 106, 107, 108, 109, and 110. Sub-circuits with the same function operate only one at a time during the scanning of one frame of an image, and can switch to another at a preset operating time, thereby extending the lifespan of the shift register. During the noise reduction phase, since the pull-up node PU is pulled down to a low level during the reset phase, and the fifth transistor M5 and the ninth transistor M9 are continuously controlled by the first power supply voltage written to the first power supply voltage terminal VDD1, the potential of the pull-down node PD1 is a high level signal. The eleventh transistor M11 is turned on, and the second power supply voltage written to the second power supply voltage terminal VSS reduces noise at the first output terminal Output1 through the eleventh transistor M11. Simultaneously, the twelfth transistor M12 and the tenth transistor M10 are also turned on, and the second power supply voltage written to the second power supply voltage terminal VSS reduces noise at the second output terminal Output2 and the output of the pull-up node PU through the twelfth transistor M12 and the tenth transistor M10, respectively.

[0110] For example, the initialization sub-circuit 111 includes a seventh transistor M7, the gate of the seventh transistor M7 is connected to the initialization signal terminal STV, the source is connected to the pull-up node PU, and the drain is connected to the second power supply voltage terminal VSS.

[0111] It should be noted that when displaying the next frame, a high-level signal is written to the initialization signal terminal STV, the seventh transistor M7 is turned on, and the potential of the pull-up node PU is initialized by the low power supply voltage written to the second power supply voltage terminal VSS, so as to prevent the display of adjacent frames from interfering with each other and affecting the display effect.

[0112] It is understood that the first shift register unit and the second shift register unit provided in the embodiments of this disclosure can be other circuit structures besides the 19T1C structure described above, such as the 17T1C structure, the 18T2C structure, the 21T1C structure, etc. The embodiments of this disclosure do not limit the specific structure of the first shift register unit and the second shift register unit. For example, when the structure of the first shift register unit and the second shift register unit is a 17T1C structure, compared with the 19T1C structure described above, the 17T1C may not have the ninth transistors M9 and M9′, but its implementation principle is the same as that of the shift register unit of the 19T1C structure described above, and will not be repeated here.

[0113] For example, the first output sub-circuit 102 includes a first output transistor and a third transistor M3 as the first output transistor; the second output sub-circuit 103 includes a second output transistor and a thirteenth transistor M13 as the second output transistor; the gate 300 of the first output transistor is connected to the first node PU, the first terminal of the first output transistor is connected to the clock signal terminal to receive the clock signal, and the second terminal of the first output transistor is connected to the shift output terminal Output2; the gate 300 of the second output transistor is connected to the first node PU, the first terminal of the second output transistor is connected to the clock signal terminal to receive the clock signal, and the second terminal of the second output transistor is connected to the scan signal output terminal Output1; the clock signal is transmitted to the output terminal Output1 as an output signal; both the first output transistor and the second output transistor are thin-film transistors provided in the embodiments of this disclosure.

[0114] The total width W of the channel regions of the third transistor M3 and the thirteenth transistor M13 is relatively large, resulting in a particularly large threshold voltage offset Δth and severe heat generation. For example, both the third transistor M3 and the thirteenth transistor M13 satisfy P ≥ 3 and N ≥ 2, meaning both the first and second output transistors satisfy P ≥ 3 and N ≥ 2; or, both the third transistor M3 and the thirteenth transistor M13 satisfy P × N ≥ 12, meaning both the first and second output transistors satisfy P × N ≥ 12; or, both the third transistor M3 and the thirteenth transistor M13 satisfy P × N ≥ 16, meaning both the first and second output transistors satisfy P × N ≥ 16. This effectively reduces the threshold voltage offset Δth of the third transistor M3 and the thirteenth transistor M13, reduces their heat generation, ensures that the shift register unit 01 has better and more stable operating performance, and ensures that the display panel using the gate drive circuit including the shift register unit 01 as the scan drive circuit has a better display effect.

[0115] For example, in the shift register unit 01 provided in the embodiments of this disclosure, the third transistor M3 and the thirteenth transistor M13 are respectively Figure 3A The transistors shown have the following properties: the thirteenth transistor M13 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M13, P=3 and N=2. The third transistor M3 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M3, P=4 and N=3. The sources of both the third transistor M3 and the thirteenth transistor M13 are connected to the same clock signal line CLK; the drains of both transistors are connected to the first drain trace 210A and the second drain trace 210B, respectively.

[0116] For example, the third transistor M3 satisfies 235 ≤ W / L ≤ 400 and P×N ≥ 32. For example, the third transistor M3 and the thirteenth transistor M13 are respectively... Figure 3B The transistors shown have the following properties: the thirteenth transistor M13 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M13, P=4 and N=4. The third transistor M3 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M3, P=8 and N=4. The sources of the third transistor M3 and the thirteenth transistor M13 are connected to the first source trace 110A and the second source trace 110B, respectively. The first source trace 110A is connected to the same clock signal line CLK. The drains of the third transistor M3 and the thirteenth transistor M13 are connected to the first drain trace 210A and the second drain trace 210B, respectively.

[0117] For example, the first transistor M1, the second transistor M2, the sixth transistor M6, the eighth transistor M8 / M8', the tenth transistor M10 / M10', and the eleventh transistor M11 / M11' are all thin-film transistors provided in the embodiments of this disclosure, and all satisfy 12≤W / L≤400, P and N are both integers greater than or equal to 1, M is an integer greater than or equal to 2, and P×N ≥ 4. Therefore, by relying on the relationship between W / L and P and N, the design limits for the number of P and N can be controlled, making the design rules clearer. This enables the reasonable arrangement of multiple thin-film transistors in the limited GOA area (non-display area, such as at least partially surrounding the display area) of the display panel using the GOA driving circuit of the shift register unit 01, based on the foreseeable improvement of heat dissipation. More shift register units can be set to drive more rows of pixels in the display area of ​​the display panel, which is beneficial for driving high PPI display panels. Furthermore, in the GOA area of ​​high PPI display panels, the thin-film transistors in the GOA driving circuit are more densely arranged. In this case, it is particularly necessary to improve the heat dissipation of thin-film transistors. Designing according to the relationship between W / L and the product of P and N in this application can effectively obtain the design boundary, improve the heat dissipation problem of thin-film transistors, and prevent the threshold voltage offset Δth of thin-film transistors from being too large.

[0118] For example, some embodiments provide Figure 7 In the shift register unit shown, any of the transistors other than the first transistor M1, the second transistor M2, the sixth transistor M6 / M6', the eighth transistor M8 / M8', the tenth transistor M10 / M10', the eleventh transistor M11 / M11', the third transistor M3, and the thirteenth transistor M13 can be thin-film transistors provided in the embodiments of this disclosure. The specific design can be carried out according to the design boundaries of the thin-film transistors provided in the embodiments of this disclosure, based on the different design requirements of the transistors.

[0119] For example, Figure 7 The design data for each thin-film transistor in shift register unit 01 shown is illustrated in Table 1 below. This approach allows for the rational design of each thin-film transistor based on its functional requirements, while also considering space and performance.

[0120] Table 1. Data of each thin-film transistor (TFT) in a shift register unit.

[0121]

[0122] Figure 8 This is an exemplary circuit diagram of another shift register unit provided in at least one embodiment of the present disclosure. Figure 8The various thin-film transistors in the and Figure 7 The corresponding thin-film transistors perform similar functions. For example, the third transistor M3 and the thirteenth transistor M13 are the first and second output transistors, respectively, and the second transistor M2 is the reset transistor, etc. The connection relationships between the transistors and capacitors are as follows: Figure 8 As shown, they will not be described in detail here; please refer to the relevant documentation. Figure 7 The description uses conventional techniques in the art to... Figure 8 The exemplary circuitry of the shift register unit shown is used for understanding.

[0123] For example, in Figure 8 In the shift register unit shown, the total width W of the channel regions of the third transistor M3 and the thirteenth transistor M13 is relatively large, resulting in a particularly large threshold voltage offset Δth and severe heat generation. For example, both the third transistor M3 and the thirteenth transistor M13 satisfy P ≥ 3 and N ≥ 2, meaning both the first and second output transistors satisfy P ≥ 3 and N ≥ 2; or, both the third transistor M3 and the thirteenth transistor M13 satisfy P × N ≥ 12, meaning both the first and second output transistors satisfy P × N ≥ 12; or, both the third transistor M3 and the thirteenth transistor M13 satisfy P × N ≥ 16, meaning both the first and second output transistors satisfy P × N ≥ 16. This effectively reduces the threshold voltage offset Δth of the third transistor M3 and the thirteenth transistor M13, lowers their heat generation, ensures the shift register unit has good and stable operating performance, and guarantees a better display effect for display panels using the gate drive circuit including this shift register unit as the scan drive circuit.

[0124] For example, in the shift register unit provided in the embodiments of this disclosure, the third transistor M3 and the thirteenth transistor M13 are respectively Figure 3A The transistors shown, the thirteenth transistor M13 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M13, P=3 and N=2. The third transistor M3 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M3, P=4 and N=3.

[0125] For example, the third transistor M3 satisfies 235 ≤ W / L ≤ 400 and P×N ≥ 32. For example, the third transistor M3 and the thirteenth transistor M13 are respectively... Figure 3B The transistors shown, the thirteenth transistor M13 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M13, P=4 and N=4. The third transistor M3 satisfies 112 ≤ W / L ≤ 400, and in the thin-film transistor M3, P=8 and N=4.

[0126] For example, the first transistor M1, the second transistor M2, the sixth transistor M6 / M6', the tenth transistor M10 / M10', the eleventh transistor M11 / M11', and the sixteenth transistor M16 / M16' are all thin-film transistors provided in the embodiments of this disclosure, and all satisfy 12≤W / L≤400, P and N are both integers greater than or equal to 1, M is an integer greater than or equal to 2, and P×N ≥ 4. Therefore, by considering the relationship between W / L and P and N, the design limits for the number of P and N can be controlled, making the design rules clearer. This allows for the reasonable arrangement of multiple thin-film transistors in the limited GOA region (non-display area, such as at least partially surrounding the display area) of the display panel using the shift register unit, based on the foreseeable improvement in heat dissipation. More shift register units can be set to drive more rows of pixels in the display area of ​​the display panel, which is beneficial for driving high PPI display panels. Furthermore, in the GOA region of high PPI display panels, the thin-film transistors in the GOA driving circuit are more densely arranged. In this case, it is particularly necessary to improve the heat dissipation of the thin-film transistors. Designing according to the relationship between W / L and the product of P and N in this application can effectively obtain the design boundaries, improve the heat dissipation problem of thin-film transistors, and prevent the threshold voltage offset Δth of the thin-film transistors from being too large.

[0127] For example, Figure 8 The design data for each thin-film transistor in the shift register unit shown is illustrated in Table 2. This approach allows for the rational design of each thin-film transistor based on its functional requirements, while also considering space and performance.

[0128] Table 2. Data of each thin-film transistor (TFT) in a shift register unit.

[0129]

[0130] At least one embodiment of this disclosure also provides a gate driving circuit, which includes any of the shift register units provided in the embodiments of this disclosure. The gate driving circuit includes multiple cascaded shift register units; except for the first to s-th level shift register units, the precharge control terminal of each of the remaining shift register units is connected to the output terminal of the upper-level shift register unit at least s levels away; except for the first to s-th level shift register units, the input terminal of each of the remaining shift register units is connected to the output terminal of the upper-level shift register unit at s-1 levels away; except for the last s-th level shift register unit, the reset terminal of each of the remaining shift register units is connected to the output terminal of the lower-level shift register unit at s-1 levels away; wherein s is an integer greater than 2.

[0131] At least one embodiment of this disclosure also provides a display panel, including the gate driving circuit provided in any embodiment of this disclosure. For example, the display panel provided in the embodiments of this disclosure can be an organic light-emitting diode display panel or a liquid crystal display panel, etc.

[0132] Figure 9 This is a schematic diagram of a display panel provided in at least one embodiment of this disclosure. For example... Figure 9As shown, for example, the display panel 1000 includes a display area 10A and a non-display area at least partially surrounding the display area 10A. The non-display area includes gate drive circuit regions 10B / 10C and circuit lead regions 10D. For example, the non-display area includes a first circuit region 10B and a second circuit region 10C, both of which extend longitudinally. Multiple cascaded shift register units 01 are respectively disposed in the first circuit region 10B and the second circuit region 10C, which are arranged longitudinally. The multiple cascaded shift register units 01 are arranged longitudinally. The circuit lead region 10D, i.e., the Fanout area, is provided with circuit leads (not shown). The circuit lead region 10D extends laterally intersecting the longitudinal direction and is adjacent to the gate drive circuit regions 10B / 10C. The circuit leads include a first lead connected to the gate drive circuit and a second lead connected to the display area 10A. The multiple cascaded shift register units 01 are arranged longitudinally. The register unit 01 includes a first end shift register unit 01a located at one end of the first circuit region 10B near the circuit lead region 10D and a second end shift register unit 01b located at one end of the second circuit region 10C near the circuit lead region 10D. The P×N values ​​of the first output transistor in the first end shift register unit 01a and the second output transistor in the first end shift register unit 01a are respectively greater than the P×N values ​​of the first output transistors in other shift register units in the multiple cascaded shift register units 01 in the first circuit region 10B and the P×N value of the second output transistor in the first end shift register unit 01a. In the display panel, the wiring at the location of the first end shift register unit 01a and the area of ​​the circuit lead region 10D near the first end shift register unit 01a is relatively dense, resulting in particularly severe heat generation. This solution can effectively reduce the heat generation in this severely overheated area, improve the performance of the gate drive circuit, improve the display effect, and help extend the lifespan of the circuit in this area. Similarly, the same applies to the second end shift register unit 01b. The P×N value of the first output transistor in the second end shift register unit 01b and the P×N value of the second output transistor in the second end shift register unit 01b are respectively greater than the P×N values ​​of the first output transistors in other shift register units 01 in the plurality of cascaded shift register units 01 located in the second circuit region 10C and the P×N value of the second output transistor in the second end shift register unit 01b. Here, the first output transistor and the second output transistor refer to the first output transistor and the second output transistor in the previous embodiment of the shift register unit, which can be referred to in detail in the previous description.

[0133] For example, at least one embodiment of this disclosure also provides a display device, which includes the display panel provided in any embodiment of this disclosure. For example, the display device can be any product or component with display function, such as a liquid crystal panel, liquid crystal television, monitor, OLED panel, OLED television, electronic paper display device, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator. The display device may also include other conventional components such as the display panel, and the embodiments of this disclosure do not limit this.

[0134] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. The scope of protection of this disclosure is determined by the scope defined in the claims.

Claims

1. A thin-film transistor, comprising: A source includes a source trace and P source units electrically connected to the source trace, wherein each of the P source units includes M source branches, each of the M source branches extending along a first direction and spaced apart in a second direction intersecting the first direction; The drain includes a drain trace and P drain cells electrically connected to the drain trace and corresponding one-to-one with the P source cells. Each of the P drain cells includes N drain branches, each of the N drain branches extending along a first direction and spaced apart in a second direction. The thin-film transistor includes P source-drain cells, one source cell and one corresponding drain cell forming one source-drain cell. In each of the P source-drain cells, the M source branches and the N drain branches are alternately arranged, spaced apart from each other, and insulated from each other. The gate electrode is insulated from the source and the drain electrode; and A semiconductor layer electrically connected to the M source branches and N drain branches of each of the source and drain cells, wherein the semiconductor layer includes a plurality of sub-channel regions located in each of the P source and drain cells, each of the plurality of sub-channel regions being located between adjacent drain branches and source branches; The sum of the widths of the multiple sub-channel regions of the P source-drain units in the first direction is W, and the average length of the multiple sub-channel regions of the P source-drain units in the direction perpendicular to the first direction is L. 12≤W / L≤400, P, M and N are all integers greater than or equal to 1, P×N ≥ 4.

2. The thin-film transistor according to claim 1, wherein, 112≤ W / L≤ 400, P×N≥ 6.

3. The thin-film transistor according to claim 2, wherein, P ≥ 3 and N ≥ 2.

4. The thin-film transistor according to claim 2, wherein, P×N≥ 12.

5. The thin-film transistor according to claim 2, wherein, P×N≥ 16.

6. The thin-film transistor according to claim 2, wherein, 235≤ W / L≤ 400, P×N≥ 32.

7. The thin-film transistor according to claim 1, wherein, W / L <180, where W ranges from 10μm to 1600μm.

8. The thin-film transistor according to claim 1, wherein, W / L >180, where L ranges from 4μm to 15μm.

9. The thin-film transistor according to any one of claims 1-8, wherein, The plurality of source-drain cells are arranged in at least one cell row, and each cell row in the at least one cell row includes at least one source-drain cell; In the same cell row, the distance between adjacent source and drain cells is d, W≥500μm, and the range of d is 50μm~500μm.

10. The thin-film transistor according to any one of claims 1-8, wherein, The plurality of source-drain cells are arranged in at least one cell row, and each cell row in the at least one cell row includes at least one source-drain cell; In the same cell row, the distance between adjacent source and drain cells is d, where W < 500 μm, and d ranges from 20 μm to 300 μm.

11. The thin-film transistor according to any one of claims 1-8, wherein, The plurality of source / drain cells are arranged in at least two cell rows, and each cell row in the at least one cell row includes at least one source / drain cell.

12. The thin-film transistor according to any one of claims 1-8, wherein, The semiconductor layer includes a sub-section overlapping with each of the plurality of source and drain cells, the sub-section including Q semiconductor branches, and the plurality of sub-channel regions including sub-channel cells of the Q semiconductor branches located between adjacent source and drain branches, where Q is an integer greater than or equal to 1. W is the sum of the widths of the sub-channel cells of the Q semiconductor branches of the P source / drain cells in the first direction, and L is the average length of the plurality of sub-channel cells of the P source / drain cells in the direction perpendicular to the first direction.

13. The thin-film transistor according to any one of claims 1-8, wherein, The semiconductor layer includes a sub-section overlapping with each of the plurality of source / drain cells, and the plurality of sub-sections overlapping with the source / drain cells constitute a continuous, integrated structure.

14. The thin-film transistor according to any one of claims 1-8, wherein, The plurality of source-drain cells are disposed in the region between adjacent source and drain traces to arrange the plurality of source-drain cells into at least two cell rows, each of the at least two cell rows including at least one source-drain cell. The source branches of at least one source-drain cell within each cell row are electrically connected to the same source trace, and the drain branches of at least one source-drain cell within each cell row are electrically connected to the same drain trace.

15. A shift register unit comprising a thin-film transistor according to any one of claims 1-14.

16. The shift register unit according to claim 15, wherein, The gate row driving circuit includes an input circuit, an output circuit, and a first node reset circuit. The input circuit is connected to the first node and configured to charge the first node in response to an input signal; the output circuit is connected to the first node and configured to output an output signal at the output terminal under the control of the level signal of the first node; the first node reset circuit is connected to the first node and configured to reset the first node in response to a reset signal. The output circuit, the input circuit, and the first node reset circuit all include the thin-film transistor according to claim 1.

17. The shift register unit according to claim 16, wherein, The output terminal includes a shift output terminal and a scan signal output terminal; the output circuit includes a first output transistor and a second output transistor. The gate of the first output transistor is connected to the first node, the first terminal of the first output transistor is connected to the clock signal terminal to receive the clock signal, and the second terminal of the first output transistor is connected to the shift output terminal; the gate of the second output transistor is connected to the first node, the first terminal of the second output transistor is connected to the clock signal terminal to receive the clock signal, and the second terminal of the second output transistor is connected to the scan signal output terminal; the clock signal is transmitted to the output terminal as the output signal; Both the first output transistor and the second output transistor are thin-film transistors according to claim 1; Both the first output transistor and the second output transistor satisfy P ≥ 3 and N ≥ 2, or, Both the first output transistor and the second output transistor satisfy P×N≥ 12, or, Both the first output transistor and the second output transistor satisfy P×N≥ 16.

18. The shift register unit according to claim 17, wherein, The first output transistor satisfies 235 ≤ W / L ≤ 400 and P×N ≥ 32.

19. A gate driving circuit, comprising a shift register unit according to any one of claims 15-18, wherein, The gate drive circuit includes multiple cascaded shift register units; Except for the shift register units from level 1 to level s, the precharge control terminals of the remaining shift register units are connected to the output terminals of the upper-level shift register units that are at least level s away from them; Except for the shift register units from level 1 to level s, the input terminals of the remaining shift register units are connected to the output terminals of the shift register units at level s-1. Except for the last s-stage shift register unit, the reset terminals of all other shift register units are connected to the output terminals of the next shift register unit that is s-1 stages below it. Where s is an integer greater than 2.

20. A display panel comprising the gate driving circuit of claim 19.

21. The display panel of claim 20, wherein, The display panel includes a display area and a non-display area that at least partially surrounds the display area; The non-display area includes: A gate drive circuit region, extending longitudinally, is provided with the gate drive circuit, wherein the plurality of cascaded shift register units are arranged along the longitudinal direction; and The circuit lead area is provided with circuit leads that extend laterally along the longitudinal direction and are adjacent to the gate driving circuit area. The circuit leads include a first lead connected to the gate driving circuit and a second lead connected to the display area. The plurality of cascaded shift register units include an end shift register unit located at one end of the circuit region near the circuit lead region; In each of the shift registers, the output terminal includes a shift output terminal and a scan signal output terminal; the output circuit includes a first output transistor and a second output transistor; The gate of the first output transistor is connected to the first node, the first terminal of the first output transistor is connected to the clock signal terminal to receive the clock signal, and the second terminal of the first output transistor is connected to the shift output terminal; the gate of the second output transistor is connected to the first node, the first terminal of the second output transistor is connected to the clock signal terminal to receive the clock signal, and the second terminal of the second output transistor is connected to the scan signal output terminal; the clock signal is transmitted to the output terminal as the output signal; Both the first output transistor and the second output transistor are thin-film transistors according to claim 1; The P×N values ​​of the first output transistor in the end shift register unit and the second output transistor in the end shift register unit are respectively greater than the P×N values ​​of the first output transistors in the other shift register units in the plurality of cascaded shift register units and the P×N value of the second output transistor in the end shift register unit.

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