JFET device

Abstract

A JFET device is disclosed. A gate lead structure formation region has a gate lead trench formed therein and in communication with a unit trench. A second conductivity type doped gate connection region is formed at the bottom of the gate lead trench. The gate connection region is in contact with the gate region at the bottom of each unit trench and the surface of the gate region has a metal silicide formed thereon. A barrier layer is formed at the bottom of a gate contact hole in the gate lead structure formation region and in contact with the gate contact hole. A first PN junction is formed between the barrier layer and the gate connection region. The top of the gate contact hole is connected to the gate. When the device is off, the gate voltage forward biases the first PN junction and the gate voltage is transmitted to the gate region through the gate connection region. When the device is on, the gate voltage reverse biases the first PN junction to prevent charge from the gate region from leaking to the gate and to prevent fluctuations in the gate voltage from being transmitted to the gate region.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a JFET device. Background Technology

[0002] The structure of a SiC JFET chip mainly consists of a trench unit cell region (device cell region) and an outer gate connection structure region (gate lead-out structure formation region). During turn-off, the gate drive applies a negative voltage through the gate bus. The gate connects to the pwell (gate region) of the unit cell region through a self-aligned metal silicide layer on the SiC surface. The reverse bias between the pwell and the source region pinches off the current path from the source to the drain region, thus turning off the device. During turn-on, the gate voltage returns to zero bias, and a large portion of the reverse bias charge in the pwell returns to the gate bus and enters the gate drive. This process introduces two problems: 1. The additional current increases the gate drive power consumption; 2. More seriously, the return current causes oscillations in the drive circuit.

[0003] like Figure 1 The figure shows the edge of an existing JFET device. Figure 3 A schematic diagram of the cross-sectional structure at line AA1 in the diagram; as shown. Figure 2 The figure shows the edge of an existing JFET device. Figure 3 A schematic diagram of the cross-sectional structure at line AA2 in the middle; as shown. Figure 3 The diagram shown is a top view of an existing JFET device. Taking an N-type device as an example, the existing JFET device has a device cell structure formed in the device cell region.

[0004] like Figure 1 As shown, the device unit structure includes: two unit trenches 102 formed in the top region of an N-type lightly doped semiconductor substrate 101, and the semiconductor substrate 101 located between the unit trenches 102 forms a platform region 103.

[0005] P-type doped gate regions 104 are formed in the semiconductor substrate 101 at the side and bottom surfaces of the cell trench 102. The gate regions 104 are typically formed using p-wells.

[0006] An N-type heavily doped source region 105 is formed on the top surface of the platform region 103.

[0007] The semiconductor substrate 101 located at the bottom of the source region 105 and between the gate region 104 forms a channel region, and the semiconductor substrate 101 at the bottom of the channel region forms a drift region.

[0008] A gate lead-out structure formation region is provided on the outside of the device cell region.

[0009] like Figure 2 As shown, a gate lead-out trench 112 is formed in the gate lead-out structure forming region; the width of the gate lead-out trench 112 is greater than the width of the unit trench 102, and each of the unit trenches 102 is connected to the gate lead-out trench 112.

[0010] A P-type doped gate connection region 113 is formed in the semiconductor substrate 101 at the bottom surface of the gate lead-out trench 112, and the gate region 104 at the bottom of each unit trench 102 is in contact with and connected to the gate connection region 113. Figure 2 In the cross-section shown, the gate region 104 and the gate connection region 113 are an integral structure. Metal silicide 111 is formed on the surface of each of the gate regions 104 and the gate connection region 113.

[0011] A gate contact hole 109b is formed in the gate lead-out structure forming region, and the top of the gate contact hole 109b is connected to the gate composed of the front metal layer. Figure 2 The front metal layer shown is the gate, which is indicated by the symbol 110b. Figure 2 The gate mentioned in the text is also called the gate bus, which will eventually be connected to the gate driver. The gate voltage will be applied to the gate first, and then transmitted to the gate connection area 113 and the gate area 104.

[0012] When the device is turned off, the gate voltage is transmitted through the gate connection region 113 to the gate region 104 and reverse biases the gate region 104 and the channel region to achieve the device turn-off.

[0013] When the device is turned on, the charge in the gate region 104, such as reverse-biased charge, will be discharged to the gate through the gate connection region 113. This forward biases the gate region 104 and the channel region, causing the channel region to conduct. Therefore, at this time, there will be a charge discharge path from the gate region 104 to the gate, i.e., a return current to the gate will be formed. This will have an adverse effect on the gate circuit, as mentioned above, increasing gate drive power consumption and causing oscillations in the drive circuit. Summary of the Invention

[0014] The technical problem to be solved by the present invention is to provide a JFET device that can eliminate the return of charge in the gate region to the gate when the device is turned on, thereby reducing the extra current and oscillation in the gate circuit, and also preventing voltage fluctuations in the gate from being transmitted to the gate region when the device is turned on, thereby damping the oscillation of the gate circuit.

[0015] To solve the above-mentioned technical problems, the JFET device provided by the present invention has a device cell structure formed in the device cell region. The device cell structure includes: two cell trenches formed in the top region of a lightly doped semiconductor substrate of a first conductivity type, and the semiconductor substrate located between the cell trenches forms a platform region.

[0016] A gate region doped with a second conductivity type is formed in the semiconductor substrate at the side and bottom surfaces of the cell trench.

[0017] A source region heavily doped with a first conductivity type is formed on the top surface of the platform region.

[0018] The semiconductor substrate located at the bottom of the source region and between the gate region forms a channel region, and the semiconductor substrate at the bottom of the channel region forms a drift region.

[0019] A gate lead-out structure formation region is provided on the outside of the device cell region.

[0020] A gate lead-out trench is formed in the gate lead-out structure forming region; the width of the gate lead-out trench is greater than the width of the unit trench, and each unit trench is connected to the gate lead-out trench.

[0021] A gate connection region doped with a second conductivity type is formed in the semiconductor substrate at the bottom surface of the gate lead-out trench, and the gate region at the bottom of each unit trench is in contact with the gate connection region.

[0022] Metal silicide is formed on the surface of the gate region at the bottom of each of the cell trenches.

[0023] A gate contact hole is formed in the gate lead-out structure forming region, and a barrier layer of a first conductivity type is formed on the surface of the gate connection region at the bottom of the gate contact hole; the bottom surface of the gate contact hole and the top surface of the barrier layer are in contact, and a first PN junction is formed between the barrier layer and the gate connection region.

[0024] The top of the gate contact hole is connected to the gate, which is composed of a front metal layer.

[0025] When the device is turned off, the gate voltage forward biases the first PN junction, allowing the gate voltage to be transmitted through the gate connection region to the gate region and reverse biasing the gate region and the channel region to achieve device turn-off.

[0026] When the device is turned on, the gate voltage reverse-biases the first PN junction to prevent charge leakage from the gate region to the gate and to prevent fluctuations in the gate voltage from being transmitted to the gate region.

[0027] A further improvement is that both the cell trench and the gate lead-out trench are filled with a first dielectric layer, and the gate contact hole passes through the first dielectric layer.

[0028] A further improvement is that there is a gap between the gate contact hole and the gate region; in the gap region between the gate contact hole and the gate region, the surface of the gate connection region is wholly or partially free of the metal silicide, and the gate connection region free of the metal silicide forms a gate path resistor to control the charging and discharging current of the gate region.

[0029] A further improvement is that, in the space between the gate contact hole and the gate region, when the surface portion of the gate connection region is not provided with the metal silicide, the region where the metal silicide is provided is adjacent to the device cell region, and the metal silicide on the surface of the gate connection region is in contact with the metal silicide on the surface of the gate region.

[0030] A further improvement is that the metal silicide is not disposed on the entire surface of the gate connection region outside the gate contact hole.

[0031] A further improvement is that a lightly doped source side region of a first conductivity type is also formed on the side of the gate region on the side of the cell trench, and the bottom surface of the source side region is located above the bottom surface of the gate region at the bottom of the bottom surface of the cell trench.

[0032] A further improvement is that the JFET device is composed of multiple of the aforementioned device unit structures connected in parallel.

[0033] The platform regions of each of the device unit structures are arranged in parallel, and each of the unit trenches corresponding to each of the device unit structures is connected to the gate lead-out trench.

[0034] A further improvement is that an active contact hole is formed on the top of the source region in each of the platform regions, and the top of the source contact hole is connected to the source electrode composed of the front metal layer.

[0035] A further improvement is that, along the width direction of the platform area, the width edges of each of the source contact holes are aligned and spaced apart from the inner edge of the gate lead-out trench.

[0036] A further improvement is that a heavily doped drain region of a first conductivity type is formed on the back side of the drift region.

[0037] A further improvement is that the material of the first dielectric layer includes an oxide layer.

[0038] A further improvement is that the first dielectric layer is composed of an interlayer film; the interlayer film also extends to the surface of the semiconductor substrate outside the cell trenches and the gate lead-out trenches.

[0039] A further improvement is that the semiconductor substrate is made of SiC.

[0040] A further improvement is that the JFET device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the JFET device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0041] In this invention, a barrier layer doped with a first conductivity type is formed on the surface of the gate connection region at the bottom of the gate contact hole. A first PN junction is formed between the barrier layer and the gate connection region. The gate contact hole is connected to the gate. Thus, a first PN junction exists on the path from the gate formed by the front metal layer to the gate region of the device cell region. The polarity of the bias voltage across the first PN junction is exactly opposite to the polarity of the bias voltage across the PN junction between the gate region and the channel region. That is, when the first PN junction is forward biased, the PN junction between the gate region and the channel region is reverse biased; when the first PN junction is reverse biased, the PN junction between the gate region and the channel region is forward biased. This achieves the following: When the device is off, the PN junction between the gate region and the channel region will be reverse biased. At this time, the first PN junction is forward biased, so the gate voltage will be applied to the gate region normally, and thus will not have an adverse effect on the device's turn-off.

[0042] When the device is turned on, the PN junction between the gate region and the channel region is forward biased. At this time, the first PN junction is reverse biased. Therefore, the first PN junction will block the charge in the gate region, such as the reverse bias charge, from returning to the gate, thereby reducing the extra current and oscillation in the gate circuit. At this time, the reverse bias charge in the gate region will be discharged into the main circuit between the source and drain. Since the main circuit current is large, the discharge current of the reverse bias charge in the gate region has a negligible effect on the main circuit current.

[0043] Meanwhile, in this invention, when the device is turned on, the reverse-biased first PN junction can also block the voltage fluctuation of the gate from being transmitted to the gate region, thereby damping the oscillation of the gate circuit.

[0044] The embodiments of the present invention can further reduce the formation area of ​​metal silicide, so that the surface of the gate connection region in the gap area between the gate contact hole and the gate region is not provided with metal silicide in all or part. Since the resistance will increase after the metal silicide is not provided, a gate path resistance will be formed. The gate path resistance will further block the current in the current path between the gate region and the gate, thereby controlling the charging and discharging current of the gate region. Attached Figure Description

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 It is the edge of existing JFET devices Figure 3 A schematic diagram of the cross-sectional structure at line AA1 in the middle; Figure 2 It is the edge of existing JFET devices Figure 3 A schematic diagram of the cross-sectional structure at line AA2 in the middle; Figure 3 This is a top view of an existing JFET device. Figure 4 This is the edge of the JFET device in the embodiment of the present invention. Figure 6 A schematic diagram of the cross-sectional structure at line AA1 in the middle; Figure 5 This is the edge of the JFET device in the embodiment of the present invention. Figure 6 A schematic diagram of the cross-sectional structure at line AA2 in the middle; Figure 6 This is a top view structural diagram of the JFET device according to an embodiment of the present invention. Detailed Implementation

[0046] like Figure 4 As shown, this is the edge of the JFET device in an embodiment of the present invention. Figure 6 A schematic diagram of the cross-sectional structure at line AA1 in the diagram; as shown. Figure 5 As shown, this is the edge of the JFET device in an embodiment of the present invention. Figure 6 A schematic diagram of the cross-sectional structure at line AA2 in the middle; as shown. Figure 6 The diagram shown is a top view of the JFET device according to an embodiment of the present invention; a device cell structure is formed in the device cell region of the JFET device according to an embodiment of the present invention.

[0047] like Figure 4 As shown, the device unit structure includes: two unit trenches 202 formed in the top region of a lightly doped semiconductor substrate 201 of a first conductivity type, and the semiconductor substrate 201 located between the unit trenches 202 forms a platform region 203.

[0048] A gate region 204 doped with a second conductivity type is formed in the semiconductor substrate 201 at the side and bottom surfaces of the unit trench 202.

[0049] A source region 205 heavily doped with a first conductivity type is formed on the top surface of the platform region 203.

[0050] The semiconductor substrate 201 located at the bottom of the source region 205 and between the gate region 204 forms a channel region, and the semiconductor substrate 201 at the bottom of the channel region forms a drift region.

[0051] A gate lead-out structure formation region is provided on the outside of the device cell region.

[0052] like Figure 5 As shown, a gate lead-out trench 212 is formed in the gate lead-out structure forming region; the width of the gate lead-out trench 212 is greater than the width of the unit trench 202, and each of the unit trenches 202 is connected to the gate lead-out trench 212.

[0053] A gate connection region 213 doped with a second conductivity type is formed in the semiconductor substrate 201 at the bottom surface of the gate lead-out trench 212, and the gate region 204 at the bottom of each unit trench 202 is in contact with and connected to the gate connection region 213. Figure 5 In the cross-section shown, the gate region 204 and the gate connection region 213 are an integral structure.

[0054] Metal silicide 211 is formed on the surface of the gate region 204 at the bottom of each of the unit trenches 202. The metal silicide 211 is typically formed by a self-aligned metal silicide process, and is therefore also called a self-aligned metal silicide or salicide.

[0055] A gate contact hole 209b is formed in the gate lead-out structure forming region. A barrier layer 214 of the first conductivity type is formed on the surface of the gate connection region 213 at the bottom of the gate contact hole 209b. The bottom surface of the gate contact hole 209b and the top surface of the barrier layer 214 are in contact. A first PN junction is formed between the barrier layer 214 and the gate connection region 213.

[0056] The top of the gate contact hole 209b is connected to the gate composed of a front metal layer. Figure 5 The front metal layer shown is the gate, which is indicated by the symbol 210b.

[0057] When the device is turned off, the gate voltage forward biases the first PN junction, and the gate voltage is transmitted through the gate connection region 213 to the gate region 204, causing the gate region 204 and the channel region to be reverse biased to achieve the device turn-off.

[0058] When the device is turned on, the gate voltage reverse-biases the first PN junction to prevent charge leakage from the gate region 204 to the gate and to prevent fluctuations in the gate voltage from being transmitted to the gate region 204.

[0059] In this embodiment of the invention, both the unit trench 202 and the gate lead-out trench 212 are filled with a first dielectric layer 207, and the gate contact hole 209b passes through the first dielectric layer 207. Figure 4In this process, the first dielectric layer 207 will completely fill the unit trench 202; Figure 5 In this process, because the width of the gate lead-out trench 212 is relatively wide, the first dielectric layer 207 does not completely fill the gate lead-out trench 212.

[0060] There is a gap between the gate contact hole 209b and the gate region 204; in the gap region between the gate contact hole 209b and the gate region 204, the surface of the gate connection region 213 is not provided with the metal silicide 211 in whole or in part, and the gate connection region 213 without the metal silicide 211 on its surface forms a gate path resistor R1 to control the charging and discharging current of the gate region 204.

[0061] In the space between the gate contact hole 209b and the gate region 204, when the surface portion of the gate connection region 213 is not provided with the metal silicide 211, the area where the metal silicide 211 is provided is adjacent to the device cell region, and the metal silicide 211 on the surface of the gate connection region 213 is in contact with the metal silicide 211 on the surface of the gate region 204.

[0062] The metal silicide 211 is not disposed on the entire surface of the gate connection region 213 outside the gate contact hole 209b. Figure 6 As shown, the area indicated by curly braces 215 is the formation region of the metal silicide 211. It can be seen that the formation region of the metal silicide 211 includes the entire device cell region and extends to the bottom of the gate trench 212. No metal silicide 211 is formed in other areas.

[0063] In this embodiment of the invention, returning to Figure 4 As shown, a lightly doped source side region 206 of the first conductivity type is also formed on the side of the gate region 204 on the side of the unit trench 202. The bottom surface of the source side region 206 is located above the bottom surface of the gate region 204 at the bottom of the bottom surface of the unit trench 202.

[0064] A JFET device is composed of multiple such device unit structures connected in parallel.

[0065] like Figure 6 As shown, the platform regions 203 of each device unit structure are arranged in parallel, and each unit trench 202 corresponding to each device unit structure is connected to the gate lead-out trench 212.

[0066] Back Figure 4As shown, an active contact hole 209a is formed on the top of the source region 205 of each of the platform regions 203, and the top of the source contact hole 209a is connected to the source electrode composed of the front metal layer. Figure 4 The front metal layer shown in the figure is the source electrode, which is indicated by the symbol 210a.

[0067] Along the width direction of the platform region 203, the width edges of each source contact hole 209a are aligned and spaced from the inner edge of the gate lead-out groove 212. For example... Figure 6 As shown, the formation area of ​​the source contact hole 209a is the intersection area of ​​the dashed frame 209 and the platform area 203. It can be seen that the dashed frame 209 and the inner edge of the gate lead-out groove 212 are spaced apart.

[0068] In this embodiment of the invention, a heavily doped drain region (not shown) of a first conductivity type is formed on the back side of the drift region.

[0069] The material of the first dielectric layer 207 includes an oxide layer. Preferably, the first dielectric layer 207 is composed of an interlayer film 208; the interlayer film 208 also extends to the surface of the semiconductor substrate 201 outside the cell trench 202 and the gate lead-out trench 212.

[0070] In this embodiment of the invention, the semiconductor substrate 201 is made of SiC. The JFET device is a SiC JFET device. In other embodiments, the semiconductor substrate 201 may also be made of other semiconductor materials such as silicon, germanium-silicon, etc.

[0071] In this embodiment of the invention, the JFET device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the JFET device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0072] In this embodiment of the invention, a barrier layer 214 doped with a first conductivity type is formed on the surface of the gate connection region 213 at the bottom of the gate contact hole 209b. A first PN junction is formed between the barrier layer 214 and the gate connection region 213. The gate contact hole 209b is connected to the gate. Thus, a first PN junction exists on the path from the gate formed by the front metal layer to the gate region 204 of the device cell region. The polarity of the bias voltage across the first PN junction is exactly opposite to the polarity of the bias voltage across the PN junction between the gate region 204 and the channel region. That is, when the first PN junction is forward biased, the PN junction between the gate region 204 and the channel region is reverse biased; when the first PN junction is reverse biased, the PN junction between the gate region 204 and the channel region is forward biased. This achieves the following: When the device is off, the PN junction between the gate region 204 and the channel region will be reverse biased. At this time, the first PN junction is forward biased, so the gate voltage will be applied to the gate region 204 normally, and thus will not have an adverse effect on the device's turn-off.

[0073] When the device is turned on, the PN junction between the gate region 204 and the channel region is forward biased. At this time, the first PN junction is reverse biased. Therefore, the first PN junction will block the charge in the gate region 204 from returning to the gate, thereby reducing the extra current and oscillation in the gate circuit. At this time, the reverse bias charge in the gate region 204 will be discharged into the main circuit between the source and drain. Since the main circuit current is large, the discharge current of the reverse bias charge in the gate region 204 has a negligible effect on the main circuit current.

[0074] Meanwhile, in this embodiment of the invention, when the device is turned on, the first PN junction, which can also be reverse biased, can also block the voltage fluctuation of the gate from being transmitted to the gate region 204, thereby damping the oscillation of the gate circuit.

[0075] The embodiments of the present invention can further reduce the formation area of ​​the metal silicide 211, so that the surface of the gate connection region 213 in the space between the gate contact hole 209b and the gate region 204 is not provided with the metal silicide 211 in whole or in part. Since the resistance will increase after the metal silicide 211 is not provided, the gate path resistance R1 will be formed. The gate path resistance R1 will further block the current in the current path between the gate region 204 and the gate, thereby controlling the charging and discharging current of the gate region 204.

[0076] In this embodiment of the invention, by reducing the area of ​​the saclide to create a certain distance between it and the gate bus, a controllable path resistance, namely the gate path resistance R1, is introduced to further control the charging and discharging current. Secondly, in this embodiment, a barrier layer, namely the blocking layer 214, is injected into the gate contact hole 209b region. Taking an N-type device as an example, the n-type barrier layer and the pwell, i.e., the gate region 204, form an np junction. During the JFET turn-off process, the negative voltage of the gate causes this np junction to be forward biased, and the charging current normally charges the pwell, turning off the cell. At this time, the pwell / source, i.e., the source region 205, is reverse biased, and the potential increases from the gate to the source. When the gate driver sends an on-signal, the barrier formed by the barrier layer and the pwell prevents the charge (negative) from flowing to the gate circuit. This charge is mainly discharged to the main circuit through the pwell / source. Compared to the driver circuit, the impact of this magnitude of current on the main circuit is negligible. This effectively reduces the additional current and oscillation in the gate circuit. At the same time, any positive bias voltage fluctuations in the gate drive circuit will be prevented from entering the pwell, which dampens the circuit oscillation.

[0077] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A JFET device, characterized in that: A device unit structure is formed in the device unit region, the device unit structure including: two unit trenches formed in the top region of a lightly doped semiconductor substrate of a first conductivity type, and the semiconductor substrate located between the unit trenches forming a platform region; A gate region doped with a second conductivity type is formed in the semiconductor substrate at the side and bottom surfaces of the unit trench; A heavily doped source region of the first conductivity type is formed on the top surface of the platform region; The semiconductor substrate located at the bottom of the source region and between the gate region forms a channel region, and the semiconductor substrate at the bottom of the channel region forms a drift region; A gate lead-out structure formation region is provided on the outer side of the device cell region; A gate lead-out trench is formed in the gate lead-out structure forming region; the width of the gate lead-out trench is greater than the width of the unit trench, and each unit trench is connected to the gate lead-out trench. A gate connection region doped with a second conductivity type is formed in the semiconductor substrate at the bottom surface of the gate lead-out trench, and the gate region at the bottom of each unit trench is in contact with and connected to the gate connection region. Metal silicide is formed on the surface of the gate region at the bottom of each of the unit trenches; A gate contact hole is formed in the gate lead-out structure forming region, and a barrier layer of a first conductivity type is formed on the surface of the gate connection region at the bottom of the gate contact hole; the bottom surface of the gate contact hole and the top surface of the barrier layer are in contact, and a first PN junction is formed between the barrier layer and the gate connection region; The top of the gate contact hole is connected to the gate, which is composed of a front metal layer; When the device is turned off, the gate voltage forward biases the first PN junction, allowing the gate voltage to be transmitted through the gate connection region to the gate region and reverse biasing the gate region and the channel region to achieve device turn-off. When the device is turned on, the gate voltage reverse-biases the first PN junction to prevent charge leakage from the gate region to the gate and to prevent fluctuations in the gate voltage from being transmitted to the gate region.

2. The JFET device as described in claim 1, characterized in that: Both the cell trench and the gate lead-out trench are filled with a first dielectric layer, and the gate contact hole passes through the first dielectric layer.

3. The JFET device as described in claim 2, characterized in that: There is a gap between the gate contact hole and the gate region; in the gap region between the gate contact hole and the gate region, the surface of the gate connection region is not provided with the metal silicide in whole or in part, and the gate connection region without the metal silicide on the surface forms a gate path resistor to control the charging and discharging current of the gate region.

4. The JFET device as described in claim 3, characterized in that: In the space between the gate contact hole and the gate region, when the surface portion of the gate connection region is not provided with the metal silicide, the region where the metal silicide is provided is adjacent to the device cell region, and the metal silicide on the surface of the gate connection region is in contact with the metal silicide on the surface of the gate region.

5. The JFET device as described in claim 3, characterized in that: The metal silicide is not disposed on the surface of the gate connection region outside the gate contact hole.

6. The JFET device as claimed in claim 1, characterized in that: A lightly doped source side region of a first conductivity type is also formed on the side of the gate region on the side of the cell trench, and the bottom surface of the source side region is located above the bottom surface of the gate region at the bottom of the bottom surface of the cell trench.

7. The JFET device as claimed in claim 1, characterized in that: A JFET device is composed of multiple device unit structures connected in parallel; The platform regions of each of the device unit structures are arranged in parallel, and each of the unit trenches corresponding to each of the device unit structures is connected to the gate lead-out trench.

8. The JFET device as claimed in claim 7, characterized in that: An active contact hole is formed on the top of the source region in each of the platform regions, and the top of the source contact hole is connected to the source electrode composed of a front metal layer.

9. The JFET device as claimed in claim 8, characterized in that: Along the width direction of the platform area, the width edges of each of the source contact holes are aligned and spaced apart from the inner edge of the gate lead-out trench.

10. The JFET device as claimed in claim 1, characterized in that: A heavily doped drain region of the first conductivity type is formed on the back side of the drift region.

11. The JFET device as claimed in claim 2, characterized in that: The material of the first dielectric layer includes an oxide layer.

12. The JFET device as claimed in claim 11, characterized in that: The first dielectric layer is composed of an interlayer film; the interlayer film also extends to the surface of the semiconductor substrate outside the cell trench and the gate lead-out trench.

13. The JFET device as claimed in claim 1, characterized in that: The semiconductor substrate is made of SiC.

14. The JFET device according to any one of claims 1 to 11, characterized in that: The JFET device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the JFET device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

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