Semiconductor structure and method of forming the same
Patent Information
- Application Number
- CN202510422211.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2026-10-16
AI Technical Summary
[0004]然而，当前的高压器件还存在不足
[0019] In the semiconductor structure formation method of the present invention, the barrier sidewall is located on the sidewall of the first gate and the gate oxide layer, and the barrier sidewall protects the gate oxide layer between the substrate and the first gate and the gate oxide layer located below the barrier sidewall. When light doping drain implantation is performed on the substrate on both sides of the first gate to form the lightly doped region, since the barrier sidewall protects the gate oxide layer between the substrate and the first gate and the gate oxide layer located below the barrier sidewall, the loss of the gate oxide layer between the substrate and the first gate caused by light doping drain implantation is reduced, improving the quality and integrity of the gate oxide layer between the substrate and the first gate, thereby improving the reliability of the semiconductor device; moreover, this solution can achieve a significant improvement in device performance without major modifications, has low process cost, high practical value, and strong market competitiveness.
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Figure CN122934873A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Flash memory has been widely used in non-volatile memory due to its advantages of high density, low price, and programmability and erasure.
[0003] With the development of flash memory technology, Nor Flash technology has been widely used in automotive electronics (Microcontroller Units, or MCUs), smart cards, and IoT devices. NOR flash memory utilizes high-voltage devices and core components. The high-voltage devices can provide voltages such as 5.0V, which are used for programming and erasing the flash memory cells. The core components are mainly logic devices operating at 3.3V or 1.8V. The reliability of these high-voltage devices is of paramount importance.
[0004] However, current high-voltage devices still have shortcomings. Summary of the Invention
[0005] The problem addressed by this invention is how to improve the process flow to enhance the reliability of high-voltage devices.
[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a gate oxide layer on the substrate, the substrate including a first region; forming a first gate on the first region; forming a protective layer on the first region; etching the protective layer of the first region to form a barrier sidewall, the barrier sidewall being located on the sidewall of the first gate and the gate oxide layer; and after forming the barrier sidewall, performing light doping drain implantation on the substrate on both sides of the first gate to form a lightly doped region in the substrate below the first gate.
[0007] Optionally, in the step of providing a substrate and a gate oxide layer on the substrate, the substrate further includes a second region, wherein the substrate in the first region is suitable for forming a first type device, and the substrate in the second region is suitable for forming a second type device, wherein the first type device is one of a P-type device and an N-type device, and the second type device is the other of a P-type device and an N-type device; in the step of forming a protective layer on the first region, a protective layer is formed on the first region and the second region; further comprising: after forming the protective layer on the first region and before etching the protective layer on the first region, removing the protective layer on the second region to expose the substrate in the second region; and forming the second type device on the exposed second region.
[0008] Optionally, the substrate includes a core region and a logic region, the logic region including the first region and the second region.
[0009] Optionally, it further includes: before performing light doping drain implantation on the substrates on both sides of the first gate to form a lightly doped region in the substrate below the first gate, thinning the barrier sidewall and the gate oxide layer exposed by the first gate; in the step of forming a lightly doped region in the substrate below the first gate, performing light doping drain implantation on the substrate on the side of the barrier sidewall away from the first gate to form a lightly doped region in the substrate below the first gate.
[0010] Optionally, in the step of lightly doped drain implantation of the substrate on the side of the barrier sidewall away from the first gate, the thinned gate oxide layer is used as a protection to perform lightly doped drain implantation on the substrate on the side of the barrier sidewall away from the first gate.
[0011] Optionally, it further includes: after performing light doping drain implantation on the substrates on both sides of the first gate to form a lightly doped region in the substrate below the first gate, removing the barrier sidewall.
[0012] Optionally, it also includes: forming a sidewall on the sidewall of the first gate after removing the blocking sidewall.
[0013] Optionally, the material of the barrier sidewall includes silicon nitride.
[0014] Optionally, the thickness of the barrier sidewall is in the range of 70 angstroms to 80 angstroms.
[0015] Optionally, the doping concentration range of the lightly doped drain implantation is: 10E13 atom / cm³. 3 ~10E14atom / cm 3 The doping dose range for the lightly doped drain implantation is 10E13 atom / cm². 2 ~10E14atom / cm 2 .
[0016] Optionally, the thickness of the gate oxide layer ranges from 100 angstroms to 120 angstroms.
[0017] Accordingly, the present invention also provides a semiconductor structure comprising: a substrate including a first region and a second region, the first region being adapted to form a first type device and the second region being adapted to form a second type device, wherein the first type device is one of a P-type device and an N-type device, and the second type device is the other of a P-type device and an N-type device; a gate oxide layer on the substrate; a first gate on the first region and a second gate on the second region; a barrier sidewall on the first gate sidewall and the gate oxide layer; and a lightly doped region in the substrate below the first gate, the lightly doped region further extending below the barrier sidewall.
[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0019] In the semiconductor structure formation method of the present invention, the barrier sidewall is located on the sidewall of the first gate and the gate oxide layer, and the barrier sidewall protects the gate oxide layer between the substrate and the first gate and the gate oxide layer located below the barrier sidewall. When light doping drain implantation is performed on the substrate on both sides of the first gate to form the lightly doped region, since the barrier sidewall protects the gate oxide layer between the substrate and the first gate and the gate oxide layer located below the barrier sidewall, the loss of the gate oxide layer between the substrate and the first gate caused by light doping drain implantation is reduced, improving the quality and integrity of the gate oxide layer between the substrate and the first gate, thereby improving the reliability of the semiconductor device; moreover, this solution can achieve a significant improvement in device performance without major modifications, has low process cost, high practical value, and strong market competitiveness.
[0020] In an optional embodiment of the present invention, in the step of providing a substrate and a gate oxide layer on the substrate, the substrate further includes a second region. The substrate in the first region is suitable for forming a first type of device, and the substrate in the second region is suitable for forming a second type of device. The first type of device is one of a P-type device and an N-type device, and the second type of device is the other of a P-type device and an N-type device. In the step of forming a protective layer on the first region, the protective layer is formed on both the first and second regions. The step further includes: after forming the protective layer on the first region and before etching the protective layer on the first region, removing the protective layer on the second region to expose the substrate in the second region; and forming the second type of device on the exposed second region. Removing the protective layer on the second region to expose the substrate in the second region provides a structural basis for forming the second type of device. During the formation of the second type of device, the protective layer also acts as a mask. Using the mask during the formation of the second type of device to form a barrier sidewall eliminates the need for additional film layers, achieving the goal of reducing the loss of the gate oxide layer between the substrate and the first gate with minimal process modifications. This improves the quality and integrity of the gate oxide layer between the substrate and the first gate, significantly enhancing the performance of the semiconductor device. It has high practical value and strong market competitiveness. Attached Figure Description
[0021] Figures 1 to 4 It is a schematic diagram of the various steps in the formation process of a semiconductor structure;
[0022] Figures 5 to 12 This is a schematic diagram of the various steps in the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0023] As can be seen from the background technology, existing high-voltage devices still have shortcomings. The reasons for these problems are analyzed below:
[0024] Please refer to Figure 1 The system provides a substrate 100, a gate oxide material layer 101 on the substrate 100, and a gate 102 on the gate oxide material layer 101.
[0025] Please refer to Figure 2 The gate oxide material layer 101 on the substrate 100 located on both sides of the gate 102 is thinned.
[0026] Please refer to Figure 3 After thinning the gate oxide material layer 101 on the substrate 100 located on both sides of the gate 102, light doping drain implantation is performed on the substrate 100 below the gate 102 to form a lightly doped region 103 located in the substrate 100 below the gate 102.
[0027] Please refer to Figure 4 After forming the lightly doped region 103, a protective layer 104 is formed on the substrate 100 and the gate 102.
[0028] The material of the protective layer 104 includes silicon nitride.
[0029] During the process of lightly doped drain implantation of the substrate 100 below the gate 102 to form a lightly doped region 103 located in the substrate 100 below the gate 102, since the sidewalls of the gate 102 are not protected by sidewalls, the lightly doped drain implantation will consume the gate oxide material layer 101 located below the gate 102 during the lightly doped drain implantation process. This will cause the gate oxide material layer 101 located below the gate 102 to be damaged, affecting the quality of the gate oxide material layer 101 and reducing the reliability of the semiconductor device.
[0030] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a gate oxide layer on the substrate, the substrate including a first region; forming a first gate on the first region; forming a protective layer on the first region; etching the protective layer of the first region to form a barrier sidewall, the barrier sidewall being located on the sidewall of the first gate and the gate oxide layer; and after forming the barrier sidewall, performing light doping drain implantation on the substrate on both sides of the first gate to form a lightly doped region in the substrate below the first gate.
[0031] In the semiconductor structure formation method of the present invention, the barrier sidewall is located on the sidewall of the first gate and the gate oxide layer. The barrier sidewall protects the gate oxide layer between the substrate and the first gate and the gate oxide layer below the barrier sidewall. When light doping drain implantation is performed on the substrate on both sides of the first gate to form the lightly doped region, the barrier sidewall protects the gate oxide layer between the substrate and the first gate and the gate oxide layer below the barrier sidewall, reducing the loss of the gate oxide layer between the substrate and the first gate caused by light doping drain implantation, improving the quality integrity of the gate oxide layer between the substrate and the first gate, and thus improving the reliability of the semiconductor device. Furthermore, this solution can achieve a significant improvement in device performance without major modifications, has low process cost, high practical value, and strong market competitiveness.
[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0033] Figures 5 to 12 This is a schematic diagram of the various steps in the formation process of the semiconductor structure according to an embodiment of the present invention.
[0034] Please refer to Figure 5A substrate 200 and a gate oxide layer 201 located on the substrate 200 are provided, the substrate 200 including a first region I.
[0035] In the step of providing a substrate 200 and a gate oxide layer 201 on the substrate 200, the substrate 200 further includes a second region II, wherein the substrate 200 of the first region I is adapted to form a first type device, and the substrate 200 of the second region II is adapted to form a second type device, wherein the first type device is one of a P-type device and an N-type device, and the second type device is the other of a P-type device and an N-type device.
[0036] The substrate 200 includes a core region and a logic region, the logic region including the first region I and the second region II.
[0037] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium arsenide, silicon on insulator (SOI), or germanium on insulator (GOI). Specifically, in some embodiments of the present invention, the substrate 200 is made of silicon.
[0038] The gate oxide layer 201 is made of silicon oxide. The thickness of the gate oxide layer 201 ranges from 100 angstroms to 120 angstroms.
[0039] Please refer to Figure 6 A first gate 202 is formed on the first region I.
[0040] The first gate 202 provides a basis for forming a first type of device. In some embodiments of the present invention, the channel of the first gate 202 is a P-type channel; in other embodiments of the present invention, the channel of the first gate 202 is an N-type channel.
[0041] Specifically, in some embodiments of the present invention, the material of the first gate 202 includes polycrystalline silicon.
[0042] Please refer to Figure 7 A protective layer 203 is formed on the first region I.
[0043] Specifically, in some embodiments of the present invention, in the step of forming a protective layer 203 on the first region I, a protective layer 203 is formed on the first region I and the second region II.
[0044] The protective layer 203 provides a structural basis for forming the barrier sidewall 205.
[0045] Specifically, in some embodiments of the present invention, the material of the protective layer 203 includes silicon nitride. The thickness of the protective layer 203 ranges from 70 angstroms to 80 angstroms.
[0046] Please refer to Figure 8 After forming a protective layer 203 on the first region I and the second region II, the protective layer 203 on the second region II is removed to expose the substrate 200 of the second region II; the second type of device is formed on the exposed second region II.
[0047] Specifically, in some embodiments of the present invention, a second gate 204 is formed on the exposed second region II. The second gate 204 provides a basis for forming a second type of device.
[0048] Specifically, the protective layer 203 on the second region II is removed to expose the substrate 200 of the second region II, providing a structural basis for the formation of the second gate 204.
[0049] Specifically, during the formation of the second type of device, the protective layer 203 can also act as a mask to protect the first gate 202 located in the first region I.
[0050] The conductivity type of the channel of the second gate 204 is opposite to that of the channel of the first gate 202. In some embodiments of the present invention, the channel of the second gate 204 is an N-type channel and the channel of the first gate 202 is a P-type channel; in other embodiments of the present invention, the channel of the second gate 204 is a P-type channel and the channel of the first gate 202 is an N-type channel.
[0051] Please refer to Figure 9 The protective layer 203 of the first region I is etched to form a barrier sidewall 205, which is located on the sidewall of the first gate 202 and the gate oxide layer 201.
[0052] The barrier sidewall 205 is in contact with the sidewall of the first gate 202 and the gate oxide layer 201. The barrier sidewall 205 protects the gate oxide layer 201 located between the substrate 200 and the first gate 202 and the gate oxide layer 201 located below the barrier sidewall 205.
[0053] By using a mask formed during the second type of device formation process to form a barrier sidewall 205, no additional film layer is required. With minimal process modifications, the loss of the gate oxide layer 201 located between the substrate 200 and the first gate 202 is reduced, thereby improving the quality and integrity of the gate oxide layer 201 located between the substrate 200 and the first gate 202. This significantly improves the performance of the semiconductor device, has high practical value, and strong market competitiveness.
[0054] Specifically, in some embodiments of the present invention, the method for etching the protective layer 203 of the first region I includes dry etching.
[0055] Specifically, in some embodiments of the present invention, the thickness of the barrier sidewall 205 ranges from 70 angstroms to 80 angstroms. The material of the barrier sidewall 205 includes silicon nitride.
[0056] Please refer to Figure 10 The gate oxide layer 201 exposed on the barrier sidewall 205 and the first gate 202 is thinned.
[0057] Thinning the gate oxide layer 201 exposed on the barrier sidewall 205 and the first gate 202 reduces the thickness of the gate oxide layer 201 on the substrate 200 on both sides of the first gate 202, providing a structural basis for light doping and drain implantation of the substrate 200 on both sides of the first gate 202.
[0058] Please refer to Figure 11 After forming the barrier sidewall 205, light doping drain implantation is performed on the substrates 200 on both sides of the first gate 202 to form a lightly doped region 206 located in the substrate 200 below the first gate 202.
[0059] The barrier sidewall 205 is located on the sidewall of the first gate 202 and the gate oxide layer 201. The barrier sidewall 205 protects the gate oxide layer 201 between the substrate 200 and the first gate 202, and the gate oxide layer 201 located below the barrier sidewall 205. When light doping drain implantation is performed on the substrate 200 on both sides of the first gate 202 to form the lightly doped region 206, the barrier sidewall 205 protects the gate oxide layer 201 between the substrate 200 and the first gate 202, and the gate oxide layer 201 located below the barrier sidewall 205. This reduces the loss of the gate oxide layer 201 between the substrate 200 and the first gate 202 caused by light doping drain implantation, improves the quality and integrity of the gate oxide layer 201 between the substrate 200 and the first gate 202, and enhances the reliability of the semiconductor structure.
[0060] Please refer to Figure 11 The barrier sidewall 205 has a side A adjacent to the first gate 202 and a side B away from the first gate 202. In the step of forming a lightly doped region 206 located in the substrate 200 below the first gate 202, a lightly doped drain implantation is performed on the side B of the barrier sidewall 205 away from the first gate 202 to form a lightly doped region 206 located in the substrate 200 below the first gate 202.
[0061] In the step of lightly doped drain implantation of the substrate 200 on the side B away from the first gate 202 of the barrier sidewall 205, the substrate 200 on the side B away from the first gate 202 of the barrier sidewall 205 is lightly doped drain implanted with the thinned gate oxide layer 201 as protection.
[0062] Specifically, in some embodiments of the present invention, the doping concentration range of the lightly doped drain implantation is: 10E13 atom / cm 3 ~10E14atom / cm 3 The doping dose range for the lightly doped drain implantation is 10E13 atom / cm². 2 ~10E14atom / cm 2 .
[0063] The high doping dose of the lightly doped drain implant reduces the possibility of a decrease in the doping concentration of the lightly doped drain region 206 due to the presence of the blocking sidewall 205, thus ensuring the performance stability of the chip.
[0064] Specifically, after forming the barrier sidewall 205, this solution performs light doping drain implantation on the substrates 200 on both sides of the first gate 202, and the light doped drain region 206 extends below the barrier sidewall 205.
[0065] Please refer to Figure 12 After performing light doping drain implantation on the substrates 200 on both sides of the first gate 202 to form a lightly doped region 206 located in the substrate 200 below the first gate 202, the blocking sidewall 205 is removed.
[0066] Specifically, in some embodiments of the present invention, the method for removing the blocking sidewall 205 includes: dry etching.
[0067] The method for forming the semiconductor structure further includes: after removing the blocking sidewall 205, forming a sidewall (not shown) on the sidewall of the first gate 202.
[0068] The device formed by the semiconductor structure formation method is subjected to multiple reliability tests, such as t0.1% lifetime, gate oxide integrity (GOI), time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), negative-bias temperature instability (NBTI), and EM tests. Because the barrier sidewall 205 protects the gate oxide layer 201 between the substrate 200 and the first gate 202 and the gate oxide layer 201 located below the barrier sidewall 205, it reduces the loss of the gate oxide layer 201 between the substrate 200 and the first gate 202 caused by lightly doped drain injection, improves the quality of the gate oxide layer 201 between the substrate 200 and the first gate 202, and improves the reliability of the semiconductor device. Specifically, the time-dependent dielectric breakdown lifetime of the semiconductor structure formed by this solution is increased by 207 times.
[0069] Accordingly, this invention also provides a semiconductor structure, please refer to [the relevant documentation]. Figure 11 The device includes: a substrate 200, the substrate 200 including a first region I and a second region II, the first region I being adapted to form a first type device, the second region II being adapted to form a second type device, wherein the first type device is one of a P-type device and an N-type device, and the second type device is the other of a P-type device and an N-type device; a gate oxide layer 201 located on the substrate 200; a first gate 202 located on the first region I and a second gate 204 located on the second region II; a barrier sidewall 205 located on the sidewall of the first gate 202 and on the gate oxide layer 201; and a lightly doped region 206 located in the substrate 200 below the first gate 202, the lightly doped region 206 further extending below the barrier sidewall 205.
[0070] The semiconductor structure includes a substrate 200, which includes a first region I and a second region II. The first region I is adapted to form a first type of device, and the second region II is adapted to form a second type of device. The first type of device is one of a P-type device and an N-type device, and the second type of device is the other of a P-type device and an N-type device.
[0071] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium arsenide, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Specifically, in some embodiments of the present invention, the substrate 200 is made of silicon.
[0072] The substrate 200 includes a core region and a logic region, the logic region including the first region I and the second region II.
[0073] The semiconductor structure includes a gate oxide layer 201 located on the substrate 200. The material of the gate oxide layer 201 includes silicon oxide. The thickness of the gate oxide layer 201 ranges from 100 angstroms to 120 angstroms.
[0074] The semiconductor structure includes a first gate 202 located on the first region I and a second gate 204 located on the second region II.
[0075] The materials of the first gate 202 and the second gate 204 include polycrystalline silicon.
[0076] The conductivity type of the channel of the second gate 204 is opposite to that of the channel of the first gate 202. In some embodiments of the present invention, the channel of the second gate 204 is an N-type channel and the channel of the first gate 202 is a P-type channel; in other embodiments of the present invention, the channel of the second gate 204 is a P-type channel and the channel of the first gate 202 is an N-type channel.
[0077] The semiconductor structure includes a barrier sidewall 205 located on the sidewall of the first gate 202 and the gate oxide layer 201.
[0078] The thickness of the barrier sidewall 205 ranges from 70 angstroms to 80 angstroms. The material of the barrier sidewall 205 includes silicon nitride.
[0079] The semiconductor structure includes a lightly doped region 206 located in a substrate 200 below the first gate 202, the lightly doped region 206 further extending below the barrier sidewall 205.
[0080] In summary, the barrier sidewall 205 is located on the sidewall of the first gate 202 and the gate oxide layer 201. The barrier sidewall 205 protects the gate oxide layer 201 between the substrate 200 and the first gate 202, as well as the gate oxide layer 201 located below the barrier sidewall 205. When light doping drain implantation is performed on the substrate 200 on both sides of the first gate 202 to form the lightly doped region 206, the barrier sidewall 205 protects the gate oxide layer 201 between the substrate 200 and the first gate 202, reducing the loss of the gate oxide layer 201 between the substrate 200 and the first gate 202 caused by light doping drain implantation. This improves the quality and integrity of the gate oxide layer 201 between the substrate 200 and the first gate 202, thereby improving the reliability of the semiconductor device. Furthermore, this solution can achieve a significant improvement in device performance without major modifications, has low process costs, and high practical value.
[0081] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate and a gate oxide layer located on the substrate are provided, the substrate including a first region; A first gate is formed on the first region; A protective layer is formed on the first region; The protective layer of the first region is etched to form a barrier sidewall, which is located on the sidewall of the first gate and the gate oxide layer; After forming the barrier sidewall, light doping drain implantation is performed on the substrates on both sides of the first gate to form a lightly doped region located in the substrate below the first gate.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate and a gate oxide layer on the substrate, the substrate further includes a second region, wherein the substrate in the first region is suitable for forming a first type device, and the substrate in the second region is suitable for forming a second type device, wherein the first type device is one of a P-type device and an N-type device, and the second type device is the other of a P-type device and an N-type device; In the step of forming a protective layer on the first region, protective layers are formed on the first region and the second region; Also includes: After forming a protective layer on the first region and before etching the protective layer on the first region, the protective layer on the second region is removed to expose the substrate of the second region. The second type of device is formed on the exposed second region.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The substrate includes a core region and a logic region, the logic region including the first region and the second region.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: Before performing light doping drain implantation on the substrates on both sides of the first gate to form a lightly doped region in the substrate below the first gate, the barrier sidewalls and the gate oxide layer exposed by the first gate are thinned. In the step of forming a lightly doped region in the substrate below the first gate, a lightly doped drain implantation is performed on the substrate on the side of the barrier sidewall away from the first gate to form a lightly doped region in the substrate below the first gate.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, In the step of performing light doping drain implantation on the substrate on the side of the barrier sidewall away from the first gate, the thinned gate oxide layer is used as a protection layer to perform light doping drain implantation on the substrate on the side of the barrier sidewall away from the first gate.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After performing light doping drain implantation on the substrates on both sides of the first gate to form a lightly doped region in the substrate below the first gate, the barrier sidewalls are removed.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, Also includes: After the blocking sidewall is removed, a sidewall is formed on the sidewall of the first gate.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the barrier sidewall includes silicon nitride.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the barrier sidewall ranges from 70 angstroms to 80 angstroms.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The doping concentration range for the lightly doped drain implantation is: 10E13atom / cm³. 3 ~10E14atom / cm 3 The doping dose range for the lightly doped drain implantation is 10E13 atom / cm². 2 ~10E14atom / cm 2 .
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the gate oxide layer ranges from 100 angstroms to 120 angstroms.
12. A semiconductor structure, characterized in that, include: A substrate comprising a first region and a second region, the first region being adapted to form a first type of device, the second region being adapted to form a second type of device, wherein the first type of device is one of a P-type device and an N-type device, and the second type of device is the other of a P-type device and an N-type device; Gate oxide layer located on the substrate; A first gate located on the first region and a second gate located on the second region; Barrier sidewalls located on the first gate sidewall and the gate oxide layer; A lightly doped region is located in the substrate below the first gate, and the lightly doped region also extends below the barrier sidewall.