E-mode gan hemt power semiconductor epitaxial wafer using si growth substrate

Abstract

The present application provides an E-mode GaN HEMT power semiconductor epitaxial wafer using a Si(100) growth substrate, comprising: a growth substrate with a Si(100) crystal structure; a first AlN layer formed on the growth substrate; a dislocation annihilation layer (DAL) formed on the first AlN layer and containing a three-dimensional shape structure; a second AlN layer formed on the dislocation annihilation layer; a GaN channel layer formed above the second AlN layer; a barrier layer formed on the GaN channel layer; and a p-type GaN layer formed on the barrier layer.

Description

Technical Field

[0001] This invention relates to the field of Group III nitride-based epitaxial growth technology for power semiconductors. Specifically, this invention relates to an E-mode GaN HEMT power semiconductor epitaxial wafer grown on a Si (100) substrate (100), which maintains high-quality crystal properties despite having a thin-film structure. Background Technology

[0002] As a promising new generation of power semiconductor material in recent years, GaN HEMT-on-Si epitaxial wafers typically use thicker Si(111) growth substrates. However, Si(111) substrates are relatively expensive and have low inherent resistance, which presents a technical limitation—to block leakage current, a carbon-doped (C) semi-insulating GaN buffer layer must be grown to a thickness of more than 5 μm.

[0003] As the total thickness of the epitaxial layer increases, the thermo-mechanical stress caused by the difference in thermal expansion coefficients between the substrate and the epitaxial layer continues to accumulate, leading to frequent wafer warpage and cracking phenomena, which in turn increases the difficulty of operation in semiconductor manufacturing processes (Fab) and reduces photolithography accuracy.

[0004] In addition, a thicker GaN buffer layer can hinder the dissipation of heat generated inside the device, and when used in RF power amplifiers, it can also increase the substrate parasitic capacitance, resulting in a decrease in high-frequency performance.

[0005] Therefore, there is an urgent need for a new type of epitaxial wafer technology that can reduce the thickness of the epitaxial layer and effectively control crystal defects while using low-cost substrates. Summary of the Invention

[0006] Technical problems to be solved The present invention aims to reduce the production cost of power semiconductors by using a relatively inexpensive Si(100) growth substrate that is highly compatible with standard CMOS processes.

[0007] Furthermore, the present invention aims to reduce the total thickness of the epitaxial layer to below 2 μm without the need for a separate thick GaN buffer layer by introducing a three-dimensional dislocation annihilation layer (DAL) structure, while ensuring high-quality crystallinity.

[0008] Furthermore, this invention aims to suppress wafer warpage and crack formation through thin epitaxial structures, thereby improving process yield.

[0009] Furthermore, this invention aims to reduce leakage current and maximize breakdown voltage and heat dissipation characteristics by combining a high-resistivity substrate with the lower region of AlN, thereby achieving stable operation in both RF and power switching devices.

[0010] Technical solution To solve the above-mentioned technical problems, the present invention provides a structure comprising a growth substrate having a Si(100) crystal structure, a first AlN layer formed thereon, and a three-dimensional dislocation annihilation layer.

[0011] An active region consisting of a second AlN layer, a GaN channel layer, and a barrier layer is formed on the dislocation annihilation layer, with a p-type GaN layer for normally-off operation disposed at the top.

[0012] Specifically, a high-resistivity substrate with a resistivity of 10 kΩ·cm or higher is used as the growth substrate, and a dislocation annihilation layer is used to effectively control the penetrating dislocations that propagate upwards from the bottom, thereby improving the crystal quality.

[0013] Furthermore, according to the embodiment, a stress relief region containing a superlattice structure or a gradient in aluminum composition is introduced between the second AlN layer and the channel layer, employing an overall stress management approach.

[0014] Invention Effects According to the present invention, the following significant effects can be obtained.

[0015] First, by using low-cost Si(100) substrates and thin-film epitaxial layers, production costs and process efficiency can be significantly improved.

[0016] Second, by introducing a dislocation annihilation layer structure, excellent crystal quality can be ensured even at a relatively thin thickness, which is objectively proven by the low full width at half maximum (FWHM) values ​​in the XRD analysis data.

[0017] Third, the combination of a high-resistivity substrate and an AlN-based lower region can suppress vertical leakage current and improve breakdown voltage, while the thin epitaxial structure helps dissipate heat, thereby maximizing the thermal reliability of the device.

[0018] Fourth, by reducing parasitic effects through thin active region structures, a solid foundation is provided for achieving stable and fast operating speeds in RF power amplifiers and power switching devices. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view illustrating the basic stacked structure of an E-mode GaN HEMT power semiconductor epitaxial wafer according to an embodiment of the present invention.

[0020] Figure 2 Detailed diagram illustrating the microstructure of a dislocation annihilation layer (DAL) according to an embodiment of the present invention and the resulting dislocation blocking mechanism.

[0021] Figure 3The diagram illustrates the stress relief region structure of various embodiments of the present invention, showing a component-gradient structure.

[0022] Figure 4 The diagram illustrating the stress relief region structure of various embodiments of the present invention shows a superlattice structure.

[0023] Figure 5 A diagram illustrating an embodiment of the active region interface improvement structure of the present invention.

[0024] (Explanation of reference numerals in the attached image) 100: Growth substrate (Si(100)) 210: First AlN layer 220: Dislocation Annihilation Layer (DAL) 230: Second AlN Layer 300: Stress relief regions (AlGaN Layers) 310: Superlattice structure 400: Active region; 410: GaN channel layer; 420: Barrier layer (AlGaN or AlInN) 421: Ultrathin AlN film; 500: p-type GaN layer (pGaN) Detailed Implementation Hereinafter, embodiments of the present invention, including an E-mode GaN HEMT power semiconductor epitaxial wafer using a Si(100) grown substrate and its manufacturing method, will be described in detail with reference to the accompanying drawings.

[0025] Reference Figure 1 In one embodiment of the present invention, the E-mode GaN HEMT power semiconductor epitaxial wafer adopts a growth substrate (100) with a Si (100) crystal structure to maximize productivity while maintaining high-quality device characteristics.

[0026] On the growth substrate (100), a first AlN layer (210), a dislocation annihilation layer (DAL) (220), and a second AlN layer (230) are stacked sequentially from bottom to top, forming an active region containing a GaN channel layer (410) and a barrier layer (420) as well as a p-type GaN layer (500) for final E-mode operation.

[0027] The Si(100) wafer used as the growth substrate (100) is different from the previously commonly used thick and expensive Si(111) substrate (1.15t). It is relatively inexpensive and has a standard thickness (0.725t), which has advantages in reducing process costs and achieving large area.

[0028] The first and second AlN layers (210, 230) formed on the growth substrate (100) serve as nucleation material layers, playing a role in helping the subsequent high-quality growth of GaN substrates.

[0029] AlN has an extremely high bandgap energy of about 6.2 eV, excellent vertical electric field blocking effect, and with a high thermal conductivity of over 100 W / m·K, it also functions as a heat sink to quickly dissipate the heat generated during device operation to the growth substrate (100).

[0030] The dislocation annihilation layer (DAL) (220) is inserted between the first AlN layer (210) and the second AlN layer (230) in a sandwich structure to form a physical bond.

[0031] The dislocation annihilation layer (DAL) (220) is composed of a nanoscale three-dimensional shaped structure that is responsible for reducing the defect density by physically bending or blocking threading dislocations generated at the interface of the growth substrate (100) and attempting to propagate upward.

[0032] The GaN channel layer (410) and the barrier layer (420) form a high-concentration two-dimensional electron gas (2DEG) channel at the interface through a hetero-junction structure. The uppermost p-type GaN layer (500) performs vertical depletion on the channel region, achieving the normally-off characteristic that no current flows even when no gate voltage is applied.

[0033] Therefore, by leveraging the dislocation control capability of the dislocation annihilation layer (DAL) (220), epitaxial layers that previously had to be grown to a thickness of more than 5 μm to ensure crystal quality can now be achieved with a thickness of less than 2 μm, which directly leads to a reduction in epitaxial growth time and an increase in productivity.

[0034] Furthermore, the thin epitaxial structure reduces the thermo-mechanical stress on the wafer, minimizes the possibility of warpage and crack formation, and tightly binds the active region to the high-resistivity Si (100) growth substrate (100), thereby simultaneously improving mechanical stability and electrical operating speed.

[0035] In addition, in this embodiment, the dislocation annihilation layer (DAL) (220) can be made of nitride semiconductors such as AlGaN, GaN, InGaN, and AlInGaN, as well as MgNX and SiN, in addition to AlN. X This can be achieved using insulating or nitride-based materials such as SiO2.

[0036] The barrier layer (420) may be formed by replacing the Al(1-X)Ga(X)N (0<X<1) material with Al(1-X)In(X)N (0<X<1) according to design purposes. If it is required to change the device operation mode, the p-type GaN layer (500) may be replaced by introducing a GaN Cap layer or a SiNX layer, so as to flexibly deform into a D-mode (Normally-on) device for implementation.

[0037] Secondly, the E-mode GaN HEMT power semiconductor epitaxial wafer according to another embodiment of the present invention includes all the configurations of the foregoing embodiment, but particularly adopts a high-resistivity Si(100) substrate (100) with a resistivity of 10 kΩ·cm or more as the growth substrate (100).

[0038] This is a constituent element for maximizing the breakdown voltage of the power device and controlling unintended current flow generated during device operation.

[0039] The high-resistivity Si(100) growth substrate (100) has a significantly higher resistivity value than a common silicon substrate, thereby effectively suppressing the diffusion of a strong electric field vertically applied to the device into the interior of the substrate (100).

[0040] These physical characteristics create conditions for fundamentally blocking the leakage current flowing out through the growth substrate (100).

[0041] The growth substrate (100) is physically bonded to the first and second AlN layers (210, 230) and the DAL (220) structure, and in particular, generates a synergistic effect with the lower region of AlN having a wide band gap, so that the electric field blocking effect is doubled.

[0042] The use of the high-resistivity Si(100) growth substrate (100) can improve the breakdown voltage characteristic of the device, ensuring stable switching operation even in a high-voltage environment. In addition, the inherent excellent thermal conductivity of the silicon substrate (100) is combined with the high-resistivity characteristic, which can not only rapidly dissipate the heat generated in the GaN active region to the substrate (100), but also reduce the parasitic effect generated in the substrate (100) during high-frequency operation, thereby improving device reliability.

[0043] In addition, according to the required specifications of the device, in the case of an extremely high power environment, the growth substrate (100) may be replaced with a 4H-structure SiC substrate having similar high-resistivity characteristics or a p-type substrate doped with a specific dopant for implementation.

[0044] Reference Figure 2In another embodiment of the present invention, the E-mode GaN HEMT power semiconductor epitaxial wafer comprises the structure of the aforementioned embodiment, wherein the dislocation annihilation layer (DAL) (220) is formed of AlN, AlGaN, GaN, InGaN, AlInGaN, or MgN. X SiN X At least one of SiO2.

[0045] The material forming the dislocation annihilation layer (DAL) (220) is formed into a three-dimensional shape structure with nanoscale dimensions, which plays a role in effectively controlling crystal defects propagating from the growth substrate (100).

[0046] Specifically, when the material forming the dislocation annihilation layer (DAL) (220) is deposited on the first AlN layer (210), it grows in a discontinuous island-like three-dimensional structure rather than a complete thin film morphology, depending on specific growth conditions.

[0047] The dislocation annihilation layer (220) is located between the lower first AlN layer (210) and the upper second AlN layer (230), and is physically combined with it to produce dislocation bending or dislocation blocking effects, thereby significantly reducing the crystal defect density of the upper GaN channel layer (410).

[0048] Especially using SiN X At the same time, the vertical propagation of dislocations can be suppressed through the masking effect, and dislocations can be induced to combine in the horizontal direction, thereby improving the quality of the epitaxial layer.

[0049] The material forming the dislocation annihilation layer (DAL) (220) can be used alone or in the form of a composite layer of two or more materials, and can be implemented by adjusting the composition of the nitride semiconductor to optimize the lattice matching.

[0050] Furthermore, the vertical thickness of the dislocation annihilation layer (DAL) (220) is preferably in the range of 1 nm to 50 nm. This is the optimal numerical range that maximizes the dislocation annihilation effect while maintaining the overall thinning of the epitaxial wafer.

[0051] If the thickness of the dislocation annihilation layer (220) is less than 1 nm, the physical volume for blocking or bending dislocations is insufficient, and the defect control effect may be weak; if it exceeds 50 nm, there is a risk that the layer itself will become a new source of defect generation or increase the stress of the entire epitaxial layer.

[0052] The dislocation annihilation layer (220) is defined as a three-dimensional structure with nanoscale particle structures arranged on it, rather than a simple flat layer. The particles are arranged on the surface of the first AlN layer (210) in the form of dots or islands spaced apart or partially connected.

[0053] In terms of arrangement, the three-dimensional structure preferentially covers the dislocation-dense region in the first AlN layer (210) to form a physical barrier, preventing dislocations from the lower part from directly propagating to the upper second AlN layer (230) and GaN channel layer (410), thus having this binding relationship.

[0054] Thus, the three-dimensional nanostructure formed in the thickness range of 1nm to 50nm bends the dislocation ends, causing them to collide and annihilate each other, ultimately greatly improving the XRD full width at half maximum (FWHM) of the GaN channel layer (410).

[0055] The density and particle size of the aforementioned three-dimensional structure can be varied by adjusting the growth temperature, time, and gas partial pressure, or it can be implemented by arranging multiple layers to gradually improve the dislocation blocking efficiency. As an example, the specific growth process conditions for forming a three-dimensional structure of a dislocation annihilation layer (DAL) (220) are as follows. First, above the first AlN layer (210), without supplying a nitrogen source containing ammonia (NH3), a metal-organic source of group III elements (Al, Ga, In) is preflowed. Under a N2 / H2 mixed atmosphere, the group III elements are aggregated through a pyrolysis reaction at a growth temperature of 600°C to 1300°C, a growth pressure of 30 torr to 400 torr, and a V / III ratio of 300 to 4000, thereby forming a three-dimensional nitride structure as a three-dimensional dot-shaped precursor cluster. Subsequently, a nitrogen source containing ammonia (NH3) is supplied to the three-dimensional nitride structure, and the three-dimensional nitride structure is recrystallized into a single crystal, thereby completing the dislocation annihilation layer (DAL) (220). By repeating the above two steps once or multiple times, the thickness and lateral composition ratio of the dislocation annihilation layer (DAL) (220) can be controlled according to the purpose.

[0056] Secondly, it is preferable that the thicknesses of the first AlN layer (210) and the second AlN layer (230) are each formed in the range of 10 nm to 100 nm.

[0057] If the thickness of each layer is less than 10 nm, it may be difficult to form a continuous thin film to suppress the reaction with the substrate (100) or to induce high-quality epitaxial growth. Conversely, if it exceeds 100 nm, there are concerns about the generation of new cracks due to the relatively high critical thickness of AlN itself, or the unnecessary increase in epitaxial process time. Therefore, a thickness range of 10 nm to 100 nm is the optimal range for achieving thin film formation of the entire epitaxial layer while utilizing the electric field blocking effect of AlN's high bandgap (6.2 eV) and heat dissipation characteristics of its high thermal conductivity.

[0058] This configuration is designed to provide an optimal nucleation environment for controlling lower faults and ensuring the crystallinity of the upper channel layer (410).

[0059] Specifically, the first AlN layer (210) is formed directly on the Si (100) growth substrate (100) and serves as a seed layer to alleviate the lattice mismatch between silicon and nitride semiconductors. The second AlN layer (230) flattens the surface that is bent due to the dislocation annihilation layer (DAL) (220) and provides a substrate for the stable growth of the upper GaN channel layer (410).

[0060] The first and second AlN layers (210, 230) form a bond that vertically surrounds the dislocation annihilation layer (DAL) (220), physically supporting and protecting the dislocation blocking effect of the dislocation annihilation layer (DAL) (220).

[0061] In this embodiment, the thicknesses of the first AlN layer (210) and the second AlN layer (230) can be set to be different from each other according to the device's withstand voltage characteristics, or various deposition methods can be selected for implementation.

[0062] Secondly, the E-mode GaN HEMT power semiconductor epitaxial wafer of another embodiment of the present invention includes the configuration of the aforementioned embodiment and further includes a stress relief region (300), which is composed of at least one AlGaN thin film layer and is formed between the second AlN layer (230) and the GaN channel layer (410).

[0063] This is a structure used to gradually eliminate physical stress caused by differences in lattice constants between heterogeneous materials.

[0064] The stress relief region (300) acts as a buffer zone between the lower AlN layer (210, 230) with high physical rigidity and the upper GaN channel layer (410) with relatively good ductility.

[0065] The stress relief region (300) is formed directly on the upper surface of the second AlN layer (230) and is in contact with the upper GaN channel layer (410). This bonding relationship induces compressive stress at the interface to counteract the tensile stress generated when GaN is cooled on the growth substrate (100).

[0066] The resulting effect is to suppress wafer warpage and cracking. The presence of the stress-relief region (300) effectively controls the accumulated thermo-mechanical stress within the epitaxial layer without increasing the overall epitaxial thickness, leading to improved wafer handling precision in subsequent semiconductor processes.

[0067] The stress relief region (300) can be formed using a single-component AlGaN layer or by stacking multiple component layers as needed, and can be implemented by adjusting the aluminum (Al) content.

[0068] Secondly, refer to Figure 3 In another embodiment of the present invention, the E-mode GaN HEMT power semiconductor epitaxial wafer has a stress relief region (300) composed of multiple AlGaN thin film layers, having a structure in which the aluminum composition gradually or stepwise decreases upwards.

[0069] The plurality of AlGaN thin film layers form a compositionally graded structure (310), designed to smoothly transition from the lower AlN composition to the upper GaN composition.

[0070] Each layer has a lattice-matched bonding relationship with its adjacent layers, which minimizes dislocations caused by lattice mismatch and improves stress relief efficiency.

[0071] Therefore, by gradually reducing the aluminum composition, additional dislocation bending is induced within the epitaxial layer, further improving crystal quality. Furthermore, the total thickness of the stress-relief region (300) can be thinned to below 200 nm. This eliminates the need for the numerical... (The sentence is incomplete and requires more context to translate accurately.) The thick buffer layer can also achieve high-quality epitaxy, while reducing production costs and parasitic capacitance.

[0072] In this embodiment, the component gradient structure (310) can be implemented by linearly and continuously changing the components or by adjusting the thickness of each layer.

[0073] Secondly, refer to Figure 4 In another embodiment of the present invention, the stress relief region (300) of the E-mode GaN HEMT power semiconductor epitaxial wafer includes a superlattice structure (310) in which high-concentration AlGaN layers and low-concentration AlGaN layers are repeatedly stacked alternately.

[0074] The high-component layer is formed with 15-100% Al content and a thickness of 1-5 nm, while the low-component layer is formed with 0-25% Al content and a thickness of 5-30 nm, with the total thickness maintained below 200 nm.

[0075] The superlattice structure (310) has the structural characteristic of ultrathin thin film layers with different lattice constants being repeatedly bonded over dozens of cycles.

[0076] This structure provides a powerful defect filtering mechanism for residual dislocations propagating from the bottom to be refracted or annihilated in the horizontal direction each time they pass through multiple interfaces.

[0077] The superlattice structure (310) functions as a multiple barrier between the second AlN layer (230) and the GaN channel layer (410) to block the vertical movement of dislocations.

[0078] The resulting effect is to ensure extremely low dislocation density and precise stress control. The superlattice structure (310) disperses the elastic energy within the epitaxial layer, maintaining optimal wafer flatness and ensuring the high uniformity epitaxial quality required for high-power and high-frequency devices. Furthermore, by maximizing the above effects within a thickness range below 200 nm, it has the advantage of minimizing the heat dissipation path to the growth substrate (100).

[0079] In this embodiment, it can be implemented by adjusting the number of repeating periods of the superlattice or by fine-tuning the composition of each layer.

[0080] Secondly, in another embodiment of the present invention, the thickness of the GaN channel layer (410) in the E-mode GaN HEMT power semiconductor epitaxial wafer is limited to the range of 50 nm to 500 nm.

[0081] This configuration is made to ensure high electron mobility characteristics for the active region (400) of the power device, while minimizing parasitic effects with the substrate (100) by maintaining a relatively thin thickness throughout the epitaxial layer.

[0082] The GaN channel layer (410) is formed directly on the lower second AlN layer (230) or the stress relief region (300), and a barrier layer (420) is stacked on it.

[0083] In this invention, due to the action of the dislocation annihilation layer (DAL) (220), defects propagating from the bottom are effectively blocked, even without the number required by the prior art. Even a unit thickness of buffer layer can form a high-quality channel region with low crystal defect density (410) within the defined thickness range.

[0084] Accordingly, the GaN channel layer (410) has a thin structure of 500 nm or less, which shortens the distance between the GaN channel layer and the high-resistivity Si(100) growth substrate (100), and the effect of reducing the parasitic capacitance of the substrate can be expected, which ensures excellent performance in high-frequency application fields such as RF power amplifiers. That is, it is manifested as improved device operating speed and stabilized wafer quality. In addition, the thin channel structure (410) helps reduce thermo-mechanical stress and solves the problem of wafer warpage.

[0085] In this embodiment, implementation can be carried out by controlling the unintentional doping level or finely adjusting the thickness.

[0086] Next, in the E-mode GaN HEMT power semiconductor epitaxial wafer according to another embodiment of the present invention, the barrier layer (420) is defined to be made of Al(1-X)Ga(X)N (0<X<1) or Al(1-X)In(X)N (0<X<1) material, and has a thickness ranging from 10 nm to 50 nm.

[0087] This configuration is designed to induce a strong polarization phenomenon through the heterojunction with the channel layer (410) and ensure a stable electron channel.

[0088] The barrier layer (420) is formed on the upper surface of the GaN channel layer (410), and is lattice-matched and bonded at the interface.

[0089] The aluminum or indium composition of the barrier layer (420) determines the band gap difference with the channel (410), whereby high-concentration two-dimensional electron gas (2DEG) can be induced and formed at the interface without intentional doping.

[0090] The thickness range of 10 nm to 50 nm is an optimal value designed to maintain sufficient polarization strength while ensuring that the deformation energy inside the layer does not exceed the critical value.

[0091] Accordingly, the barrier layer (420) with defined material and thickness provides high electron density and mobility, and functions to reduce the on-resistance of the device. In addition, maintaining an appropriate thickness improves the gate control efficiency when bonded to the upper p-type GaN layer (500), thereby ensuring a stable threshold voltage.

[0092] In this embodiment, the barrier layer (420) can be implemented by adopting a composition-graded barrier structure or using a composite stacked structure.

[0093] Next, referring to Figure 5 , the E-mode GaN HEMT power semiconductor epitaxial wafer according to another embodiment of the present invention includes a configuration in which an ultra-thin AlN film (421) with a thickness of less than 2 nm is additionally formed on the GaN channel layer (410) before the barrier layer (420) is formed.

[0094] This is a functional configuration used to improve the interface quality between the GaN channel layer (410) and the barrier layer (420) and to suppress electron scattering.

[0095] The ultrathin AlN film (421) plays a role in preventing alloy scattering and locally increasing the energy barrier height.

[0096] The ultrathin AlN film (421) is preferably controlled to an ultrathin film thickness of less than 2 nm in order to optimize electrical connectivity while suppressing dislocations caused by lattice mismatch.

[0097] The effect of ultrathin AlN films (421) is to increase the confinement effect of the two-dimensional electron gas (2DEG), thereby improving electron mobility. This results in improved high-frequency characteristics and power efficiency of the device.

[0098] In this embodiment, it can be implemented by using an AlGaN layer with an extremely high aluminum content instead of an ultrathin AlN film (421), or by controlling the growth temperature.

[0099] Secondly, in another embodiment of the present invention, the E-mode GaN HEMT power semiconductor epitaxial wafer forms a p-type GaN layer (500) with a thickness in the range of 2 nm to 100 nm.

[0100] This is the configuration used to achieve the normally-off characteristic required for safe driving of power semiconductors and to control gate leakage current.

[0101] A p-type GaN layer (500) is formed on top of the barrier layer (420) and physically bonded to the region where the gate electrode is disposed.

[0102] The p-type GaN layer (500) bends the energy band of the lower channel region (410) upward through internally doped p-type impurities, forming a bond that depletes the 2DEG channel when no gate voltage is applied.

[0103] A thickness of approximately 100 nm is within the range that can minimize the overall resistivity of the device while fully maintaining the aforementioned depletion effect.

[0104] The p-type GaN layer (500) of the specified thickness ensures stable E-mode operation of the device, maintaining a cutoff state at a gate voltage of 0V (zero gate voltage). This contributes to system-level circuit protection and reduces power consumption.

[0105] In this embodiment, if it is necessary to change the device operating mode, it can be implemented by forming a GaN Cap layer or a SiNX layer instead of a p-type GaN layer (500) in a D-mode device manner.

[0106] Secondly, in another embodiment of the present invention, the E-mode GaN HEMT power semiconductor epitaxial wafer has a crystal structure that satisfies a specific numerical range of XRD rocking curve measurement data.

[0107] Specifically, the crystallinity of the epitaxial wafer satisfies a full width at half maximum (FWHM) of less than 400 arcsec for the GaN(002) plane and a full width at half maximum (FWHM) of less than 450 arcsec for the GaN(102) plane. This is a key factor demonstrating that the combination of the high-resistivity Si(100) substrate (100) and the DAL(220) structure significantly reduces the crystal defect density.

[0108] The XRD measurement data are physical indicators reflecting the lattice distortion and dislocation density inside the GaN crystal. This invention achieves high-quality crystals, which contrast with existing structures showing values ​​above 500 arcsec in GaN(002) and above 800 arcsec in GaN(102).

[0109] This crystallinity is achieved through the physical blocking and annihilation of dislocation binding relationships formed by the DAL(220) structure.

[0110] Wafers with the defined crystallinity minimize charge carrier scattering, ensuring high electron mobility and suppressing leakage current, thereby maximizing breakdown voltage characteristics. Furthermore, they reduce trapping effects, improving device reliability and operating speed.

Claims

1. An E-mode GaN HEMT power semiconductor epitaxial wafer using a Si(100) grown substrate, characterized in that, include: Growth substrate with Si(100) crystal structure; The first AlN layer formed on the growth substrate; A dislocation annihilation layer (DAL) formed on the first AlN layer and containing a three-dimensional shape structure; A second AlN layer is formed on the dislocation annihilation layer; A GaN channel layer is formed above the second AlN layer; A barrier layer formed on the GaN channel layer; as well as A p-type GaN layer is formed on the barrier layer.

2. The epitaxial wafer according to claim 1, characterized in that, The growth substrate is a high-resistivity Si(100) substrate with a resistivity of 10 kΩ·cm or higher.

3. The epitaxial wafer according to claim 1, characterized in that, The dislocation annihilation layer (DAL) is a nanoscale three-dimensional structure containing at least one of AlN, AlGaN, GaN, InGaN, AlInGaN, MgNX, SiNX, and SiO2.

4. The epitaxial wafer according to claim 1, characterized in that, The thickness of the dislocation annihilation layer (DAL) is in the range of 1 nm to 50 nm.

5. The epitaxial wafer according to claim 1, characterized in that, The thicknesses of the first AlN layer and the second AlN layer are each in the range of 10 nm to 100 nm.

6. The epitaxial wafer according to claim 1, characterized in that, Also includes: The stress relief region comprises at least one AlGaN thin film layer formed between the second AlN layer and the GaN channel layer.

7. The epitaxial wafer according to claim 6, characterized in that, The stress relief region comprises multiple AlGaN thin film layers, with the aluminum (Al) composition gradually or stepwise decreasing upwards, and the total thickness being less than 200 nm.

8. The epitaxial wafer according to claim 6, characterized in that, The stress relief region comprises a superlattice structure consisting of alternating layers of high-content AlGaN (15-100% Al content, 1-5 nm thickness) and low-content AlGaN (0-25% Al content, 5-30 nm thickness).

9. The epitaxial wafer according to claim 1, characterized in that, Also includes: An ultrathin AlN film, which is formed on the GaN channel layer and below the barrier layer, has a thickness of less than 2 nm.

10. The epitaxial wafer according to claim 1, characterized in that, According to XRD rocking curve measurements, the full width at half maximum (FWHM) of the GaN(002) surface is less than 400 arcsec, and the full width at half maximum (FWHM) of the GaN(102) surface is less than 450 arcsec.

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