Shielded gate semiconductor device and method of manufacturing the same

Abstract

The application discloses a shield gate semiconductor device, which comprises a trench and a source conductive material layer formed in the trench. The trench is formed in a first epitaxial layer of a first conductive type, and a shielding medium layer is arranged between the source conductive material layer and the side of the trench. The top of the source conductive material layer is connected to a source electrode composed of a front metal layer. A protection layer of a second conductive type is formed in the first epitaxial layer at the bottom of the trench, and the protection layer covers the bottom surface of the trench to reduce the electric field intensity at the bottom surface of the trench. The bottom surface of the source conductive material layer at least passes through the bottom surface of the trench to contact the protection layer, and the protection layer is connected to the source electrode through the source conductive material layer. The application also discloses a manufacturing method of the shield gate semiconductor device. The application can form the protection layer at the bottom of the trench of the gate structure to reduce the electric field intensity at the bottom of the trench, and meanwhile, the protection layer can be connected to the fixed electrode without increasing the chip area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a shielded gate (SGT) semiconductor device. This invention also relates to a method for manufacturing a shielded gate semiconductor device. Background Technology

[0002] In the SiC SGT structure, the presence of the shielding gate can flatten the longitudinal electric field strength and reduce the drift region resistance. However, the high electric field strength at the bottom of the trench still poses a problem, which can easily lead to premature breakdown, especially in SiC devices. Reducing the electric field at the corner of the trench is a problem that needs to be continuously addressed in SiC devices.

[0003] The existing SiC shielded gate structure is based on the existing conventional SGT structure, such as the Si SGT structure, with the addition of a P+ protective layer at the bottom of the trench. The purpose is to protect the bottom and surrounding area of ​​the corresponding trench and reduce the electric field. However, this structure has a drawback: the bottom P+ protective layer is difficult to bring out on the layout. If the P+ protective layer is floating, it will affect the carrier extraction speed of the device and affect the switching performance of the device.

[0004] In existing connection structures with P+ protection layers, most of them sacrifice some device structures, set up multiple mesa structures, and form intermittent line segment trenches to solve the grounding problem. However, these existing connection structures waste chip area and increase losses. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a shielded gate semiconductor device that can form a protective layer at the bottom of the trench of the gate structure to reduce the electric field intensity at the bottom of the trench while connecting the protective layer to a fixed electrode without increasing the chip area. This invention also provides a method for manufacturing the shielded gate semiconductor device.

[0006] To solve the above-mentioned technical problems, the shielded gate semiconductor device provided by the present invention includes: a trench and a source conductive material layer formed in the trench.

[0007] The trench is formed in a first epitaxial layer doped with a first conductivity type, and a shielding dielectric layer is spaced between the source conductive material layer and the sidewall of the trench.

[0008] The top of the source conductive material layer is connected to the source, which is composed of a front metal layer.

[0009] A protective layer doped with a second conductivity type is formed in the first epitaxial layer at the bottom of the trench, the protective layer covering the bottom surface of the trench to reduce the electric field strength at the bottom surface of the trench.

[0010] The bottom surface of the source conductive material layer extends at least through the bottom surface of the trench to contact the protective layer, which is connected to the source electrode through the source conductive material layer.

[0011] A further improvement is that a gate conductive material layer is also formed in the trench, and a gate dielectric layer is spaced between the gate conductive material layer and the sidewall of the trench.

[0012] A body region doped with a second conductivity type is also formed in the surface region of the first epitaxial layer. The gate conductive material layer extends longitudinally through the body region, and the surface of the body region covered by the side of the gate conductive material layer is used to form a conductive channel.

[0013] An inter-gate dielectric layer is provided between the gate conductive material layer and the source conductive material layer.

[0014] A further improvement is that the gate conductive material layer and the source conductive material layer have an upper and lower structure, with the entire source conductive material layer located at the bottom of the gate conductive material layer.

[0015] Alternatively, the gate conductive material layer and the source conductive material layer are arranged in a left-right structure, the source conductive material layer extends longitudinally through the entire depth range of the trench, and the gate conductive material layer is located on the left and right sides of the top region of the source conductive material layer.

[0016] A further improvement is that the material of the first epitaxial layer includes Si or SiC.

[0017] A further improvement is that the source conductive material layer is made of polycrystalline silicon.

[0018] The material of the gate conductive material layer includes polycrystalline silicon.

[0019] A further improvement is that the protective layer is either an ion-implanted region doped with a second conductivity type or a second epitaxial layer doped with a second conductivity type.

[0020] A further improvement is that a source region heavily doped with a first conductivity type and a body lead-out region heavily doped with a second conductivity type are also formed on the surface region of the body region.

[0021] The source region and the corresponding side of the trench are aligned, and there is a gap between the body lead-out region and the corresponding side of the trench.

[0022] A further improvement is that a heavily doped drain region of a first conductivity type is formed at the bottom of the first epitaxial layer.

[0023] To solve the above-mentioned technical problems, the manufacturing method of the shielded gate semiconductor device provided by the present invention includes the following steps: A trench is formed in the first epitaxial layer doped with the first conductivity type.

[0024] A protective layer doped with a second conductivity type is formed in the first epitaxial layer at the bottom of the trench, the protective layer covering the bottom surface of the trench to reduce the electric field strength at the bottom surface of the trench.

[0025] A shielding medium layer is formed, which covers the inner surface of the trench and extends to the outside of the trench.

[0026] A first etching is performed, which removes at least all of the shielding dielectric layer on the bottom surface of the trench to expose the protective layer. The first etching does not etch or etches only a portion of the thickness of the protective layer at the bottom.

[0027] A source conductive material layer is formed in the trench, which is connected to the source electrode composed of the front metal layer. The bottom of the source conductive material layer passes through the bottom surface of the trench and contacts the protective layer. The protective layer is connected to the source electrode through the source conductive material layer.

[0028] A further improvement is that, before forming the trench, the method further includes: A body region is formed in the surface region of the first epitaxial layer by performing a second conductivity type doping.

[0029] A source region is formed in the surface region of the body region by performing a first type of heavy doping source implantation; the source region and the corresponding trench side are aligned.

[0030] Ions of a second conductivity type are implanted to form a body exit region in a selected region of the body region, the bottom surface of the body exit region being in contact with the body region; and there is a gap between the body exit region and the sidewall of the corresponding trench.

[0031] A further improvement is that the shielding dielectric layer is formed by field oxygen growth.

[0032] A further improvement is that the process further includes the step of forming an inter-gate dielectric layer, a gate dielectric layer, and a gate conductive material layer in the trench.

[0033] A gate dielectric layer is spaced between the gate conductive material layer and the trench sidewall; the gate conductive material layer extends longitudinally through the body region, and the surface of the body region covered by the sidewall of the gate conductive material layer is used to form a conductive channel; an inter-gate dielectric layer is spaced between the gate conductive material layer and the source conductive material layer.

[0034] A further improvement is that the gate conductive material layer and the source conductive material layer have an upper and lower structure, with the entire source conductive material layer located at the bottom of the gate conductive material layer; the steps of forming the inter-gate dielectric layer, the gate dielectric layer, and the gate conductive material layer include: After the source conductive material layer completely fills the trench, the source conductive material layer is etched back so that it is located in the bottom region of the trench.

[0035] The gate dielectric layer is formed on the top surface of the source conductive material layer.

[0036] The gate dielectric layer is formed on the side of the trench above the top surface of the inter-gate dielectric layer.

[0037] The trench is filled with the gate conductive material layer.

[0038] A further improvement is that the photomask used in the first etching process is a photomask that performs a back etching of the source conductive material layer.

[0039] A further improvement is that the gate conductive material layer and the source conductive material layer are arranged in a left-right structure, the source conductive material layer extends longitudinally through the entire depth range of the trench, and the gate conductive material layer is located on the left and right sides of the top region of the source conductive material layer.

[0040] A further improvement is that the material of the first epitaxial layer includes Si or SiC.

[0041] A further improvement is that the source conductive material layer is made of polycrystalline silicon.

[0042] The material of the gate conductive material layer includes polycrystalline silicon.

[0043] A further improvement is that the protective layer is formed by ion implantation with second conductivity type doping or by epitaxial growth with second conductivity type doping.

[0044] In this invention, a protective layer with a different doping type than the drift region is formed at the bottom of the trench. This protective layer depletes the drift region, thereby reducing the electric field strength at the bottom of the trench and improving device reliability. Simultaneously, utilizing the characteristic of shielded gate semiconductor devices where the top of the source conductive material layer (serving as a shielding structure) is connected to a fixed source and the bottom of the source conductive material layer is located at the bottom of the trench, the shielding dielectric layer between the source conductive material layer and the bottom surface of the trench is removed. This allows the protective layer to directly contact the source conductive material layer, enabling the protective layer to directly pass through the source conductive material layer and ultimately connect to the source. Therefore, this invention eliminates the need for an additional electrode lead structure with a protective layer, thus saving chip area. Therefore, this invention can form a protective layer at the bottom of the trench in the gate structure to reduce the electric field strength at the bottom of the trench while simultaneously connecting the protective layer to a fixed electrode without increasing the chip area. Attached Figure Description

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the structure of the shielded gate semiconductor device according to an embodiment of the present invention; Figures 2-8 This is a schematic diagram of the device structure in each step of the manufacturing method of the shielded gate semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0046] like Figure 1 The diagram shown is a schematic diagram of the structure of a shielded gate semiconductor device according to an embodiment of the present invention. The shielded gate semiconductor device according to an embodiment of the present invention includes: a trench 102 and a source conductive material layer 104 formed in the trench 102.

[0047] The trench 102 is formed in the first epitaxial layer 101 doped with the first conductivity type, and a shielding dielectric layer 105 is spaced between the source conductive material layer 104 and the side of the trench 102.

[0048] In this embodiment of the invention, the material of the first epitaxial layer 101 is SiC. In other embodiments, the first epitaxial layer 101 may also be made of other semiconductor materials such as Si.

[0049] The top of the source conductive material layer 104 is connected to the source, which is composed of a front metal layer (not shown).

[0050] In this embodiment of the invention, the source conductive material layer 104 is made of polycrystalline silicon. In other embodiments, the source conductive material layer 104 can also be made of other suitable conductive materials, such as metals, as needed.

[0051] A protective layer 103 of a second conductivity type is formed in the first epitaxial layer 101 at the bottom of the trench 102. The protective layer 103 covers the bottom surface of the trench 102 to reduce the electric field strength at the bottom surface of the trench 102.

[0052] In this embodiment of the invention, the protective layer 103 is an ion-implanted region doped with a second conductivity type. In other embodiments, the protective layer 103 may also be a second epitaxial layer doped with a second conductivity type.

[0053] The bottom surface of the source conductive material layer 104 extends at least through the bottom surface of the trench 102 to contact the protective layer 103, and the protective layer 103 is connected to the source through the source conductive material layer 104.

[0054] In this embodiment of the invention, the bottom surface of the source conductive material layer 104 passes through the bottom surface of the trench 102 to expose the surface of the protective layer 103, thereby enabling contact between the source conductive material layer 104 and the protective layer 103. By etching away a portion of the thickness of the protective layer 103, the contact area between the source conductive material layer 104 and the protective layer 103 can be increased. In some embodiments, the over-etching thickness of the protective layer 103 includes 0.1 micrometers.

[0055] In this embodiment of the invention, a gate conductive material layer 108 is also formed in the trench 102, and a gate dielectric layer 107 is spaced between the gate conductive material layer 108 and the sidewall of the trench 102.

[0056] In this embodiment of the invention, the gate conductive material layer 108 is made of polycrystalline silicon. In other embodiments, the gate conductive material layer 108 may also be made of other suitable conductive materials such as metals, as needed.

[0057] A body region 109 with a second conductivity type doped is also formed in the surface region of the first epitaxial layer 101. The gate conductive material layer 108 extends longitudinally through the body region 109, and the surface of the body region 109 covered by the side of the gate conductive material layer 108 is used to form a conductive channel.

[0058] An inter-gate dielectric layer 106 is provided between the gate conductive material layer 108 and the source conductive material layer 104.

[0059] In this embodiment of the invention, the gate conductive material layer 108 and the source conductive material layer 104 are arranged in an upper and lower structure, with the source conductive material layer 104 entirely located at the bottom of the gate conductive material layer 108.

[0060] In other embodiments, the gate conductive material layer 108 and the source conductive material layer 104 may be arranged in a left-right structure, with the source conductive material layer 104 extending longitudinally through the entire depth range of the trench 102, and the gate conductive material layer 108 located on the left and right sides of the top region of the source conductive material layer 104.

[0061] In this embodiment of the invention, a source region 110 heavily doped with a first conductivity type and a body lead-out region 111 heavily doped with a second conductivity type are also formed on the surface region of the body region 109.

[0062] The source region 110 and the corresponding side of the trench 102 are aligned, and there is a gap between the body lead-out region 111 and the corresponding side of the trench 102.

[0063] In this embodiment of the invention, the shielded gate semiconductor device is a shielded gate MOSFET, and a heavily doped drain region (not shown) of a first conductivity type is formed at the bottom of the first epitaxial layer 101. In other embodiments, the shielded gate semiconductor device may also be a shielded gate IGBT, and a heavily doped collector region of a second conductivity type is formed at the bottom of the first epitaxial layer 101.

[0064] In this embodiment of the invention, the shielding gate semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the shielding gate semiconductor device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0065] In this embodiment of the invention, a protective layer 103 with a different doping type than the drift region is formed at the bottom of the trench 102 to deplete the drift region and reduce the electric field strength at the bottom of the trench 102, thus providing device reliability. Simultaneously, utilizing the characteristics of the source conductive material layer 104 (which serves as a shielding structure) in the shielded gate semiconductor device, where the top of the shielding structure is connected to a fixed source and the bottom of the source conductive material layer 104 is located at the bottom of the trench 102, the shielding dielectric layer 105 between the source conductive material layer 104 and the bottom surface of the trench 102 is removed, allowing the protective layer 103 and the source conductive material layer 104 to directly contact each other. Thus, the protective layer 103 can directly pass through the source conductive material layer 104 and ultimately connect to the source. Therefore, this embodiment of the invention does not require an additional electrode lead-out structure for the protective layer 103, thereby saving chip area. Therefore, the embodiments of the present invention can form a protective layer 103 at the bottom of the trench 102 of the gate structure to reduce the electric field strength at the bottom of the trench 102 while connecting the protective layer 103 to the fixed electrode without increasing the chip area.

[0066] like Figures 2 to 8The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the shielded gate semiconductor device according to an embodiment of the present invention. The manufacturing method of the shielded gate semiconductor device according to an embodiment of the present invention includes the following steps: Step S101, as follows Figure 2 As shown, a trench 102 is formed in the first epitaxial layer 101 doped with the first conductivity type.

[0067] In the method of this embodiment of the invention, before forming the trench 102, the method further includes: A body region 109 is formed in the surface region of the first epitaxial layer 101 by performing a second conductivity type doping.

[0068] A source region 110 is formed in the surface region of the body region 109 by performing a first type of heavy doping source implantation; the source region 110 is aligned with the side of the corresponding trench 102.

[0069] Ions of a second conductivity type are implanted to form a body exit region 111 in a selected region of the body region 109. The bottom surface of the body exit region 111 is in contact with the body region 109. There is a gap between the body exit region 111 and the side of the corresponding trench 102.

[0070] In the method of this embodiment, the material of the first epitaxial layer 101 is SiC. In other embodiments, the first epitaxial layer 101 may also be made of other semiconductor materials such as Si.

[0071] Step S102, as follows Figure 2 As shown, a protective layer 103 doped with a second conductivity type is formed in the first epitaxial layer 101 at the bottom of the trench 102. The protective layer 103 covers the bottom surface of the trench 102 to reduce the electric field strength at the bottom surface of the trench 102.

[0072] In the method of this embodiment, the protective layer 103 is formed by ion implantation with doping of a second conductivity type. In other embodiments, the protective layer 103 may also be formed by epitaxial growth with doping of a second conductivity type.

[0073] Step S103, as follows Figure 3 As shown, a shielding medium layer 105 is formed, which covers the inner surface of the trench 102 and extends to the outside of the trench 102.

[0074] In the method of this embodiment of the invention, the shielding dielectric layer 105 is formed by field oxygen growth.

[0075] Step S104, as follows Figure 4As shown, a first etching is performed, which removes at least all of the shielding medium layer 105 on the bottom surface of the trench 102 to expose the protective layer 103. The first etching does not etch or etches only a portion of the thickness of the bottom protective layer 103.

[0076] In the method of this invention, contact between the subsequently formed source conductive material layer 104 and the protective layer 103 can be achieved by exposing the surface of the protective layer 103. By etching away a portion of the thickness of the protective layer 103, the contact area between the subsequently formed source conductive material layer 104 and the protective layer 103 can be increased. In some embodiments, the over-etching thickness of the protective layer 103 includes 0.1 micrometers.

[0077] Step S105, as follows Figure 5 As shown, a source conductive material layer 104 is formed in the trench 102, which is connected to the source electrode composed of the front metal layer. The bottom of the source conductive material layer 104 passes through the bottom surface of the trench 102 and contacts the protective layer 103. The protective layer 103 is connected to the source electrode through the source conductive material layer 104.

[0078] The subsequent steps also include: forming an inter-gate dielectric layer 106, a gate dielectric layer 107, and a gate conductive material layer 108 in the trench 102.

[0079] A gate dielectric layer 107 is spaced between the gate conductive material layer 108 and the sidewall of the trench 102; the gate conductive material layer 108 extends longitudinally through the body region 109, and the surface of the body region 109 covered by the sidewall of the gate conductive material layer 108 is used to form a conductive channel; an inter-gate dielectric layer 106 is spaced between the gate conductive material layer 108 and the source conductive material layer 104.

[0080] In the method of this embodiment of the invention, the gate conductive material layer 108 and the source conductive material layer 104 are arranged in an upper and lower structure, with the source conductive material layer 104 entirely located at the bottom of the gate conductive material layer 108; the steps of forming the inter-gate dielectric layer 106, the gate dielectric layer 107, and the gate conductive material layer 108 include: like Figure 5 As shown, after the source conductive material layer 104 completely fills the trench 102, the source conductive material layer 104 is etched back so that it is located in the bottom region of the trench 102. The photomask used in the first etching process employs a photomask with the source conductive material layer 104 etched back, thus enabling photomask sharing and saving photomask costs. In some embodiments, the material of the source conductive material layer 104 includes polycrystalline silicon.

[0081] like Figure 7 As shown, the inter-gate dielectric layer 106 is formed on the top surface of the source conductive material layer 104. Preferably, the inter-gate dielectric layer 106 is an oxide layer formed using an HDP CVD process. The process includes the following steps: like Figure 6 As shown, the inter-gate dielectric layer 106 is formed using HDP CVD process to completely fill the trench 102.

[0082] like Figure 7 As shown, the inter-gate dielectric layer 106 is etched back to obtain the inter-gate dielectric layer 106 of the required thickness.

[0083] like Figure 8 As shown, the gate dielectric layer 107 is formed on the side of the trench 102 above the top surface of the inter-gate dielectric layer 106. In some embodiments, the gate dielectric layer 107 is formed by a thermal oxidation process.

[0084] Back Figure 1 As shown, the gate conductive material layer 108 is filled in the trench 102. In the method of this embodiment of the invention, the material of the gate conductive material layer 108 includes polysilicon, and the gate conductive material layer 108 can be formed by polysilicon deposition and etch-back.

[0085] In other embodiments, the method may also be such that the gate conductive material layer 108 and the source conductive material layer 104 are arranged in a left-right structure, the source conductive material layer 104 extends longitudinally through the entire depth range of the trench 102, and the gate conductive material layer 108 is located on the left and right sides of the top region of the source conductive material layer 104.

[0086] In the method of this embodiment, the shielded gate semiconductor device is a shielded gate MOSFET. After the front-side process is completed, the method further includes: forming a heavily doped drain region (not shown) of a first conductivity type at the bottom of the first epitaxial layer 101. In other embodiments, the shielded gate semiconductor device may be a shielded gate IGBT. After the front-side process is completed, the method further includes: forming a heavily doped collector region of a second conductivity type at the bottom of the first epitaxial layer 101.

[0087] In the method of this embodiment, the shielding gate semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the shielding gate semiconductor device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0088] In this embodiment of the invention, by directly connecting the bottom P+ doped protective layer 103 to the shielding gate, i.e., the source conductive material layer 104, an electrical connection between the source metal and the bottom protective layer 103 can be directly achieved, ensuring that the bottom P+ is not a floating potential but a hard ground. The electric field distribution diagram obtained from simulation shows that the highest electric field intensity is concentrated in the P+ protective layer 103, rather than at the trench corner, thus achieving protection of the trench bottom.

[0089] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A shielded gate semiconductor device, characterized in that, include: The trench and the source conductive material layer formed in the trench; The trench is formed in a first epitaxial layer doped with a first conductivity type, and a shielding dielectric layer is spaced between the source conductive material layer and the sidewall of the trench. The top of the source conductive material layer is connected to the source electrode, which is composed of a front metal layer; A protective layer doped with a second conductivity type is formed in the first epitaxial layer at the bottom of the trench, and the protective layer covers the bottom surface of the trench to reduce the electric field strength at the bottom surface of the trench. The bottom surface of the source conductive material layer extends at least through the bottom surface of the trench to contact the protective layer, which is connected to the source electrode through the source conductive material layer.

2. The shielded gate semiconductor device as described in claim 1, characterized in that: A gate conductive material layer is also formed in the trench, and a gate dielectric layer is spaced between the gate conductive material layer and the sidewall of the trench. A body region doped with a second conductivity type is also formed in the surface region of the first epitaxial layer. The gate conductive material layer extends longitudinally through the body region, and the surface of the body region covered by the side of the gate conductive material layer is used to form a conductive channel. An inter-gate dielectric layer is provided between the gate conductive material layer and the source conductive material layer.

3. The shielded gate semiconductor device as described in claim 2, characterized in that: The gate conductive material layer and the source conductive material layer are arranged in an upper and lower structure, with the entire source conductive material layer located at the bottom of the gate conductive material layer; Alternatively, the gate conductive material layer and the source conductive material layer are arranged in a left-right structure, the source conductive material layer extends longitudinally through the entire depth range of the trench, and the gate conductive material layer is located on the left and right sides of the top region of the source conductive material layer.

4. The shielded gate semiconductor device as described in claim 1, characterized in that: The material of the first epitaxial layer includes Si or SiC.

5. The shielded gate semiconductor device as described in claim 2, characterized in that: The material of the source conductive material layer includes polycrystalline silicon; The material of the gate conductive material layer includes polycrystalline silicon.

6. The shielded gate semiconductor device as described in claim 1, characterized in that: The protective layer is either an ion-implanted region doped with a second conductivity type or a second epitaxial layer doped with a second conductivity type.

7. The shielded gate semiconductor device as described in claim 2, characterized in that: A source region heavily doped with a first conductivity type and a body lead-out region heavily doped with a second conductivity type are also formed on the surface region of the body region. The source region and the corresponding side of the trench are aligned, and there is a gap between the body lead-out region and the corresponding side of the trench.

8. The shielded gate semiconductor device as described in claim 7, characterized in that: A heavily doped drain region of the first conductivity type is formed at the bottom of the first epitaxial layer.

9. A method for manufacturing a shielded gate semiconductor device, characterized in that, Includes the following steps: A trench is formed in the first epitaxial layer doped with the first conductivity type; A protective layer doped with a second conductivity type is formed in the first epitaxial layer at the bottom of the trench, the protective layer covering the bottom surface of the trench to reduce the electric field strength at the bottom surface of the trench. A shielding medium layer is formed, which covers the inner surface of the trench and extends to the outside of the trench; A first etching is performed, which removes at least all of the shielding dielectric layer on the bottom surface of the trench to expose the protective layer. The first etching does not etch or etches only a portion of the thickness of the protective layer at the bottom. A source conductive material layer is formed in the trench, which is connected to the source electrode composed of the front metal layer. The bottom of the source conductive material layer passes through the bottom surface of the trench and contacts the protective layer. The protective layer is connected to the source electrode through the source conductive material layer.

10. The method for manufacturing a shielded gate semiconductor device as described in claim 9, characterized in that: The process includes the following steps prior to forming the trench: A body region is formed in the surface region of the first epitaxial layer by performing a second conductivity type doping; A source region is formed in the surface region of the body region by implanting a source with a first conductivity class of heavy doping; the source region and the sidewall of the corresponding trench are aligned; Ions of a second conductivity type are implanted to form a body exit region in a selected region of the body region, the bottom surface of the body exit region being in contact with the body region; and there is a gap between the body exit region and the sidewall of the corresponding trench.

11. The method for manufacturing the shielded gate semiconductor device as described in claim 10, characterized in that: The shielding dielectric layer is formed by field oxygen growth.

12. The method for manufacturing the shielded gate semiconductor device as described in claim 10, characterized in that: The subsequent steps also include: forming an inter-gate dielectric layer, a gate dielectric layer, and a gate conductive material layer in the trench; A gate dielectric layer is spaced between the gate conductive material layer and the trench sidewall; the gate conductive material layer extends longitudinally through the body region, and the surface of the body region covered by the sidewall of the gate conductive material layer is used to form a conductive channel; an inter-gate dielectric layer is spaced between the gate conductive material layer and the source conductive material layer.

13. The method for manufacturing a shielded gate semiconductor device as described in claim 12, characterized in that: The gate conductive material layer and the source conductive material layer are arranged in an upper and lower structure, with the entire source conductive material layer located at the bottom of the gate conductive material layer; The steps of forming the inter-gate dielectric layer, the gate dielectric layer, and the gate conductive material layer include: After the source conductive material layer completely fills the trench, the source conductive material layer is etched back so that the source conductive material layer is located in the bottom region of the trench; The inter-gate dielectric layer is formed on the top surface of the source conductive material layer; The gate dielectric layer is formed on the side of the trench above the top surface of the inter-gate dielectric layer; The trench is filled with the gate conductive material layer.

14. The method for manufacturing the shielded gate semiconductor device as described in claim 13, characterized in that: The photomask used in the first etching process is a photomask used for back etching of the source conductive material layer.

15. The method for manufacturing a shielded gate semiconductor device as described in claim 12, characterized in that: The gate conductive material layer and the source conductive material layer are arranged in a left-right structure. The source conductive material layer extends longitudinally through the entire depth range of the trench, and the gate conductive material layer is located on the left and right sides of the top region of the source conductive material layer.

16. The method for manufacturing a shielded gate semiconductor device as described in claim 9, characterized in that: The material of the first epitaxial layer includes Si or SiC.

17. The method for manufacturing a shielded gate semiconductor device as described in claim 12, characterized in that: The material of the source conductive material layer includes polycrystalline silicon; The material of the gate conductive material layer includes polycrystalline silicon.

18. The method for manufacturing a shielded gate semiconductor device as described in claim 9, characterized in that: The protective layer is formed by ion implantation with second conductivity type doping or by epitaxial growth with second conductivity type doping.

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