Fluorine-containing plasma processing in semiconductor processes

Abstract

The present disclosure relates generally to fluorine-containing plasma processing in semiconductor processing for forming semiconductor devices. In an example, a semiconductor device includes a semiconductor substrate (502), a gate dielectric layer (520) located above the semiconductor substrate (502), and a gate electrode (602) located above the gate dielectric layer (520). The gate dielectric layer (520) includes silicon oxynitride including fluorine. The gate electrode (602) includes a proximal portion proximate to the gate dielectric layer (520), and the proximal portion of the gate electrode (602) does not include fluorine.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 783,020, filed April 3, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to semiconductor devices, and more specifically, to fluorine-containing plasma processing in semiconductor processes. Background Technology

[0004] Integrated circuits (ICs) can comprise various semiconductor devices having components formed in or on a semiconductor substrate. One approach to achieving improved performance characteristics of ICs (e.g., reduced power consumption and increased speed) is to scale the semiconductor devices of the IC to smaller technology nodes. Scaling these semiconductor devices to smaller technology nodes may present challenges that may not have been encountered previously at larger technology nodes. Furthermore, these challenges can adversely affect the performance characteristics of the IC that are sought to be improved through scaling. Therefore, scaling devices in ICs to smaller technology nodes typically requires novel methods of semiconductor fabrication for manufacturing these devices. Summary of the Invention

[0005] An example is a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate dielectric layer above the semiconductor substrate, and a gate electrode above the gate dielectric layer. The gate dielectric layer comprises silicon oxide nitride including fluorine. The gate electrode includes a portion adjacent to the gate dielectric layer, and said portion does not contain fluorine.

[0006] Another example is a method. An oxide layer is formed over a semiconductor substrate. The oxide layer is subjected to a fluorine-containing plasma treatment. The oxide layer is then nitrided.

[0007] Another example is a method. A gate oxide layer is formed over a semiconductor substrate. Fluorine is doped into the gate oxide layer, including plasma treatment. The gate oxide layer is nitrided. A gate electrode is formed over the gate oxide layer.

[0008] Another example is a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate dielectric layer, a gate electrode, source / drain regions, and a metal-semiconductor compound. The gate dielectric layer is above the semiconductor substrate. The gate electrode is above the gate dielectric layer. The source / drain regions are located in the semiconductor substrate and laterally adjacent to the gate electrode. The metal-semiconductor compound is located on the semiconductor substrate at the source / drain regions. The metal-semiconductor compound contains fluorine.

[0009] Another example is a method in which a semiconductor material is subjected to a fluorine-containing plasma treatment. A metal is formed on the semiconductor material. The metal is then reacted with the semiconductor material to form a metal-semiconductor compound.

[0010] Another example is a method. A gate dielectric layer is formed over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. Fluorine is doped into the source / drain region of the semiconductor substrate near the gate electrode, including plasma treatment. A metal is formed on the source / drain region. An annealing process is performed to cause the metal to react with a portion of the semiconductor substrate at the source / drain region.

[0011] The foregoing summary provides a fairly broad overview of the various features of the examples disclosed herein in order to better understand the following detailed description. Various features and advantages of such examples will be described below. The described examples can be readily used as the basis for modifying or designing other examples within the scope of the appended claims. Attached Figure Description

[0012] To understand the above features in detail, please refer to the following detailed description in conjunction with the accompanying drawings.

[0013] Figure 1 This is a flowchart illustrating, based on some examples, a method for forming a dielectric layer containing nitrogen and fluorine.

[0014] Figure 2 This is a flowchart illustrating another method for forming a dielectric layer containing nitrogen and fluorine, based on some examples.

[0015] Figure 3A , 3B 3C is a chart showing the process parameters for example peak annealing based on some examples.

[0016] Figure 4 This is a flowchart illustrating methods for forming metal-semiconductor compounds based on some examples.

[0017] Figure 5 , 6 Figures 7, 8, and 9 are corresponding cross-sectional views of semiconductor devices in the intermediate manufacturing stage, based on some examples.

[0018] Figure 10 This is a graph showing the fluorine distribution across the gate electrode, gate dielectric layer, and semiconductor substrate according to some examples.

[0019] The drawings and accompanying detailed description are provided to help understand the features of the various examples and do not limit the scope of the appended claims. Examples shown in the drawings and described in the accompanying detailed description can be readily used as the basis for modifications or designs of other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same common elements in the drawings. The drawings are drawn to clearly show the relevant elements or features, and are not necessarily drawn to scale. Detailed Implementation

[0020] Various features are described below with reference to the diagrams. Other examples may include any arrangement that includes or excludes the described aspects or features. The examples shown may not have all the aspects or advantages shown. The aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example, even if not shown or explicitly described in this way. In addition, the methods described herein may be described with a specific order of operations, but may be implemented with various other orders of operations (e.g., different serial or parallel executions of various operations) depending on other methods in other examples.

[0021] This disclosure generally, but not exclusively, relates to fluorine-containing plasma processing in semiconductor fabrication for forming semiconductor devices. In some embodiments, the semiconductor device includes a gate dielectric layer over a semiconductor substrate and a gate electrode over the gate dielectric layer. The gate dielectric layer includes silicon oxide nitride comprising fluorine, and the gate electrode includes a fluorine-free portion adjacent to the gate dielectric layer. In some embodiments, an oxide layer is formed over the semiconductor substrate. A fluorine-containing plasma processing is performed on the oxide layer, and the oxide layer is nitrided. The oxide layer may be a gate oxide layer, and the fluorine-containing plasma processing may cause fluorine doping into the oxide layer. A gate electrode may be formed over the oxide layer. Such embodiments can achieve an improved interface between the oxide layer and the semiconductor substrate, and can achieve improved carrier mobility in the channel region of, for example, a semiconductor device (e.g., a field-effect transistor (FET)). Performance mismatch and noise between different semiconductor devices can be reduced. Other benefits and advantages can be achieved.

[0022] In some examples, the semiconductor device includes a gate dielectric layer above a semiconductor substrate, a gate electrode above the gate dielectric layer, a source / drain region in the semiconductor substrate, and a metal-semiconductor compound located at the source / drain region on the semiconductor substrate. The source / drain region is laterally adjacent to the gate electrode. The metal-semiconductor compound and / or the semiconductor substrate adjacent to the metal-semiconductor compound contain fluorine. In some examples, a fluorine-containing plasma treatment is performed on the semiconductor material (e.g., the semiconductor substrate). A metal is formed on the semiconductor material and reacts with the semiconductor material, for example, by an annealing process, to form a metal-semiconductor compound. The fluorine-containing plasma treatment can cause fluorine to be incorporated into the semiconductor material. The semiconductor material may be located at the source / drain region in the semiconductor substrate, such that a metal is formed on the source / drain region and reacts with a portion of the semiconductor substrate at the source / drain region. The gate dielectric layer may be formed above the semiconductor substrate, and the gate electrode may be formed above the gate dielectric layer, wherein the source / drain region is laterally adjacent to the gate dielectric layer and the gate electrode. When a metal reacts with a semiconductor material, the addition of fluorine to the semiconductor material can reduce metal piping into the semiconductor. This can lead to other benefits and advantages.

[0023] Various examples are then described. While specific examples may illustrate aspects of the features generally described above, examples may be incorporated into any combination of features generally described above (which are described in more detail in the examples below).

[0024] Figure 1This is a flowchart of a method 100 for forming a dielectric layer comprising nitrogen and fluorine, according to some examples. At block 102, a dielectric layer is formed, for example on a substrate, and more specifically, on a semiconductor substrate. In some examples, the dielectric layer is or comprises an oxide, such as silicon oxide. In some examples, an oxidation process is used to form the dielectric layer on a semiconductor substrate (e.g., a bulk silicon substrate). The oxidation process forms an oxide layer at the upper surface of the semiconductor substrate. The oxidation process can be or includes in-situ water vapor generation (ISSG) oxidation. ISSG oxidation may involve flowing a gas mixture comprising nitrous oxide (N2O) gas and hydrogen (H2) into a processing chamber in which the semiconductor substrate is located. The flow rate of nitrous oxide (N2O) gas into the processing chamber may be in the range of 5,000 standard cubic centimeters per minute (sccm) to 50,000 sccm, and the flow rate of hydrogen (H2) gas into the processing chamber may be in the range of 50 sccm to 5,000 sccm. ISSG oxidation can be performed in a processing chamber at temperatures ranging from 950°C to 1,050°C. Typically, the gas flowing into the processing chamber reacts and / or decomposes, causing oxygen to react with the semiconductor material at the upper surface of the semiconductor substrate. In examples where the semiconductor material is silicon, ISSG oxidation forms silicon oxide. In some instances, no significant amount of nitrogen is formed in the oxide formed at the upper surface of the semiconductor substrate by ISSG oxidation. Nitrogen from the nitrous oxide (N₂O) gas typically does not react with the semiconductor material at the upper surface and flows out of or is purged from the processing chamber. In some instances, the dielectric layer (e.g., an oxide layer) has a thickness ranging from 18 angstroms to 22 angstroms.

[0025] At box 104, a fluorine-containing plasma treatment is performed on the dielectric layer. The fluorine-containing plasma treatment causes fluorine to be incorporated into the dielectric layer. The fluorine-containing plasma treatment substantially does not etch the dielectric layer (e.g., does not remove more than 1 angstrom). In some instances, the fluorine-containing plasma treatment involves flowing a fluorine-containing gas at a low flow rate into a processing chamber in which plasma is generated. The fluorine-containing gas can be or contains nitrogen trifluoride (NF3), dinitrogen hexafluoride (N2F6), another fluorine-containing gas, or a combination thereof. More precisely, the fluorine-containing plasma treatment directly incorporates a controlled amount of fluorine into the dielectric layer (e.g., the gate oxide layer). Furthermore, fluorine-containing gases containing molecular compounds (e.g., NF3, N2F6, or various molecules containing combinations of N with F, C, and / or H) help to incorporate nitrogen into the dielectric layer while reducing nitrogen permeation into the substrate, for example, due to the reduced energy associated with nitrogen during molecular decomposition. Therefore, the fluorine-containing plasma treatment may also include molecular nitriding or molecular nitriding processes.

[0026] In some instances, fluorinated plasma processing involves flowing a mixture of fluorinated gas and inert gas (e.g., helium (He), argon (Ar), etc.). In some instances, the fluorinated gas flows at a rate of 5 sccm to 15 sccm, and the inert gas flows at a rate equal to or greater than 100 sccm (e.g., in the range of 100 sccm to 200 sccm). In some instances, fluorinated plasma processing is performed in an inductively coupled plasma (ICP) processing chamber with high pressure (e.g., equal to or greater than 50 mTorr) and low source power (e.g., equal to or less than 300 watts (W)). The pressure of the fluorinated plasma processing can range from 50 mTorr to 300 mTorr. In some instances, the source power of the fluorinated plasma processing can be equal to or less than 100 W. The fluorinated plasma processing can be isotropic, e.g., without bias power.

[0027] At box 106, an annealing process is performed as needed to anneal the dielectric layer. The annealing process can be furnace annealing, spike annealing, and / or laser annealing (e.g., flash lamp annealing or pulsed laser annealing). Furnace annealing can be performed at temperatures ranging from 600°C to 800°C. The environment for furnace annealing can be or contains nitrogen (N2) or another gas. Typically, spike annealing is performed in a processing chamber containing a mixture of nitrogen (N2) and oxygen (O2) flowing at a peak temperature equal to or greater than 950°C (e.g., equal to or greater than 1,150°C). The flow rate of nitrogen (N2) is much greater than that of oxygen (O2), for example, at a ratio equal to or greater than 90:1 (N2:O2), and more precisely, at a ratio equal to or greater than 100:1 (N2:O2). Typically, laser annealing (e.g., flash annealing) achieves a peak temperature equal to or greater than 1,175°C, for example, in the range of 1,175°C to 1,350°C, for a duration equal to or less than 800 milliseconds, for example, in the range of 200 milliseconds to 400 milliseconds. In some instances, laser annealing (e.g., pulsed laser annealing) achieves a peak temperature equal to or greater than 1,175°C, for example, in the range of 1,175°C to 1,350°C, for a duration equal to or less than 200 nanoseconds, for example, in the range of 100 nanoseconds to 200 nanoseconds. Laser annealing can be performed in an ambient environment (e.g., a factory environment) or in an environment such as nitrogen (N2). Other annealing processes can be performed at box 106.

[0028] At box 108, a nitriding process is performed on the dielectric layer. The nitriding process causes the dielectric layer (e.g., an oxide layer) to be nitrided or contain nitrogen. In some instances, the nitriding process is decoupled plasma nitriding (DPN). As an example, DPN can be performed in an ICP processing chamber where nitrogen gas (N2) flows in a low-energy plasma (e.g., equal to or less than 2 kilowatts (kW)). The electrical duty cycle (e.g., the percentage of time the power is on relative to the total time) can range from 5% to 40%. The flow rate of nitrogen gas (N2) in the DPN can range from 100 sccm to 600 sccm. DPN can be performed in the processing chamber at a temperature ranging from 20°C to 40°C. DPN can be performed at a pressure ranging from 5 mTorr to 80 mTorr (e.g., 20 mTorr). DPN can be performed for a duration ranging from 20 seconds to 300 seconds. Another nitriding process can be implemented.

[0029] At box 110, a post-nitriding annealing process is performed on the dielectric layer. The post-nitriding annealing process of box 110 may be similar to the annealing process of box 106 described above. The post-nitriding annealing process at box 110 may restore bonds that broke during the previous DPN (e.g., for replacing oxygen with nitrogen) and may drive oxygen to, for example, the oxide-silicon interface.

[0030] The fluorine-containing plasma treatment of box 104 and the nitriding process of box 108 (alone or in combination) can be repeated any number of times, with various annealing processes performed or not performed in the iterations. For example, the fluorine-containing plasma treatment of box 104 can be added between the nitriding process of box 108 and the nitriding-annealing process of box 110.

[0031] Figure 2 This is a flowchart of a method 200 for forming a dielectric layer containing nitrogen and fluorine, based on some examples. The dielectric layer is formed at block 202, as described above. Figure 1 As described in box 102. At box 204, a nitriding process is performed on the dielectric layer, as described above. Figure 1 As described in box 108. At box 206, a nitriding followed by annealing process is performed on the dielectric layer, as described above regarding... Figure 1 As described in boxes 110 (and 106) in the diagram. At box 208, a fluorine-containing plasma treatment is performed on the dielectric layer, as described above regarding... Figure 1 As described in box 104. At box 210, an annealing process is performed on the dielectric layer, as described above regarding... Figure 1As described in box 106. The nitriding process of box 204 and the fluorine-containing plasma treatment of box 208 (alone or in combination) can be repeated any number of times, wherein various annealing processes are performed or not performed in the iterations. For example, the fluorine-containing plasma treatment of box 208 can be performed between the nitriding process of box 204 and the nitriding-annealing process at box 206, for example, except as described in box 106. Figure 2 The fluorine-containing plasma treatment of box 208 shown in the figure is other than or replaced by, for example Figure 2 Fluorine-containing plasma treatment of box 208 shown.

[0032] Figure 3A , 3B 3C is a chart showing the process parameters for example peak annealing based on some examples. Figure 3A , 3B Peak annealing of 3C products can be like Figure 1 and 2 The same process is performed for one or more annealing processes. Figure 3A Displays temperature in degrees Celsius. Figure 3B Shows the oxygen (O2) flow rate in sccm. Figure 3C The nitrogen (N2) flow rate is shown in sccm. In some instances, peak annealing is performed in a radiation chamber. Peak annealing includes a setup period 302, a stabilization period 304, a ramp-up period 306, and a cooling period 308.

[0033] At time t0, a semiconductor substrate with a dielectric layer formed on it enters the processing chamber, and a setup period 302 begins and continues until time t1. The temperature during setup period 302 may vary, for example, depending on the requirements of the processing chamber. Nitrogen (N2) flows into the processing chamber at a rate of 5,000 sccm at the beginning of time t0. The nitrogen (N2) flow rate then increases to 10,000 sccm during the setup period and is maintained throughout the remaining setup period 302, stabilization period 304, ramp-up period 306, and cooling period 308 (e.g., maintained until time t4), as... Figure 3C As shown in the diagram. During setup period 302, no oxygen (O2) flows into the processing chamber, as... Figure 3B As shown in the image.

[0034] At time t1, the steady-state period 304 begins and continues until time t2. Throughout the steady-state period 304, the temperature remains constant within the range of 500°C to 600°C (e.g., as shown in the image). Figure 3A (Approximately 525°C as shown). At time t1, oxygen (O2) begins to flow into the processing chamber at a rate of 100 sccm and is maintained throughout the stabilization period 304, the ramp-up period 306, and the cooling period 308 (e.g., maintained until time t4), as shown. Figure 3BAs shown in the diagram. The stabilization period 304 stabilizes the environment in the processing chamber (e.g., including gas flow rates) for performing spike annealing.

[0035] At time t2, the ramp-up period 306 begins and continues until time t3, at which point the temperature reaches its peak. The peak temperature can be equal to or greater than 950°C, for example, equal to or greater than 1,150°C (e.g., equal to 1,150°C, such as...). Figure 3A As shown). Figure 3A The temperature is depicted increasing from a steady-state temperature at time t2 to a peak temperature at time t3. The duration from time t2 to time t3 can range from 3 to 5 seconds. The rate of temperature increase can be substantially linear and can be equal to or greater than 100°C / second, and more precisely equal to or greater than 160°C / second.

[0036] Once the peak temperature is reached at time t3, the cooling phase 308 begins, during which the temperature decreases, as follows: Figure 3A As shown. The temperature can be decreased at any rate. In the example shown, the temperature decrease varies from 12 °C / s to approximately 50 °C / s. At time t4, the flow of oxygen (O2) stops, and the flow rate of nitrogen (N2) decreases to 5,000 sccm. The semiconductor substrate can then be removed from the processing chamber.

[0037] Figure 4 This is a flowchart of a method 400 for forming a metal-semiconductor compound (e.g., silicide, germanide, etc.) according to some examples. At block 402, a semiconductor material is exposed. The semiconductor material may be, for example, silicon (Si), silicon-germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), etc., or combinations thereof. The semiconductor material may be single-crystal, polycrystalline, or amorphous. The semiconductor material may be contained in a substrate, such as a semiconductor material on a semiconductor substrate, or may be on and / or above the substrate. Exposing the semiconductor material may involve removing another material, such as a dielectric material, from the semiconductor material. For example, a dielectric layer (e.g., an oxide layer) may be on the semiconductor material, and exposing the semiconductor material includes, for example, removing the dielectric layer by etching. If the dielectric layer is an oxide layer, exposing the semiconductor material may include using an etching process, such as wet etching, which uses hydrofluoric acid (HF), such as wet dilute hydrofluoric acid (dHF).

[0038] At box 404, a fluorine-containing plasma treatment is performed on the semiconductor material. The fluorine-containing plasma treatment can be similar to the process described above. Figure 1As described in box 104. Fluorine-containing plasma treatment causes fluorine to be incorporated into the semiconductor material. Fluorine-containing plasma treatment does not substantially etch the semiconductor material. At box 406, a cleaning process is performed on the semiconductor material. In some instances, the cleaning process may be operable to remove any oxides on the semiconductor material. For example, the cleaning process may be or include a dry etching process, which causes a gas combination containing nitrogen trifluoride (NF3) gas and ammonia (NH3) gas to flow, thereby etching silicon oxide. Another cleaning process may be performed. In some instances, the cleaning process may also incorporate some fluorine into the semiconductor material. At box 408, fluorine-containing plasma treatment is performed on the semiconductor material. Fluorine-containing plasma treatment may be similar to that described above with respect to box 404 and... Figure 1 The fluorine-containing plasma treatments in boxes 404 and 408 are described in various instances.

[0039] At box 410, a metal is formed on the semiconductor material. The metal can be or includes nickel (Ni), platinum (Pt), titanium (Ti), cobalt (Co), another metal, or a combination thereof. In some instances, any suitable deposition technique (e.g., sputtering, physical vapor deposition (PVD), etc.) can be used to form the metal on the semiconductor material. At box 412, an annealing process is performed. The annealing process reacts the metal and the semiconductor material to form a metal-semiconductor compound (e.g., silicide, germanide, etc.). The annealing process can be or includes rapid thermal annealing (RTA) or another annealing process.

[0040] Figures 5 to 9 These are cross-sectional views of semiconductor devices in the intermediate manufacturing stages, based on some examples. Figure 1 , 2 Methods 100, 200, and 400 can be used in 4. Figures 5 to 9 This is implemented within the context of the manufacture of semiconductor devices. Figures 5 to 9 Semiconductor devices manufactured in intermediate stages include FETs, and more specifically, n-channel FETs (e.g., n-channel metal-oxide-semiconductor (NMOS) transistors). In some instances, the semiconductor device may include a p-channel FET (e.g., a p-channel metal-oxide-semiconductor (PMOS) transistor). In other instances, different semiconductor devices may be manufactured.

[0041] refer to Figure 5A semiconductor substrate 502 is provided. The semiconductor substrate 502 may be or comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. The semiconductor substrate 502 may also comprise a support (or disposal) substrate and an epitaxial layer epitaxially grown on the support substrate. In some examples, the semiconductor substrate 502 is or comprises a silicon substrate (which may be sliced ​​from a bulk silicon wafer at the end of semiconductor processing). In other examples, the semiconductor substrate 502 comprises a silicon substrate on which an epitaxial silicon layer is grown. The semiconductor substrate 502 is or comprises a semiconductor material on which a device (e.g., a FET) is formed. In some examples, the semiconductor material is or comprises silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), etc., or combinations thereof. The semiconductor substrate 502 has an upper surface 504 on which a device (e.g., a FET) is formed. In the illustrated example, the semiconductor material of the semiconductor substrate 502 is p-doped with a p-type dopant. In some instances, the semiconductor substrate 502 uses a concentration of 1×10⁻⁶. 14 cm -3 Up to 1×10 15 cm -3 p-type dopant (e.g., boron (B)) within the range can be p-doped. Another dopant type and / or other doping concentrations may be implemented.

[0042] An isolation structure 510 is formed in a semiconductor substrate 502. In the illustrated example, the isolation structure 510 is a shallow trench isolation structure (STI) extending from the upper surface 504 of the semiconductor substrate 502 into the semiconductor substrate 502. In the illustrated example, the isolation structure 510 may have a corresponding upper surface coplanar with the upper surface 504 of the semiconductor substrate 502. In other examples, the isolation structure 510 may have a corresponding upper surface above and / or below the upper surface 504 of the semiconductor substrate 502. The isolation structure 510 may include, for example, a liner layer (e.g., comprising silicon oxide or silicon nitride) conformally along the surface of the corresponding trench in the semiconductor substrate 502, and a filling isolation material (e.g., silicon oxide) above and on the liner layer.

[0043] The isolation structure 510 can be formed by depositing a hard mask layer over a semiconductor substrate 502. The hard mask layer can be any suitable material, such as silicon nitride, silicon oxynitride, etc., and can be deposited using any suitable deposition process, such as chemical vapor deposition (CVD). The hard mask layer is patterned, for example, by using photolithography and etching processes (e.g., reactive ion etching (RIE)). Using the patterned hard mask layer as a mask, notches or trenches are etched in the semiconductor substrate 502, for example, by RIE. A liner layer can then be conformally formed or deposited in the notches or trenches, for example, by an oxidation process, plasma-enhanced CVD (PECVD), etc., and can be deposited over the patterned hard mask layer. A filler material can be deposited over the liner layer, for example, by high aspect ratio CVD (HAR-CVD), flowable CVD (FCVD), or the like. Excess filler material and liner layer can be removed from over the hard mask layer by a planarization process (e.g., chemical mechanical polishing (CMP)). The hard mask layer can then be removed by a planarization process and / or selective etching, which may be a wet etching process. In other examples, the isolation structure 510 may be a field oxide structure at the upper surface 504 of the semiconductor substrate 502, such as a localized oxidation of silicon (LOCOS) structure, which can be formed using a LOCOS process.

[0044] An isolation structure 510 laterally defines an active region on the upper surface 504 of a semiconductor substrate 502, on which a FET will be formed. A corresponding isolation structure 510 laterally surrounds the active region on the upper surface 504 of the semiconductor substrate 502, on which a FET will be formed.

[0045] To form a p-channel FET, well implantation can be performed. A well can be formed through well implantation. For example, an n-type doped well can be formed. An n-type doped well can be formed by masking (e.g., using photolithography with photoresist) a region of the semiconductor substrate 502 where no n-type doped well would be formed and implanting an n-type dopant into the semiconductor substrate 502. The n-type doped well can extend from the upper surface 504 of the semiconductor substrate 502 to a depth within the semiconductor substrate 502, which can be a horizontal plane below, at, or above the bottom surface of the isolation structure 510. The isolation structure 510 can generally laterally define the n-type doped well. The concentration of the n-type dopant in the n-type doped well can be greater than the concentration of the p-type dopant in the p-type doped semiconductor substrate 502. In some examples, the n-type doped well can be doped with a concentration of 1 × 10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 The range of n-type dopants (e.g., phosphorus (P) or arsenic (As)) is acceptable. Other doping concentrations and / or dopant types may be implemented for the doped well.

[0046] A gate dielectric layer 520 is formed above and on a semiconductor substrate 502. In the illustrated example, the gate dielectric layer 520 is formed on the upper surface 504 of the semiconductor substrate 502. The gate dielectric layer 520 is nitrided (e.g., containing nitrogen gas) and contains fluorine. In some examples, the gate dielectric layer 520 comprises nitrided silicon oxide and contains fluorine.

[0047] Gate dielectric layer 520 according to Figure 1 and 2 The gate dielectric layer 520 is formed by any of methods 100 and 200. In the illustrated example, forming the gate dielectric layer 520 includes forming an oxide layer, for example by an oxidation process, similar to that described above. Figure 1 and 2 The ISSG oxidation is described in boxes 102 and 202. Although only one FET is shown in the figure, any number of different gate dielectric layers for FETs can be formed on the semiconductor substrate 502. The different gate dielectric layers can have different thicknesses, allowing the corresponding FETs to have different operating voltage ratings (e.g., 1.5 V, 1.8 V, 3.3 V, 5 V, etc.). The different gate dielectric layers of the FETs can be subjected to… Figure 1 The subsequent operation of methods 100 and 200, and / or 2. FETs with different operating voltage ratings can also achieve the advantages and benefits described herein.

[0048] Following the various sequences described above, a fluorine-containing plasma treatment is performed on the gate dielectric layer 520 (e.g., a gate oxide layer) to dope fluorine (and nitrogen as described above) into the gate dielectric layer 520, and a nitriding process is performed on the gate dielectric layer 520 to nitrid the gate dielectric layer 520 and / or to dope nitrogen into the gate dielectric layer 520. Various annealing processes can be performed, as described above regarding... Figure 1 and 2 As described.

[0049] refer to Figure 6A gate electrode 602 is formed above and on the gate dielectric layer 520. The gate electrode 602 can be or contains any conductive material, such as a metal, a doped semiconductor material, or a combination thereof. A material layer of the gate electrode 602 can be formed above the gate dielectric layer 520 (e.g., in a layer). The material layer of the gate electrode 602 can be deposited above the gate dielectric layer 520 using any deposition process (e.g., CVD). In some instances, the gate electrode 602 is or contains a semiconductor material, such as polycrystalline silicon, and in some such instances, the semiconductor material can be doped in situ during deposition and / or implanted with a dopant after deposition (e.g., during implantation to form the source / drain regions). In some instances, the gate electrode 602 is polycrystalline silicon, which is p-type doped with a p-type dopant (e.g., for a p-channel FET) or n-type doped with an n-type dopant (e.g., for an n-channel FET) at a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 Within the range. A hard mask layer can be formed over the material of the gate electrode 602, for example, for subsequent patterning. In some instances, the hard mask layer may be or contain silicon nitride deposited by CVD, but in other instances other hard mask (e.g., dielectric) materials and / or other deposition processes may be used. The material of the gate electrode 602 may then be patterned into the gate electrode 602. In some instances, the hard mask layer is patterned corresponding to a pattern of the gate electrode 602, and the patterned hard mask layer is used as a mask to pattern the gate electrode 602. The hard mask layer can be patterned using appropriate photolithography and etching processes, and the gate electrode 602 can be patterned using appropriate etching processes. For example, anisotropic etching, such as RIE, can be performed. The hard mask layer can be removed, for example, by selective etching and / or wet stripping processes on the material of the hard mask layer.

[0050] As shown in the figure, for example when the gate electrode 602 comprises a semiconductor material (e.g., polysilicon), a re-oxidation layer 604 is formed on the exposed surface of the gate electrode 602. In some instances, the re-oxidation layer 604 may be omitted. The re-oxidation layer 604 can be formed by an oxidation process, such as ISSG oxidation, thermal oxidation, or another oxidation process. The re-oxidation layer 604 can remove surface damage to the gate electrode 602 caused by patterning the gate electrode 602.

[0051] A lightly doped drain (LDD) region 606 is formed in a semiconductor substrate 502. The LDD region 606 is formed on the laterally opposite side of the gate electrode 602 in the semiconductor substrate 502. The LDD region 606 can be formed by masking (e.g., using photolithography with photoresist) a region where the LDD region 606 is not formed and implanting a p-type dopant (e.g., for a p-channel FET) or an n-type dopant (e.g., for an n-channel FET) into the semiconductor substrate 502. The gate electrode 602 can also be doped and acts as a mask to prevent dopant implantation in at least some portions of the semiconductor substrate 502 underlying the gate electrode 602. The concentration of the p-type or n-type dopant in the LDD region 606 can be greater than the concentration of the p-type dopant in the p-type doped semiconductor substrate 502, and if an n-type doped well is implemented for a p-channel FET, the concentration of the p-type or n-type dopant in the LDD region 606 can be greater than the concentration of the n-type dopant in the n-type doped well. In some instances, LDD region 606 can be doped with a concentration of 1×10⁻⁶. 16 cm -3 Up to 1×10 19 cm -3 p-type or n-type dopants within the range.

[0052] refer to Figure 7 A gate spacer 702 is formed on or along a corresponding sidewall of the gate electrode 602 (e.g., on the re-oxide layer 604). The gate spacer 702 can be formed by conformally depositing a material layer of the gate spacer 702 over the semiconductor substrate 502 and anisotropically etching the layer to retain the gate spacer 702. The material of the gate spacer 702 can be or includes silicon nitride, silicon oxynitride, another dielectric material, or a combination thereof. The layer can be deposited by CVD, PECVD, atomic layer deposition (ALD), etc., and can be etched by anisotropic etching processes (e.g., RIE).

[0053] Source / drain regions 704 are formed in a semiconductor substrate 502. The source / drain regions 704 are located on opposite lateral sides of the gate electrode 602 and the gate spacer 702. An LDD region 606 is located between the source / drain regions 704 and below the respective gate spacer 702. The source / drain regions 704 can be formed by masking (e.g., using photolithography with photoresist) areas where no source / drain regions are formed and by implanting p-type dopant (e.g., for a p-channel FET) or n-type dopant (e.g., for an n-channel FET) into the semiconductor substrate 502. The gate electrode 602 and the gate spacer 702 (having a re-oxidation layer 604 thereon) can also be doped and act as a mask to prevent dopant implantation into at least some portions of the semiconductor substrate 502 beneath the gate electrode 602 and the gate spacer 702. The concentration of p-type or n-type dopant in the source / drain region 704 is greater than the concentration of n-type dopant in the n-type doped well (if implemented), the concentration of p-type or n-type dopant in the LDD region 606, and the concentration of p-type dopant in the p-type doped semiconductor substrate 502. In some examples, the source / drain region 704 may be doped with a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 p-type or n-type dopants within the range.

[0054] refer to Figure 8 A metal-semiconductor compound 802 is formed on the semiconductor substrate 502 at the source / drain region 704, and a metal-semiconductor compound 804 is formed on the gate electrode 602. The metal-semiconductor compound 804 is formed, for example, in instances where the gate electrode 602 is or comprises a semiconductor material (e.g., polysilicon). In other instances, the metal-semiconductor compound 804 may be omitted. Figure 4 Method 400 forms metal-semiconductor compounds 802 and 804. According to... Figure 4 Block 402 exposes the upper surface 504 of the semiconductor substrate 502 at the source / drain region 704 and the upper surface of the gate electrode 602. Exposing these surfaces involves removing corresponding portions of the gate dielectric layer 520 and the re-oxide layer 604. These corresponding portions can be removed using a selective etching process for the gate dielectric layer 520 and the re-oxide layer 604. For example, when the gate dielectric layer 520 is silicon oxide, a wet etching process containing dilute hydrofluoric acid (dHF) can be used to remove the corresponding portions of the gate dielectric layer 520 and the re-oxide layer 604. One or more fluorine-containing plasma treatments are performed in blocks 404 and 408, and the cleaning process in block 406 is performed, as described above. Figure 4 In block 410, metal is formed above semiconductor substrate 502, and according to block 412, an annealing process is performed to cause the semiconductor and metal to react. Figure 8 In this example, the metal reacts with the semiconductor material on the upper surface 504 of the source / drain region 704 of the semiconductor substrate 502 to form a metal-semiconductor compound 802, and the metal reacts with the semiconductor material of the gate electrode 602 to form a metal-semiconductor compound 804. Any unreacted metal can then be removed, for example, by a selective etching process.

[0055] exist Figure 9 In this process, a dielectric layer 902 is formed over a semiconductor substrate 502, a gate spacer 702, and metal-semiconductor compounds 802 and 804. The dielectric layer 902 may comprise multiple sublayers, such as a conformally conformally formed contact etch stop layer (CESL) over the semiconductor substrate 502 and a metal front dielectric (PMD) layer over the CESL. The CESL may be or comprise silicon nitride, silicon oxynitride, or a combination thereof. The PMD layer may be or comprise silicon oxide, silicon nitride, or a combination thereof. The dielectric layer 902 may be deposited using CVD, PECVD, ALD, or similar methods. The dielectric layer 902 may be planarized, for example, by a CMP process.

[0056] Contact 912 is formed on the source / drain region 704 onto the metal-semiconductor compound 802. Contact 912 extends through the dielectric layer 902 and contacts the corresponding metal-semiconductor compound 802 on the source / drain region 704. Contact 912 may each include one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc. or combinations thereof) conformally located in the corresponding openings through the dielectric layer 902, and filler metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc. or combinations thereof) above and / or on the one or more barrier and / or adhesion layers.

[0057] To form the contact 912, a corresponding opening through the dielectric layer 902 to the metal-semiconductor compound 802 can be formed using appropriate photolithography and etching processes. One or more metals of the contact 912 are deposited in the openings through the dielectric layer 902. One or more suitable deposition processes (e.g., CVD, PVD, etc.) can be used to deposit the one or more metals. Any excess metal can be removed, for example, by CMP and / or by patterning using photolithography and etching processes. Subsequent back-end processing (BEOL) can then be performed.

[0058] like Figure 9As shown, the FET includes a gate electrode 602, a gate dielectric layer 520 underlying the gate electrode 602, source / drain regions 704 in a semiconductor substrate 502, LDD regions 606 in the semiconductor substrate 502, and a channel region in the semiconductor substrate 502. The channel region is underlying (e.g., directly underlying) the gate electrode 602 and the gate dielectric layer 520. The channel region lies between the LDD regions 606 and between the source / drain regions 704. One LDD region 606 lies between the channel region and the corresponding source / drain region 704, and another LDD region 606 lies between the channel region and another source / drain region 704. Gate spacers 702 are located along the respective sidewalls of the gate electrode 602. If the FET is an n-channel FET, the source / drain regions 704 and LDD regions 606 may be n-type doped. If the FET is a p-channel FET, the source / drain region 704 and the LDD region 606 can be p-type doped, and the p-channel FET can further include an n-type doped well in the semiconductor substrate 502, wherein the source / drain region 704 and the LDD region 606 are in the n-type doped well.

[0059] In formation Figure 9 The FET shown is used Figure 1 and 2 Any of methods 100 and 200 causes the gate dielectric layer 520 to be nitrided (e.g., containing nitrogen) and fluorinated (e.g., containing fluorine). Fluorine can be incorporated into the gate dielectric layer 520 in a controlled manner. In some instances, fluorine is not implanted into the gate dielectric layer 520 and the gate electrode 602 by an implantation process. Fluorine-containing plasma treatment can allow fluorine to diffuse to a shallow depth in the gate dielectric layer 520, such as 22 angstroms or less. Therefore, fluorine may not be present at a significant depth in the semiconductor substrate 502. Furthermore, since fluorine is incorporated into the gate dielectric layer 520 prior to the formation of the gate electrode 602 and the gate electrode 602 is not implanted with fluorine, in some instances, the gate electrode 602 does not contain fluorine at least in the portion adjacent to the gate dielectric layer 520. In some instances, another portion of the gate electrode 602 at the metal-semiconductor compound 804 may contain fluorine due to the formation of the metal-semiconductor compound 804 as described above.

[0060] Figure 10This is a graph illustrating fluorine distributions 1002, 1004, and 1006 across gate electrode 602, gate dielectric layer 520, and semiconductor substrate 502 according to some examples. As shown, for any of fluorine distributions 1002, 1004, and 1006, there is no significant amount of fluorine in a portion of gate electrode 602 near gate dielectric layer 520 (e.g., no fluorine). For each of fluorine distributions 1002, 1004, and 1006, the fluorine concentration peaks in gate dielectric layer 520. For each of fluorine distributions 1002, 1004, and 1006, some fluorine is present in semiconductor substrate 502 at the interface between gate dielectric layer 520 and semiconductor substrate 502. The fluorine concentration decreases to a negligible amount (e.g., no fluorine) in semiconductor substrate 502 at a relatively shallow depth from the interface (e.g., no deeper than 15 angstroms from the interface). In some instances, the gate dielectric layer 520 may have a fluorine concentration of 29 atoms and a nitrogen concentration of 19 atoms.

[0061] Fluorine doping via fluorine-containing plasma, as described, allows for more controlled doping, enabling a reduction in the thickness of the gate dielectric layer 520. Furthermore, as the thickness of the gate dielectric layer 520 decreases, fluorine-containing plasma treatment allows nitriding of the gate dielectric layer 520 to occur based on molecular nitriding, which reduces nitrogen diffusion into the semiconductor substrate 502. Reducing nitrogen diffusion into the semiconductor substrate 502 reduces nitrogen-induced fixed charge, which may be undesirable for the reliability characteristics of the FET. Fluorine can improve the quality of the interface between the gate dielectric layer 520 (e.g., the gate oxide layer) and the semiconductor substrate 502. Fluorine can fill vacancies and defects at the interface to improve quality. Improved interface improves carrier mobility in the channel region of the FET. By reducing fixed charge and improving carrier mobility in the channel region, doping in the channel region can be reduced, which allows for reduced variability in the electrical characteristics of the FET, thus reducing performance mismatch between the FET and noise.

[0062] In the experiment, an improvement in the performance of the NMOS transistor was observed. The drain-source on-state current (Id) of the core NMOS transistor was... DS Compared to the drain-source turn-off current (I) OFF An improvement of approximately 12% was observed. Furthermore, I0 was observed in both 1.8 V input / output (IO) NMOS and PMOS transistors. DS -I OFF There has been some improvement. The drain-induced barrier lowering (DIBL) of the core NMOS transistor has decreased by approximately 6%.

[0063] use Figure 4Method 400 for forming a metal-semiconductor compound 802 involves incorporating fluorine into the metal-semiconductor compound 802 and into the semiconductor substrate 502 at the upper surface 504 of the metal-semiconductor compound 802. The concentration of fluorine can decrease (e.g., rapidly) from the interface between the metal-semiconductor compound 802 and the semiconductor substrate 502 to the depth within the semiconductor substrate 502. Fluorine can interact with defects (e.g., silicon interstitial atoms) in the semiconductor substrate 502, which can reduce metal channeling into the semiconductor substrate 502. Metal channeling into the semiconductor substrate 502 (e.g., via nickel) can penetrate the pn junction in the semiconductor substrate 502, thereby adversely affecting the FET in which metal channeling occurs. Therefore, reducing metal channeling can improve the operation and reliability of the FET. Similarly, using Figure 4 Method 400 is used to form a metal-semiconductor compound 804 by incorporating fluorine into the metal-semiconductor compound 804 and forming a gate electrode 602 in the upper portion of the metal-semiconductor compound 804. The concentration of fluorine can decrease (e.g., rapidly) from the interface between the metal-semiconductor compound 804 and the gate electrode 602 to the depth within the gate electrode 602.

[0064] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations may be made therein without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: Semiconductor substrate; A gate dielectric layer located above the semiconductor substrate, the gate dielectric layer comprising silicon nitride including fluorine; and A gate electrode is located above the gate dielectric layer, the gate electrode comprising a first portion adjacent to the gate dielectric layer, the first portion being free of fluorine.

2. The semiconductor device of claim 1, wherein the semiconductor substrate comprises fluorine at the interface between the semiconductor substrate and the gate dielectric layer.

3. The semiconductor device of claim 1, further comprising a first source / drain region and a second source / drain region located in the semiconductor substrate, the first source / drain region being located on the side of the gate electrode laterally opposite to the second source / drain region.

4. The semiconductor device of claim 3, further comprising a metal-semiconductor compound located on the semiconductor substrate at the first source / drain region, the metal-semiconductor compound comprising fluorine.

5. The semiconductor device of claim 4, wherein the metal-semiconductor compound comprises a silicide including nickel.

6. The semiconductor device of claim 1, further comprising a metal-semiconductor compound on the gate electrode, the gate electrode comprising polycrystalline silicon, the gate electrode comprising a second portion located at the metal-semiconductor compound, the metal-semiconductor compound comprising fluorine.

7. A method comprising: An oxide layer is formed over a semiconductor substrate; The oxide layer is subjected to fluorine-containing plasma treatment; and The oxide layer is nitrided.

8. The method of claim 7, wherein the fluorine-containing plasma treatment is performed prior to nitriding the oxide layer.

9. The method of claim 7, wherein the oxide layer is nitrided prior to performing the fluorine-containing plasma treatment.

10. The method of claim 7, further comprising performing an annealing process after performing the fluorine-containing plasma treatment and nitriding the oxide layer.

11. The method of claim 7, wherein the fluorine-containing plasma treatment is performed at a pressure equal to or greater than 50 millitor.

12. The method of claim 7, wherein the fluorine-containing plasma treatment is performed at a source power of 300 watts or less.

13. The method of claim 7, wherein the fluorine-containing plasma treatment comprises flowing a gas mixture comprising nitrogen trifluoride (NF3) gas, dinitrogen hexafluoride (N2F6) gas, or a combination thereof.

14. The method of claim 7, wherein the fluorine-containing plasma treatment comprises: Fluorine-containing gas is allowed to flow at a rate ranging from 5 standard cubic centimeters per minute (sccm) to 15 sccm; The inert gas is flowed at a rate in the range of 100 sccm to 200 sccm; Pressure range of 50 mTorr to 300 mTorr; and Source power equal to or less than 100 watts.

15. The method of claim 7, further comprising forming a gate electrode over the oxide layer after performing the fluorine-containing plasma treatment and nitriding the oxide layer.

16. A method comprising: A gate oxide layer is formed above the semiconductor substrate; Incorporating fluorine into the gate oxide layer includes plasma treatment; Nitriding the gate oxide layer; and A gate electrode is formed over the gate oxide layer.

17. The method of claim 16, wherein the plasma treatment is performed prior to nitriding the gate oxide layer.

18. The method of claim 16, wherein nitriding of the gate oxide layer is performed prior to the plasma treatment.

19. The method of claim 16, further comprising annealing the gate oxide layer after the plasma treatment and nitriding of the gate oxide layer.

20. The method of claim 16, wherein the plasma treatment comprises flowing a fluorine-containing gas.

21. The method of claim 16, wherein the plasma treatment uses a source power of 300 watts or less and a pressure of 50 millitors or more.

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