Method for improving gate height difference and semiconductor device

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, and discloses a method for improving gate height difference and a semiconductor device. The application selectively retains a photoresist layer on an NMOS region, exposes a first etching protection layer on a PMOS region, and then etches the first etching protection layer on the PMOS region and the photoresist layer and the first etching protection layer on the NMOS region until the top of a gate structure and the semiconductor substrate outside the gate structure sidewall on the PMOS region are exposed, so that the height of the gate structure after etching is the same, and other operations for compensating the height difference are not needed, and the subsequent process is simplified.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method and semiconductor device for improving gate height difference. Background Technology

[0002] With the development of semiconductor technology, the feature size of various semiconductor devices is constantly shrinking, which limits the mobility of transistors and poses a challenge to improving the performance of semiconductor devices. To overcome these limitations, strained silicon germanium (SiGe) technology has emerged as a leading candidate technology. Strained silicon germanium technology introduces strain into the silicon substrate material to change the lattice structure of silicon, thereby effectively improving device performance. Strain can not only significantly improve the mobility and switching speed of transistors, but also enhance the performance and efficiency of the entire circuit.

[0003] As Complementary Metal Oxide Semiconductor (CMOS) processes reach critical dimensions of 28nm and below, strained germanium-silicon technology is essential to optimize PMOS hole mobility, reduce short-channel effects, and enhance driving capability. Strained germanium-silicon technology first forms a Sigma trench structure in the PMOS region, and then forms an epitaxial layer within the Sigma trench structure, thereby improving PMOS device performance. The formation of the Sigma trench structure requires a cap-on-P operation, where a protective layer covers the NMOS region while simultaneously opening the PMOS region, allowing subsequent Sigma trench etching and germanium-silicon epitaxial growth to occur only in the PMOS region. This operation results in a difference in the thickness of the protective layer over the NMOS and PMOS regions. Without compensation, this height difference will be directly transmitted to subsequent processes, potentially increasing the difficulty of process window control or even leading to device performance mismatch or yield loss. Summary of the Invention

[0004] This invention discloses a method and semiconductor device for improving gate height difference, so that after etching, the gate height difference of NMOS and PMOS are the same, simplifying subsequent processes.

[0005] The first aspect of this invention discloses a method for improving gate height difference, the method comprising: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure is formed on the NMOS region and the PMOS region respectively, a first etch protection layer is formed on the top and sidewalls of the gate structure and on the exposed semiconductor substrate, a photoresist layer is formed on the first etch protection layer on the NMOS region and the first etch protection layer on the PMOS region is exposed. The first etch protection layer located on the PMOS region and the photoresist layer and the first etch protection layer on the NMOS region are etched until the top of the gate structure and the semiconductor substrate outside the gate structure sidewalls on the PMOS region are exposed, so that the height of the etched gate structure is the same.

[0006] As can be seen, in this embodiment of the invention, by selectively retaining the photoresist layer on the NMOS region and exposing the first etch protection layer on the PMOS region, the first etch protection layer on the PMOS region and the photoresist layer and the first etch protection layer on the NMOS region are etched until the top of the gate structure and the semiconductor substrate outside the sidewall of the gate structure on the PMOS region are exposed, so that the height of the etched gate structure is the same, thereby eliminating the need to perform other operations to compensate for the height difference and simplifying the subsequent process.

[0007] As an optional implementation, in a first aspect of the invention, a second etch protection layer is formed above the gate structure, the second etch protection layer being located on the side of the gate structure away from the semiconductor substrate, and a first etch protection layer is formed on the top of the second etch protection layer, the sidewalls of the second etch protection layer and the gate structure, and on the exposed semiconductor substrate. The etching of the first etch protection layer located on the PMOS region and the photoresist layer and the first etch protection layer located on the NMOS region includes: The photoresist layer on the NMOS region is etched back to below the top of the second etch protection layer to expose the first etch protection layer on the top of the gate structure on the NMOS region and the first etch protection layer on the sidewall of the second etch protection layer. The first etch protection layer located on the PMOS region and the first etch protection layer on the top of the gate structure on the NMOS region and the first etch protection layer on the sidewall of the second etch protection layer are etched.

[0008] As can be seen, in this embodiment of the invention, before etching the first etch protection layer, a photoresist back etching is added to etch the photoresist layer on the NMOS region back to below the top of the second etch protection layer, so as to expose the first etch protection layer on the top of the gate structure and the first etch protection layer on the sidewall of the second etch protection layer on the NMOS region. In this way, when subsequent etching is performed, after the first etch protection layer on the top of the gate structure is completely consumed, the second etch protection layer above the gate structure will also be subjected to the same loss, so that after etching, the height of the gate structure above the NMOS and PMOS will not be significantly different.

[0009] As an optional implementation, in the first aspect of the invention, the photoresist layer and the first etch protection layer on the NMOS region are partially consumed. After etching the first etch protection layer located on the PMOS region and the first etch protection layer on the top of the gate structure and the first etch protection layer on the sidewall of the second etch protection layer on the NMOS region, the method further includes: Remove the remaining portion of the photoresist layer on the NMOS region to expose a stepped first etch protection layer on the NMOS region. The stepped first etch protection layer is formed on the sidewall of the gate structure of the NMOS region.

[0010] As can be seen, in this embodiment of the invention, the photoresist etch-back process does not completely consume all the photoresist layer. A portion of the sidewalls of the gate structure on the NMOS region is not covered by the photoresist layer, while another portion is. During the etching operation, when the first etch protection layer on the semiconductor substrate other than the sidewalls of the gate structure on the PMOS region is completely consumed, the first etch protection layer on the sidewalls of the gate structure on the NMOS region is also consumed, but not entirely. Therefore, it forms a stepped first etch protection layer together with the unconsumed sidewalls of the first etch protection layer and the first etch protection layer on the semiconductor substrate other than the gate structure on the NMOS region. It can be seen that in the process of improving the height difference between the gate structures above the NMOS and PMOS, this embodiment of the invention also forms a stepped first etch protection layer. This stepped first etch protection layer is exposed after the photoresist layer is removed, allowing the etching amount on the sidewalls of the gate structure to be controllably distributed along the height direction. This stepped first etching protective layer avoids the "one-cut" etching effect caused by a uniform protective layer, providing additional controllability for subsequent processes, and thus producing unexpected beneficial effects.

[0011] As an optional implementation, in a first aspect of the invention, the step height of the stepped first etch protection layer is used to regulate the ion concentration gradient of the subsequent source / drain implantation region and / or threshold voltage adjustment implantation region of the NMOS region. Before etching the photoresist layer on the NMOS region back below the top of the second etch protection layer to expose the first etch protection layer on top of the gate structure on the NMOS region and the first etch protection layer on the sidewall of the second etch protection layer, the method further includes: The step height of the stepped first etched protective layer is determined based on the design performance. The re-etching endpoint position and the etching endpoint position are determined based on the step height of the stepped first etching protective layer.

[0012] As can be seen in this embodiment of the invention, the step-like first etch protection layer—an unexpected byproduct of improving the height difference between the gate structures above NMOS and PMOS—can subsequently have its concentration gradient controlled by adjusting the step height. This allows designers to deduce the required ion concentration gradient characteristics based on the target device performance indicators. For example, the correlation between step height and concentration gradient can be qualitatively studied experimentally. After this correlation is experimentally determined, the step height can be determined by looking up a table based on the required concentration gradient characteristics, directly transforming the electrical design goal into processable geometric parameters, namely the etch-back endpoint and the etch-back endpoint. This approach facilitates a closed loop from performance design to process implementation, reducing the blind spots in process development and increasing the success rate of new product fabrication. Secondly, since the step height is continuously controllable, the ion concentration gradient also becomes continuously controllable, realizing ion concentration gradient design from qualitative to quantitative methods.

[0013] As an optional implementation, in the first aspect of the present invention, an NMOS source-drain region is formed in the NMOS region near the gate structure side, an NMOS conductive channel region is formed between the NMOS source-drain regions, the threshold voltage adjustment injection region is located below the gate structure of the NMOS region near the NMOS conductive channel region, and the source-drain injection regions are located on both sides of the gate structure of the NMOS region away from the NMOS conductive channel region.

[0014] As an optional implementation, in a first aspect of the invention, after etching the first etch protection layer located on the PMOS region and the photoresist layer and the first etch protection layer on the NMOS region until the top of the gate structure and the semiconductor substrate other than the gate structure sidewalls on the PMOS region are exposed, the method further includes: A sigma trench is formed in the semiconductor substrate outside the gate structure sidewalls on the PMOS region.

[0015] As can be seen, in this embodiment of the invention, after the gate height equalization etching is completed, the semiconductor substrate outside the sidewalls of the PMOS region gate structure has been exposed. This embodiment of the invention fully utilizes this exposure window, directly etching sigma trenches in the PMOS region substrate, eliminating the need for a dedicated source / drain region windowing photolithography step, thereby shortening the process time. Simultaneously, the formation of sigma trenches helps optimize PMOS hole mobility, reduce short-channel effects, and enhance driving capability.

[0016] As an optional implementation, in a first aspect of the present invention, the PMOS region has a PMOS source-drain structure. After etching the first etch protection layer located on the PMOS region and the photoresist layer and the first etch protection layer on the NMOS region until the top of the gate structure and the semiconductor substrate other than the gate structure sidewalls on the PMOS region are exposed, the method further includes: A sigma trench is formed in the PMOS source-drain structure.

[0017] As can be seen, in this embodiment of the invention, the source and drain structures of the PMOS region have already been formed. The sigma trench etching directly uses the existing boundaries of the PMOS source and drain structures as the etching range, eliminating the need for dedicated photolithographic windows for the sigma trenches. This avoids excessive expansion of the trenches in unintended directions, and the etching range has self-constraining characteristics. In addition, the bottom of the trench remains inside the source and drain structures, far from the substrate junction region, reducing the risk of leakage and defects.

[0018] As an optional implementation, in the first aspect of the present invention, the PMOS region is further provided with a shallow trench isolation structure, the shallow trench isolation structure being located on both sides of the PMOS source-drain structure.

[0019] As can be seen, in this embodiment of the invention, when forming a sigma trench in the PMOS source-drain structure, the etching not only extends in the depth direction and along the channel direction, but also has a lateral etching component in the gate width direction. This shallow trench isolation structure can form a physical barrier in the gate width direction. The shallow trench isolation structures on both sides can define the width of the source-drain active region, allowing the sigma trench to be formed within this width range with good width consistency, avoiding the trench width drift along the gate width direction caused by the lack of constraint on the active region. At the same time, if the PMOS region does not have a shallow trench isolation structure for boundary constraint, the lateral etching of the sigma trench may cross the PMOS region boundary and erode the active region of the NMOS region, causing short circuits or leakage between devices. In addition, the shallow trench isolation structure itself is a standard active region isolation structure in CMOS technology. This embodiment does not introduce an additional dedicated isolation structure, but rather utilizes the existing shallow trench isolation structure to additionally exert the sigma trench boundary constraint function, achieving unexpected functions without adding additional process steps.

[0020] As an optional implementation, in a first aspect of the invention, the shallow trench isolation structure is located on both sides of the gate structure on the PMOS source-drain structure away from the PMOS region.

[0021] As can be seen, in this embodiment of the invention, compared with the previous embodiment, the shallow trench isolation structure is further restricted to both sides of the gate structure on the PMOS source-drain structure away from the PMOS region, so that the critical region between the gate and the source-drain is not directly disturbed by the mechanical stress caused by the shallow trench isolation structure, ensuring that the main contribution of the channel strain comes from the controllable sigma trench epitaxy, rather than the edge effect caused by the uncontrollable shallow trench isolation structure.

[0022] A second aspect of the present invention discloses a semiconductor device fabricated according to any one of the methods for improving gate height difference as described in the first aspect.

[0023] The unexpected technical effects achieved by the second aspect of the present invention are derived from the derivation of the beneficial effects of a method for improving gate height difference in the first aspect described above, and will not be repeated here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic flowchart of a prior art Sigma trench forming method is shown; Figure 2 It shows Figure 1 The diagram shows the structure of each step in the method shown. Figure 3 A flowchart illustrating a prior art method for improving gate height difference is shown. Figure 4 It shows Figure 3 The diagram shows the structure of each step in the method shown. Figure 5 A flowchart illustrating the first method for improving gate height difference in this invention is shown; Figure 6 It shows Figure 5 The diagram shows the structure of each step in the method shown. Figure 7 A schematic diagram of a gate structure provided in an embodiment of the present invention is shown; Figure 8 A flowchart illustrating the second method for improving gate height difference in this invention is shown. Figure 9 It shows Figure 8 The diagram shows the structure of each step in the method shown. Figure 10A flowchart illustrating the third method for improving gate height difference in this invention is shown; Figure 11 It shows Figure 10 The diagram shows the structure of each step in the method shown. Figure 12 A flowchart illustrating the fourth method for improving gate height difference in this invention is shown. Figure 13 A schematic diagram of the structure of a semiconductor device according to the present invention is shown; Figure 14 A flowchart illustrating the fifth method for improving gate height difference in this invention is shown. Figure 15 It shows Figure 14 The diagram shows the structure of each step in the method shown. Figure 16 A flowchart illustrating the sixth method for improving gate height difference in this invention is shown. Figure 17 It shows Figure 16 The diagram shows the structure of each step in the method shown.

[0026] In the figure: 100, N-well; 110, source-drain structure; 200, P-well; 210, NMOS source region; 220, NMOS conductive channel region; 230, threshold voltage adjustment injection region; 240, drain injection region; 300, gate structure; 301, substrate protection layer; 302, gate dielectric layer; 303, gate layer; 304, shielding layer; 400, first etch protection layer; 500, photoresist layer; 600, sigma trench; 700, second etch protection layer; 800, germanium-silicon epitaxial layer. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] Existing technology Please see Figure 1 and Figure 2 , Figure 1 A schematic flowchart of a prior art Sigma trench formation method is shown. Figure 2 It shows Figure 1 The diagram illustrates the structure of each step in the method shown. The existing Sigma trench formation method mainly includes the following steps: Step S101: Provide a semiconductor substrate, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure 300 is formed on the NMOS region and the PMOS region respectively, a first etch protection layer 400 is formed on the top and sidewalls of the gate structure and on the exposed semiconductor substrate, a photoresist layer 500 is formed on the first etch protection layer 400 on the NMOS region and the first etch protection layer 400 on the PMOS region is exposed.

[0031] Step S102: Etch the first etch protection layer 400 located on the PMOS region until the top of the gate structure 300 and the semiconductor substrate outside the sidewalls of the gate structure 300 on the PMOS region are exposed.

[0032] Step S103: A sigma trench 600 is formed in the semiconductor substrate outside the sidewall of the gate structure 300 in the PMOS region.

[0033] Step S104: Remove the remaining portion of the photoresist layer 500 on the NMOS region.

[0034] from Figure 2It can be seen that, due to the protection of the photoresist, the hard mask layer on the NMOS region cannot be etched away or is etched away less than that on the PMOS region. As a result, the heights of the hard mask layers on the gate structures on the PMOS region and the gate structures on the NMOS region in the final semiconductor device are inconsistent, which causes great difficulties for subsequent processes.

[0035] To address this height difference, existing technologies typically employ photoresist etch-back (PREB) and hard mask etch-back (HMEB). See [link to relevant documentation]. Figure 3 and Figure 4 , Figure 3 A schematic flowchart of a prior art method for improving gate height difference is shown. Figure 4 It shows Figure 3 The diagram illustrates the structure of each step in the method shown. A prior art method for improving gate height difference mainly includes the following steps: Step S105: Spin-coat the photoresist again to form a photoresist layer 500; Step S106: The spin-coated photoresist layer 500 is etched back to the area between the second etch protection layer 700 on the PMOS region and the first etch protection layer 400 on the gate structure 300 on the NMOS region. The second etch protection layer 700 is located at the head of the gate. Step S107: The first etch protection layer 400 is etched back to the second etch protection layer 700 until the height of the hard mask layer on the gate structure 300 on the PMOS region and the gate structure 300 on the NMOS region is consistent. Step S108: Remove the remaining portion of the photoresist layer 500 on the NMOS region and the PMOS region.

[0036] It should be noted that, Figure 1 N-well 100 and P-well 200 are formed by impurity implantation, and Figure 3 Non-closely related steps, such as growing germanium-silicon epitaxial layers at 800°C, have been omitted.

[0037] As can be seen, the above-mentioned method for improving the gate height difference is cumbersome and requires at least three additional steps. Moreover, before performing these three steps, SiGe epitaxial growth must be performed first; otherwise, the photoresist layer spin-coated in step S105 will fill the formed Sigma trench.

[0038] To address the technical problems existing in the prior art, this invention discloses a method and semiconductor device for improving the gate height difference, so that the gate height difference of NMOS and PMOS is the same after etching, thus simplifying subsequent processes.

[0039] Example 1 Please see Figure 5 and Figure 6 , Figure 5 A flowchart illustrating the first method for improving gate height difference according to the present invention is shown. Figure 6 It shows Figure 5 The diagram illustrates the structure of each step in the method shown. A method for improving gate height difference according to the present invention mainly includes the following steps: Step S201: Provide a semiconductor substrate, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure 300 is formed on the NMOS region and the PMOS region respectively, a first etch protection layer 400 is formed on the top and sidewalls of the gate structure and on the exposed semiconductor substrate, a photoresist layer 500 is formed on the first etch protection layer 400 located on the NMOS region and the first etch protection layer 400 located on the PMOS region is exposed.

[0040] The semiconductor substrate is made of semiconductor materials such as silicon, germanium, silicon germanide, and gallium arsenide, and can be a bulk material or a composite structure such as silicon-on-insulator. Those skilled in the art can select the type of semiconductor substrate based on the semiconductor device formed on it; therefore, the type of semiconductor substrate should not limit the scope of protection of this invention.

[0041] The material of the first etched protective layer 400 can be, for example, silicon nitride (SiN), silicon oxide (SiO2), titanium nitride (TiN), or other materials, which are not limited here. In this embodiment of the invention, SiN is preferred.

[0042] The NMOS region is used to form an NMOS transistor therein, and the PMOS region is used to form a PMOS transistor therein. The NMOS transistor and the PMOS transistor can be either a planar MOS transistor or a Fin Field-Effect Transistor (FinFET).

[0043] The gate structure 300 is the core component of the MOS transistor, located between the source and drain. By applying an external voltage, the gate can precisely control the concentration of charge carriers in the semiconductor channel, thereby regulating the conduction and cutoff of the source-drain current and realizing the "on" and "off" of the transistor.

[0044] In one specific embodiment provided in this application, the gate structure 300 includes a gate dielectric layer 302 and a gate layer 303 located on the gate dielectric layer 302. The gate dielectric layer 302 is formed on a substrate protective layer 301, and a shielding layer 304 is used to protect the gate dielectric layer 302 and the gate layer 303 it covers during dry etching. See also Figure 7 The diagram shows a schematic diagram of a gate structure provided in an embodiment of the present invention.

[0045] The gate dielectric layer 302 is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of SiO2. For example, it can be selected from one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicate (HfSiO), hafnium oxysilicate (HfSiON), hafnium tantalate (HfTaO), hafnium titanate (HfTiO), hafnium zirconate (HfZrO), or aluminum oxide (Al2O3). The gate layer 303 serves as an electrode for electrical connection to external circuits, and its material can be, for example, tungsten (W), aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), or titanium (Ti). The substrate protective layer 301 is made of SiO2 or silicon oxynitride (SiON), etc., and the shielding layer 304 can be made of SiO2, SiN, TiN, etc. In order to distinguish it from the first etching protective layer, SiO2 is preferred in this embodiment of the invention.

[0046] Step S202: Etch the first etch protection layer 400 located on the PMOS region and the photoresist layer 500 and the first etch protection layer 400 located on the NMOS region until the top of the gate structure 300 and the semiconductor substrate outside the sidewalls of the gate structure 300 on the PMOS region are exposed, so that the height of the gate structure 300 after etching is the same.

[0047] The etching method can be either dry etching or wet etching, and is not limited here. Selective material removal is performed on the exposed areas using a photoresist layer and a first etch protective layer as shielding. By precisely controlling the etching time, gas formulation, or chemical solution concentration, it is ensured that the etching stops precisely at a predetermined material interface while removing the first shielding layer, exposing the top of the gate structure and the semiconductor substrate of the PMOS region, thereby avoiding over-etching or damage to the underlying structure. For specific implementation details, please refer to [reference needed]. Figure 3 and Figure 4 The implementation method in this paper can also be other implementation methods, which are not limited here.

[0048] As can be seen, in this embodiment of the invention, by selectively retaining the photoresist layer on the NMOS region and exposing the first etch protection layer on the PMOS region, the first etch protection layer on the PMOS region and the photoresist layer and the first etch protection layer on the NMOS region are etched until the top of the gate structure and the semiconductor substrate outside the sidewall of the gate structure on the PMOS region are exposed, so that the height of the etched gate structure is the same, thereby eliminating the need to perform other operations to compensate for the height difference and simplifying the subsequent process.

[0049] Example 2 Figure 3 and Figure 4 The current method for improving gate height difference is cumbersome, requiring at least three additional steps. If the semiconductor device requires trenching, trenching must be performed before SiGe epitaxial growth; otherwise, the photoresist layer spin-coated in step S105 will fill the formed Sigma trenches. To address the above technical problems, this application provides another method for improving gate height difference. Please refer to... Figure 8 and Figure 9 , Figure 8 A flowchart illustrating the second method for improving gate height difference in this invention is shown. Figure 9 It shows Figure 8 The diagram illustrates the structure of each step in the method shown. Another method for improving gate height difference in this invention mainly includes the following steps: Step S201: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure 300 is formed on the NMOS region and the PMOS region respectively, a second etch protection layer 700 is formed above the gate structure 300, the second etch protection layer 700 is located on the side of the semiconductor substrate away from the gate structure 300, a first etch protection layer 400 is formed on the top of the second etch protection layer 700, the sidewalls of the second etch protection layer 700 and the gate structure 300 and the exposed semiconductor substrate, a photoresist layer 500 is formed on the first etch protection layer 400 located on the NMOS region and the first etch protection layer 400 located on the PMOS region is exposed.

[0050] The material of the second etch protection layer 700 differs from the material of the first etch protection layer 400. In a preferred embodiment, the material of the first etch protection layer 400 is SiN, and the material of the second etch protection layer 700 is SiO2. The second etch protection layer 700 can be in direct contact with the gate structure 300 or indirect contact with the gate structure. In a preferred embodiment of the present invention, the two are in direct contact, and the second etch protection layer 700 is... Figure 7 The shielding layer 304 in the illustrated embodiment. Thus, during the fabrication process, it is not necessary to remove the shielding layer 304; instead, the first etching protection layer 400 can be formed directly on top of the shielding layer 304.

[0051] For a detailed description of the remaining parts of step S201, please refer to Example 1, which will not be repeated here.

[0052] Step S2021: The photoresist layer 500 on the NMOS region is etched back to below the top of the second etch protection layer 700 to expose the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700.

[0053] The etching process employs techniques such as dry plasma etching. This step, through precise control of etching time or endpoint detection, reduces the thickness of the photoresist layer 500 on the NMOS region, making its top surface height lower than the top surface height of the underlying second etch protection layer 700. Through this etching process, the first etch protection layer 400 on top of the NMOS region gate structure 300, originally covered by the photoresist layer 500, is exposed, providing a basis for the subsequent simultaneous etching of both the first etch protection layer 400 on the PMOS region and the first etch protection layer 400 on top of the NMOS region gate structure 300.

[0054] Step S2022: Etch the first etch protection layer 400 located on the PMOS region and the first etch protection layer 400 on the top of the gate structure 300 and the first etch protection layer 400 on the sidewall of the second etch protection layer 700, until the top of the gate structure 300 and the semiconductor substrate other than the sidewall of the gate structure 300 on the PMOS region are exposed, so that the height of the gate structure 300 is the same after etching.

[0055] In this step, etching continues. Since the first etch protection layer 400 (preferably SiN) and the second etch protection layer 700 (preferably SiO2) are made of different materials, this step utilizes the high etch selectivity of the gas formulation for these two materials to directionally remove the exposed first etch protection layer 400. Thus, the first etch protection layer 400 originally exposed in the PMOS region, and the first etch protection layer 400 exposed on the top and sidewalls of the gate structure in the NMOS region due to photoresist etchback, are simultaneously etched away.

[0056] Meanwhile, due to the extremely high etching resistance of the second etch protection layer 700 (SiO2) to the current etching gas, its structure is completely or at least partially preserved. Ultimately, in the NMOS region, the first etch protection layer 400 is removed, exposing the underlying second etch protection layer 700 (masking layer 304) and the gate structure 300; while in the PMOS region, after the first etch protection layer 400 is removed, the underlying gate structure 300 and the semiconductor substrate are exposed. In this way, the height difference of the gate structure 300 in the NMOS and PMOS regions will be consistent.

[0057] As can be seen, in this embodiment of the invention, before etching the first etch protection layer, a photoresist back etching is added to etch the photoresist layer on the NMOS region back to below the top of the second etch protection layer, so as to expose the first etch protection layer on the top of the gate structure and the first etch protection layer on the sidewall of the second etch protection layer on the NMOS region. In this way, when subsequent etching is performed, after the first etch protection layer on the top of the gate structure is completely consumed, the second etch protection layer above the gate structure will also be subjected to the same loss, so that after etching, the height of the gate structure above the NMOS and PMOS will not be significantly different.

[0058] In addition, compared to Figure 3 and Figure 4 In the embodiments described above, spin coating of photoresist is no longer required, and Sigma grooving and SiGe epitaxial growth are not required before spin coating of photoresist. Therefore, there are also unexpected technical effects such as reducing process steps and simplifying subsequent processes.

[0059] Example 3 Please see Figure 10 and Figure 11 , Figure 10 A flowchart illustrating the third method for improving gate height difference in this invention is shown. Figure 11 It shows Figure 10 The diagram shows the structural schematics of each step in the method. Another method for improving gate height difference in this invention mainly includes the following steps: Step S201: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure 300 is formed on the NMOS region and the PMOS region respectively, a second etch protection layer 700 is formed above the gate structure 300, the second etch protection layer 700 is located on the side of the semiconductor substrate away from the gate structure 300, a first etch protection layer 400 is formed on the top of the second etch protection layer 700, the sidewalls of the second etch protection layer 700 and the gate structure 300 and the exposed semiconductor substrate, a photoresist layer 500 is formed on the first etch protection layer 400 located on the NMOS region and the first etch protection layer 400 located on the PMOS region is exposed.

[0060] Step S2021: The photoresist layer 500 on the NMOS region is etched back to below the top of the second etch protection layer 700 to expose the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700.

[0061] Step S2022: Etch the first etch protection layer 400 located on the PMOS region and the first etch protection layer 400 on the top of the gate structure 300 and the first etch protection layer 400 on the sidewall of the second etch protection layer 700, until the top of the gate structure 300 and the semiconductor substrate other than the sidewall of the gate structure 300 on the PMOS region are exposed, so that the height of the gate structure 300 is the same after etching.

[0062] Step S203: Remove the remaining portion of the photoresist layer 500 on the NMOS region, exposing a stepped first etch protection layer 400 on the NMOS region. The stepped first etch protection layer 400 is formed on the sidewall of the gate structure 300 of the NMOS region.

[0063] For a detailed description of steps S201, S2021, and S2022, please refer to Embodiment 1 and Embodiment 2. They will not be repeated here.

[0064] After completing the preceding etching steps, a photoresist stripping process, such as plasma ashing or wet stripping, is used to completely remove the remaining photoresist layer 500 on the NMOS region after the etch back. Since the photoresist layer 500 only serves as a temporary sacrificial mask, its complete removal will not damage the underlying first etch protection layer 400, which has already formed a pattern, thus ensuring the exposure of a clean process surface.

[0065] During the etching process in step S2022, the first etch protection layer 400, which was originally exposed in the PMOS region, is completely consumed. In the NMOS region, since the sidewalls of the gate structure 300 and the remaining areas of the substrate (excluding the gate structure 300) are covered by the photoresist layer 500, the photoresist layer 500 on the sidewalls of the gate structure 300 is consumed simultaneously during etching, but not completely depleted. Therefore, the first etch protection layer 400 on a portion of the sidewalls of the gate structure 300 can be retained. Simultaneously, the photoresist layer 500 on the remaining areas of the substrate (excluding the gate structure 300) is not consumed, and therefore, its first etch protection layer 400 can be completely retained. After removing the photoresist, the first etch protection layer 400 on a portion of the sidewalls of the gate structure 300 in the NMOS region is partially consumed and thinned, while the first etch protection layer 400 on another portion of the sidewalls remains intact, thus naturally forming a "stepped" first etch protection layer 400 with a height difference.

[0066] As can be seen, in this embodiment of the invention, the photoresist etch-back process does not completely consume all the photoresist layer. A portion of the sidewalls of the gate structure on the NMOS region is not covered by the photoresist layer, while another portion is. During the etching operation, when the first etch protection layer on the semiconductor substrate other than the sidewalls of the gate structure on the PMOS region is completely consumed, the first etch protection layer on the sidewalls of the gate structure on the NMOS region is also consumed, but not entirely. Therefore, it forms a stepped first etch protection layer together with the unconsumed sidewalls of the first etch protection layer and the first etch protection layer on the semiconductor substrate other than the gate structure on the NMOS region. It can be seen that in the process of improving the height difference between the gate structures above the NMOS and PMOS, this embodiment of the invention also forms a stepped first etch protection layer. This stepped first etch protection layer is exposed after the photoresist layer is removed, allowing the etching amount on the sidewalls of the gate structure to be controllably distributed along the height direction. This stepped first etching protective layer avoids the "one-cut" etching effect caused by a uniform protective layer, providing additional controllability for subsequent processes, and thus producing unexpected beneficial effects.

[0067] Example 4 Please see Figure 12 , Figure 12 A flowchart illustrating the fourth method for improving gate height difference according to the present invention is shown. Another method for improving gate height difference according to the present invention mainly includes the following steps: Step S201: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure 300 is formed on the NMOS region and the PMOS region respectively, a second etch protection layer 700 is formed above the gate structure 300, the second etch protection layer 700 is located on the side of the semiconductor substrate away from the gate structure 300, a first etch protection layer 400 is formed on the top of the second etch protection layer 700, the sidewalls of the second etch protection layer 700 and the gate structure 300 and the exposed semiconductor substrate, a photoresist layer 500 is formed on the first etch protection layer 400 located on the NMOS region and the first etch protection layer 400 located on the PMOS region is exposed.

[0068] Step S204: Determine the step height of the stepped first etch protection layer 400 according to the designed performance. The step height of the stepped first etch protection layer 400 is used to regulate the ion concentration gradient of the source / drain injection region and / or threshold voltage adjustment injection region of the subsequent NMOS region.

[0069] The height of the step is not arbitrarily set, but directly linked to the electrical performance of the device. By precisely calculating and setting the step height, it can be used as a physical mask for subsequent ion implantation processes. Steps of different heights can change the penetration depth and lateral diffusion range of implanted ions, thereby precisely controlling the ion concentration gradient at the source / drain of the NMOS region, and even adjusting the threshold voltage, ultimately optimizing the device's on-current and short-channel effects.

[0070] Step S205: Determine the end point of the back etching and the end point of the etching based on the step height of the stepped first etching protective layer 400.

[0071] Here, the etch-back endpoint represents the specific depth of the photoresist etch-back, and the etching endpoint represents the amount of the first etch protective layer removed in the subsequent etching process. Mapping the step height to the specific depth of the photoresist etch-back and the amount of the first etch protective layer removed in the subsequent etching process enables the conversion of design parameters into process control parameters in the actual manufacturing process.

[0072] Step S2021: According to the etch-back endpoint position, etch the photoresist layer 500 on the NMOS region back to below the top of the second etch protection layer 700 to expose the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700.

[0073] Step S2022: Etch the first etch protection layer 400 located on the PMOS region and the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700 according to the etch endpoint position, until the top of the gate structure 300 and the semiconductor substrate other than the sidewall of the gate structure 300 on the PMOS region are exposed, so that the height of the gate structure 300 after etching is the same.

[0074] Step S203: Remove the remaining portion of the photoresist layer on the NMOS region to expose a stepped first etch protection layer on the NMOS region. The stepped first etch protection layer is formed on the sidewall of the gate structure of the NMOS region.

[0075] As can be seen in this embodiment of the invention, the step-like first etch protection layer—an unexpected byproduct of improving the height difference between the gate structures above NMOS and PMOS—can subsequently have its concentration gradient controlled by adjusting the step height. This allows designers to deduce the required ion concentration gradient characteristics based on the target device performance indicators. For example, the correlation between step height and concentration gradient can be qualitatively studied experimentally. After this correlation is experimentally determined, the step height can be determined by looking up a table based on the required concentration gradient characteristics, directly transforming the electrical design goal into processable geometric parameters, namely the etch-back endpoint and the etch-back endpoint. This approach facilitates a closed loop from performance design to process implementation, reducing the blind spots in process development and increasing the success rate of new product fabrication. Secondly, since the step height is continuously controllable, the ion concentration gradient also becomes continuously controllable, realizing ion concentration gradient design from qualitative to quantitative methods.

[0076] Example 5 Please see Figure 13 , Figure 13A schematic diagram of a semiconductor device according to the present invention is shown. The semiconductor device includes a semiconductor substrate, the semiconductor substrate including an NMOS region, a gate structure 300 formed in the NMOS region, an NMOS source region 210 and an NMOS drain region (not shown in the figure) formed in the NMOS region near the gate structure 300, an NMOS conductive channel region 220 formed between the NMOS source and drain regions, a threshold voltage adjustment injection region 230 located below the gate structure 300 in the NMOS region near the NMOS conductive channel region 220, and source / drain injection regions (taking drain injection region 240 as an example) located on both sides of the gate structure 300 in the NMOS region away from the NMOS conductive channel region 220. A second etch protection layer 700 is formed above the gate structure 300, the second etch protection layer 700 is located on the side of the gate structure 300 away from the semiconductor substrate, and a first etch protection layer 400 is formed on the sidewalls of the second etch protection layer 700, the gate structure 300, and the exposed semiconductor substrate.

[0077] In semiconductor manufacturing, the threshold voltage adjustment implantation region 230 precisely adjusts the impurity concentration distribution in the channel region through ion implantation processes (such as implanting impurities like boron or phosphorus). Since the threshold voltage (Vt) is closely related to the impurity concentration in the channel region, increasing the impurity concentration in this region can effectively improve the threshold voltage, thereby optimizing the leakage current characteristics of the device and preventing leakage current from occurring in the device in the off state.

[0078] In semiconductor manufacturing, the source / drain injection region is typically heavily doped. Its core function is to reduce the contact resistance between the source / drain and the external metal interconnect layer, ensuring efficient current transmission. In the actual device structure, the lightly doped drain near the gate edge and the heavily doped source / drain contact region (i.e., drain injection region 240) far from the gate together constitute a complete source / drain structure. This design can reduce on-resistance and effectively suppress short-channel effects and hot carrier effects.

[0079] Example 6 Please see Figure 14 and Figure 15 , Figure 14 A flowchart illustrating the fifth method for improving gate height difference in this invention is shown. Figure 15 It shows Figure 14 The diagram shows the structural schematics of each step in the method. Another method for improving gate height difference in this invention mainly includes the following steps: Step S201: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure 300 is formed on the NMOS region and the PMOS region respectively, a second etch protection layer 700 is formed above the gate structure 300, the second etch protection layer 700 is located on the side of the semiconductor substrate away from the gate structure 300, a first etch protection layer 400 is formed on the top of the second etch protection layer 700, the sidewalls of the second etch protection layer 700 and the gate structure 300 and the exposed semiconductor substrate, a photoresist layer 500 is formed on the first etch protection layer 400 located on the NMOS region and the first etch protection layer 400 located on the PMOS region is exposed.

[0080] Step S204: Determine the step height of the stepped first etch protection layer 400 according to the designed performance. The step height of the stepped first etch protection layer 400 is used to regulate the ion concentration gradient of the source / drain injection region and / or threshold voltage adjustment injection region of the subsequent NMOS region.

[0081] Step S205: Determine the end point of the back etching and the end point of the etching based on the step height of the stepped first etching protective layer 400.

[0082] Step S2021: According to the etch-back endpoint position, etch the photoresist layer 500 on the NMOS region back to below the top of the second etch protection layer 700 to expose the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700.

[0083] Step S2022: Etch the first etch protection layer 400 located on the PMOS region and the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700 according to the etch endpoint position, until the top of the gate structure 300 and the semiconductor substrate other than the sidewall of the gate structure 300 on the PMOS region are exposed, so that the height of the gate structure 300 after etching is the same.

[0084] Step S206: A sigma trench 600 is formed in the semiconductor substrate outside the sidewall of the gate structure 300 in the PMOS region.

[0085] Step S203: Remove the remaining portion of the photoresist layer 500 on the NMOS region, exposing a stepped first etch protection layer 400 on the NMOS region. The stepped first etch protection layer 400 is formed on the sidewall of the gate structure 300 of the NMOS region.

[0086] As can be seen, in this embodiment of the invention, after the gate height equalization etching is completed, the semiconductor substrate outside the sidewalls of the PMOS region gate structure has been exposed. This embodiment of the invention fully utilizes this exposure window, directly etching sigma trenches in the PMOS region substrate, eliminating the need for a dedicated source / drain region windowing photolithography step, thereby shortening the process time. Simultaneously, the formation of sigma trenches helps optimize PMOS hole mobility, reduce short-channel effects, and enhance driving capability.

[0087] Example 7 Please see Figure 16 and Figure 17 , Figure 16 A flowchart illustrating the sixth method for improving gate height difference in this invention is shown. Figure 17 It shows Figure 16 The diagram illustrates the structure of each step in the method shown. Another method for improving gate height difference in this invention mainly includes the following steps: Step S201: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure 300 and a source-drain structure 110 are formed on the NMOS region and the PMOS region respectively, a second etch protection layer 700 is formed above the gate structure 300, the second etch protection layer 700 is located on the side of the semiconductor substrate away from the gate structure 300, a first etch protection layer 400 is formed on the top of the second etch protection layer 700, the sidewalls of the second etch protection layer 700 and the gate structure 300, and on the exposed semiconductor substrate, a photoresist layer 500 is formed on the first etch protection layer 400 located on the NMOS region, and the first etch protection layer 400 located on the PMOS region is exposed.

[0088] Step S204: Determine the step height of the stepped first etch protection layer 400 according to the designed performance. The step height of the stepped first etch protection layer 400 is used to regulate the ion concentration gradient of the source / drain injection region and / or threshold voltage adjustment injection region of the subsequent NMOS region.

[0089] Step S205: Determine the end point of the back etching and the end point of the etching based on the step height of the stepped first etching protective layer 400.

[0090] Step S2021: According to the etch-back endpoint position, etch the photoresist layer 500 on the NMOS region back to below the top of the second etch protection layer 700 to expose the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700.

[0091] Step S2022: Etch the first etch protection layer 400 located on the PMOS region and the first etch protection layer 400 on the top of the gate structure 300 on the NMOS region and the first etch protection layer 400 on the sidewall of the second etch protection layer 700 according to the etch endpoint position, until the top of the gate structure 300 and the semiconductor substrate other than the sidewall of the gate structure 300 on the PMOS region are exposed, so that the height of the gate structure 300 after etching is the same.

[0092] Step S207: A sigma trench 600 is formed in the PMOS source-drain structure 110.

[0093] Step S203: Remove the remaining portion of the photoresist layer 500 on the NMOS region, exposing a stepped first etch protection layer 400 on the NMOS region. The stepped first etch protection layer 400 is formed on the sidewall of the gate structure 300 of the NMOS region.

[0094] As can be seen, in this embodiment of the invention, the source and drain structures of the PMOS region have already been formed. The sigma trench etching directly uses the existing boundaries of the PMOS source and drain structures as the etching range, eliminating the need for dedicated photolithographic windows for the sigma trenches. This avoids excessive expansion of the trenches in unintended directions, and the etching range has self-constraining characteristics. In addition, the bottom of the trench remains inside the source and drain structures, far from the substrate junction region, reducing the risk of leakage and defects.

[0095] Example 8 In a specific embodiment of the present invention, a shallow trench isolation structure is further formed in the PMOS region, and the shallow trench isolation structure is located on both sides of the PMOS source-drain structure.

[0096] As can be seen, in this embodiment of the invention, when forming a sigma trench in the PMOS source-drain structure, the etching not only extends in the depth direction and along the channel direction, but also has a lateral etching component in the gate width direction. This shallow trench isolation structure can form a physical barrier in the gate width direction. The shallow trench isolation structures on both sides can define the width of the source-drain active region, allowing the sigma trench to be formed within this width range with good width consistency, avoiding the trench width drift along the gate width direction caused by the lack of constraint on the active region. At the same time, if the PMOS region does not have a shallow trench isolation structure for boundary constraint, the lateral etching of the sigma trench may cross the PMOS region boundary and erode the active region of the NMOS region, causing short circuits or leakage between devices. In addition, the shallow trench isolation structure itself is a standard active region isolation structure in CMOS technology. This embodiment does not introduce an additional dedicated isolation structure, but rather utilizes the existing shallow trench isolation structure to additionally exert the sigma trench boundary constraint function, achieving unexpected functions without adding additional process steps.

[0097] Example 9 In another specific embodiment of the present invention, the shallow trench isolation structure is located on both sides of the gate structure on the PMOS source-drain structure away from the PMOS region.

[0098] As can be seen, in this embodiment of the invention, compared with the previous embodiment, the shallow trench isolation structure is further restricted to both sides of the gate structure on the PMOS source-drain structure away from the PMOS region, so that the critical region between the gate and the source-drain is not directly disturbed by the mechanical stress caused by the shallow trench isolation structure, ensuring that the main contribution of the channel strain comes from the controllable sigma trench epitaxy, rather than the edge effect caused by the uncontrollable shallow trench isolation structure.

[0099] The present invention also provides a semiconductor device that can be manufactured using any of the above embodiments of a method for improving gate height difference, a method for forming a stepped etch protective layer, or a method for forming a sigma trench.

[0100] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0101] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0102] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0103] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a kind," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0104] As should be understood from the several embodiments provided in this application, the disclosed semiconductor devices can be implemented in other ways. For example, the embodiments of the semiconductor devices described above are merely illustrative.

[0105] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for improving gate height difference, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including an NMOS region and a PMOS region, a gate structure is formed on the NMOS region and the PMOS region respectively, a second etch protection layer is formed above the gate structure, the second etch protection layer is located on the side of the semiconductor substrate away from the gate structure, a first etch protection layer is formed on the top of the second etch protection layer, the sidewall of the second etch protection layer and the gate structure and on the exposed semiconductor substrate, a photoresist layer is formed on the first etch protection layer located on the NMOS region and the first etch protection layer located on the PMOS region is exposed; The photoresist layer on the NMOS region is etched back to below the top of the second etch protection layer to expose the first etch protection layer on the top of the gate structure on the NMOS region and the first etch protection layer on the sidewall of the second etch protection layer. The first etch protection layer located on the PMOS region and the first etch protection layer on the top of the gate structure and the first etch protection layer on the sidewall of the second etch protection layer on the NMOS region are etched until the top of the gate structure and the semiconductor substrate outside the sidewall of the gate structure on the PMOS region are exposed, so that the height of the gate structure is the same after etching.

2. The method for improving gate height difference according to claim 1, characterized in that, The photoresist layer and the first etch protection layer on the NMOS region are partially consumed. After etching the first etch protection layer located on the PMOS region and the first etch protection layer on the top of the gate structure and the first etch protection layer on the sidewall of the second etch protection layer on the NMOS region, the method further includes: Remove the remaining portion of the photoresist layer on the NMOS region to expose a stepped first etch protection layer on the NMOS region. The stepped first etch protection layer is formed on the sidewall of the gate structure of the NMOS region.

3. The method for improving gate height difference according to claim 2, characterized in that, The step height of the stepped first etch protection layer is used to regulate the ion concentration gradient of the subsequent source / drain implantation region and / or threshold voltage adjustment implantation region of the NMOS region. Before etching the photoresist layer on the NMOS region back below the top of the second etch protection layer to expose the first etch protection layer on the top of the gate structure on the NMOS region and the first etch protection layer on the sidewall of the second etch protection layer, the method further includes: The step height of the stepped first etched protective layer is determined based on the design performance. The re-etching endpoint position and the etching endpoint position are determined based on the step height of the stepped first etching protective layer.

4. The method for improving gate height difference according to claim 3, characterized in that, The NMOS region has an NMOS source-drain region formed near the gate structure side, and an NMOS conductive channel region is formed between the NMOS source-drain regions. The threshold voltage adjustment injection region is located below the gate structure of the NMOS region and near the NMOS conductive channel region. The source-drain injection regions are located on both sides of the gate structure of the NMOS region and away from the NMOS conductive channel region.

5. The method for improving gate height difference according to any one of claims 1-4, characterized in that, After etching the first etch protection layer located on the PMOS region and the first etch protection layer on the top of the gate structure on the NMOS region and the first etch protection layer on the sidewalls of the second etch protection layer, until the top of the gate structure and the semiconductor substrate other than the sidewalls of the gate structure on the PMOS region are exposed, the method further includes: A sigma trench is formed in the semiconductor substrate outside the gate structure sidewalls on the PMOS region.

6. The method for improving gate height difference according to any one of claims 1-4, characterized in that, The PMOS region has a PMOS source-drain structure. After etching the first etch protection layer located on the PMOS region and the first etch protection layer on the top of the gate structure and the first etch protection layer on the sidewalls of the second etch protection layer on the NMOS region, until the top of the gate structure and the semiconductor substrate other than the sidewalls of the gate structure on the PMOS region are exposed, the method further includes: A sigma trench is formed in the PMOS source-drain structure.

7. The method for improving gate height difference according to claim 6, characterized in that, The PMOS region also has a shallow trench isolation structure, which is located on both sides of the PMOS source-drain structure.

8. The method for improving gate height difference according to claim 7, characterized in that, The shallow trench isolation structure is located on both sides of the gate structure of the PMOS source-drain structure away from the PMOS region.

9. A semiconductor device, characterized in that, Prepared according to any one of claims 1-8 by the method for improving gate height difference.

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