Semiconductor device including buried pattern

Abstract

Semiconductor devices including a buried pattern are provided. A semiconductor device includes a substrate including an insulating pattern of a first region and a first semiconductor pattern of a second region; a separation pattern separating the insulating pattern and the first semiconductor pattern; a first active pattern on an upper surface of the insulating pattern; a first gate structure crossing the first active pattern; a first source / drain region connected to the first active pattern on a sidewall of the first gate structure; a second active pattern on an upper surface of the first semiconductor pattern; a second gate structure crossing the second active pattern; a buried pattern on a lower surface of the first semiconductor pattern; a backside wiring structure on a lower surface of the insulating pattern and the buried pattern; and a backside source / drain contact penetrating the insulating pattern and connecting the first source / drain region and the backside wiring structure. The buried pattern includes a liner extending along a contour of the lower surface of the first semiconductor pattern and a sidewall of the separation pattern and a buried insulating film on the liner.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0041916, filed on April 1, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. More specifically, this disclosure relates to a semiconductor device including a back-side power distribution network (BSPD) and a method of manufacturing the semiconductor device. Background Technology

[0003] Semiconductor devices have attracted much attention as important components in the electronics industry due to their characteristics such as small size, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that perform computational processing on logic data, and hybrid semiconductor devices that include memory elements and logic elements, etc.

[0004] As the electronics industry develops to a higher level, the requirements for the characteristics of semiconductor devices are gradually increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these requirements, the internal structure of semiconductor devices is becoming increasingly complex and highly integrated.

[0005] On the other hand, as semiconductor devices become increasingly integrated, the width of wiring patterns and via patterns used to implement semiconductor devices is gradually decreasing. Therefore, the voltage drop (e.g., IR drop) of the power distribution network (PDN) that supplies power to integrated circuits has become a significant issue. Summary of the Invention

[0006] This disclosure provides a semiconductor device in which logic element regions and passive element regions are easily integrated.

[0007] This disclosure provides a method for manufacturing a semiconductor device in which logic element regions and passive element regions are easily integrated.

[0008] According to an aspect of this disclosure, a semiconductor device is provided, comprising a first region and a second region distinct from each other. The semiconductor device includes: a substrate including an insulating pattern in the first region and a first semiconductor pattern in the second region; a separation pattern separating the insulating pattern and the first semiconductor pattern between the insulating pattern and the first semiconductor pattern; a first active pattern on an upper surface of the insulating pattern; a first gate structure intersecting the first active pattern; a first source / drain region connected to the first active pattern on a sidewall of the first gate structure; a second active pattern on the upper surface of the first semiconductor pattern; a second gate structure intersecting the second active pattern; a buried pattern on a lower surface of the first semiconductor pattern; a back-side wiring structure on the lower surface of the insulating pattern and the lower surface of the buried pattern; and a back source / drain contact penetrating the insulating pattern and connecting the first source / drain region and the back-side wiring structure. The buried pattern includes a substrate and a buried insulating film, the substrate extending along the contour of the lower surface of the first semiconductor pattern and the sidewall of the separation pattern, and the buried insulating film on the substrate.

[0009] According to an aspect of this disclosure, a semiconductor device is provided, comprising a first region and a second region distinct from each other. The semiconductor device includes: a substrate; an insulating pattern in the first region; a semiconductor pattern in the second region; and a field insulating film covering at least a portion of the sidewalls of the insulating pattern and at least a portion of the sidewalls of the semiconductor pattern; a first active pattern on an upper surface of the insulating pattern; a first gate structure intersecting the first active pattern; a source / drain region connected to the first active pattern on a sidewall of the first gate structure; a second active pattern on an upper surface of the semiconductor pattern; a second gate structure intersecting the second active pattern; a buried pattern on a lower surface of the semiconductor pattern; a back-side wiring structure on the lower surface of the insulating pattern, the lower surface of the field insulating film, and the lower surface of the buried pattern; and a back source / drain contact penetrating the insulating pattern and connecting the source / drain region and the back-side wiring structure. The buried pattern includes a substrate and a buried insulating film, the substrate extending along the contour of the lower surface of the semiconductor pattern and the sidewalls of the field insulating film, and the buried insulating film on the substrate.

[0010] According to an aspect of this disclosure, a semiconductor device is provided, comprising a first region and a second region distinct from each other. The semiconductor device includes: a substrate including an insulating pattern in the first region and a semiconductor pattern in the second region; a first active pattern on an upper surface of the insulating pattern; a first gate structure intersecting the first active pattern; a source / drain region connected to the first active pattern on a sidewall of the first gate structure; a second active pattern on the upper surface of the semiconductor pattern; a second gate structure intersecting the second active pattern; a buried pattern on a lower surface of the semiconductor pattern; a back-side wiring structure on the lower surface of the insulating pattern and the lower surface of the buried pattern; and a back source / drain contact penetrating the insulating pattern and connecting the source / drain region and the back-side wiring structure. The second region comprises a first sub-region and a second sub-region distinct from each other, and the thickness of the semiconductor pattern in the first sub-region is greater than the thickness of the semiconductor pattern in the second sub-region.

[0011] [0011 However, the aspects of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become clearer to those skilled in the art upon reference to the detailed description of this disclosure given below.] Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0013] Figure 1 This is an example layout diagram used to explain a semiconductor device according to some embodiments.

[0014] Figure 2 and Figure 3 This is a schematic cross-sectional view used to explain a semiconductor device according to some embodiments.

[0015] Figures 4 to 8 These are schematic cross-sectional views used to explain various semiconductor devices according to some embodiments.

[0016] Figures 9 to 20 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments.

[0017] Figure 21 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments.

[0018] Figures 22 to 25 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0019] It will be understood that although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0020] In this specification, although only a multi-bridge channel field-effect transistor (MBCFET®) is shown as an example of an electronic device included in a semiconductor device, this is merely an example. As another example, it is self-evident that the semiconductor device may include a tunnel transistor (tunnel FET), a VFET (vertical FET), a CFET (complementary FET), or a three-dimensional (3D) transistor. Alternatively, the semiconductor device may include a bipolar junction transistor, a laterally diffused metal-oxide-semiconductor (LDMOS), etc.

[0021] Although terms such as "first" and "second" are used in this specification to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used only to distinguish individual elements or components from other elements or components. Therefore, it is understood that, within the technical concept of this disclosure, the first element or component mentioned below may be a second element or component.

[0022] In this specification, the term "identical" means not only completely identical, but also includes minor differences that may arise due to process margins, etc.

[0023] The following will refer to Figures 1 to 8 A semiconductor device according to an example embodiment is described.

[0024] Figure 1 This is an example layout diagram used to explain a semiconductor device according to some embodiments. Figure 2 and Figure 3 This is a schematic cross-sectional view used to explain a semiconductor device according to some embodiments.

[0025] Reference Figure 1 According to some embodiments, a semiconductor device includes a first region I and a second region II that are distinct from each other.

[0026] The first region I and the second region II can be adjacent to each other or can be spaced apart from each other. In some embodiments, from a plan view perspective, at least a portion of the second region II may surround the periphery of the first region I. In some embodiments, from a plan view perspective, a portion of the second region II may be located inside the first region I. The arrangement of the first region I and the second region II is merely an example and is not limited to the arrangement shown.

[0027] The first region I can be a logic element region. For example, the first region I may include one or more logic elements (such as a central processing unit (CPU), a graphics processing unit (GPU), and / or general-purpose logic circuits).

[0028] The second region II can be a passive component region. For example, the second region II may include one or more passive components (such as resistors, capacitors, inductors, transformers, and / or diodes).

[0029] Reference Figures 1 to 3 A semiconductor device according to some embodiments includes a substrate 100, a first active pattern AP1, a second active pattern AP2, a first gate structure GS1, a second gate structure GS2, a first source / drain region SD1, a second source / drain region SD2, a separation pattern 180, a first interlayer insulating film 190, a second interlayer insulating film 192, a third interlayer insulating film 194, a first source / drain contact FC1, a second source / drain contact FC2, a first gate contact CB1, a second gate contact CB2, a front wiring structure FW, a buried pattern 300, a back source / drain contact BC, and a back-side wiring structure BW.

[0030] The substrate 100 may include an insulating pattern 102, a first semiconductor pattern 101, and a field insulating film 105.

[0031] An insulating pattern 102 may be formed in the first region I. The insulating pattern 102 may extend relatively long (or be extended extensively) in the first direction X1. The insulating pattern 102 may include a first front side 102a and a first back side 102b opposite to each other. For example, in... Figure 2 and Figure 3 In the first front side 102a, the first front side 102a may be the upper surface of the insulating pattern 102, and the first back side 102b may be the lower surface of the insulating pattern 102.

[0032] The insulating pattern 102 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and / or combinations thereof. As an example, the insulating pattern 102 may include a silicon oxide film.

[0033] A first semiconductor pattern 101 may be formed in a second region II. The first semiconductor pattern 101 may extend relatively long in a second direction X2. The second direction X2 may be the same as or different from the first direction X1. The first semiconductor pattern 101 may include a second front side 101a and a second back side 101b opposite to each other. For example, in... Figure 2 and Figure 3 In the first semiconductor pattern 101, the second front side 101a can be the upper surface of the first semiconductor pattern 101, and the second back side 101b can be the lower surface of the first semiconductor pattern 101.

[0034] The first semiconductor pattern 101 may include semiconductor materials, such as, but not limited to, at least one of silicon, germanium silicon, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and / or combinations thereof.

[0035] A field insulating film 105 may be formed in a first region I and a second region II. The field insulating film 105 may cover at least a portion of the sidewalls of the insulating pattern 102 and at least a portion of the sidewalls of the first semiconductor pattern 101. The field insulating film 105 may include a third front side 105a and a third back side 105b opposite to each other. For example, in... Figure 3 In the middle, the third front side 105a can be the upper surface of the field insulating film 105, and the third back side 105b can be the lower surface of the field insulating film 105.

[0036] The field insulating film 105 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and / or combinations thereof. As an example, the field insulating film 105 may include a silicon oxide film.

[0037] although Figure 3 The diagram shows the boundary between the insulating pattern 102 and the field insulating film 105, but this is only an example. In some cases, there may be no boundary between the insulating pattern 102 and the field insulating film 105.

[0038] In some embodiments, the upper portion of the insulating pattern 102 may protrude above the field insulating film 105. For example, as Figure 3 As shown, the first front side 102a of the insulating pattern 102 may be configured to be higher than the third front side 105a of the field insulating film 105.

[0039] In some embodiments, the upper portion of the first semiconductor pattern 101 may protrude above the field insulating film 105. For example, as Figure 3 As shown, the second front side 101a of the first semiconductor pattern 101 may be configured to be higher than the third front side 105a of the field insulating film 105.

[0040] In some embodiments, the first front side 102a of the insulating pattern 102 and the second front side 101a of the first semiconductor pattern 101 may be positioned as coplanar (or at the same level). For example, based on the third front side 105a of the field insulating film 105, the height of the first front side 102a of the insulating pattern 102 and the height of the second front side 101a of the first semiconductor pattern 101 may be the same.

[0041] In some embodiments, the first back side 102b of the insulating pattern 102 and the third back side 105b of the field insulating film 105 may be configured to be coplanar (or at the same level).

[0042] In some embodiments, the second back side 101b of the first semiconductor pattern 101 may be configured to be higher than the third back side 105b of the field insulating film 105. For example, the lower portion of the field insulating film 105 may protrude below the second back side 101b of the first semiconductor pattern 101.

[0043] In some embodiments, the thickness T1 of the insulating pattern 102 may be greater than the thickness T2 of the first semiconductor pattern 101. For example, as Figure 2 and Figure 3 As shown, the first front side 102a of the insulating pattern 102 and the second front side 101a of the first semiconductor pattern 101 may be positioned as coplanar (or at the same level), and the second back side 102b of the insulating pattern 102 may be positioned lower than the second back side 101b of the first insulating pattern 101.

[0044] In some embodiments, the thickness T2 of the first semiconductor pattern 101 may be about 50 nm or greater. For example, the thickness T2 of the first semiconductor pattern 101 may be about 50 nm to about 200 nm, about 50 nm to about 100 nm, or about 50 nm to about 70 nm. Within the above ranges, the first semiconductor pattern 101 may be set at a thickness suitable for forming passive components.

[0045] A first active pattern AP1 may be formed in a first region I. The first active pattern AP1 may be formed on a first front side 102a of an insulating pattern 102. The first active pattern AP1 may extend relatively long in a first direction X1.

[0046] The second active pattern AP2 may be formed in the second region II. The second active pattern AP2 may be formed on the second front side 101a of the first semiconductor pattern 101. The second active pattern AP2 may extend relatively long in the second direction X2.

[0047] Each of the first active pattern AP1 and the second active pattern AP2 may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. Optionally, each of the first active pattern AP1 and the second active pattern AP2 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. A group IV-IV compound semiconductor may be, for example, a binary or ternary compound containing at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with group IV elements. A group III-V compound semiconductor may be, for example, a binary, ternary, or quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements.

[0048] In some embodiments, each of the first active pattern AP1 and the second active pattern AP2 may include a plurality of bridging patterns 111 to 113 spaced apart from the substrate 100. For example, the bridging patterns 111 to 113 of the first active pattern AP1 may be spaced apart from the insulating pattern 102 in a first vertical direction Z1 intersecting the first front side 102a. For example, the bridging patterns 111 to 113 of the second active pattern AP2 may be spaced apart from the first semiconductor pattern 101 in a second vertical direction Z2 intersecting the second front side 101a. The first vertical direction Z1 and the second vertical direction Z2 may be equal to each other. The bridging patterns 111 to 113 may be arranged sequentially along the first vertical direction Z1 or the second vertical direction Z2 and spaced apart from each other. The bridging patterns 111 to 113 may be used as channel regions of an MBCFET® including multiple bridging channels. The number of bridging patterns 111 to 113 included in each of the first active pattern AP1 and the second active pattern AP2 is merely an example and is not limited to the number shown.

[0049] A first gate structure GS1 may be formed in the first region I. The first gate structure GS1 may be formed on the first front side 102a of the insulating pattern 102 and the third front side 105a of the field insulating film 105. The first gate structure GS1 may intersect with the first active pattern AP1. For example, the first gate structure GS1 may extend relatively long in a third direction Y1 that intersects with the first direction X1. In some embodiments, the bridging patterns 111 to 113 of the first active pattern AP1 may extend in the first direction X1 and penetrate the first gate structure GS1.

[0050] A second gate structure GS2 may be formed in the second region II. The second gate structure GS2 may be formed on the second front side 101a of the first semiconductor pattern 101 and the third front side 105a of the field insulating film 105. The second gate structure GS2 may intersect with the second active pattern AP2. For example, the second gate structure GS2 may extend relatively long in the fourth direction Y2, which intersects the second direction X2. In some embodiments, the bridging patterns 111 to 113 of the second active pattern AP2 may extend in the second direction X2 and penetrate the second gate structure GS2.

[0051] In some embodiments, each of the first gate structure GS1 and the second gate structure GS2 may include a gate dielectric film 120, a gate electrode 130, a gate spacer 140, and a gate cover film 150.

[0052] A gate dielectric film 120 may be stacked on a substrate 100, a first active pattern AP1, and a second active pattern AP2. The gate dielectric film 120 may be disposed between the first active pattern AP1 and the gate electrode 130, and between the second active pattern AP2 and the gate electrode 130. For example, the gate dielectric film 120 may extend along the periphery of each of the bridging patterns 111 to 113. A portion of the gate dielectric film 120 may be disposed between the substrate 100 and the gate electrode 130. For example, the gate dielectric film 120 may further extend along the third front side 105a of the field insulating film 105, the upper portion of the insulating pattern 102 protruding from the field insulating film 105, and the upper portion of the first semiconductor pattern 101 protruding from the field insulating film 105.

[0053] The gate dielectric film 120 may include a dielectric material, such as at least one of silicon oxide, silicon oxynitride, silicon nitride, and / or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, but not limited to, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), and hafnium oxynitride (HfO2). x N y Zirconium oxynitride (ZrO) x N y ), Lanthanum oxide (La2O) x N y ), aluminum oxide (Al2O) x N y ), titanium oxynitride (TiO2) x N y ), SrTiO2 x N y ), Lanthanum aluminum oxynitride (LaAlO) x Ny ), Yttrium oxynitride (Y2O) x N y ( ) and / or at least one of their combinations.

[0054] The gate electrode 130 may intersect with the first active pattern AP1 and the second active pattern AP2. Each of the bridging patterns 111 to 113 of the first active pattern AP1 may extend in the first direction X1 and penetrate the gate electrode 130 of the first gate structure GS1. Each of the bridging patterns 111 to 113 of the second active pattern AP2 may extend in the second direction X2 and penetrate the gate electrode 130 of the second gate structure GS2.

[0055] The gate electrode 130 may comprise a conductive material, such as, but not limited to, at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and / or combinations thereof. The gate electrode 130 may be formed by, but not limited to, alternative processes.

[0056] Although the gate electrode 130 is shown as a single film, this is merely an example, and it is self-evident that the gate electrode 130 can be a multilayer film formed by stacking multiple conductive films. For example, the gate electrode 130 may include a work function regulating film (or work function control film) for regulating the work function (or "work function") and a filling conductive film for filling the space formed by the work function regulating film. The work function control film may include at least one of, for example, TiN, TaN, TiC, TaC, TiAlCl, and / or combinations thereof. The filling conductive film may include, for example, W or Al.

[0057] Gate spacer 140 may extend along the sidewall of gate electrode 130. Each of the bridging patterns 111 to 113 of the first active pattern AP1 may extend in the first direction X1 and penetrate the gate spacer 140 of the first gate structure GS1. Each of the bridging patterns 111 to 113 of the second active pattern AP2 may extend in the second direction X2 and penetrate the gate spacer 140 of the second gate structure GS2. Gate spacer 140 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and / or combinations thereof.

[0058] The gate capping film 150 may extend along the upper surface of the gate electrode 130. The gate capping film 150 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and / or combinations thereof.

[0059] In some embodiments, each of the first gate structure GS1 and the second gate structure GS2 may further include an inner spacer 145. The inner spacer 145 may be formed on the sidewall of the gate electrode 130 between the bridging patterns 111 to 113. The inner spacer 145 may be formed on the sidewall of the gate electrode 130 between the substrate 100 and the bridging patterns 111 to 113. The inner spacer 145 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and / or combinations thereof. In some embodiments, the inner spacer 145 may be omitted.

[0060] A first source / drain region SD1 may be formed in the first region I. The first source / drain region SD1 may be formed on at least one sidewall (e.g., both sides) of the first gate structure GS1. The first source / drain region SD1 may be connected to a first active pattern AP1. For example, each of the bridging patterns 111 to 113 of the first active pattern AP1 may penetrate the first gate structure GS1 and be connected to the first source / drain region SD1. The first source / drain region SD1 may be separated from the gate electrode 130 of the first gate structure GS1 via the gate dielectric film 120, the gate spacer 140, and / or the inner spacer 145.

[0061] In some embodiments, the first source / drain region SD1 may include an epitaxial layer. For example, the first source / drain region SD1 may include an epitaxial pattern grown from the first active pattern AP1 by an epitaxial growth method.

[0062] A second source / drain region SD2 may be formed in the second region II. The second source / drain region SD2 may be formed on at least one sidewall (e.g., both sides) of the second gate structure GS2. The second source / drain region SD2 may be connected to the second active pattern AP2. For example, each of the bridging patterns 111 to 113 of the second active pattern AP2 may penetrate the second gate structure GS2 and be connected to the second source / drain region SD2. The second source / drain region SD2 may be separated from the gate electrode 130 of the second gate structure GS2 through the gate dielectric film 120, the gate spacer 140, and / or the inner spacer 145.

[0063] In some embodiments, the second source / drain region SD2 may include an epitaxial layer. For example, the second source / drain region SD2 may include an epitaxial pattern grown from the second active pattern AP2 by an epitaxial growth method.

[0064] The first source / drain region SD1 and the second source / drain region SD2 may have the same conductivity type or different conductivity types. When the first source / drain region SD1 and / or the second source / drain region SD2 are configured as the source / drain regions of an N-type field-effect transistor (NFET), each of the first source / drain region SD1 and / or the second source / drain region SD2 may include an N-type impurity (e.g., P, Sb, or As) or an impurity for preventing the diffusion of N-type impurities. When the first source / drain region SD1 and / or the second source / drain region SD2 are configured as the source / drain regions of a P-type field-effect transistor (PFET), each of the first source / drain region SD1 and / or the second source / drain region SD2 may include a P-type impurity (e.g., B, In, Ga, or Al) or an impurity for preventing the diffusion of P-type impurities.

[0065] In some embodiments, the first semiconductor pattern 101 may include a first impurity region 100i and / or a second impurity region 100j. Each of the first impurity region 100i and / or the second impurity region 100j may be formed by doping the first semiconductor pattern 101 with an N-type impurity (e.g., P, Sb, or As) or a P-type impurity (e.g., B, In, Ga, or Al).

[0066] The second source / drain region SD2 may be electrically connected to the first impurity region 100i and / or the second impurity region 100j. For example, the second source / drain region SD2 may be in direct contact with the upper surface of the first impurity region 100i and / or the upper surface of the second impurity region 100j. Each of the first impurity region 100i and / or the second impurity region 100j may have the same conductivity type as the second source / drain region SD2, or may have a different conductivity type than the second source / drain region SD2. The first impurity region 100i and / or the second impurity region 100j may be included in, but are not limited to, passive elements (e.g., PN junctions) formed in the second region II.

[0067] In some embodiments, the first impurity region 100i and the second impurity region 100j may have different conductivity types from each other. As an example, the first impurity region 100i may include a P-type impurity, and the second impurity region 100j may include an N-type impurity. The first impurity region 100i and the second impurity region 100j may be joined together to form a PN junction in the first semiconductor pattern 101.

[0068] The first interlayer insulating film 190 can fill the space on the sidewalls of the first gate structure GS1 and the second gate structure GS2. The first interlayer insulating film 190 can cover the first source / drain region SD1 and the second source / drain region SD2. The second interlayer insulating film 192 can be formed on the first gate structure GS1, the second gate structure GS2 and the first interlayer insulating film 190. The third interlayer insulating film 194 can be formed on the second interlayer insulating film 192.

[0069] Each of the first interlayer insulating film 190, the second interlayer insulating film 192, and the third interlayer insulating film 194 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and / or a low dielectric constant material having a dielectric constant lower than that of silicon oxide. The low dielectric constant material may include, for example, but not limited to, FOX (flowable oxide), TOSZ (Toron silazane), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silica), degelatin, aerogel, amorphous fluorinated carbon, OSG (organosilicate glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials, and combinations thereof.

[0070] The separation pattern 180 can separate the substrate 100 of the first region I from the substrate 100 of the second region II. For example, the separation pattern 180 can be placed between the insulating pattern 102 and the first semiconductor pattern 101. The insulating pattern 102 and the first semiconductor pattern 101 can be separated by the separation pattern 180.

[0071] The separation pattern 180 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and / or combinations thereof. As an example, the separation pattern 180 may include a silicon oxide film.

[0072] although Figure 2 The diagram shows a boundary between the insulating pattern 102 and the separating pattern 180, but this is only an example. In some cases, there may be no boundary between the insulating pattern 102 and the separating pattern 180.

[0073] In some embodiments, the lower surface of the separation pattern 180 may be configured to be coplanar (or at the same level) with the first back side 102b of the insulating pattern 102 and / or the third back side 105b of the field insulating film 105. Although the upper surface of the separation pattern 180 is only shown as being positioned coplanar (or at the same level) with the upper surface of the first gate structure GS1 and / or the upper surface of the second gate structure GS2, this is merely an example. The upper surface of the separation pattern 180 may be positioned lower than the upper surface of the first gate structure GS1 and / or the upper surface of the second gate structure GS2, or it may be positioned higher than the upper surface of the first gate structure GS1 and / or the upper surface of the second gate structure GS2.

[0074] In some embodiments, the second back side 101b of the first semiconductor pattern 101 may be configured to be higher than the lower surface of the separation pattern 180. For example, the lower portion of the separation pattern 180 may protrude below the second back side 101b of the first semiconductor pattern 101.

[0075] In some embodiments, the separation pattern 180 may have a tapered shape with a decreasing width downwards. For example, the width of the separation pattern 180 may gradually decrease towards the back wiring structure BW. Here, the width refers to the width in the horizontal direction (e.g., the first direction X1 or the second direction X2) intersecting the vertical direction Z1 or Z2. This may be due to the characteristics of the etching process used to form the separation pattern 180.

[0076] A first source / drain contact FC1 may be formed on the upper surface of the first source / drain region SD1. The first source / drain contact FC1 may be electrically connected to the first source / drain region SD1. For example, the first source / drain contact FC1 may penetrate the first interlayer insulating film 190 and the second interlayer insulating film 192 and be in direct contact with the upper surface of the first source / drain region SD1. In some embodiments, the first source / drain contact FC1 may be formed to penetrate a portion of the first source / drain region SD1.

[0077] A second source / drain contact FC2 may be formed on the upper surface of the second source / drain region SD2. The second source / drain contact FC2 may be electrically connected to the second source / drain region SD2. For example, the second source / drain contact FC2 may penetrate the first interlayer insulating film 190 and the second interlayer insulating film 192 and be in direct contact with the upper surface of the second source / drain region SD2. In some embodiments, the second source / drain contact FC2 may be formed to penetrate a portion of the second source / drain region SD2.

[0078] A first gate contact CB1 may be formed on the upper surface of the gate electrode 130 of the first gate structure GS1. The first gate contact CB1 may be electrically connected to the gate electrode 130 of the first gate structure GS1. For example, the first gate contact CB1 may penetrate the gate cover film 150, the second interlayer insulating film 192 and the third interlayer insulating film 194 of the first gate structure GS1 and be in direct contact with the upper surface of the gate electrode 130 of the first gate structure GS1.

[0079] The second gate contact CB2 may be formed on the upper surface of the gate electrode 130 of the second gate structure GS2. The second gate contact CB2 may be electrically connected to the gate electrode 130 of the second gate structure GS2. For example, the second gate contact CB2 may penetrate the gate cover film 150, the second interlayer insulating film 192 and the third interlayer insulating film 194 of the second gate structure GS2, and be in direct contact with the upper surface of the gate electrode 130 of the second gate structure GS2.

[0080] Each of the first source / drain contact FC1, the second source / drain contact FC2, the first gate contact CB1, and the second gate contact CB2 may include a conductive material, such as at least one of the following: a metal (e.g., cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphide (CoWP)); a conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)); and / or a silicide (e.g., nickel silicide (NiSi), cobalt silicide (CoSi), tungsten silicide (WSi), titanium silicide (TiSi), niobium silicide (NbSi), or tantalum silicide (TaSi)).

[0081] The front wiring structure FW can be formed in the first region I and the second region II. For example, the front wiring structure FW can be formed on the third interlayer insulating film 194. The front wiring structure FW may include a front interlayer insulating film 210, a front wiring pattern 220, and a front via pattern 225. The front wiring pattern 220 may form a multilayer wiring structure inside the front interlayer insulating film 210. The front via pattern 225 may interconnect the front wiring pattern 220 in the vertical direction Z1 or Z2. The number, quantity, and arrangement of the front interlayer insulating film 210, the front wiring pattern 220, and the front via pattern 225 are merely examples and are not limited to those shown in the figures.

[0082] The front wiring structure FW can be electrically connected to the first source / drain region SD1, the first gate structure GS1, the second source / drain region SD2, and / or the second gate structure GS2. For example, the front wiring pattern 220 and / or the front via pattern 225 can be electrically connected to the first source / drain contact FC1, the first gate contact CB1, the second source / drain contact FC2, and / or the second gate contact CB2.

[0083] In some embodiments, a via contact VA penetrating the third interlayer insulating film 194 may be formed. Each of the first source / drain contact FC1 and / or the second source / drain contact FC2 may be electrically connected to the front wiring pattern 220 via the via contact VA.

[0084] The buried pattern 300 may be formed in the second region II. The buried pattern 300 may be formed on the second back side 101b of the first semiconductor pattern 101. The buried pattern 300 may be buried in the substrate 100 of the second region II. For example, a recess 101r may be formed in the substrate 100 by a recessing process performed on the second back side 101b of the first semiconductor pattern 101. The buried pattern 300 may be formed to fill at least a portion of the recess 101r.

[0085] In some embodiments, at least a portion of the recess 101r may be defined by the second back side 101b of the first semiconductor pattern 101 and the sidewall of the separation pattern 180. For example, as Figure 2 As shown, the buried pattern 300 can directly contact the second back side 101b of the first semiconductor pattern 101 and the sidewall of the lower part of the separation pattern 180 protruding below the second back side 101b.

[0086] In some embodiments, the lower surface of the burial pattern 300 may be configured to be coplanar (or at the same level) with the lower surface of the separation pattern 180.

[0087] In some embodiments, at least a portion of the recess 101r may be defined by the second back side 101b of the first semiconductor pattern 101 and the sidewalls of the field insulating film 105. For example, as Figure 3 As shown, the buried pattern 300 can directly contact the second back side 101b of the first semiconductor pattern 101 and the sidewall of the lower portion of the field insulating film 105 protruding below the second back side 101b.

[0088] In some embodiments, the lower surface of the buried pattern 300 may be positioned coplanar (or at the same level) with the third back side 105b of the field insulating film 105.

[0089] In some embodiments, the thickness T1 of the insulating pattern 102 may be greater than the thickness T3 of the buried pattern 300. For example, as Figure 2 and Figure 3 As shown, the first back side 102b of the insulating pattern 102 and the lower surface of the buried pattern 300 may be positioned as coplanar (or at the same level), while the first front side 102a of the insulating pattern 102 may be positioned higher than the upper surface of the buried pattern 300.

[0090] In some embodiments, the sum (T2+T3) of the thickness T2 of the first semiconductor pattern 101 and the thickness T3 of the buried pattern 300 may be equal to the thickness T1 of the insulating pattern 102. For example, as Figure 2 and Figure 3 As shown, the first front side 102a of the insulating pattern 102 and the second front side 101a of the first semiconductor pattern 101 can be positioned as coplanar (or at the same level), and the first back side 102b of the insulating pattern 102 and the lower surface of the buried pattern 300 can be positioned as coplanar (or at the same level).

[0091] The buried pattern 300 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and / or combinations thereof. As an example, the buried pattern 300 may include a silicon nitride film.

[0092] In the first region I, including the back source / drain contact BC, the thickness of the substrate 100 and / or the first semiconductor pattern 101 can be minimized or eliminated. In contrast, in the second region II, the substrate 100 and / or the first semiconductor pattern 101 may need to be maintained at a thickness equal to or greater than a predetermined thickness. To separate the thickness control of the substrate 100 and / or the first semiconductor pattern 101 between the first region I and the second region II, the present invention provides a buried pattern 300 formed in an embedded manner in the second region II. With the buried pattern 300, the thickness of the substrate 100 and / or the first semiconductor pattern 101 in the first region I and the second region II can be controlled independently.

[0093] In some embodiments, the buried pattern 300 may include a liner 302 and a buried insulating film 304 sequentially stacked in the recess 101r.

[0094] The substrate 302 may extend conformally along the contour of the recess 101r. For example, the substrate 302 may extend conformally along the contours of the second back side 101b of the first semiconductor pattern 101, the sidewall of the separation pattern 180, and the sidewall of the field insulating film 105. The substrate 302 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide, and / or combinations thereof. As an example, the substrate 302 may include an aluminum oxide film.

[0095] The buried insulating film 304 may be formed to fill the area remaining after the filling substrate 302 in the recess 101r. For example, the substrate 302 may be positioned between the first semiconductor pattern 101 and the buried insulating film 304, between the separation pattern 180 and the buried insulating film 304, and between the field insulating film 105 and the buried insulating film 304. The buried insulating film 304 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon carbonitride, and / or combinations thereof. As an example, the buried insulating film 304 may include a silicon nitride film.

[0096] A back source / drain contact BC may be formed in the first region I. The back source / drain contact BC may not be formed in the second region II. The back source / drain contact BC may be formed on the lower surface of the first source / drain region SD1. The back source / drain contact BC may be electrically connected to the first source / drain region SD1. For example, the back source / drain contact BC may penetrate the insulating pattern 102 and directly contact the lower surface of the first source / drain region SD1. In some embodiments, the back source / drain contact BC may be formed to penetrate a portion of the first source / drain region SD1.

[0097] The back source / drain contact BC includes at least one of the following: a conductive material, such as a metal (e.g., cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphide (CoWP)); a conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)); and / or a silicide (e.g., nickel silicide (NiSi), cobalt silicide (CoSi), tungsten silicide (WSi), titanium silicide (TiSi), niobium silicide (NbSi), or tantalum silicide (TaSi)).

[0098] The back-side wiring structure BW can be formed in the first region I and the second region II. For example, the back-side wiring structure BW can be formed below the substrate 100 and the buried pattern 300. The buried pattern 300 can be placed between the first semiconductor pattern 101 and the back-side wiring structure BW. The back-side wiring structure BW may include a back-side wiring inter-insulating film 310, a back-side wiring pattern 320, and a back-side via pattern 325. The back-side wiring pattern 320 can form a multilayer wiring structure in the back-side wiring inter-insulating film 310. The back-side via pattern 325 can interconnect the back-side wiring patterns 320 in the vertical direction Z1 or Z2. The number, quantity, arrangement, etc. of the back-side wiring inter-insulating film 310, the back-side wiring pattern 320, and the back-side via pattern 325 are merely examples and are not limited to those shown in the figures.

[0099] The back-side wiring structure BW can be electrically connected to the first source / drain region SD1 and / or the first gate structure GS1. For example, the back wiring pattern 320 and / or the back via pattern 325 can be electrically connected to the back source / drain contact BC.

[0100] Figures 4 to 8 These are schematic cross-sectional views used to explain various semiconductor devices according to some embodiments. For ease of explanation, the above uses... Figures 1 to 3 Repeated parts of the explanation will be briefly explained or omitted.

[0101] Reference Figure 4 The semiconductor device according to some embodiments also includes an oxide film 103.

[0102] An oxide film 103 may be formed in the second region II. The oxide film 103 may be formed on the second back side 101b of the first semiconductor pattern 101. The oxide film 103 may extend along the second back side 101b of the first semiconductor pattern 101. The oxide film 103 may be disposed between the first semiconductor pattern 101 and the buried pattern 300.

[0103] The oxide film 103 may include an oxide of the first semiconductor pattern 101. For example, the oxide film 103 may be formed by oxidizing a portion of the first semiconductor pattern 101. As an example, when the first semiconductor pattern 101 is a silicon pattern, the oxide film 103 may include silicon oxide.

[0104] Reference Figure 5 In a semiconductor device according to some embodiments, the substrate 100 further includes a second semiconductor pattern 101P.

[0105] A second semiconductor pattern 101P may be formed in the first region I. The second semiconductor pattern 101P may extend relatively long in the first direction X1. The second semiconductor pattern 101P may be formed on the first front side 102a of the insulating pattern 102. For example, the second semiconductor pattern 101P may be positioned between the insulating pattern 102 and the first gate structure GS1 in the first vertical direction Z1 and / or between the insulating pattern 102 and the first active pattern AP1 in the first vertical direction Z1. In some embodiments, the bridging patterns 111 to 113 of the first active pattern AP1 may be spaced apart from the second semiconductor pattern 101P in the first vertical direction Z1.

[0106] The second semiconductor pattern 101P may include a semiconductor material, such as, but not limited to, at least one of silicon, germanium silicon, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and / or combinations thereof.

[0107] The first semiconductor pattern 101 and the second semiconductor pattern 101P may be formed at the same level. In this specification, the statement "formed at the same level" means formed by the same manufacturing process. For example, the first semiconductor pattern 101 and the second semiconductor pattern 101P may have the same material composition.

[0108] In some embodiments, the upper surface of the second semiconductor pattern 101P may be configured to be coplanar (or at the same level) with the second front side 101a of the first semiconductor pattern 101.

[0109] In some embodiments, the thickness T2a of the second semiconductor pattern 101P may be less than the thickness T2b of the first semiconductor pattern 101. For example, the upper surface of the second semiconductor pattern 101P may be positioned coplanar (or at the same level) with the second front side 101a of the first semiconductor pattern 101, and the lower surface of the second semiconductor pattern 101P may be positioned higher than the second back side 101b of the first semiconductor pattern 101.

[0110] In some embodiments, the thickness T2a of the second semiconductor pattern 101P can be about 40 nm or less. For example, the thickness T2a of the second semiconductor pattern 101P can be about 1 nm to about 40 nm.

[0111] In some embodiments, the sum of the thickness T1 of the insulating pattern 102 and the thickness T2a of the second semiconductor pattern 101P (T1+T2a) may be equal to the sum of the thickness T2b of the first semiconductor pattern 101 and the thickness T3 of the buried pattern 300 (T2b+T3). For example, the upper surface of the second semiconductor pattern 101P and the second front side 101a of the first semiconductor pattern 101 may be positioned coplanar (or at the same level), and the first back side 102b of the insulating pattern 102 and the lower surface of the buried pattern 300 may be positioned coplanar (or at the same level).

[0112] In some embodiments, the second semiconductor pattern 101P may include a third impurity region 10i. The third impurity region 10i may be superimposed on at least a portion of the first gate structure GS1 in the first vertical direction Z1. The third impurity region 10i may be formed by doping the second semiconductor pattern 101P with an N-type impurity (e.g., P, Sb, or As) or a P-type impurity (e.g., B, In, Ga, or Al).

[0113] The third impurity region 10i can block leakage current that may occur along the first direction X1 in the second semiconductor pattern 101P. As an example, when the first source / drain region SD1 is set as the source / drain region of an NFET, the third impurity region 10i may include a P-type impurity. As another example, when the first source / drain region SD1 is set as the source / drain region of a PFET, the third impurity region 10i may include an N-type impurity.

[0114] The back source / drain contact BC can penetrate the insulating pattern 102 and the second semiconductor pattern 101P, and is electrically connected to the first source / drain region SD1.

[0115] Reference Figure 6 The semiconductor device according to some embodiments also includes a second semiconductor pattern 101P, a conductive plate 306, and a diced pattern 308.

[0116] A second semiconductor pattern 101P can be formed in the first region I. Since the second semiconductor pattern 101P can be used with the above... Figure 5 The second semiconductor pattern 101P is similar to that explained, so its detailed description will not be provided below.

[0117] A conductive plate 306 may be formed on the first back side 102b of the insulating pattern 102. The conductive plate 306 may be positioned between the back source / drain contact BC and the back wiring structure BW. The back source / drain contact BC may be electrically connected to the back wiring structure BW via the conductive plate 306.

[0118] The dicing pattern 308 may be placed between the first gate structure GS1 and the back-side wiring structure BW. The dicing pattern 308 may be superimposed on at least a portion of the first gate structure GS1 in the first vertical direction Z1. The dicing pattern 308 may extend in the first vertical direction Z1 to cut the conductive plate 306, the insulating pattern 102, and the second semiconductor pattern 101P.

[0119] The cutting pattern 308 may include, for example, but not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and combinations thereof.

[0120] Reference Figure 7 In a semiconductor device according to some embodiments, the second region II includes a first sub-region IIa and a second sub-region IIb that are distinct from each other.

[0121] The first sub-region IIa and the second sub-region IIb may be adjacent to each other or spaced apart from each other. Each of the first sub-region IIa and the second sub-region IIb may be a passive element region. For example, each of the first sub-region IIa and the second sub-region IIb may include a first semiconductor pattern 101, a field insulating film 105, a second active pattern AP2, a second gate structure GS2, a second source / drain region SD2, a second source / drain contact FC2, a second gate contact CB2, and a buried pattern 300.

[0122] The buried pattern 300 of the first sub-region IIa and the buried pattern 300 of the second sub-region IIb may have different thicknesses. For example, the thickness T3a of the buried pattern 300 of the first sub-region IIa may be less than the thickness T3b of the buried pattern 300 of the second sub-region IIb. The thickness of the first semiconductor pattern 101 can be adjusted by the thickness of the buried pattern 300. For example, as shown, when the thickness T3a of the buried pattern 300 of the first sub-region IIa is less than the thickness T3b of the buried pattern 300 of the second sub-region IIb, the thickness T2c of the first semiconductor pattern 101 of the first sub-region IIa may be greater than the thickness T2d of the first semiconductor pattern 101 of the second sub-region IIb.

[0123] In some embodiments, the sum of the thickness T2c of the first semiconductor pattern 101 in the first sub-region IIa and the thickness T3a of the buried pattern 300 (T2c+T3a) may be equal to the sum of the thickness T2d of the first semiconductor pattern 101 in the second sub-region IIb and the thickness T3b of the buried pattern 300 (T2d+T3b).

[0124] Reference Figure 8 The semiconductor device according to some embodiments also includes an oxide film 103.

[0125] Oxide film 103 may be formed in each of the first sub-region IIa and the second sub-region IIb. Since oxide film 103 can be used with the above... Figure 4 The oxide film explained is similar, so its detailed description will not be provided.

[0126] In the following text, reference will be made to Figures 1 to 25 A method for manufacturing a semiconductor device according to an example embodiment is described.

[0127] Figures 9 to 20 This is a diagram illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, it is used in conjunction with the methods described above. Figures 1 to 8 Repeated parts of the explanation will be briefly explained or omitted.

[0128] Reference Figure 9 and Figure 10A substrate pattern 101F, a field insulating film 105, a first active pattern AP1, a second active pattern AP2, a first gate structure GS1, a second gate structure GS2, a first source / drain region SD1, a second source / drain region SD2, a first interlayer insulating film 190, a separation pattern 180, a second interlayer insulating film 192, a third interlayer insulating film 194, a first source / drain contact FC1, a second source / drain contact FC2, a first gate contact CB1, and a second gate contact CB2 are formed on a substrate 100P.

[0129] The substrate 100P can be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100P can be a silicon substrate, or may include other materials such as silicon germanium, SGOI (silicon germanium-on-insulator), SOSG (silicon germanium-on-silicon), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100P may have an epitaxial layer formed on the substrate.

[0130] The substrate pattern 101F may protrude from the upper surface of the substrate 100P. The substrate pattern 101F of the first region I may extend longer in the first direction X1. The substrate pattern 101F of the second region II may extend longer in the second direction X2.

[0131] The substrate pattern 101F may include a semiconductor material, such as, but not limited to, at least one of silicon, germanium silicon, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and / or combinations thereof. The substrate pattern 101F may be formed by etching a portion of the substrate 100P, or the substrate pattern 101F may be an epitaxial layer grown from the substrate 100P.

[0132] In some embodiments, the substrate pattern 101F of the second region II may include a first impurity region 100i and / or a second impurity region 100j. Each of the first impurity regions 100i and / or the second impurity regions 100j may be formed by doping the substrate pattern 101F of the second region II with an N-type impurity (e.g., P, Sb, or As) or a P-type impurity (e.g., B, In, Ga, or Al).

[0133] A field insulating film 105 may be formed on a substrate 100P. The field insulating film 105 may cover at least a portion of the sidewalls of the substrate pattern 101F. In some embodiments, the upper portion of the substrate pattern 101F may protrude above the field insulating film 105.

[0134] A first active pattern AP1 may be formed on the front side (e.g., the upper surface) of the substrate pattern 101F in the first region I. A second active pattern AP2 may be formed on the front side (e.g., the upper surface) of the substrate pattern 101F in the second region II. A first gate structure GS1 may intersect with the first active pattern AP1. A second gate structure GS2 may intersect with the second active pattern AP2. A first source / drain region SD1 is formed on at least one side (e.g., both sides) of the first gate structure GS1, and the first source / drain region SD1 may be connected to the first active pattern AP1. A second source / drain region SD2 is formed on at least one side (e.g., both sides) of the second gate structure GS2, and the second source / drain region SD2 may be connected to the second active pattern AP2.

[0135] The first interlayer insulating film 190 can fill the space on the sidewalls of the first gate structure GS1 and the second gate structure GS2. The first interlayer insulating film 190 can cover the first source / drain region SD1 and the second source / drain region SD2. The separation pattern 180 can separate the substrate pattern 101F of the first region I and the substrate pattern 101F of the second region II. A second interlayer insulating film 192 can be formed on the first gate structure GS1, the second gate structure GS2 and the first interlayer insulating film 190. A third interlayer insulating film 194 can be formed on the second interlayer insulating film 192.

[0136] The first source / drain contact FC1 penetrates the first interlayer insulating film 190 and the second interlayer insulating film 192, and can be connected to the first source / drain region SD1. The second source / drain contact FC2 penetrates the first interlayer insulating film 190 and the second interlayer insulating film 192, and can be connected to the second source / drain region SD2. The first gate contact CB1 penetrates the gate capping film 150, the second interlayer insulating film 192 and the third interlayer insulating film 194 of the first gate structure GS1, and can be connected to the gate electrode 130 of the first gate structure GS1. The second gate contact CB2 penetrates the gate capping film 150, the second interlayer insulating film 192 and the third interlayer insulating film 194 of the second gate structure GS2, and can be connected to the gate electrode 130 of the second gate structure GS2.

[0137] Reference Figure 11 This forms the front wiring structure (FW).

[0138] A front wiring structure FW can be formed on the third interlayer insulating film 194. The front wiring pattern 220 and / or the front via pattern 225 can be electrically connected to the first source / drain contact FC1, the first gate contact CB1, the second source / drain contact FC2 and / or the second gate contact CB2.

[0139] Reference Figure 12A thinning process was performed on the 100P substrate.

[0140] For example, the carrier substrate 400 can be attached to Figure 11 On the obtained product. After attaching the carrier substrate 400, it can be Figure 11 The resulting material is then reversed. Therefore, the back side of the substrate 100P can be facing upwards. A thinning process (e.g., back grinding) can then be performed on the back side of the substrate 100P. Due to the thinning process, at least a portion of the substrate 100P can be removed.

[0141] In some embodiments, a thinning process may be used to expose the substrate pattern 101F and / or the field insulating film 105. In some embodiments, a thinning process may be used to expose the separation pattern 180.

[0142] Reference Figure 13 A first hard mask 510, a second hard mask 520, and a first mask pattern 530 are formed on the back side of the substrate pattern 101F.

[0143] A first hard mask film 510, a second hard mask film 520, and a first mask pattern 530 can be sequentially stacked on the back side of a substrate pattern 101F. The first mask pattern 530 can be patterned to cover a first region I and expose a second region II. The first mask pattern 530 may include, but is not limited to, a photoresist pattern. Next, a patterning process can be performed to pattern the second hard mask film 520 using the first mask pattern 530 as an etching mask. Thus, the second hard mask film 520 can cover the first hard mask film 510 in the first region I and expose the first hard mask film 510 in the second region II.

[0144] The first hard mask 510 and the second hard mask 520 may have different etching selectivity than each other. As an example, the first hard mask 510 may include a silicon oxide film, and the second hard mask 520 may include a silicon nitride film.

[0145] Reference Figure 14 The first recessed process is performed on the substrate pattern 101F of the second region II.

[0146] For example, an etching process using a second hard mask film 520 as an etching mask can be performed. Due to the performance of the first recess process, a recess 101r can be formed in the substrate pattern 101F of the second region II. Furthermore, the substrate pattern 101F of the second region II, including the recess 101r, can form a first semiconductor pattern 101 of the second region II. As a result, the thickness T4b of the first semiconductor pattern 101 of the second region II can become smaller than the thickness T4a of the substrate pattern 101F of the first region I.

[0147] Reference Figure 15This forms a liner 302 and a buried insulating film 304.

[0148] A substrate 302 and a buried insulating film 304 may be sequentially stacked on the second hard mask film 520 of the first region I and the first semiconductor pattern 101 of the second region II. The substrate 302 and the buried insulating film 304 may fill at least a portion of the recess 101r. For example, the substrate 302 may conformally extend along the contour of the recess 101r. The substrate 302 may mitigate or mitigate defects in the first semiconductor pattern 101 that may occur during the first recess process. The buried insulating film 304 may fill the remaining area of ​​the recess 101r after the substrate 302 has been filled.

[0149] Reference Figure 16 Remove the liner 302 and the buried insulating film 304 from the first region I.

[0150] For example, a planarization process can be performed on the first region I and the second region II. The planarization process may include, but is not limited to, a chemical mechanical polishing process. Due to the planarization process, the first hard mask film 510 can be exposed. Therefore, the liner film 302 and the buried insulating film 304 in the first region I can be removed. Furthermore, a buried pattern 300 filling at least a portion of the recess 101r can be formed in the second region II.

[0151] Reference Figure 17 A second recessed process is performed on the substrate pattern 101F of the first region I.

[0152] For example, an etching process using the buried pattern 300 as an etching mask can be performed. Due to the second recess process, at least a portion of the substrate pattern 101F of the first region I can be removed. In some embodiments, as shown, the first source / drain region SD1 can be exposed by the second recess process. In some embodiments, as shown, the substrate pattern 101F of the first region I can be completely removed by the second recess process.

[0153] In some embodiments, unlike the example shown, a portion of the substrate pattern 101F of the first region I may be retained after performing the second recessing process. Therefore, the substrate pattern 101F of the first region I can be formed as described above. Figure 5 and Figure 6 The second semiconductor pattern 101P is explained.

[0154] Reference Figure 18 , forming a filled insulating film 102P.

[0155] A filling insulating film 102P can be formed in the first region I and the second region II. The filling insulating film 102P can fill at least a portion of the area of ​​the substrate pattern 101F that has been removed by the second recessing process.

[0156] Reference Figure 19 Remove the insulating film 102P filling the second region II.

[0157] For example, a planarization process can be performed on the first region I and the second region II. The planarization process may include, but is not limited to, a chemical mechanical polishing process. Due to the planarization process, the buried pattern 300 can be exposed. Therefore, the filling insulating film 102P of the second region II can be removed. In addition, an insulating pattern 102 can be formed in the first region I, the insulating pattern 102 replacing at least a portion of the area of ​​the substrate pattern 101F removed by the second recess process.

[0158] Reference Figure 20 This forms the source / drain contact BC.

[0159] The back source / drain contact BC penetrates the insulating pattern 102 and can be connected to the first source / drain region SD1.

[0160] Next, refer to Figure 2 This forms the back-side wiring structure (BW). Therefore, it can be manufactured for use in the above applications. Figures 1 to 3 Explanation of semiconductor devices.

[0161] Figure 21 This is a diagram illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, it is used in conjunction with the methods described above. Figures 1 to 20 Repeated parts of the explanation will be briefly explained or omitted. For reference, Figure 21 It is used for explanation Figure 14 The intermediate steps of the subsequent steps are shown in the diagram.

[0162] Reference Figure 21 A cleaning process is performed on the second back side 101b of the first semiconductor pattern 101.

[0163] For example, an oxygen plasma ashing (O2 plasma ashing) process and a DHF (dilute hydrofluoric acid) treatment process can be sequentially performed on the second back side 101b of the first semiconductor pattern 101. This removes impurities and residues from the second back side 101b of the first semiconductor pattern 101. In some embodiments, after performing the cleaning process, an oxide film 103 can be retained on the second back side 101b of the first semiconductor pattern 101.

[0164] Next, you can perform the above steps. Figures 15 to 20 and Figure 2 The steps explained. Therefore, the above-mentioned uses can be manufactured. Figure 4 Explanation of semiconductor devices.

[0165] Figures 22 to 25This is a diagram illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, it is used in conjunction with the methods described above. Figures 1 to 21 Repeated parts of the explanation will be briefly explained or omitted. For reference, Figure 22 It is used for explanation Figure 12 The intermediate steps of the subsequent steps are shown in the diagram.

[0166] Reference Figure 22 A first hard mask 510, a second hard mask 520, and a second mask pattern 530a are formed on the back side of the substrate pattern 101F.

[0167] A first hard mask film 510, a second hard mask film 520, and a second mask pattern 530a can be sequentially stacked on the back side of a substrate pattern 101F. The second mask pattern 530a can be patterned to cover a first region I and a first sub-region IIa and expose a second sub-region IIb. The second mask pattern 530a may include, but is not limited to, a photoresist pattern. Next, a patterning process can be performed to pattern the second hard mask film 520 using the second mask pattern 530a as an etching mask. Therefore, the second hard mask film 520 can cover the first hard mask film 510 covering the first region I and the first sub-region IIa, and can expose the first hard mask film 510 covering the second sub-region IIb.

[0168] Reference Figure 23 A third recessing process is performed on the substrate pattern 101F of the second sub-region IIb.

[0169] For example, an etching process using a second hard mask film 520 as an etching mask can be performed. Due to the performance of the third recess process, a recess 101r can be formed in the substrate pattern 101F of the second sub-region IIb. Furthermore, the substrate pattern 101F of the second sub-region IIb, including the recess 101r, can form a first semiconductor pattern 101 of the second sub-region IIb. Therefore, the thickness T5b of the first semiconductor pattern 101 of the second sub-region IIb can become smaller than the thickness T5a of the substrate pattern 101F of the first region I and the first sub-region IIa.

[0170] Reference Figure 24 A third mask pattern 530b is formed on the second hard mask film 520.

[0171] A third mask pattern 530b can be patterned to cover the first region I and expose the second region II. The third mask pattern 530b may include, but is not limited to, a photoresist pattern. Next, a patterning process can be performed to pattern the second hard mask film 520 using the third mask pattern 530b as an etching mask. Therefore, the second hard mask film 520 can cover the first hard mask film 510 of the first region I and can expose the first hard mask film 510 of the first sub-region IIa and the first semiconductor pattern 101 of the second sub-region IIb.

[0172] Reference Figure 25 A fourth recess process is performed on the substrate pattern 101F of the first sub-region IIa and the first semiconductor pattern 101 of the second sub-region IIb.

[0173] For example, an etching process using a second hard mask film 520 as an etching mask can be performed. Due to the performance of the fourth recess process, recesses 101ra and 101rb can be formed in the substrate pattern 101F of the second region II. Furthermore, the substrate pattern 101F of the second region II, including recesses 101ra and 101rb, can form a first semiconductor pattern 101 of the second region II.

[0174] The recess 101r may include a first sub-recess 101ra in the first sub-region IIa and a second sub-recess 101rb in the second sub-region IIb. As described above, since a fourth recess process can be performed on the first sub-region IIa, and a third and fourth recess process can be performed on the second sub-region IIb, the depth of the second sub-recess 101rb may be greater than the depth of the first sub-recess 101ra. Therefore, the thickness T5c of the first semiconductor pattern 101 in the first sub-region IIa may become less than the thickness T5a of the substrate pattern 101F in the first region I, and the thickness T5d of the first semiconductor pattern 101 in the second sub-region IIb may become less than the thickness T5c of the first semiconductor pattern 101 in the first sub-region IIa.

[0175] Next, you can perform the above steps. Figures 15 to 20 and Figure 2 The steps explained. Therefore, the above-mentioned uses can be manufactured. Figure 7 Explanation of semiconductor devices.

[0176] In some embodiments, a method for manufacturing a semiconductor device including different first and second regions may include: forming a substrate pattern in the first and second regions; forming a first active pattern, a first gate structure intersecting the first active pattern, and a first source / drain region connected to the first active pattern on a front side of the substrate pattern in the first region; forming a mask pattern on a back side of the substrate pattern in the first region; forming a recess in the substrate pattern in the second region using the mask pattern as an etch mask; forming a buried pattern in the recess; removing at least a portion of the substrate pattern in the first region using the buried pattern as an etch mask; forming an insulating pattern that fills at least a portion of the region where the substrate pattern has been removed; forming a back source / drain contact that penetrates the insulating pattern and connects to the first source / drain region; and forming a back-side wiring structure on the insulating pattern and the buried pattern, the back-side wiring structure being connected to the back source / drain contact.

[0177] In some embodiments, the method may further include forming sequentially stacked liner films and buried insulating films in the recesses.

[0178] In some embodiments, the method may further include forming a depression in a second region comprising different first and second sub-regions, wherein the depression comprises a first sub-depression in the first sub-region and a second sub-depression in the second sub-region, the second sub-depression being deeper than the first sub-depression.

[0179] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be practiced in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not limiting, but illustrative in all respects.

Claims

1. A semiconductor device comprising a first region and a second region distinct from each other, the semiconductor device comprising: The substrate includes an insulating pattern in a first region and a first semiconductor pattern in a second region; Separate the pattern, separate the insulating pattern and the first semiconductor pattern, and between the insulating pattern and the first semiconductor pattern; The first active pattern is on the upper surface of the insulating pattern; The first gate structure intersects with the first active pattern; The first source / drain region is connected to the first active pattern and is on the sidewall of the first gate structure; The second active pattern is on the upper surface of the first semiconductor pattern; The second gate structure intersects with the second active pattern; The buried pattern is on the lower surface of the first semiconductor pattern; Backside wiring structure, on the lower surface of the insulating pattern and on the lower surface of the buried pattern; as well as The back-side source / drain contact penetrates the insulating pattern and connects the first source / drain region and the back-side wiring structure. The buried pattern includes a liner and a buried insulating film. The liner extends along the contour of the lower surface of the first semiconductor pattern and the sidewall of the separation pattern, and the buried insulating film is on the liner.

2. The semiconductor device according to claim 1, in, The thickness of the insulating pattern is greater than the thickness of the first semiconductor pattern.

3. The semiconductor device according to claim 1, in, The upper surface of the insulating pattern and the upper surface of the first semiconductor pattern are coplanar.

4. The semiconductor device according to claim 1, in, The substrate also includes a second semiconductor pattern between the insulating pattern and the first active pattern.

5. The semiconductor device according to claim 4, in, The thickness of the first semiconductor pattern is greater than the thickness of the second semiconductor pattern.

6. The semiconductor device according to claim 4, in, The upper surfaces of the first semiconductor pattern and the second semiconductor pattern are coplanar.

7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device further comprises: The second source / drain region is connected to the second active pattern and is located on the sidewall of the second gate structure.

8. The semiconductor device according to claim 7, in, The first semiconductor pattern includes an impurity region connected to the second source / drain region.

9. The semiconductor device according to claim 1, further comprising: An oxide film comprising an oxide of a first semiconductor pattern and between the first semiconductor pattern and a substrate.

10. The semiconductor device according to any one of claims 1 to 6, in, The width of the separation pattern decreases towards the back wiring structure.

11. The semiconductor device according to any one of claims 1 to 6, in, The liner includes an alumina film.

12. The semiconductor device according to any one of claims 1 to 6, in, The buried insulating film includes silicon nitride film.

13. A semiconductor device comprising a first region and a second region distinct from each other, the semiconductor device comprising: The substrate includes an insulating pattern in a first region, a semiconductor pattern in a second region, and a field insulating film covering at least a portion of the sidewalls of the insulating pattern and at least a portion of the sidewalls of the semiconductor pattern. The first active pattern is on the upper surface of the insulating pattern; The first gate structure intersects with the first active pattern; The source / drain region is connected to the first active pattern and is located on the sidewall of the first gate structure; The second active pattern is on the upper surface of the semiconductor pattern; The second gate structure intersects with the second active pattern; Buried pattern, on the lower surface of a semiconductor pattern; The back-side wiring structure is located on the lower surface of the insulating pattern, the lower surface of the field insulating film, and the lower surface of the buried pattern. as well as The source / drain contacts penetrate the insulating pattern and connect the source / drain regions to the back-side wiring structure. The buried pattern includes a liner and a buried insulating film. The liner extends along the contour of the lower surface of the semiconductor pattern and the sidewall of the field insulating film, and the buried insulating film is on the liner.

14. The semiconductor device according to claim 13, in, The lower surface of the field insulating film and the lower surface of the buried pattern are coplanar.

15. The semiconductor device according to claim 13, in, The upper part of the semiconductor pattern protrudes above the upper surface of the field insulating film.

16. The semiconductor device according to claim 13, in, The upper part of the insulating pattern protrudes above the upper surface of the field insulating film.

17. A semiconductor device comprising a first region and a second region distinct from each other, the semiconductor device comprising: The substrate includes an insulating pattern in a first region and a semiconductor pattern in a second region; The first active pattern is on the upper surface of the insulating pattern; The first gate structure intersects with the first active pattern; The source / drain region is connected to the first active pattern and is located on the sidewall of the first gate structure; The second active pattern is on the upper surface of the semiconductor pattern; The second gate structure intersects with the second active pattern; Buried pattern, on the lower surface of a semiconductor pattern; Backside wiring structure, on the lower surface of the insulating pattern and on the lower surface of the buried pattern; as well as The source / drain contacts penetrate the insulating pattern and connect the source / drain regions to the back-side wiring structure. The second region comprises distinct first and second sub-regions, and The thickness of the semiconductor pattern in the first sub-region is greater than the thickness of the semiconductor pattern in the second sub-region.

18. The semiconductor device according to claim 17, in, The thickness of the buried pattern in the first sub-region is less than the thickness of the buried pattern in the second sub-region.

19. The semiconductor device according to claim 17, in, The buried pattern comprises a substrate and a buried insulating film sequentially stacked on the lower surface of the semiconductor pattern.

20. The semiconductor device of claim 19, further comprising: A separation pattern, situated between an insulating pattern and a semiconductor pattern, separates the insulating pattern and the semiconductor pattern. The substrate further includes a field insulating film that covers at least a portion of the sidewalls of the insulating pattern and at least a portion of the sidewalls of the semiconductor pattern. The substrate extends along the contours of the lower surface of the semiconductor pattern, the sidewalls of the separation pattern, and the sidewalls of the field insulating film.

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