Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application disclose a semiconductor device and a method of manufacturing the same. The semiconductor device comprises: in a first metallization (M_1st) layer, M_1st segments having a first pitch and substantially a first width with a uniform first gap therebetween; and a capacitor cell region arranged in an array and comprising first capacitor cells and second capacitor cells; each capacitor cell has a first number of M_1st segments and a substantially uniform physical arrangement; an electrical arrangement of the M_1st segments is different for the second capacitor cells than for the first capacitor cells; for each capacitor cell, a coupling between the M_1st segments and a respective first voltage or second voltage are arranged such that: each first capacitor cell substantially provides a first capacitance; and each second capacitor cell substantially provides a non-zero second capacitance smaller than the first capacitance.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and reduced spacing, leading to a gradual increase in transistor density. ICs have become smaller and smaller. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a semiconductor device is provided, comprising: in a first metallization layer, first metallization segments extending in a first direction and having a first pitch, wherein each first metallization segment substantially has a first width and a substantially uniform first gap therebetween, relative to a second direction perpendicular to the first direction; and capacitor cell regions (capacitor cells) arranged in an array, including one or more first capacitor cells and one or more second capacitor cells, wherein each capacitor cell has a first number of corresponding first metallization segments in the first metallization segments and a substantially uniform physical arrangement; and wherein, for each capacitor cell, the coupling between the first metallization segment and a corresponding first voltage or second voltage is arranged such that: each first... Each capacitor cell substantially provides a first capacitance; and each second capacitor cell substantially provides a non-zero second capacitance less than the first capacitance; wherein the electrical arrangement of the first metallized segments differs for the second capacitor cells from that for the first capacitor cells; and wherein, for each capacitor cell: the first ends of the odd-numbered first metallized segments and the second ends of the even-numbered first metallized segments are substantially aligned with each other and are respectively adjacent to the opposing first and second boundaries of the capacitor cell; and with respect to the second direction, the opposing third and fourth boundaries of the capacitor cell are located in the respective outermost second and third gaps adjacent to the respective outermost first metallized segments of the first metallized segments; each of the second and third gaps is larger than the first gap.

[0004] According to another aspect of the embodiments of this application, a method for manufacturing a semiconductor device is provided, the method comprising: forming an array of capacitor cell regions (capacitor cells), the capacitor cells including one or more first capacitor cells and one or more second capacitor cells; and forming the array of capacitor cell regions comprising forming first metallization segments in a first metallization layer, the forming of the first metallization segment comprising: depositing a first layer of metallized first material as a precursor of the first metallization segment; etching the first layer to produce: first strips of first material extending in a first direction and having a first pitch relative to a second direction perpendicular to the first direction; and each first strip having a substantially first width relative to the first direction and having a substantially uniform first gap therebetween; for each capacitor cell, etching the first strips to produce the first metallization segment, such that: each capacitor cell has a first number of corresponding first metallization segments in the first metallization segment and a substantially uniform first gap therebetween. A uniform physical arrangement; relative to the second direction, the outermost first metallized segment of the first metallized segment is adjacent to a corresponding outer second gap and a third gap, each of the second gap and the third gap being larger than the first gap, and the opposing first and second boundaries of the capacitor cells are respectively located in the third gap and the fourth gap; and, relative to the first direction, the opposing third and fourth boundaries of each capacitor cell are respectively adjacent to (i) one or more substantially aligned first ends and (i) one or more substantially aligned second ends of the first metallized segments; and for each capacitor cell, the first metallized segment is correspondingly coupled to a first voltage or a second voltage such that: each first capacitor cell substantially provides a first capacitance; each second capacitor cell substantially provides a non-zero second capacitance different from the first capacitance; and the electrical arrangement of the first metallized segments is different for the second capacitor cell than for the first capacitor cell.

[0005] According to another aspect of the embodiments of this application, a semiconductor device is provided, comprising: in a first metallization layer, first metallization segments extending in a first direction and having a first pitch, wherein each first metallization segment substantially has a first width and a substantially uniform first gap therebetween relative to a second direction perpendicular to the first direction; in a second metallization layer, second metallization segments extending in a third direction and having a second pitch, wherein each of the second metallization segments substantially has a second width relative to a fourth direction perpendicular to the third direction; and capacitor cell regions (capacitor cells) arranged in an array, including one or more first capacitor cells and one or more second capacitor cells, wherein each capacitor cell has (i) a first number and substantially uniform physical arrangement of corresponding first metallization segments in the first metallization segments, and (ii) a second number of corresponding second metallization segments in the second metallization segments; and wherein, for each capacitor cell, ( (A) The coupling between the first metallized segment and the corresponding first voltage or second voltage and (B) the coupling between the second metallized segment and the corresponding first voltage or second voltage are arranged such that: each first capacitor cell substantially provides a first capacitance; and each second capacitor cell substantially provides a non-zero second capacitance different from the first capacitance; wherein the electrical arrangement of the first metallized segments is different for the second capacitor cells than for the first capacitor cells; and wherein, for each capacitor cell: the first ends of the odd-numbered first metallized segments and the second ends of the even-numbered first metallized segments are substantially aligned with each other and are correspondingly adjacent to the opposing first and second boundaries of the capacitor cell; and, relative to the second direction, the opposing third and fourth boundaries of the capacitor cell are located in the corresponding outermost second and third gaps adjacent to the corresponding outermost first metallized segments in the first metallized segments; each of the second and third gaps is larger than the first gap. Attached Figure Description

[0006] In the accompanying drawings, one or more embodiments are shown by way of example and not limitation, wherein elements having the same reference numerals denote the same elements throughout. Unless otherwise disclosed, the drawings are not drawn to scale.

[0007] Figures 1A-1C These are corresponding block diagrams based on some embodiments.

[0008] Figure 2 This is a block diagram of an array according to some embodiments.

[0009] Figures 3A-3H These are layout diagrams based on some embodiments.

[0010] Figures 4A-4B These are corresponding cross-sectional views based on some embodiments.

[0011] Figures 5A-5C , Figures 5D(1)-5D(2) and Figures 5E(1)-5E(4) These are corresponding tables based on some embodiments.

[0012] Figure 6 and Figures 7A-7C These are flowcharts of corresponding methods according to some embodiments.

[0013] Figure 8 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0014] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, operations, arrangements, etc., may be considered. For example, in the following description, forming a first component on or above a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spacing relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. Devices may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein can be interpreted accordingly. In some embodiments, the term standard cell structure refers to standardized building blocks included in various standard cell structure libraries. In some embodiments, various standard cell structures are selected from their libraries and used as components in layout diagrams representing circuits.

[0017] In some embodiments, the semiconductor device includes: in a first metallization (M_1st) layer, M_1st segments extending in a first direction and having a first pitch, wherein each M_1st segment substantially has a first width and a substantially uniform first gap therebetween, relative to a second direction perpendicular to the first direction; and a capacitor cell region (capacitor cell) arranged in an array and including one or more first capacitor cells and one or more second capacitor cells, wherein each capacitor cell has a first number and substantially uniform physical arrangement of corresponding M_1st segments in the M_1st segments; and wherein, for each capacitor cell, the coupling between the M_1st segments and a corresponding first voltage or second voltage is arranged such that: each first capacitor cell substantially provides a first capacitance; and each second capacitor cell substantially provides a non-zero second capacitance less than the first capacitance; and wherein the electrical arrangement of the M_1st segments differs for the second capacitor cell from that for the first capacitor cell. In some embodiments, the capacitor cell in the semiconductor device based on the layout is referred to as a fabricated capacitor cell. In some embodiments, when segments of a pair of adjacent segments in the M_1st segment are correspondingly coupled to V_Net_A and V_Net_B, the pair is referred to as an M_1st capacitor pair (CPR). In some embodiments, when both segments of the pair are coupled to V_Net_A or both segments of the pair are coupled to V_Net_B, the pair is referred to as an M_1st dummy pair.

[0018] According to another method, each capacitor cell can have at most N M_1st segments for the M_1st layer, and the capacitor cells have correspondingly different physical arrangements of conductive segments to achieve different cell capacitances. That is, according to another method, the capacitor cells have a substantially non-uniform physical arrangement. According to another method, the non-uniformity of the capacitor cells in the corresponding manufactured capacitor cells is worsened / amplified due to (A) non-uniformity correction introduced by resolution enhancement technology (RET) and / or optical proximity correction (OPC) and (B) manufacturing tolerances, wherein the effects of (A) and / or (B) lead to worsened / amplified capacitor mismatch. Capacitor mismatch reduces the reliability and / or performance of the manufactured capacitor cells and / or increases power consumption, etc. In contrast, at least some of the embodiments in this example produce an array of capacitor cells consisting of uniformly counted M_1st segments, wherein, compared to the other method, uniformity reduces the variation in manufactured capacitor cells caused by (i) RET and / or OPC and (ii) manufacturing tolerances, i.e., uniformity reduces mismatch between manufactured capacitor cells compared to the other method. Compared to another method, the array of at least some of the uniform M_1st segment counting capacitor cells according to this embodiment improves the reliability and / or performance and / or power consumption of the manufactured capacitor cells.

[0019] Figures 1A-1C These are block diagrams of corresponding devices 100A, 100B, and 100C according to some embodiments.

[0020] Each of devices 100A-100C is an example of an integrated circuit (IC). In some embodiments, each of devices 100A-100C is referred to as a semiconductor device. Devices 100A, 100B, and 100C respectively include macro regions 101A, 101B, and 101C.

[0021] exist Figure 1A In the middle, macro region 101A includes capacitor cell region (capacitor cell) (see...) Figures 3A-3H ) array 102 (see Figure 2 Each capacitor cell has a substantially identical set of substantially uniform conductive segments, which can be configured as the plates of the corresponding capacitor. Figure 1B In the macro region 101B, a capacitor digital-to-analog converter (CDAC) 104 is included, wherein the CDAC 104 includes a capacitor cell array 102.

[0022] exist Figure 1C In the macro region 102C, a delay chain 106 is included. In some embodiments, the delay chain 106 is referred to as a delay line. The delay chain 106 includes multiple instances of a CDAC 104. In some embodiments, the delay chain 106 includes series-coupled delay stages (not shown), each delay stage including a driver device (not shown) coupled between an input node and an output node of the delay stage, and a corresponding instance of a CDAC 104, wherein each instance of the CDAC 104 includes a corresponding instance of a capacitor cell array 102.

[0023] In some embodiments, each of macro regions 101A-101C includes one or more active devices, passive devices, etc. Examples of active devices or active elements include, but are not limited to, transistors, diodes, etc. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, etc.

[0024] In some embodiments, macroregion 101A comprises instances of one or more functional unit regions (not shown), and each of macroregions 101B and 101C also correspondingly comprises instances of one or more functional unit regions. In such embodiments, macroregion 101A is configured to provide / perform a given computational function, which comprises relatively simple functions provided by one or more instances of the functional unit regions accordingly. In some embodiments, one or more instances of the functional unit regions represent mutually coupled building blocks comprising macroregion 101A.

[0025] In some embodiments, each of macro regions 101A-101C is understood in a context similar to the architectural hierarchy of modular programming, where subroutines / procedures are called by a main program (or other subroutines) to perform a given computational function. In this context, devices 100A-100C accordingly use macro regions 101A-101 to perform one or more given functions. Therefore, in this case, in terms of architectural hierarchy, each of devices 100A-100C is analogous to a main program, and each of macro regions 101A-101C is analogous to a subroutine / procedure. In some embodiments, each of macro regions 101A-101C is a soft macro. In some embodiments, each of macro regions 101A-101C is a hard macro. In some embodiments, each of macro regions 101A-101C is a soft macro described in register-transfer-level (RTL) code numbers. In some embodiments, composition, placement, and routing are not performed on each of macro regions 101A-101C so that the corresponding soft macros can be composed, placed, and routed for various process technology nodes. In some embodiments, each of the macro regions 101A-101C is a hard macro, digitally described in a binary file format (e.g., Graphical Database System II (GDSII) stream format), wherein the binary file format represents, in a hierarchical form, the planar geometry, text labels, other information, etc., of one or more layouts corresponding to each macro region 101A-101C. In some embodiments, the binary file format is referred to as a non-text file format. In some embodiments, composition, placement, and routing have been performed on the macro regions 101 to make the hard macros specific to a particular process technology node.

[0026] In some embodiments, examples of functionality provided by macro regions (e.g., macro regions 101A, 101B, and / or 101C) include memory, power grid, clock tree, adder, phase-locked loop (PLL), delay-locked loop (DLL), flip-flop, shift register, analog-to-digital converter (ADC), digital-to-analog converter (DAC), interface, high-level Boolean logic, etc. Example memory includes static random-access memory (SRAM), dynamic RAM (DRAM), resistive RAM, magnetoresistive RAM (MRAM), read-only memory (ROM), etc. Examples of flip-flops are scan-insertion D flip-flops (SDFQ), etc. In some embodiments, examples of functionality provided by functional unit areas include inverters, tri-state inverters, buffers, latches, multiplexers (MUX), drivers, latches, delays, half-adders, full adders, compressors, low-level Boolean logic, etc. Examples of low-level Boolean logic include AND, OR, NAND, NOR, XOR, INV, AND OR Invert (AOI), OR AND Invert (OAI), etc.

[0027] Each of the macroregions 101A-101C includes a corresponding segment in one or more metallization layers. The figures in this disclosure assume a Cartesian coordinate system (unless otherwise stated), where the first, second, and third directions are, for example, parallel to the X, Y, and Z axes respectively. In some embodiments, the first to third directions correspond to directions other than the X, Y, and Z axes. In some embodiments, the major and minor axes of the segment extend respectively in the first and second directions in one of the even-numbered metallization layers; in such embodiments, the major and minor axes of the segment extend respectively in the second and first directions in the odd-numbered metallization layers. In some embodiments, the boundaries of the cell regions are described according to the first and second directions.

[0028] In some embodiments, each of the macro regions 101A-101C includes one or more portions corresponding to a transistor element layer (not shown) having circuit elements, such as transistors, formed thereon in front-end process (FEOL) fabrication. Correspondingly, in back-end process (BEOL) fabrication, in each macro region 101A-101C above and / or below the active region (AR) layer (not shown), various metal layers (see...) Figures 4A-4B ) and one or more corresponding interconnect layers in the stacked architecture above and / or below the AR layer (see Figures 4A-4B Interleaved. BEOL manufactures power networks and / or wiring for the circuitry of devices 100A-100C and the corresponding macro regions 101A-101C therein.

[0029] Figure 2 This is a block diagram of array 202 according to some embodiments.

[0030] Array 202 is an array of capacitor cell regions (capacitor cells) 208. Capacitor cell array 202 is... Figures 1A-1C An example of a capacitor cell array 102, etc.

[0031] Each instance of capacitor cell 208 includes the same number of one or more metallization layers. On a per-layer basis, each capacitor cell 208 has a substantially identical set of physically uniform conductive segments, wherein each set of conductive segments has a substantially uniform physical arrangement. Each conductive segment is selectively configured to couple to either a first reference voltage or a second reference voltage, wherein the first and second reference voltages are different. When the conductive segments of a pair of adjacent conductive segments are coupled corresponding to the first and second reference voltages, a capacitance is induced between the pair of conductive segments. In each instance of capacitor cell 208, for a given metallization layer, while the physical arrangement of the conductive segment groups is substantially uniform, the electrical arrangement of the conductive segment groups is not necessarily uniform. Instead, in order to adjust the total capacitance of array 202, in some embodiments, one or more instances of capacitor cell 208 have different cell capacitances.

[0032] For example, consider an instance of array 202, where all capacitor cells 208, except for one instance of capacitor cell 208, are first capacitor cells configured with the maximum cell capacitance, and a single instance of capacitor cell 208 is a second capacitor cell configured with a capacitance less than the maximum cell capacitance (e.g., half the maximum cell capacitance). Continuing this example, for a given metallization layer, the electrical arrangement of the conductive segment groups in each first capacitor cell (e.g., Figure 3A 308(1), Figure 3C 308(3) Figure 3E 308(5) and Figure 3G Compared to 308(7)), the electrical arrangement of the conductive segment group in the second capacitor unit (e.g., Figure 3B 308(2), Figure 3D 308(4), Figure 3F 308(6) and Figure 3H The 308(8)) has a different electrical arrangement.

[0033] Figures 3A-3H This is a layout diagram of the corresponding capacitor units 308(1)-308(8) according to some embodiments.

[0034] In some embodiments, Figures 3A-3H The capacitor cell region is a type of capacitor called a metal oxide metal (MOM) capacitor. In some embodiments, Figures 3A-3H The capacitor cell region is a type of capacitor other than a MOM capacitor. In some embodiments, the maximum capacitance (kp_1) of the first manufactured capacitor cell region based on the maximum capacitance versions of the capacitor cell regions disclosed herein (e.g., 308(1), 308(3), 308(5), and 308(7)) is in the range of approximately one femtofarad (1fF), such that (1×10-15 )≤ kp_1 <(1×10 -14 In some embodiments, the maximum capacitance kp_2 of the second manufactured capacitor cell region based on the maximum capacitance versions of the capacitor cell regions disclosed herein (e.g., 308(1), 308(3), 308(5), and 308(7)) is in a second range of approximately one-tenth of a femtofarad (0.1 fF), such that (1 × 10⁻⁶) -16 )≤ kp_2 <(1×10 -15 In some embodiments, the maximum capacitance kp_4 of the capacitor cell region manufactured based on the maximum capacitance versions of the capacitor cell region disclosed herein (e.g., 308(1), 308(3), 308(5), and 308(7)) is a fourth range less than 0.1fF, such that kp_4 < (1 × 10⁻⁶)fF. -16 ).

[0035] In a layout diagram, the structure of the corresponding semiconductor device is represented by a pattern (also called a shape). To simplify the discussion, Figures 3A-3H The components in the layout diagram will be referred to as structures rather than patterns. For example, Figure 1A The shape of an instance of a through-hole structure (through hole) is referred to as the through hole itself, not the through hole shape.

[0036] A layout diagram is a top view. The shapes in a layout diagram are two-dimensional relative to the X and Y axes, while the devices represented are three-dimensional. Therefore, shapes in such layout diagrams are described as having a width / length relative to the X-axis and a height relative to the Y-axis. Relative to the Z-axis, for example, the bottom / back side of a first component shown in the layout diagram is stacked on top / front of a second component device shown in the layout diagram, or the top / front back side of the first component is stacked below the bottom / back side of the second component.

[0037] Generally, layout diagrams use a Cartesian coordinate system, showing dimensions parallel to the X or Y axis. Typically, semiconductor devices are organized as layer stacks relative to the Z-axis, with corresponding structures placed within them; that is, the corresponding structures belong to them. Each shape in the layout diagram more specifically represents an component in the corresponding layer of the corresponding device. Furthermore, layout diagrams typically represent the relative depth of a shape and its corresponding layer, i.e., its position along the Z-axis, by superimposing a second shape on top of a first shape such that the second shape at least partially overlaps the first shape. For simplicity, a second stacking order along the Z-axis (i.e., a different / twisted stacking order) is used in layout diagrams to represent some structures in the device that have a first stacking order along the Z-axis.

[0038] Layout diagrams vary in the amount of detail they represent. In some cases, selected layers of a layout diagram are combined / abstracted into a single layer, for example, for simplicity. Alternatively, and / or additionally, in some cases, not all layers of the corresponding device are represented; that is, for example, selected layers of the layout diagram are omitted for simplicity. Alternatively, and / or additionally, in some cases, not all elements of a given depicted layer of the corresponding device are represented; that is, for example, selected elements of a given depicted layer of the layout diagram are omitted for simplicity. The layout diagrams disclosed herein are examples in which selected layers and / or selected elements of a given layer are omitted.

[0039] According to the numbering convention of the corresponding process technology nodes in the manufacturing device, on the front side of the device, the initial metallization layer, i.e., the metallization layer closest to the active region (AR) layer, is metallization layer zero (MET0) or metallization layer one (MET1). Correspondingly, the initial interconnect layer, i.e., the nearest interconnect layer on the initial metallization layer, is interconnect layer zero (VIA0) or interconnect layer one (VIA1). In such an embodiment, also depending on the numbering convention of the corresponding process technology nodes, on the back side of the device (not shown), the initial buried metallization layer, i.e., the buried metallization layer closest to the AR layer, is buried metallization layer zero (BMET0) or buried metallization layer one (BMET1). Correspondingly, the initial interconnect layer, i.e., the nearest buried interconnect layer below the initial buried metallization layer, is interconnect layer zero (VIA0) or interconnect layer one (VIA1).

[0040] Generally, for the illustrations disclosed herein (unless otherwise stated), the following naming convention is used for the front side of the device: The initial metallization layer is assumed to be MET0; the initial interconnect layer is assumed to be VIA0; the first next metallization layer is assumed to be MET1; the next interconnect layer is assumed to be VIA1; and the second next metallization layer is assumed to be MET2. Metallized segments in the MET0 layer are called M0 segments. Via structures in layer VIA0 are called V0 structures. Metallized segments in the MET1 layer are called M1 segments. Via structures in layer VIA1 are called V1 structures. Metallized segments in the MET2 layer are called M2 segments. In some embodiments, within a given metallization layer, the width of segments in a given metallization layer has a uniform width, where the width is defined along the minor axis of the segment. In some embodiments, the segment width increases with the number of metallization layers, i.e., segments in layer MET1 are wider than segments in layer MET0, segments in layer MET2 are wider than segments in layer MET1, and so on.

[0041] Generally, for the illustrations disclosed herein (unless otherwise stated), the following nomenclature is used for the back side of the device: The initial buried metallization layer is assumed to be BMET0; the initial buried interconnect layer is assumed to be BVIA0; the first next buried metallization layer is assumed to be BMET1; the next buried interconnect layer is assumed to be BVIA1; and the second next buried metallization layer is assumed to be BMET2. The metallized sections in layer BMET0 are called buried M0 (BM0) sections. The via structures in layer BVIA0 are called BV0 structures. The metallized sections in layer BMET1 are called buried M1 (BM1) sections. The via structures in layer BVIA1 are called BV1 structures. The metallized sections in layer BMET2 are called buried M2 (BM2) sections. In some embodiments, in a given buried metallization layer, the width of the sections in the given buried metallization layer has a uniform width. In some embodiments, the segment width increases with the increase of the number of metallization layers, that is, the segment in layer BMET1 is wider than the segment in layer BMET0, the segment in layer BMET2 is wider than the segment in layer BMET1, and so on.

[0042] More specifically, Figures 3A-3B This is a layout diagram of the corresponding capacitor units 308(1)-308(2) according to some embodiments.

[0043] exist Figure 3A In the middle, capacitor cell area (capacitor cell) 308(1) is Figure 2 An example of one or more capacitor cells 208. Figure 3B In the middle, capacitor unit 308(2) is Figure 2 An example of one or more capacitor cells 208 in the example.

[0044] exist Figures 3A-3B In the first metallization (M_1st) layer, each capacitor cell 308(1) and 308(2) includes an M_1st segment 310(1)-310(5) extending along a first direction (e.g., parallel to the Y-axis) and having a pitch p_M_1st(1). In some embodiments, the M_1st layer is layer MET0, layer MET1, layer MET2, layer MET3, or layer MET4. In some embodiments, the M_1st layer is layer BMET0, layer BMET1, layer BMEM2, layer BMET3, or layer BMET4. In some embodiments, the M_1st layer is a layer other than one of layers MET0-MET4 or BMET0-BMET4.

[0045] Each of the M_1st segments 310(1)-310(5) has a uniform width relative to a second direction perpendicular to the first direction (e.g., parallel to the X-axis), i.e., essentially has a first width W1. Due to the pitch and uniform width, adjacent segments in the M_1st segments 310(1)-310(5) are spaced apart from each other by a uniform distance, i.e., essentially spaced apart by a distance S1.

[0046] More generally, capacitor units 308(1) and 308(2) comprise N M_1st segments, where N is a positive integer, 3 ≤ N, and ... Figures 3A-3B In this example, N is assumed to be N=5. In some embodiments, N is a positive integer equal to or greater than 3 but not equal to 5.

[0047] Each of the M_1st segments 310(1)-310(5) has a length L1 relative to the Y-axis. Capacitor cell 308(1) has cell boundary 314(1).

[0048] exist Figure 3A Each capacitor cell 308(1) and Figure 3B In 308(2), each of the M_1st segments 310(1)-310(5) has an overlap relative to the adjacent corresponding segment in the M_1st segment, and each overlap has an overlap length D_ovrlp_1 relative to the adjacent corresponding segment in the M_1st segments 310(1)-310(5).

[0049] exist Figures 3A-3B In each of the M_1st segments 310(1)-310(5), the overlapping portion substantially spans the entire M_1st segment, such that the overlapping length is substantially the same as the total length (=≈), i.e., D_ovrlp_1=≈L1. In some embodiments, the overlapping portion spans a portion of the length (e.g., Figure 3G-Figure 3H Capacitor cell 308(1) has an overlapping boundary 315(1). Since D_ovrlp_1=≈L1, the overlapping boundary 315(1) is the same as the cell boundary 314(1).

[0050] During manufacturing, for example during BEOL manufacturing, each of the M_1st segments 310(1)-310(5) is selectively configured to be coupled to a first voltage V_Net_A or a second voltage V_Net_B, wherein V_Net_A is different from V_Net_B, i.e., V_Net_A ≠ V_Net_B. In some embodiments, V_Net_A is VDD and V_Net_B is VSS. In some embodiments, V_Net_A and V_Net_B are voltages that are respectively different from VDD and VSS.

[0051] In some embodiments, the arrangement of coupling M_1st segments 310(1)-310(5) to V_Net_A or V_Net_B is referred to as configuration planning. (Review) Figure 3A Assuming N=5, there are 2 N = 2 5 = 32 possible combinations, of which the M_1st segment 310(1)-310(5) corresponds to being coupled to V_Net_A or V_Net_B (see Figure 5C In other words, there are 32 configuration plans for the M_1st segment 310(1)-310(5) of capacitor unit 308(1).

[0052] For a pair of adjacent segments in M_1st segments 310(1)-310(5), where the pair of segments are correspondingly coupled to V_Net_A and V_Net_B, a capacitance is induced between the overlapping portions of the pair of conductive segments. In some embodiments, when a pair of adjacent segments in M_1st segments 310(1)-310(5) are correspondingly coupled to V_Net_A and V_Net_B, the pair is referred to as an M_1st capacitor pair (CPR), and the capacitance of the M_1st CPR is referred to as the M_1st core capacitance cap_krnl_1. The total capacitance of the capacitor cell is the product of cap_krnl_1 and the number of capacitor pairs in the capacitor cell configuration plan.

[0053] For a pair of adjacent segments in M_1st segments 310(1)-310(5), where both segments of the pair are coupled to V_Net_A, or both segments of the pair are coupled to V_Net_B, there is essentially no induced capacitance between the overlapping portions of the pair of conductive segments. In some embodiments, when both segments of the pair are coupled to V_Net_A or both segments of the pair are coupled to V_Net_B, the pair is referred to as an M_1st pseudo-pair.

[0054] For a given capacitor cell, such as capacitor cell 308(1), having N M_1st segments and no segments in another layer, a configuration scheme with alternating V_Net_A and V_Net_B produces the maximum number of CPRs for the given capacitor cell. For a given capacitor cell, there are two configuration schemes that can achieve the maximum number of CPRs, i.e., the maximum capacitance. In some embodiments, the two configuration schemes that achieve the maximum number of CPRs are referred to as the first maximum CPR (max-CPR) configuration scheme and the second maximum CPR configuration scheme. The first maximum CPR configuration scheme has an odd number of M_1st segments coupled to V_Net_A and an even number of M_1st segments coupled to V_Net_B (see...). Figure 5C(Line 13). The second maximum CPR configuration plan is the opposite of the first maximum CPR configuration plan. The second maximum CPR configuration plan has an odd-numbered M_1st section coupled to V_Net_B and an even-numbered M_1st section coupled to V_Net_A (see line 13). Figure 5C (Line 26).

[0055] For a capacitor cell with N M_1st segments and no segments in another layer, the maximum number of CPRs, q_max, is N-1, such that q_max = (N-1). (Review) Figure 3A Assuming N=5, each of the two maximum CPR configuration plans of capacitor cell 308(1) achieves four CPRs. Figure 3A It is also assumed that the first maximum CPR configuration plan of capacitor cell 308(1) is proposed, in which the odd M_1st segment is coupled to V_Net_A and the even M_1st segment is coupled to V_Net_B, thereby producing CPR 312(1)-312(4) (see Figure 5C (Line 13), meaning a total of four CPRs. More specifically, in Figure 3A In this configuration, M_1st segments 310(1), 310(3), and 310(5) are coupled to V_Net_A, and M_1sl segments 310(2) and 310(4) are coupled to V_Net_B. In some embodiments, capacitor cell 308 has a second maximum CPR configuration plan (see [link to configuration plan]). Figure 5C (Line 26).

[0056] exist Figure 3A In the middle: CPR 312(1) consists of M_1st segments 310(1) and 310(2); CPR 312(2) consists of M_1st segments 310(2) and 310(3); CPR 312(3) consists of M_1st segments 310(3) and 310(4); CPR 312(4) consists of M_1st segments 310(4) and 310(5).

[0057] The M_1st core capacitance cap_krnl_1 is proportional to the quotient of the M_1st overlap length divided by the M_1st separation distance. Figure 3A In the capacitor unit 308(1), cap_krnl_1 is .review Figure 3A In the context of D_ovrlp_1=L1, the cap_krnl_1 of capacitor unit 308(1) can be restated as: .

[0058] about Figure 3A, in some embodiments, a capacitor unit having N M_1st segments and no segments in another layer is referred to as a single-layer capacitor unit. Capacitor unit 308(1) is an example of a single-layer capacitor unit. In some embodiments, a single-layer capacitor unit is called a single-layer capacitor unit. The overall capacitance 1L_cap_whol of a given single-layer capacitor unit is the same as the capacitance cap_layr_M_1st of the M_1st layer. The capacitance of the M_1st layer is the product of cap_krnl_1 multiplied by the number of CPRs in the configuration plan. The maximum value cap_max_M_1st of cap_layer_M_1st for a given capacitor unit is the product of cap_krnl_1 multiplied by the maximum number q_max of CPRs in the maximum CPR configuration plan. Recall Figure 3A Assume N=5, and q_max is N-1, such that q_max=(N-1)=4. The capacitance cap_308_1 of capacitor unit 308(1) is equal to cap_max_M_1st, such that cap_308_1 of capacitor unit 308(1) = cap_max_M_1st = 4×cap_krnl_1.

[0059] Regarding Figure 3A , recalling the 32 configuration plans for a capacitor unit with N=5 M_1st segments, such as capacitor unit 308(1), the following can be understood: Leaving aside the two configuration plans that achieve the maximum CPR, each of the remaining 30 configuration plans for the N=5 type capacitor unit (see Figure 5C ) achieves a number of CPRs, q_cell, that is within the range of 0 ≤ (q_cell) ≤ (N-2); the remaining 30 configuration plans produce an overall capacitance of the N=5 type capacitor unit that is a fraction of cap_max_M_1st; in some embodiments, the capacitance that is a fraction of cap_max_M_1st is referred to as fractional capacitance cap_frac; in some embodiments, the remaining 30 configuration plans for the N=5 type capacitor unit are referred to as non-maximum CPR configuration plans; and the fractional capacitance cap_frac of the non-maximum CPR configuration plans for the N=5 type capacitor unit falls within the range of 0 ≤ (cap_frac) ≤ (N-2)×cap_krnl_1, such that cap_frac < cap_max_M_1st. In some embodiments, a capacitor unit that has one of the two maximum CPR configuration plans and thus has a maximum capacitance (max-cap) value, such as capacitor unit 308(1), is referred to as a unit capacitor unit, because each of the remaining 30 configuration plans for the N=5 type capacitor unit achieves an overall capacitance that is a fraction of cap_max_M_1st.

[0060] Regarding Figure 3AIn some embodiments, the top and bottom boundaries of the manufactured capacitor cell (e.g., corresponding to capacitor cell 308(1)) can be identified as follows: the first ends of the M_1st segments 310(1)-310(5) are substantially aligned and define a first reference line substantially parallel to and at least close to (if substantially collinear) the first boundary of the capacitor cell; the second ends of the M_1st segments 310(1)-310(5) are substantially aligned and define a second reference line substantially parallel to and at least close to (if not substantially collinear) the second boundary of the capacitor cell. In some embodiments, the first and second ends of the M_1st segments (e.g., 310(1)-310(5)) are formed as part of a metal cutting process (e.g., blocks 732-734 discussed below).

[0061] In some embodiments, a first strip (e.g., see block 736) is etched (e.g., block 738) to form the M_1st segment, replacing the cut / etched portion of the first strip with a replacement dielectric (RD) structure. In some embodiments, the RD structure is formed of a first dielectric material that is different from the second dielectric material used to fill the gap space. In some embodiments, the first dielectric material is the same as the second dielectric material.

[0062] about Figure 3A In some embodiments, the context for understanding the left and right boundaries of the manufactured capacitor cell (e.g., corresponding to capacitor cell 308(1)) is as follows. In an array of capacitor cells, such as capacitor cell 308(1), having N M_1st segments and no segments in another layer, additional space in the form of a first gap is provided between adjacent first and second capacitor cells. More specifically, each first gap is disposed between M_1st segments in a first capacitor cell that are adjacent to M_1st segments in a second capacitor cell (adjacent boundary M_1st segments represent M_1st boundary pairs). Where the M_1st segments of an M_1st boundary pair are correspondingly coupled to V_Net_A and V_Net_B (and vice versa), the first gap between them ensures that there is substantially no capacitance in the M_1st boundary pair, i.e., at most negligible capacitance. Figure 3AIn the diagram, examples of first gaps are illustrated using dummy M_1st segments (M_1st dummy) 311(1) and 311(2). In some embodiments, each of the M_1st dummy 311(1) and 311(2) represents a dielectric structure (e.g., an example of the RD structure described above) that would otherwise be present in the M_1st segment. In such an array, each first gap has a size G1 (not shown), where G1 ≈ 2 × S1 + S2. In cases similar to adjacent first and second capacitor cells, although the first capacitor cell is replaced by the first circuit, a first gap is still provided between the boundary M_1st segment in the second capacitor cell and the nearest M_1st segment in the first circuit to ensure that there is substantially no induced capacitance between the boundary M_1st in the second cell and the nearest M_1st segment in the first circuit. In other words, the first gap is positioned near each boundary M_1st segment in the capacitor cell (e.g., 308(1)) to prevent the boundary M_1st segment from becoming part of an unintended capacitance pair.

[0063] about Figure 3A In some embodiments, the left and right boundaries of the manufactured capacitor cells (e.g., corresponding to capacitor cell 308(1)) can be identified as follows: M_1st segment groups (e.g., having M_1st segment groups corresponding to 310(1)-310(4)) are identified relative to a second direction (e.g., parallel to the X-axis), wherein each group of M_1st segments is separated by a first distance (e.g., S1); for each group, gaps (e.g., G1) corresponding to the left and right sides of the group are identified relative to the second direction (e.g., parallel to the X-axis); for each group, a first reference line is identified, wherein the first reference line extends in a first direction (e.g., parallel to the Y-axis) to the left of the leftmost M_1st segment (e.g., corresponding to 310(1)). And adjacent to it, and close to the left edge of the leftmost M-1st segment, but not exceeding a distance D1 (not shown) from the left edge of the leftmost M_1st segment, such that D1≈S1 / 2; For each group, identify a second reference line, wherein the second reference line extends in the first direction (e.g., parallel to the Y-axis), is located to the right of and adjacent to the rightmost M_1st segment (e.g., corresponding to 310(5)), and close to the right edge of the rightmost M_1st segment, but not exceeding a distance D1 from the right edge of the rightmost M_1st segment; Each group is considered as a manufactured capacitor cell (e.g., corresponding to 308(1)); The left boundary of the manufactured capacitor cell is considered as the first reference line; And the right boundary of the manufactured capacitor cell is considered as the first reference line.

[0064] In some embodiments, M_1st dummy structures 311(1) and 311(2) are formed of a dielectric material (e.g., an oxide) different from the gap material (not shown) filling the gap space around the M_1st segment; for example, the gap material is another dielectric material. In some embodiments, M_1st dummy structures 311(1) and 311(2) are formed of a nitride material, while the gap material is an oxide, or vice versa. In some embodiments, M_1st dummy structures 311(1) and 311(2) are formed of the same material as the gap material, such that M_1st dummy structures 311(1) and 311(2) are more easily identifiable (or identifiable) in the corresponding layout diagram than in the manufactured capacitor cell. In some embodiments, M_1st dummy structures 311(1) and 311(2) are referred to as cut M_1st (CM_1st) structures.

[0065] In some embodiments, each of the M_1st dummy 311(1)-311(2) is based on a gate segment serving as a precursor. In some embodiments, the M_1st dummy, such as 311(1)-311(2), is formed by the following steps: first forming an M_1st segment, sacrificing / removing (e.g., etching) the M_1st segment to form a trench, (optionally) removing a portion of the substrate previously located below, above, or around the M_1st segment to deepen the trench, and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrically isolated structure (i.e., the M_1st dummy) are similar to the dimensions of the sacrificed M_1st segment. In some embodiments, the M_1st dummy is a dielectric component comprising one or more dielectric materials (e.g., oxides, nitrides, oxynitrides, or other suitable materials) and used as an isolation component.

[0066] although Figure 3A Assuming the first maximum CPR configuration plan for an N=5 type capacitor cell, i.e. for capacitor cell 308(1), but Figure 3B The image shows an example of one of the 30 non-maximum CPR configuration plans for an N=5 type capacitor cell.

[0067] exist Figure 3B In the middle, capacitor unit 308(2) is similar to Figure 3A The capacitor unit 308(1). For the sake of brevity, the discussion will focus on the differences between capacitor unit 308(2) and capacitor unit 308(1), rather than their similarities. For the sake of simplicity, the M_1st dummy 311(1)-311(2) of capacitor unit 308(1) are omitted for capacitor unit 308(2).

[0068] exist Figure 3B In the middle, the M_1st section 310(3) is coupled to V_Net_B, instead of like Figure 3AIt is coupled to V_Net_A in that way. Therefore, capacitor cell 308(2) has a total of two CPRs, namely 312(1) and 312(4) (see Figure 5C (line 12), instead of Figure 3A The four CPRs are CPRs 312(1)-312(4). The capacitance cap_308_2 of capacitor cell 308(2) is half the capacitance of capacitor cell 304(1), therefore cap_308_2 = (cap_308_1) / 2. More generally, at half the capacitance of capacitor cell 308(1), the capacitance of capacitor cell 308(2) is an example of a non-maximum capacitance value (non-maximum value) of the capacitor.

[0069] In some embodiments, the configuration plan of capacitor cell 308(2) is referred to as a semi-maximum CPR configuration plan, while the configuration plan of capacitor cell 308(1) is referred to as a maximum CPR configuration plan. In some embodiments, capacitor cell 308(2) is referred to as a half cell, while capacitor cell 308(1) is referred to as a unit cell. More generally, a semi-maximum CPR configuration plan is an example of a non-maximum CPR configuration plan.

[0070] Figure 3A Capacitor unit 308(1) and Figure 3B Capacitor cell 304(2) represents two of the 32 possible configuration plans for an N=5 type capacitor cell. All 32 configuration plans for an N=5 type capacitor cell are as follows: Figure 5C As shown (discussed below).

[0071] In some embodiments, based on a layout diagram (e.g.) Figures 3A-3BIn a semiconductor device, a capacitor cell is referred to as a manufactured capacitor cell. According to another method for manufacturing an array of capacitor cells, where each capacitor cell can have at most N M_1st segments for the M_1st layer and no segments in another layer, the capacitor cells have a physical arrangement of correspondingly different conductive segments to achieve different cell capacitances. That is, according to this other method, the capacitor cells have a substantially non-uniform physical arrangement. Generally, resolution enhancement techniques (RET) and / or optical proximity correction (OPC) do not uniformly alter the cell regions. In other words, generally, RET and / or OPC tend to make cell region-specific changes, i.e., tend to make non-uniform changes to the cell regions. Furthermore, manufacturing tolerances inevitably introduce variations between the capacitances of the manufactured capacitor cells. Due to (A) the non-uniform correction introduced by RET and / or OPC and (B) manufacturing tolerances, the non-uniformity of the capacitor cells according to this other method is aggravated / amplified in the corresponding manufactured capacitor cells, where the effects of (A) and / or (B) lead to aggravated / amplified variations between the capacitances of the manufactured capacitor cells. In other words, according to another method, (A) and / or (B) worsens / amplifies the capacitance mismatch of the manufactured capacitor cells. According to another method, this mismatch reduces the reliability and / or performance and / or increases power consumption of the manufactured capacitor cells, etc. In contrast, at least some of this embodiment produces a capacitor cell array composed of uniformly counted M_1st segment capacitor cells, wherein, compared to the other method, uniformity reduces the variation in manufactured capacitor cells caused by (i) RET and / or OPC and (ii) manufacturing tolerances, i.e., uniformity reduces mismatch between manufactured capacitor cells compared to other methods. Compared to other methods, the uniform M_1st segment capacitor cell array according to at least some of this embodiment improves the reliability and / or performance and / or power consumption of the manufactured capacitor cells, etc.

[0072] Instead of continuing the discussion Figures 3C-3D Let's discuss it directly. Figure 5C Then we'll discuss it. Figures 3C-3D .

[0073] Figure 5C This is a configuration planning table of capacitor cells having B=5 M-1 segments according to some embodiments.

[0074] about Figure 5C An example of capacitor unit B = 5 M_1st segments is... Figure 3A The capacitor unit 308(1), etc. It should be noted that... Figure 5C The table assumes layer M_1st as the background. In some embodiments, Figure 5C The table assumes that layer M_2nd is the background. In some embodiments, Figure 5CThe table assumes that the metallization layer other than the M_1st or M_2nd layer is the background.

[0075] Figure 5C The table includes the following: the first column is labeled "Row #"; the second column is labeled "M_1st Segment Configuration Plan"; the third column is labeled "#CPR"; the fourth column is labeled "Gray Code Bit, N=5"; and the fifth column is labeled "Unit Capacitor Description".

[0076] exist Figure 5C In the table, the entries in the first column represent the corresponding numbers of the rows in the table.

[0077] Regarding the second column, each entry is a bit sequence representing the corresponding one of the 32 configuration plans for an N=5 type capacitor cell. That is, for each entry in the second column, the position of the bit in the sequence correspondingly represents the M_1st segment 310(1)-310(5). Each bit in the sequence is a binary number. For each bit in the sequence, if the corresponding one of the M_1st segments 310(1)-310(5) is coupled to V_Net_A, the value of that bit is zero; or, if the corresponding one of the M_1st segments 310(1)-310(5) is coupled to V_Net_B, the value is one.

[0078] Figure 5C The third column in the table represents the number of CPRs generated by the corresponding configuration plans in the second column.

[0079] The fourth column lists the Gray code for the corresponding configuration plan. For Figure 5C In the given row of the table, note that the sequence of 1s and / or 0s in the configuration plan of the second column is the same as the bit sequence of the Gray code. Figure 5C The 13th row of the table corresponds to Figure 3A Capacitor unit 308(1). Figure 5C The 12th row of the table corresponds to Figure 3B Capacitor unit 308(2).

[0080] Figure 5C The fifth column in the table describes the capacitors for the corresponding configuration plan. Figure 5C Each row in rows 13 and 26 of the table represents the maximum CPR configuration plan that achieves 4 CPRs, i.e., all four possible CPRs (4 / 4). In some embodiments, similarly, the capacitor cell with the maximum CPR configuration plan achieves the maximum capacitance value and is referred to as the unit capacitor cell. Therefore, the label in the fifth column of each row in rows 13 and 26 is "Unit (4 / 4)".

[0081] about Figure 5CIn the table, rows 4-5, 8-9, 12, 16, 18-19, 23, 27, and 30-31 each represent a half-maximum CPR configuration plan that achieves 2 CPRs, i.e., achieving half (2 / 4) of the four possible CPRs. In some embodiments, similarly, a capacitor cell with a half-maximum CPR configuration plan achieves half of the maximum capacitance value and is referred to as a half cell. Therefore, the label for rows 4-5, 8-9, 12, 16, 18-19, 23, 27, and 30-31 in column 5 is "Half (2 / 4)". The half-maximum CPR configuration plan in row 12 is adjacent to the maximum CPR configuration plan in row 13. That is, the half-maximum CPR configuration plan in row 12 differs from the maximum CPR configuration plan in row 13 by one bit. The half-maximum CPR configuration plan in row 27 is adjacent to the maximum CPR configuration plan in row 26. In other words, the semi-maximum CPR configuration plan in line 27 differs from the maximum CPR configuration plan in line 26 by one bit.

[0082] about Figure 5C In the table, each row in rows 1 and 22 represents a configuration plan that implements CPR-free configuration. In some embodiments, a configuration plan that implements CPR-free configuration is called a pseudo configuration plan, and the corresponding capacitor cell is called a pseudo cell. Therefore, the label for rows 1 and 22 in column 5 is "pseudo (0 / 4)".

[0083] about Figure 5C In the table, rows 2-3, 6, 11, 17, 21, 24, and 32 each represent a configuration plan that implements one CPR, i.e., one of the four possible CPRs (1 / 4). Therefore, the label for rows 2-3, 6, 11, 17, 21, 24, and 32 in column 5 is "(1 / 4)". Rows 7, 10, 14-15, 20, 25, and 28-29 each represent a configuration plan that implements three CPRs, i.e., three of the four possible CPRs (3 / 4). Therefore, the label for rows 7, 10, 14-15, 20, 25, and 28-29 in column 5 is "(3 / 4)".

[0084] Regarding Figure 5C The second column of the table represents 32 configuration plans, which can be represented by different binary codes. Figure 5C Assume the binary code is Gray code. In some embodiments, the binary code is natural binary code. In some embodiments, the binary code is neither Gray code nor natural binary code.

[0085] Natural binary code is an example of a weighted code. In natural binary code, an increment or decrement from the first state to the adjacent second state changes at least one bit, but depending on the digit represented by the first state and the digit represented by the second state, it may change all bits. In contrast, Gray code is an example of an unweighted code. In Gray code, an increment or decrement from the first state to the adjacent second state changes only one bit, regardless of the digit represented by the first state or the quantity represented by the second state.

[0086] exist Figure 5C In the table, each row represents the bit sequence of the configuration plan: it differs from the previous adjacent configuration plan by one bit; and it differs from the next adjacent configuration plan by one bit. For example, the half-maximum CPR configuration plan in row 12 differs from the configuration plan in row 11 by one bit; and it differs from the maximum CPR configuration plan in row 13 by one bit. Furthermore, for example, the configuration plan in row 32 differs from the configuration plan in row 31 by one bit; and it differs from the configuration plan in row 1 by one bit.

[0087] In some embodiments, in a context where each capacitor cell has at most N M_1st segments and no segments in another layer of the capacitor cell array, design guidelines attempt to reduce (if not minimize) the physical differences between adjacent instances of capacitor cells (e.g., 208). According to at least some embodiments of the invention, using uniformly counted M_1st segments for the capacitor cells helps to comply with design guidelines. Furthermore, due to the requirements of the routing and placement phases of IC design, it is beneficial to develop multiple configuration plans for uniformly counted M_1st segments of the capacitor cells in the array. Figure 5C Gray code-based configuration planning further helps to comply with design guidelines.

[0088] In some embodiments, Figure 5C Gray code-based configuration planning facilitates physical design watermarking of manufactured devices, including capacitor cells manufactured based on the example of capacitor cell 308(1), which are based on... Figure 5C The Gray code-based configuration planning is selectively varied. In some embodiments, the physical design watermark is defined using a manufacturing array (e.g., 202) of manufactured capacitor cells, which is based on an instance of capacitor cell 308(1), according to Figure 5C The Gray code-based layout diagram is selectively varied. In some embodiments, the physical design watermark is defined using two or more fabricated capacitor cell arrays (e.g., 202), the latter being based on an instance of capacitor cell 308(1), according to Figure 5C Gray code-based configuration planning can be selectively varied.

[0089] The discussion will now return to... Figures 3C-3D .

[0090] More specifically, Figures 3C-3D is a layout diagram of the corresponding capacitor units 308(3)-308(4) in accordance with some embodiments.

[0091] In Figure 3C , the capacitor unit 308(3) is an example of the one or more capacitor units 208 in Figure 2 . In Figure 3D , the capacitor unit 308(4) is an example of the one or more capacitor units 208 in Figure 2 .

[0092] With regard to Figure 3C , the capacitor unit 308(3) is similar to the capacitor unit 308(1) in Figure 3A . For the sake of brevity, the discussion will focus on the differences between the capacitor unit 308(3) and the capacitor unit 308(1) rather than the similarities.

[0093] The capacitor unit 308(3) not only includes N number of M_1st segments in the M_1st layer as the capacitor unit 308(1) in Figure 3A does, but the capacitor unit 308(3) further includes G number of segments in a second metallization (M_2nd) layer, the M_2nd layer being above or below the M_1st layer, and G being a positive integer. Figure 3C Assume G=3. In some embodiments, G<N. In some embodiments, G is a positive integer but not equal to 3. In contrast, the capacitor unit 308(1) has at most N M_1st segments and no segments in another layer (e.g., the M_2nd layer).

[0094] More specifically, each of the capacitor units 308(3) and 308(4) includes M_2nd segments 316(1)-316(3) extending in a second direction (e.g., parallel to the X-axis) and having a pitch p_M_2nd(1).

[0095] With respect to a first direction (e.g., parallel to the Y-axis), each of the M_2nd segments 316(1)-316(3) has a uniform width, i.e., substantially a second width W2. Due to the pitch and the uniform width, adjacent ones of the M_2nd segments 316(1)-316(3) are spaced apart from each other by a uniform distance, i.e., substantially a distance S2.

[0096] With respect to the X-axis, each of the M_2nd segments 316(1)-316(3) has a length L2. The capacitor unit 308(3) has a unit boundary 314(1).

[0097] In Figure 3CCapacitor unit 308(3) and Figure 3D In each of the capacitor units 308(4), each of the M_2nd segments 316(1)-316(3) has an overlap portion relative to the adjacent corresponding segment in the M_2nd segment, and each overlap portion has a substantially overlap length D_ovrlp_2 relative to the adjacent corresponding segment in the M_2nd segments 316(1)-316(3).

[0098] exist Figures 3C-3D In each of the M_2nd segments 316(1)-316(3), the overlapping portion substantially spans the entire M_2nd segment, such that the overlap length is substantially the same as the total length, D_ovrlp_2 ≈ L2. In some embodiments, the overlapping portion spans a portion of the length (e.g., Figure 3G-Figure 3H Capacitor cell 308(3) has an overlapping boundary 315(1). Since D_ovrlp_1=≈L1 and D_ovrlp_2=≈L2, the overlapping boundary 315(1) is the same as the cell boundary 314(1).

[0099] During manufacturing, for example during BEOL manufacturing, each of the M_2nd segments 316(1)-316(3) is selectively configured to be coupled to one or more corresponding segments of the M_1st segments 310(1)-310(5) via one or more instances of the V_1st via 318. Therefore, each of the M_2nd segments 316(1)-316(3) is selectively configured to be coupled to a first voltage V_Net_A or a second voltage V_Net_B. The first interconnect (V_1st) layer is located between the M_1st layer and the M_2nd layer.

[0100] review Figure 3C Assuming G=3, where the M_2nd segment 316(1)-316(3) is correspondingly coupled to V_Net_A or V_Net_B, there are 2 G = 2 3 = 8 possible combinations (see Figure 5A In other words, there are 8 configuration plans for the M_2nd section 316(1)-316(3) of capacitor unit 308(3).

[0101] In some embodiments, when a pair of adjacent segments in M_2nd segments 316(1)-316(3) are correspondingly coupled to V_Net_A and V_Net_B, the pair is called a capacitor pair (CPR), and the capacitance of the M_2nd CPR is called the M_2nd core capacitor cap_krnl_2.

[0102] The overall capacitance of capacitor unit 308(3) is the sum of the capacitance of M_1st CPR (as described above) and the capacitance of M_2nd CPR. The capacitance of M_2nd CPR is the product of cap_krnl_2 and the number of M_2nd CPRs in the M_2nd segment configuration plan.

[0103] For a pair of adjacent segments in M_2nd segments 316(1)-316(3), where both segments of the pair are coupled to V_Net_A, or both segments of the pair are coupled to V_Net_B, there is essentially no induced capacitance between the overlapping portions of the pair of conductive segments. In some embodiments, when both segments of the M_2nd pair are coupled to V_Net_A or both segments of the pair are coupled to V_Net_B, the pair is referred to as an M_2nd pseudo-pair.

[0104] about Figure 3C In addition to CPR 312(1)-312(4), capacitor unit 308(3) also includes CPR 320(1) and 320(2), for a total of six CPRs. CPR 320(1) consists of M_2nd segments 316(1) and 316(2); CPR 320(2) consists of M_2nd segments 316(2) and 316(3).

[0105] The M_1st core capacitor cap_krnl_1 of capacitor unit 308(3) is the same as that of capacitor unit 308(1). The M_2nd core capacitor cap_krnl_2 is proportional to the quotient of the M_2nd overlap length divided by the M_2nd separation distance. Figure 3C In the capacitor unit 308(3), cap_krnl_2 is .review Figure 3C In the context of D_ovrlp_2=L2, the cap_krnl_2 of capacitor unit 308(3) can be restated as: .

[0106] In some embodiments, a capacitor cell having N M_1st segments and G M_2nd segments is called a double-layer capacitor cell. Capacitor cell 308(3) is an example of a double-layer capacitor cell. More generally, a capacitor cell having two or more metallized segments is called a multilayer capacitor cell.

[0107] Capacitor cell 308(3) is also an example of a double-layer capacitor cell, wherein all instances of V_1st via 318 are at least substantially within cell boundary 314(1), but also within overlap boundary 315(1). In some embodiments, all instances of V_1st via 318 are at least substantially within cell boundary 314(1), although one or more instances of V_1st via 318 are substantially outside overlap boundary 315(1) (see...). Figure 3G-Figure 3H ).

[0108] The total capacitance 2L_cap_whol of a given double-layer capacitor cell is the sum of the first-layer capacitance cap_layr_M_1st and the second-layer capacitance cap_layr_M_2nd. Capacitor cap_layr_M_1st is as described above. Capacitor cap_layr_M_2nd is the product of cap_krnl_2 and the number of CPRs in the M_2nd configuration plan.

[0109] The maximum value of cap_max_M_2nd for a given capacitor cell is cap_krnl_2 multiplied by the maximum number of CPRs q_max_M_2nd in the maximum CPR configuration plan. (Review) Figure 3C Assume G=3, q_max_M_2nd is G-1, such that q_max_M_2nd=(G-1)=2. For capacitor unit 308(3) as a whole, q_max_308(3)=q_max_M_1st+q_max_M_2nd=(4+2)=6. The capacitance cap_308_3 of capacitor unit 308(3) as a whole is the sum of cap_max_M_1st and cap_max_M_2nd, such that cap_308_3=cap_max_M_1st+cap_max_M_2nd=4×cap_krnl_1+2×cap_krnl_2.

[0110] For a given capacitor cell, such as capacitor cell 308(3), having N M_1st segments and G M_2nd segments, the staggered configuration of V_Net_A and V_Net_B in the M_1st and M_2nd layers generates the maximum number of M_1stCPRs and M_2ndCPRs for that given capacitor cell. For a single-layer configuration of capacitor cell 308(3): the M_1st layer has two configurations with maximum M_1st CPRs; the M_2nd layer has two configurations with maximum M_2nd CPRs. Therefore, for a two-layer configuration of capacitor cells including M_1st and M_2nd segments, such as capacitor cell 308(3), there are 2 2 =4 maximum CPR configuration plans.

[0111] For the single-layer configuration planning of capacitor cells with N=5 M_1st segments and G=3 M_2nd segments, for example, capacitor cell 308(3): the M_1st layer has 2 N =2 5 =32 possible configuration plans; M_2nd layer has 2 G =2 3 =8 possible configuration plans.

[0112] For the two-layer configuration planning of capacitor cells with N=5 M_1st segments and G=3 M_2nd segments, for example, capacitor cell 308(3), there are 2 (N+G) =2 (5+3) =256 possible two-layer configuration plans.

[0113] Regarding a double-layer capacitor cell with N=5 M_1st segments and G=3 M_2nd segments, such as capacitor cell 308(3), the following should be understood: aside from the four configuration plans that achieve the maximum CPR, the number of CPRs achieved by each of the remaining 252 configuration plans is less than the maximum CPR; the remaining 252 configuration plans generate the overall capacitance of the double-layer capacitor cell, which is a fraction of the double-layer capacitor cell cap_max, and in some embodiments, the remaining 252 configuration plans of the double-layer capacitor cell are referred to as non-maximum CPR configuration plans.

[0114] In some embodiments, a double-layer capacitor cell having one of the four maximum CPR configuration plans and thus having the maximum capacitance value, such as capacitor cell 308(3), is referred to as a double-layer capacitor cell because each of the remaining 252 configuration plans of the double-layer capacitor cell achieves a fraction of the overall capacitance of cap_max.

[0115] although Figure 3C Assuming one of the four maximum CPR configuration schemes for a double-layer capacitor cell with N=5 M_1st segments and G=3 M_2nd segments, i.e. for capacitor cell 308(3), Figure 3D An example of one of the 252 non-maximum CPR configuration plans for this capacitor cell is shown in the figure.

[0116] exist Figure 3D In the middle, capacitor unit 308(4) is similar to Figure 3C The capacitor unit 308(3). For the sake of brevity, the discussion will focus on the differences between capacitor unit 308(4) and capacitor unit 308(3), rather than their similarities.

[0117] exist Figure 3DIn the M_1st section 310(3) and M_2nd section 316(2), each is coupled to V_Net_B, instead of as Figure 3C Therefore, capacitor cell 308(4) has a total of three CPRs, namely 312(1), 312(4) and 320(1), instead of Figure 3A The six CPRs are CPRs 312(1)-312(4) and 320(1)-320(2). The capacitance cap_308_4 of capacitor cell 308(4) is half the capacitance of capacitor cell 304(3), therefore cap_308_4=(cap_308_3) / 2.

[0118] exist Figure 3D In capacitor cell 308(4), the position of the instance of V_1st through hole 318 is similar to... Figure 3A The positions of the instances of V_1st through-hole 318 in capacitor unit 304(3) are the same. That is, the arrangement of the instances of V_1st through-hole 318 in capacitor unit 308(4) is the same as the arrangement of the instances of V_1st through-hole 318 in capacitor unit 308(3). In some embodiments, the arrangement of the instances of V_1st through-hole 318 in capacitor unit 308(4) is different from the arrangement of the instances of V_1st through-hole 318 in capacitor unit 308(3).

[0119] In some embodiments, the M_1st configuration plan of capacitor cell 308(4) is referred to as the M_1st half-maximum CPR configuration plan, and the M_1st configuration plan of capacitor cell 308(3) is referred to as the M_1st maximum CPR configuration plan. In some embodiments, the M_2nd configuration plan of capacitor cell 308(4) is referred to as the M_2nd half-maximum CPR configuration plan, and the M_2nd configuration plan of capacitor cell 308(3) is referred to as the M_2nd maximum CPR configuration plan. In some embodiments, capacitor cell 308(4) is referred to as a half cell, and capacitor cell 308(3) is referred to as a unit cell.

[0120] In some embodiments, Figure 3C The top and bottom boundaries of the manufactured capacitor cell (e.g., corresponding to capacitor cell 308(3)) are similar to Figure 3A The manner in which cell region 308(1) is interpreted is identifiable. In some embodiments, the left and right boundaries of the manufactured capacitor cell (e.g., corresponding to capacitor cell 308(1)) are arranged in a manner similar to Figure 3A The manner in which the unit region 308(1) is interpreted is recognizable.

[0121] Figures 3E-3Fis a layout diagram of the corresponding capacitor units 308(5)-308(6) in accordance with some embodiments.

[0122] in Figure 3E , the capacitor unit 308(5) is an example of the one or more capacitor units 208 in Figure 2 . In Figure 3F , the capacitor unit 308(6) is an example of the one or more capacitor units 208 in Figure 2 .

[0123] with respect to Figure 3E , the capacitor unit 308(5) is similar to the capacitor unit 308(1) of Figure 3A . For the sake of brevity, the discussion will focus on the differences of the capacitor unit 308(5) from the capacitor unit 308(1) rather than the similarities.

[0124] Not only does the capacitor unit 308(5) include N M_1st segments in the M_1st layer, like the capacitor unit 308(1) of Figure 3A , but the capacitor unit 308(5) further includes a number J of segments in the M_2nd layer. Figure 3E Assume J=9. In some embodiments, N<J. In some embodiments, J is a positive integer but not equal to 9. In contrast, the capacitor unit 308(1) has up to N M_1st segments and no segments in another layer (e.g., the M_2nd layer).

[0125] More specifically, each of the capacitor units 308(5) and 308(6) comprises M_2nd segments 322(1)-322(9) extending along a first direction (e.g., parallel to the Y-axis) and having a pitch p_M_2nd(2).

[0126] With respect to a second direction (e.g., parallel to the X-axis), each of the M_2nd segments 322(1)-322(9) has a uniform width, i.e., substantially a second width W3. Due to the pitch and the uniform width, adjacent ones of the M_2nd segments 322(1)-322(9) are spaced apart from each other by a uniform distance, i.e., substantially a distance S3.

[0127] With respect to the Y-axis, each of the M_2nd segments 322(1)-322(9) has a length L1. The capacitor unit 308(5) has a unit boundary 314(1).

[0128] in Figure 3E each of the capacitor units 308(5) and Figure 3FIn 308(6), each of the M_2nd segments 322(1)-322(9) has an overlap relative to the adjacent corresponding segment in the M_2nd section, and each overlap has an overlap length D_ovrlp_1 relative to the adjacent corresponding segment in the M_2nd segment 332(1)-322(9).

[0129] exist Figures 3E-3F In each of the M_2nd segments 322(1)-322(9), the overlapping portion substantially spans the entire M_2nd segment, such that the overlapping length is substantially the same as the total length, D_ovrlp_1 ≈ L1. In some embodiments, the overlapping portion spans a portion of the length (e.g., Figure 3G-Figure 3H Capacitor cell 308(5) has an overlapping boundary 315(1). Since D_ovrlp_1=≈L1, the overlapping boundary 315(1) is the same as the cell boundary 314(1).

[0130] During manufacturing, for example during BEOL manufacturing, each of the M_2nd segments 322(1)-322(9) is selectively configured to be coupled to one or more corresponding segments of the M_1st segments 310(1)-310(5) via one or more corresponding instances of the V_1st via 318; for simplicity, instances of the V_1st via 318 are not shown in the diagram. Figures 3E-3F As shown in the figure. Therefore, each of the M_2nd segments 322(1)-322(9) is selectively configured to be coupled to either the first voltage V_Net_A or the second voltage V_Net_B.

[0131] about Figure 3EIn addition to CPR312(1)-312(4), capacitor unit 308(5) also includes CPR324(1)-324(8), for a total of twelve CPRs. CPR 324(1) consists of M_2nd segments 322(1) and 322(2); CPR 324(2) consists of M_2nd segments 322(2) and 322(3); CPR 324(3) consists of M_2nd segments 322(3) and 322(4); CPR 324(4) consists of M_2nd segments 322(4) and 322(5); CPR 324(5) consists of M_2nd segments 322(5) and 322(6); CPR 324(6) consists of M_2nd segments 322(6) and 322(7); CPR 324(7) consists of M_2nd segments 322(7) and 322(8); CPR 324(8) consists of M_2nd segments 322(8) and 322(9). The overall capacitance of capacitor unit 308(5) is the sum of the capacitance of M_1st CPR (as described above) and the capacitance of M_2nd CPR (as described above).

[0132] For a given capacitor cell, such as capacitor cell 308(5), having N M_1st segments and J M_2nd segments, the staggered configuration of V_Net_A and V_Net_B in the M_1st and M_2nd layers generates the maximum number of M_1stCPRs and M_2ndCPRs for that given capacitor cell. For a single-layer configuration of capacitor cell 308(5): the M_1st layer has two configurations with maximum M_1st CPRs; the M_2nd layer has two configurations with maximum M_2nd CPRs. Therefore, for a two-layer configuration of capacitor cells including M_1st and M_2nd segments, such as capacitor cell 308(5), there are 2 2 =4 maximum CPR configuration plans.

[0133] For the single-layer configuration planning of capacitor cells with N=5 M_1st segments and J=9 M_2nd segments, for example, capacitor cell 308(5): the M_1st layer has 2 N =2 5 =32 possible configuration plans; M_2nd layer has 2 J =2 9 =512 possible configuration plans.

[0134] For the two-layer configuration planning of capacitor cells with N=5 M_1st segments and J=9 M_2nd segments, for example, capacitor cell 308(5), there are 2 (N+J) =2 (5+9) =16384 possible two-layer configuration plans.

[0135] Regarding a double-layer capacitor cell with N=5 M_1st segments and J=9 M_2nd segments, such as capacitor cell 308(5), the following should be understood: aside from the four configuration plans that achieve the maximum CPR, the number of CPRs achieved by each of the remaining 16380 configuration plans is less than the maximum CPR; the remaining 16380 configuration plans generate the overall capacitance of the double-layer capacitor cell, which is a fraction of the double-layer capacitor cell cap_max, and in some embodiments, the remaining 16380 configuration plans of the double-layer capacitor cell are referred to as non-maximum CPR configuration plans.

[0136] In some embodiments, a double-layer capacitor cell having one of the four maximum CPR configuration plans and thus having the maximum capacitance value, such as capacitor cell 308(5), is referred to as a double-layer capacitor cell because each of the remaining 16380 configuration plans of the double-layer capacitor cell realizes a fraction of the total capacitance for cap_max.

[0137] The M_1st core capacitance cap_krnl_1 of capacitor cell 308(5) is the same as that of capacitor cell 308(1). For capacitor cell 308(5), the M_2nd core capacitance cap_krnl_3 is cap_krnl_3 × D_ovrlp_1 / S3. Figure 3E In the case of D_ovrlp_1=L1, the cap_krnl_3 of capacitor unit 308(5) can be restated as cap_krnl_3 × L1 / S3.

[0138] Capacitor cell 308(5) is an example of a double-layer capacitor cell. Capacitor cell 308(5) is also an example of a double-layer capacitor cell in which all instances of the V_1st via 318 (not shown) are at least substantially within the cell boundary 314(1), but also within the overlap boundary 315(1). In other words, when the M_1st and M_2nd layers are front-side layers, each instance of the V_1st via 318 (not shown) in cell 308(5) substantially overlaps with the overlap boundary 315(1). In some embodiments, each instance of the V_1st via 318 (not shown) in cell 308(5) is described as substantially covered by the overlap boundary 315(1). In some embodiments where M_1st and M_2nd layers are back-side layers, i.e. buried layers, the M-1 segment and M_2nd segment are respectively buried segments, and each instance of V_1st via 318 (not shown) in unit 308(5) is a buried via and substantially overlaps with the overlap boundary 315(1).

[0139] In some embodiments, all instances of V_1st via 318 are at least substantially within the cell boundary 314(1), although one or more instances of V_1st via 318 are substantially outside the overlapping boundary 315(1) (see Figure 3G-Figure 3H ).

[0140] review Figure 3E Assume J=9 and q_max_M_2nd is J-1, such that q_max_M_2nd=(J-1)=8. For the overall capacitor unit 308(5), q_max_308(5)=q_max_M_1st+q_maxM_2nd=(4+8)=12. The overall capacitance cap_308_5 of the capacitor unit 308(5) is the sum of cap_max_M_1st and cap_max_M_2nd, such that cap_308_5=cap_max_M_1st+cap_max_M_2nd=4×cap_krnl_1+8×cap_knl_3.

[0141] although Figure 3E Assuming one of the four maximum CPR configuration schemes for a double-layer capacitor cell with N=5 M_1st segments and J=9 M_2nd segments, i.e. for capacitor cell 308(5), but Figure 3F An example of one of at least 16,380 non-maximum CPR configuration plans for such a capacitor cell is shown.

[0142] exist Figure 3F In the middle, capacitor unit 308(6) is similar to Figure 3E The capacitor unit 308(5). For the sake of brevity, the discussion will focus on the differences between capacitor unit 308(6) and capacitor unit 308(5), rather than their similarities.

[0143] exist Figure 3F In the M_1st section 310(3) and M_2nd section 322(5), each is coupled to V_Net_B, instead of like Figure 3E Therefore, capacitor cell 308(6) has a total of six CPRs, namely 312(1), 312(4), 324(2), 324(3), 324(6) and 324(7), instead of as shown in the diagram. Figure 3E The twelve CPRs shown are CPR312(1)-312(4) and 324(1)-324(8). The capacitance cap_308_6 of capacitor cell 308(6) is half the capacitance of capacitor cell 306(5), therefore cap_308_6=(cap_308_5) / 2.

[0144] In some embodiments, the M_1st configuration plan of capacitor cell 308(6) is referred to as the M_1st half-maximum CPR configuration plan, and the M_1st configuration plan of capacitor cell 308(5) is referred to as the M_1st maximum CPR configuration plan. In some embodiments, the M_2nd configuration plan of capacitor cell 308(6) is referred to as the M_2nd half-maximum CPR configuration plan, and the M_2nd configuration plan of capacitor cell 308(5) is referred to as the M_2nd maximum CPR configuration plan. In some embodiments, capacitor cell 308(6) is referred to as a half cell, and capacitor cell 308(5) is referred to as a unit cell.

[0145] In some embodiments, Figure 3C The top and bottom boundaries of the manufactured capacitor cell (e.g., corresponding to capacitor cell 308(5)) are similar to Figure 3A The manner in which cell region 308(1) is interpreted is identifiable. In some embodiments, the left and right boundaries of the manufactured capacitor cell (e.g., corresponding to capacitor cell 308(5)) are arranged in a manner similar to Figure 3A The manner in which the unit region 308(1) is interpreted is recognizable.

[0146] Figure 3G-Figure 3H This is a layout diagram of the corresponding capacitor units 308(7)-308(8) according to some embodiments.

[0147] exist Figure 3G In the middle, capacitor unit 308(7) is Figure 2 An example of one or more capacitor cells 208. Figure 3H In the middle, capacitor unit 308(8) is Figure 2 An example of one or more capacitor cells 208. Figure 3G In the middle, section line 4A-4A' corresponds to Figure 4A The cross section, section line 4B-4B' corresponds to Figure 4B The cross section.

[0148] about Figure 3G The capacitor unit 308(7) is similar to Figure 3C The capacitor unit 308(3). For the sake of brevity, the discussion will focus on the differences between capacitor unit 308(7) and capacitor unit 308(3), rather than their similarities.

[0149] exist Figure 3G-Figure 3H In the capacitor, each capacitor cell 308(7) and 308(8) has: a cell boundary 314(2); a height L4 along a first direction (e.g., parallel to the Y-axis); and a width L6 along a second direction (e.g., parallel to the X-axis).

[0150] exist Figure 3G-Figure 3HIn the M_1st layer, each of the capacitor units 308(7) and 308(8) includes M_1st segments 310(11)-310(17), M_1st dummy segments 311(11)-311(12), M_2nd segments 316(11)-361(15) and M_2nd dummy segments 317(11)-317(12).

[0151] More generally, each capacitor cell 308(7) and 308(8) comprises: K M_1st segments, where K is a positive integer and K≤4; and R M_2nd segments, where R is a positive integer and R≥4. Figure 3G-Figure 3H In this case, assume K = 7 and R = 5.

[0152] The M_1st segments 310(11)-310(17) and M_1st dummy segments 311(11)-311(12) extend parallel to the Y-axis and have a pitch p_M_1st(2). The M_2nd segments 316(11)-316(15) and M_2nd dummy segments 317(11)-317(12) extend parallel to the X-axis and have a pitch p_M_2nd(3). Relative to the Y-axis: each of the M_1st segments 310(11)-310(17) has a length L3; and each of the M_2nd segments 316(11)-316(15) has a length L5.

[0153] Relative to the X-axis, each of the M_1st segments 310(11)-310(17) and M_1st dummy segments 311(11)-311(12) has a uniform width, i.e., a width of approximately W4. Due to the spacing and uniform width, adjacent segments in the M_1st segments 310(11)-310(17) and M_1st dummy segments 311(11)-311(12) are spaced apart by a uniform distance, i.e., a distance of approximately S4.

[0154] Relative to the Y-axis, each of the M_2nd segments 316(11)-316(15) and M_2nd dummy segments 317(11)-317(12) has a uniform width, i.e., a width of approximately W5. Due to the spacing and uniform width, adjacent segments in the M_2nd segments 316(11)-316(15) and M_2nd dummy segments 317(11)-317(12) are spaced apart by a uniform distance, i.e., a distance of approximately S4.

[0155] Each of the M_1st segments 310(11)-310(17) has an overlapping portion relative to an adjacent corresponding segment in the M_1st segment, and each overlapping portion has an overlap length D_ovrlp_3 relative to an adjacent corresponding segment in the M_1st segments 310(11)-310(17).

[0156] In Figure 3G-Figure 3H in each of the M_1st segments 310(11)-310(17), the overlapping portion spans a part of the M_1st segment such that the overlap length is less than the total length, D_ovrlp_3<L3. With respect to the M_1st layer, the capacitor unit 308(7) has an M_1st overlap boundary 315(2). Since D_ovrlp_3<L3, the overlap boundary 315(2) is different from the unit boundary 314(2).

[0157] In Figure 3G-Figure 3H in each of the M_2nd segments 316(11)-316(15), the overlapping portion spans a part of the M_2nd segment such that the overlap length is less than the total length, D_ovrlp_4<L5. With respect to the M_2nd layer, the capacitor unit 308(7) has an M_2nd overlap boundary 315(3). Since D_ovrlp_4<L5, the overlap boundary 315(3) is different from the unit boundary 314(2).

[0158] During manufacturing, for example during BEOL manufacturing, each of the M_1st segments 310(11)-310(17) and the M_2nd segments 316(11)-316(15) is selectively configured to couple to voltage V_Net_A or voltage V_Net_B.

[0159] In Figure 3G : CPR 312(1) is composed of M_1st segments 310(12) and 310(13); CPR 312(2) is composed of M_1st segments 310(13) and 310(14); CPR 312(3) is composed of M_1st segments 310(14) and 310(15); CPR 312(4) is composed of M_1st segments 310(15) and 310(16); CPR 326(1) is composed of M_2nd segments 316(12) and 316(13); CPR 326(2) is composed of M_2nd segments 316(13) and 316(14). The overall capacitance of the capacitor unit 308(7) is the sum of the capacitance of the M_1st CPR (as described above) and the capacitance of the M_2nd CPR (as described above).

[0160] For a given capacitor cell, such as capacitor cell 308(7), with K M_1st segments and R M_2nd segments, the staggered configuration of V_Net_A and V_Net_B in the M_1st and M_2nd layers generates the maximum number of M_1stCPRs and M_2ndCPRs for the given capacitor cell. For a single-layer configuration of capacitor cell 308(7): the M_1st layer has two configurations with maximum M_1st CPRs; the M_2nd layer has two configurations with maximum M_2nd CPRs. Therefore, for a two-layer configuration of capacitor cells including M_1st and M_2nd segments, such as capacitor cell 308(7), there are 2 2 =4 maximum CPR configuration plans.

[0161] For a single-layer configuration plan of capacitor cells with K=7 M_1st segments and R=5 M_2nd segments, for example, capacitor cell 308(7): the M_1st layer has 2 K =2 7 =128 possible configuration plans; M_2nd layer has 2 R =2 5 =32 possible configuration plans.

[0162] For a two-layer configuration plan of capacitor cells with K=7 M_1st segments and R=5 M_2nd segments, for example capacitor cell 308(7), there are 2 (K+R) =2 (7+5) =4096 possible two-layer configuration plans.

[0163] Regarding a double-layer capacitor cell having K=7 M_1st segments and R=5 M_2nd segments, such as capacitor cell 308(7), the following should be understood: aside from the four configuration plans that achieve the maximum CPR, the number of CPRs achieved by each of the remaining 4092 configuration plans is less than the maximum CPR; the remaining 4092 configuration plans generate the overall capacitance for the double-layer capacitor cell, which is a fraction of the double-layer capacitor cell cap_max, and in some embodiments, the remaining 4092 configuration plans for the double-layer capacitor cell are referred to as non-maximum CPR configuration plans.

[0164] In some embodiments, a double-layer capacitor cell having one of the four maximum CPR configuration plans and thus having the maximum capacitance value, such as capacitor cell 308(7), is referred to as a double-layer capacitor cell because each of the remaining 4092 configuration plans of the double-layer capacitor cell achieves a fraction of the overall capacitance of cap_max.

[0165] For capacitor cell 308(7), the M_1st core capacitor cap_krnl_4 is cap_krnl_4 D_ovrlp_3 / S4. For capacitor cell 308(7), the M_2nd core capacitor cap_krnl_5 is cap_krn_5Dovrlp_4 / S5.

[0166] Capacitor cell 308(7) is an example of a double-layer capacitor cell. Capacitor cell 308(7) is also an example of a double-layer capacitor cell in which all instances of V_1st via 318 are: at least substantially outside the M_1st overlap boundary 315(2); and at least substantially outside the M_2nd overlap boundary 315(3). In other words, each instance of V_1st via 318 (not shown) in cell 308(5) is substantially not overlapped with the overlap boundary 315(1). In some embodiments, each instance of V_1st via 318 (not shown) in cell 308(5) is described as substantially not covered by the overlap boundary 315(1). By including M_1st dummy 311(11)-311(12), it is helpful to place the instances of V_1st via 318 at least substantially outside the M_1st overlap boundary 315(2). By including M_2nd dummy 317(11)-317(12), it helps to place instances of V_1st via 318 at least substantially outside M_2nd overlap boundary 315(3).

[0167] In some embodiments, all instances of V_1st via 318 are at least substantially within M_1st overlap boundary 315(2) and at least substantially within M_2nd overlap boundary 315(3). In some embodiments, one or more instances of V_1st via 318 are at least substantially within M_1st overlap boundary 315(2), and one or more instances of V_1st via 318 are at least substantially outside M_1st overlap boundary 315(2). In some embodiments, one or more instances of V_1st via 318 are at least substantially within M_2nd overlap boundary 315(3), and one or more instances of V_1sl via 318 are at least substantially outside M_2nd overlap boundary 315(3).

[0168] review Figure 3G Suppose K=7, and q_max_M_1st is K-1, such that q_max_M_1st=(K-1)=6. (Review) Figure 3GAssume R=5 and q_max_M_2nd is R-1, such that q_max_M_2nd=(R-1)=4. For capacitor unit 308(7) as a whole, q_max_308(7)= q_max_M_1st + q_max_M_2nd = (6+4) = 10. The capacitance cap_308_7 of capacitor unit 308(7) as a whole is the sum of cap_max_M_1st and cap_max_M_2nd, such that cap_308_7 = cap_max_M_1st + cap_max_M_2nd = 6×cap_krnl_1 + 4×cap_krnl_3.

[0169] although Figure 3G Assuming one of the four maximum CPR configuration schemes for a double-layer capacitor cell with K=7 M_1st segments and R=5 M_2nd segments, i.e. for capacitor cell 308(7), but Figure 3H An example of one of at least 4092 non-maximum CPR configuration plans for such a capacitor cell is shown in the figure.

[0170] exist Figure 3H In the middle, capacitor unit 308(8) is similar to Figure 3G The capacitor unit 308(7). For the sake of brevity, the discussion will focus on the differences between capacitor unit 308(8) and capacitor unit 308(7), rather than their similarities.

[0171] In capacitor cell 308(8), the M_1st segment 310(18) replaces the M_1st segment 310(14) of capacitor cell 308(7). Similarly, in capacitor cell 308(8), the M_2nd segment 316(16) replaces the M_2nd segment 316(14) of capacitor cell 308(7). In other words, the M_1st segment 310(18) is similar to a version of the M_1st segment 310(14) of capacitor cell 308(7) that is moved downwards within capacitor cell 308, where the positional difference is due to… Figure 3G-Figure 3H The dummy 328(1) and 328(2) appearing in the text represent this. Furthermore, in other words, the M_2nd segment 316(16) is similar to a version of the M_2nd segment 316(14) of capacitor cell 308(7) shifted to the left within capacitor cell 308, where the positional difference is due to... Figure 3G-Figure 3H The dummy 330(1) and 330(2) appearing in the text represent this.

[0172] exist Figure 3H In the M_1st section 310(18) and M_2nd section 316(16), each is coupled to V_Net_B, instead of like Figure 3ETherefore, capacitor cell 308(8) has a total of three CPRs, namely 312(11), 312(14) and 326(1), instead of being coupled to V_Net_A as in the middle. Figure 3G The six CPRs are CPRs 312(11)-312(14) and 326(1)-326(2). The capacitance cap_308_8 of capacitor cell 308(8) is half the capacitance of capacitor cell 308(7), such that cap_308_8 = (cap_308_7) / 2.

[0173] In some embodiments, the M_1st configuration plan of capacitor cell 308(8) is referred to as the M_1st half-maximum CPR configuration plan, and the M_1st configuration plan of capacitor cell 308(7) is referred to as the M_1st maximum CPR configuration plan. In some embodiments, the M_2nd configuration plan of capacitor cell 308(8) is referred to as the M_2nd half-maximum CPR configuration plan, and the M_2nd configuration plan of capacitor cell 308(7) is referred to as the M_2nd maximum CPR configuration plan. In some embodiments, capacitor cell 308(8) is referred to as a half-cell, and capacitor cell 308(7) is referred to as a cell cell.

[0174] Capacitor cell 308(8) is also an example of a double-layer capacitor cell, wherein all instances of V_1st via 318 are: at least substantially outside M_1st overlap boundary 315(2); and at least substantially outside M_2nd overlap boundary 315(3).

[0175] exist Figure 3H In capacitor cell 308(8), the position of the V_1st through-hole 318 is different. Figure 3GThe location of the V_1st via 318 instance in capacitor cell 304(7). The V_1st via 318 instance already coupled to M_1st segment 310(14) of capacitor cell 308(7) has been replaced in capacitor cell 308(8) by the V_1st via 318 instance coupled to M_1st segment 310(18). The V_1st via 318 instance already coupled to M_2nd segment 316(14) of capacitor cell 308(7) has been replaced in capacitor cell 308(8) by the V_1st via 318 instance coupled to M_2nd segment 316(16). In other words, the first arrangement of V_1st via 318 instances in capacitor cell 308(8) is different from the second arrangement of V_1st via 318 instances in capacitor cell 308(7). The first arrangement of instances of V_1st via 318 in capacitor cell 308(8) is changed to a second arrangement of instances of V_1st via 318 in capacitor cell 308(7), while all instances of V_1st via 318 can be kept at least substantially outside each of M_1st overlap boundary 315(2) and M_2nd overlap boundary 315(3) by including M_1st dummy 311(11)-311(12).

[0176] Although there are differences between the M_1st and M_2nd segment groups in (i) cell region 308(7) and the M_1st and M_2nd segment groups in (ii) cell region 308(8), the overlapping boundaries outside the M_1st overlapping boundary 315(2) and the M_2nd overlapping boundary 315(3) remain unchanged for each of capacitor cells 308(7) and 308(8). That is, although there are differences between the entire cell region 304(7) and the entire cell region 308(8), the outer boundary of the M_1st overlapping boundary 315(2) remains unchanged for each capacitor cell 308(7) and 308(8); and the outer boundary of the M_2nd overlapping boundary 315(3) remains unchanged for each capacitor cell 308(7) and 308(8). Furthermore, although the M_1st and M_2nd segment groups in unit region 308(7) differ from those in unit region 308(8), a comparison between capacitor units 308(7) and 308(8) reveals the following: the overlapping area and arrangement of the M_1st segments remain consistent between capacitor units 308(7) and 308(8); and the overlapping area and arrangement of the M_2nd segments remain consistent between capacitor units 308(7) and 308(8). This uniformity is further enhanced by including M_1st dummy segments 311(11)-311(12).

[0177] In some embodiments, the background for understanding the boundaries of the manufactured capacitor cells (e.g., corresponding to capacitor cells 308(7)-308(1)) is as follows: the leftmost M_1st segment (e.g., 310(11)) and the bottommost M_2nd segment (e.g., 316(15)) intersect to form a first L-shape corresponding to the lower left corner of the manufactured capacitor cell; the rightmost M_1st segment (e.g., 310(17)) and the topmost M_2nd segment (e.g., 316(11)) intersect to form a first L-shape corresponding to the lower left corner of the manufactured capacitor cell; The two L-shapes intersect to form a second L-shape corresponding to the upper right corner of the manufactured capacitor cell, the second L-shape being rotated approximately 180 degrees (180°) relative to the first L-shape in the XY plane; between the leftmost (e.g., 310(11)) and the rightmost (e.g., 320(17)) M_1st segments, there are one or more other M_1st segments (inner M_1st segments (e.g., 310(12)-310(16) and 310(18))); at the topmost (e.g., 316(11))... Between 1)) and the bottommost (e.g., 316(15)) M_2nd segment, there are one or more other M_2nd segments (internal M_2nd segments (e.g., 314(12)-316(14) and 316(16))); internal M_1st segments (e.g., 310(12)-310(16) and 310(18)) do not substantially extend beyond the topmost M_2nd segment (e.g., 316(11)) nor substantially extend beyond the bottommost M_2nd segment. The segments (e.g., 316(15)); the inner M_2nd segments (e.g., 316(12)-316(14) and 316(16)) do not substantially extend beyond the leftmost M_1st segment (e.g., 310(11)) nor substantially extend beyond the rightmost M_1st segment (e.g., 310(17)); and the first L-shape and the second L-shape substantially define the first rectangle; and the boundary of the manufactured capacitor cell (e.g., 314(2)) is a second rectangle that at least substantially surrounds the first rectangle.

[0178] In some embodiments, further context for understanding the boundaries of the manufactured capacitor cells (e.g., corresponding to capacitor cells 308(7)-308(1)) is as follows: any inner M_1st segments (e.g., 310(12)-310(16) and 310(18)) that do not intersect with the uppermost M_2nd segment (e.g., 316(11)) also substantially do not overlap with the upper M_2nd dummy (e.g., 317(11)); any inner M_1st segments (e.g., 310(12)-310(16) and 310(18)) that do not intersect with the lowermost M_2nd segment (e.g., 316(15)) It also does not overlap with the bottommost M_2nd dummy (e.g., 317(12)); any internal M_2nd segment (e.g., 316(12)-316(14) and 316(16)) that does not intersect with the leftmost M_1st segment (e.g., 310(11)) also does not overlap with the rightmost M_1st dummy (e.g., 311(11); and any internal M_2nd segment (e.g., 316(12)-316(14) and 316(16)) that does not intersect with the rightmost M_1st segment (e.g., 310(17)) also does not overlap with the leftmost M_1st dummy (e.g., 311(12)).

[0179] In some embodiments, the top and bottom boundaries of the manufactured capacitor cells (e.g., corresponding to capacitor cells 308(7)-308(8)) can be identified as follows: a first L-shape consisting of the leftmost M_1st segment (e.g., 310(11)) and the bottommost M_2nd segment (e.g., 316(15)) is identified; a second L-shape consisting of the rightmost M_1st segment (e.g., 310(17)) and the topmost M_2nd segment (e.g., 316(11)) is identified, the second L-shape being rotated approximately 180 degrees (180°) relative to the first L-shape in the XY plane; the first and second L-shapes are considered to define a first rectangle; the inner M_1st segments of the first rectangle (e.g., 310(12)-310(16) and 310(18)) are identified; the inner M_2nd segments of the first rectangle (e.g., 310(12)-310(16) and 310(18)) are identified. For example, 316(12)-316(14) and 316(16)); observe / confirm that none of the inner M_1st segments (e.g., 310(12)-310(16) and 310(18)) extends beyond the uppermost M_2nd segment (e.g., 316(11)) or extends beyond the lowermost M_2nd segment (e.g., 316(15)); observe / confirm that none of the inner M_2nd segments (e.g., 316(12)-316(14) and 316(16)) extends beyond the leftmost M_1st segment (e.g., 310(11)) or extends beyond the rightmost M_1st segment (e.g., 310(17)); and the boundary of the manufactured capacitor cell (e.g., 314(2)) is considered as a second rectangle that at least substantially surrounds the first rectangle.

[0180] In some embodiments, the left and right boundaries of the manufactured capacitor cells (e.g., corresponding to capacitor cells 308(7)-308(8)) are arranged in a manner similar to... Figure 3A The manner explained by cell region 308(1) is identifiable. In such an embodiment, in Figure 3G-Figure 3H In each of the following: M_1st dummy 311(13) (not shown) corresponds to Figure 3A M_1st dummy 311(1); M_1st dummy 311(14) (not shown) corresponds to Figure 3A M_1st is a dummy 311(2).

[0181] Figures 4A-4B These are cross-sectional views of corresponding capacitor cells 408A and 408B of semiconductor device 300A according to some embodiments.

[0182] Specifically, Figures 4A-4B Each of them is based on Figure 3G A cross-sectional view of the capacitor cell manufactured by capacitor cell 308(7). Figure 4A Corresponding to Figure 3G The section line is 4A-4A'. Figure 4B Corresponding to Figure 3G The section line is 4B-4B'.

[0183] exist Figure 4A In the capacitor cell 408A, the capacitor cell includes: M_1st segments 410(11)-410(17); M_1st dummy segments 411(11)-411(12); an example of V_1st via 418; and M_2nd segment 416(13). Figure 4B In the capacitor cell 408B, there are: an example of M_1st segment 410 (16); a V_1st through hole 418; and M_2nd segments 416 (11)-416 (15).

[0184] Figure 5A This is a configuration planning table of capacitor cells having B=3 M-1 segments according to some embodiments.

[0185] Figure 5A The table is similar to Figure 5C The table. For the sake of brevity, the discussion will focus on Figure 5A The table and Figure 5C The differences between the tables are not the similarities.

[0186] For B = 3 M_1st segments, there are 2 B =2 3 =8 possible configuration plans. Therefore, in Figure 5A The table has 8 rows. In other words, Figure 5A The table indicates that B = 3 M_1st segments correspond to 8 combinations coupled with V_Net_A or V_Net_B.

[0187] Notice, Figure 5A The table assumes that layer M_1st is the background. In some embodiments, Figure 5A The table assumes that layer M_2nd is the background. In some embodiments, Figure 5A The table assumes that the metallization layer other than the M_1st or M_2nd layer is the background.

[0188] Figure 5B This is a configuration planning table of capacitor cells having B=4 M-1 segments according to some embodiments.

[0189] Figure 5B The table is similar to Figure 5C The table. For the sake of brevity, the discussion will focus on Figure 5B The table and Figure 5C The differences between the tables are not the similarities.

[0190] For B = 4 M_1st segments, there are 2 B =2 4 =16 possible configuration plans. Therefore, in Figure 5B The table has 16 rows. In other words, Figure 5B The table shows 16 combinations in which B=4 M_1st segments are coupled to V_Net_A or V_Net_B.

[0191] It should be noted that Figure 5B The table assumes that layer M_1st is the background. In some embodiments, Figure 5B The table assumes that layer M_2nd is the background. In some embodiments, Figure 5B The table assumes that the metallization layer other than the M_1st or M_2nd layer is the background.

[0192] Figures 5D(1)-5D(2) This is a configuration planning table of capacitor cells with B=6 M_1st segments according to some embodiments.

[0193] Figures 5D(1)-5D(2) The table is similar to Figure 5C The table. For the sake of brevity, the discussion will focus on Figures 5D(1)-5D(2) The table and Figure 5C The differences between the tables are not the similarities.

[0194] For B = 6 M_1st segments, there are 2 B =2 6 =64 possible configuration plans. Therefore, in Figures 5D(1)-5D(2) The table has 64 rows. In other words, Figures 5D(1)-5D(2) The table represents 64 combinations of M-1 segments of type B corresponding to either V_Net_A or V_Net_B.

[0195] It should be noted that Figures 5D(1)-5D(2) The table assumes that layer M_1st is the background. In some embodiments, Figures 5D(1)-5D(2) The table assumes that layer M_2nd is the background. In some embodiments, Figures 5D(1)-5D(2) The table assumes that the metallization layer other than the M_1st or M_2nd layer is the background.

[0196] Figures 5E(1)-5E(4) Accordingly, the first and second parts of the configuration planning table of capacitor cells having B=7 M-1 segments according to some embodiments.

[0197] Figures 5E(1)-5E(4) The table is similar to Figure 5C The table. For the sake of brevity, the discussion will focus on Figures 5E(1)-5E(4) The table and Figure 5C The differences in the tables are not the similarities.

[0198] For B = 7 M_1st segments, there are 2 B =2 7 =128 possible configuration plans. Therefore, in Figures 5E(1)-5E(4) The table has 128 rows. In other words, Figures 5E(1)-5E(4) The table shows 128 combinations of B=7 M_1st segments coupled to V_Net_A or V_Net_B.

[0199] It should be noted that Figures 5E(1)-5E(4) The table assumes that layer M_1st is the background. In some embodiments, Figures 5E(1)-5E(4) The table assumes that layer M_2nd is the background. In some embodiments, Figures 5E(1)-5E(4) The table assumes that the metallization layer other than the M_1st or M_2nd layer is the background.

[0200] Figure 6 This is a flowchart (flowchart) of a method 600 for manufacturing equipment according to some embodiments.

[0201] According to some embodiments, method 600 can, for example, use EDA system 800 ( Figure 8 (discussed below) and IC Manufacturing System 900 ( Figure 9 (As discussed below) to achieve this. Examples of semiconductor devices that can be manufactured according to method 600 include the semiconductor devices disclosed herein.

[0202] exist Figure 6 In this method 600, blocks 602-604 are included. At block 602, a layout diagram is generated, which, among other things, includes one or more layout diagrams disclosed herein, or a layout diagram corresponding to one or more of the semiconductor devices disclosed herein. According to some embodiments, for example, an EDA system 800 can be used (… Figure 8 (This will be discussed below) to implement block 602. The process proceeds from block 602 to block 604.

[0203] At block 604, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures are performed, or (B) one or more photolithographic masks are fabricated, or (C) one or more components in a device (e.g., device) layer are fabricated. According to some embodiments, for example, an IC manufacturing system 900 can be used. Figure 9 (This will be discussed below) to implement block 604.

[0204] Figure 7A This is a flowchart of a method 702 for generating a layout diagram according to some embodiments.

[0205] Method 702 is an example of block 602 (see discussion above). Figure 6(Among other things, the layout generated by method 702 includes one or more layouts disclosed herein, or layouts corresponding to one or more of the semiconductor devices disclosed herein.)

[0206] According to some embodiments, method 702 can, for example, use EDA system 800 ( Figure 8 (This will be discussed below) to achieve this. Method 702 includes blocks 710-726.

[0207] At block 710, a first array of capacitor cells of a first number is converted into a second array of capacitor cells. This conversion involves replacing the first number of first capacitor cells with a second number of non-uniform second capacitor cells, the second number being less than the first number. Criteria satisfied by the first array include: a target value for total capacitance; a target total occupied area; and a target number of metallization layers to be used. The first array has a first number of non-uniform first capacitor cells. Each first capacitor cell has: a first area; and a possible first maximum cell capacitance (maximum cell capacitance), depending on whether the instance of the first capacitor cell is configured as a maximum CRP capacitor cell or a non-maximum CPR capacitor cell. Each second capacitor cell has: a second area larger than the first area; and a possible maximum cell capacitance, depending on whether the instance of the second capacitor cell is configured as a maximum CRP capacitor cell or a non-maximum CPR capacitor cell. The process proceeds from block 710 to block 712.

[0208] At block 712, the total occupied area of ​​the second array is determined. In some embodiments, the total occupied area of ​​the array includes the area of ​​each capacitor cell in the array and the required spacing between adjacent capacitor cells in the array. The process proceeds from block 712 to block 714.

[0209] In some embodiments, blocks 710 and 712 are collectively described as follows: For a target array of capacitor cells (target capacitor cells) having a target array capacitance, the target unit capacitor cell layout is designed based on the target cell capacitance value, the target total occupied area specification, and the target number of metal layers used. In other words, in these embodiments, the target array is designed as follows: In stage (i), a first version of a given array is designed to have a first number of instances of the same first given unit capacitor cells; in stage (ii), the first version of the given array is modified to a second version of the given array by replacing all instances of the first given unit cells (i.e., their first number) with two or more versions of second given unit capacitor cells; and wherein the second version of the given array represents the target array, such that a second number of two or more versions of second given unit capacitor cells represents the target capacitor cells. Regarding stage (i), the first version of the given array is designed to have at least: a total array capacitance value (target total capacitance value); each capacitor cell being an instance of a first given unit capacitor cell; and a layout of the first given unit capacitor cells based on (a) the target total capacitance value of the given array, (b)(b1) the total area specification of the given array and / or (b2) the first given unit cells, and (c) the target number of metal layers therein. Regarding stage (ii), the second version of the given array is designed to have at least: all instances of the first given unit cells (i.e., the first number) are replaced by a second number of corresponding versions of the second given unit cells; the second number includes at least (1) one or more first versions of the second given unit capacitor cells (e.g., the maximum capacitance version) and (2) one or more second versions of the second given unit capacitor cells (e.g., the half maximum capacitance version); each second given capacitor cell is larger than the first given capacitor cell; and the second number is smaller than the first number.

[0210] At block 714, it is determined whether the area occupied by the second array is less than the area occupied by the first array. If the result at block 714 is yes, the process continues to block 716. If the result at block 714 is no, the process continues to block 722.

[0211] In some embodiments, block 714 is described as follows: Evaluating whether fractional capacitance saves area. In some embodiments, the phrase "fractional capacitance" refers to one or more second versions of the capacitance (e.g., half-maximum capacitance) of a second given unit capacitor cell. In some embodiments, the phrase "fractional capacitor mismatch" refers to a capacitor cell containing "fractional capacitance," that is, a second number of second given unit capacitor cells, including not only (1) at least one or more first versions (e.g., maximum capacitance versions) of the second given unit capacitor cell, but also (2) one or more second versions (e.g., half-maximum capacitance versions) of the second given unit capacitor cell. In some embodiments, the phrase "saves area" means that the area occupied by the second version of a given array is less than the space occupied by the first version of a given array.

[0212] At block 716, the total capacitance value of the second array is determined. The process then proceeds from block 716 to block 718.

[0213] At block 718, it is determined whether the total capacitance value of the second array meets the target total capacitance value. In some embodiments, the target total capacitance value is a range of capacitance values ​​such that the target total capacitance value is met when the total capacitance value of the second array falls within this range. If the determination at block 718 is yes, the process continues to block 720. If the determination at block 718 is no, the process continues to block 722.

[0214] In some embodiments, blocks 716 and 718 are collectively described as follows: checking whether fractional capacitor mismatch meets / satisfies the target array capacitance.

[0215] At block 720, the second array is used as the third array, and the first capacitor cell is used as the third non-uniform capacitor cell. The process proceeds from block 720 to block 724.

[0216] At block 722, the first array is used as the third array, and the second capacitor cell is used as the third non-uniform capacitor cell. The process proceeds from block 720 to block 724.

[0217] At block 724, the third array is modified to produce the fourth array by replacing the non-uniform third capacitor cell with the corresponding uniform fourth capacitor cell. The uniform fourth capacitor cell accordingly has various configuration schemes (see...). Figures 5A-5E(4) (etc.). Examples of uniform fourth capacitor cells include corresponding... Figures 3A-3H The capacitor units 308(1)-308(8), etc. Block 724 includes block 726.

[0218] In some embodiments, block 724 is described as follows: ensuring that the metal formation of the fractional capacitor cells is the same as that of the unit capacitor; and changing the manner in which the signal is connected to the metal segments in the fractional cells compared to the manner in which the signal is connected to the signal in the unit cell. In some embodiments, the phrase "ensuring that the metal formation of the fractional capacitor cells is the same as that of the unit capacitor" means replacing the non-uniform third capacitor cell with a corresponding uniform fourth capacitor cell. In some embodiments, the phrase "changing the manner in which the signal is connected to the metal segments in the fractional cells compared to the manner in which the signal is connected to the signal in the unit cell" means that the fourth capacitor cell accordingly has various configuration plans (see...). Figures 5A-5E(4) wait).

[0219] In block 726, for multilayer capacitor cells, the variation in via arrangement of the corresponding configuration plan is reduced. Examples of multilayer capacitor cells include capacitor cells 308(3)-308(8), etc. Figures 3C-3D Examples are provided to reduce the variation in via arrangement in the corresponding configuration plan, where Figure 3D The through-hole arrangement of capacitor cell 308(4) and Figure 3C The through-hole arrangement of capacitor unit 308(3) is the same. Figure 3G-Figure 3H Examples are provided to reduce the variation in via arrangement in the corresponding configuration plan, where Figure 3H The through-hole arrangement of capacitor cell 308(8) is similar to Figure 3G The through-hole arrangement of capacitor unit 308(7).

[0220] In some embodiments, block 726 is described as follows: If vias are included in the formation of a capacitor region, then a similar number and location of vias are attempted. In some embodiments, the phrase "vias are included in the formation of a capacitor region" refers to a multilayer capacitor cell. In some embodiments, the phrase "attempt to have a similar number and location of vias" refers to reducing variations in the via arrangement planned for the corresponding configuration.

[0221] In some embodiments, the process proceeds from block 724 to a verification block (not shown), where a third array is verified. In some embodiments, the verification block is performed using 2D, 2.5D, or 3D verification tools, etc. In such embodiments, if the result of the verification block is unsatisfactory, the process loops back to block 724. In some embodiments, block 724 and the verification block represent an iterative loop.

[0222] Figure 7B This is a flowchart of a method 730 for manufacturing a capacitor cell array of a semiconductor device according to some embodiments.

[0223] Method 730 is discussed above. Figure 6Example of block 604. Examples of capacitor cell arrays prepared by method 730 include one or more of the capacitor cell arrays disclosed herein. According to some embodiments, method 730 may be used, for example, with IC manufacturing system 900 ( Figure 9 (This will be discussed below) to achieve this. Method 730 includes blocks 732-740.

[0224] The capacitor cell produced by method 730 is a single-layer uniform capacitor cell, comprising one or more first capacitor cells and one or more second capacitor cells.

[0225] At block 732, within the M_1st layer, the M_1st segment is formed. An example of the M_1st layer is... Figures 4A-4B Examples of the M_1st segment are shown in the diagram. Figures 3A-3F The M_1st segment 310(1)-310(5), Figure 3G-Figure 3H The corresponding M_1st sections 310(11)-310(18), etc. Block 732 includes blocks 734-738. Within block 732, the process proceeds to block 734.

[0226] At block 734, the first layer of metallic material is deposited. This first layer of metallic material is the first precursor of the M_1st section. The process proceeds from block 734 to block 736.

[0227] At block 736, a first metal layer is etched to obtain first strips, each strip having a substantially first width. The first strips extend along a first direction (e.g., parallel to the Y-axis). The first strips are the second precursor to the M_1st segment. The process proceeds from block 736 to block 738.

[0228] At block 738, each first strip is etched to produce an M_1st segment exhibiting features including a first feature (discussed below), a second feature (discussed below), and a third feature (discussed below). The first feature of the M_1st segment is that the first ends of the odd-numbered segments and the second ends of the even-numbered segments in the M_1st segment (i) are substantially aligned correspondingly to each other, and (ii) are correspondingly adjacent to the first and second boundaries of the capacitor cell. The second feature of the M_1st segment is that each of the M_1st segments has a first overlap relative to its adjacent segment, each first overlap having a substantially first overlap length. The third feature is that a first number of corresponding M_1st segments are provided in each capacitor cell. An example of a single-layer capacitor cell including M_1st segments exhibiting each of the first, second, and third features is... Figures 3A-3F The M_1st segment 310(1)-310(5) of capacitor units 308(1)-308(5), Figure 3G-Figure 3HThe M_1st segment 310(11)-310(18) of capacitor unit 3087(8), etc. From block 738, the process leaves block 732 and proceeds to block 740.

[0229] At block 740, for each capacitor cell, the M_1st segment is correspondingly coupled to either a first voltage or a second voltage, such that: each first capacitor cell provides a first capacitance, and each second capacitor cell provides a second capacitance smaller than the first capacitance. An example of a first capacitor cell providing the first capacitance is... Figure 3A Capacitor unit 308(1), etc. An example of a second capacitor unit that provides a second capacitor different from the first capacitor is... Figure 3B Capacitor unit 308(2), etc.

[0230] Figure 7C This is a flowchart of a method 750 for manufacturing a capacitor cell array of a semiconductor device according to some embodiments.

[0231] Method 750 is discussed above. Figure 6 Example of block 604. Examples of capacitor cell arrays prepared by method 750 include one or more of the capacitor cell arrays disclosed herein. According to some embodiments, method 750 may be used, for example, with IC manufacturing system 900 ( Figure 9 (This will be discussed below) to achieve this. Method 750 includes blocks 712-718 and 752-762.

[0232] The capacitor cells produced by method 750 are multilayered, such as double-layered uniform capacitor cells, comprising one or more first capacitor cells and one or more second capacitor cells.

[0233] The process begins at block 712 (as described above). The process continues within block 752 through each of blocks 714-718 (as described above). The process leaves block 712 and proceeds to block 752.

[0234] At block 752, in the V_1st layer, a V_1st via is formed on the corresponding segment within the M_1st segment. An example of the V_1st layer is shown below. Figures 4A-4B Examples of Via_1st vias are shown in the diagram. Figures 3C-3D , Figure 3G-Figure 3H An instance of V_1st through-hole 318 is shown. The flow proceeds from block 752 to block 754.

[0235] At block 754, within layer M_2nd, the M_2nd segment is formed. An example of layer M_2nd is shown below. Figures 4A-4B Examples of the M_2nd segment are shown in the diagram. Figures 3B-3D In the M_2nd section 316(1)-316(3), Figures 3E-3F In the M_2nd section 322(1)-322(9), Figure 3G-Figure 3H The M_2st section 316(11)-316(16), etc. Block 754 includes blocks 756-760. Within block 754, the process proceeds to block 756.

[0236] At block 756, a second layer of metallic material is deposited. This second layer of metallic material is the first precursor of the M_2nd section. The process proceeds from block 756 to block 758.

[0237] At block 758, a second metal layer is etched to obtain a second strip, each of which has a substantially first width. The second strip extends along a third direction (e.g., parallel to the Y-axis or X-axis). The second strip is the second precursor to the M_2nd segment. The process proceeds from block 758 to block 760.

[0238] At block 760, each second strip is etched to produce an M_2nd segment exhibiting features including a third (discussed below), a fourth (discussed below), and a fifth (discussed below) feature. The fourth feature of the M_2nd segment is that the first ends of the odd-numbered segments and the second ends of the even-numbered segments in M_2nd (i) are substantially aligned with each other, and (ii) correspond to the third and fourth boundaries of the capacitor cell. The fifth feature of the M_2nd segment is that each segment in M_2nd has a second overlap relative to its adjacent corresponding segment, each second overlap having a substantially second overlap length. The sixth feature is that a second number of corresponding M_2nd segments are provided in each capacitor cell. An example of an M_2nd segment exhibiting each of the fourth, fifth, and sixth features, included in a multilayer capacitor cell, such as a double-layer capacitor cell, is... Figures 3A-3F The M_2nd segment 316(1)-316(3) of capacitor unit 308(3)-308(4) Figures 3E-3F The M_2nd segment 322(1)-322(9) of capacitor unit 308(5)-308(6) Figure 3G-Figure 3H The corresponding M_2nd segments 316(11)-316(16) in capacitor units 308(7)-308(8). From block 760, the process leaves block 754 and proceeds to block 762.

[0239] At block 762, for each capacitor cell, the M_2nd segment is correspondingly coupled to either a first voltage or a second voltage, such that: each first capacitor cell provides a first capacitance, and each second capacitor cell provides a second capacitance smaller than the first capacitance. An example of a first capacitor cell providing the first capacitance is... Figure 3C Capacitor unit 308(3), Figure 3E Capacitor unit 308(5), Figure 3G Capacitor unit 308(7), etc. An example of a second capacitor unit that provides a second capacitor different from the first capacitor is... Figure 3D Capacitor unit 308(4), Figure 3F Capacitor unit 308(6), Figure 3H Capacitor unit 308(8), etc.

[0240] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0241] In some embodiments, EDA system 800 includes an Automatic Placement and Routing (APR) system. In some embodiments, EDA system 800 is a general-purpose computing device including processor 802 (e.g., a hardware processor) and non-transient computer-readable storage medium 804 (also referred to as memory). Among other things, storage medium 804 is also encoded with computer program code 806, i.e., a set of executable instructions. Execution of instructions 806 by processor 802 represents (at least partially) an EDA tool that implements, according to one or more embodiments (hereinafter referred to as the processes and / or methods), one or more methods for generating layouts corresponding to the layouts disclosed herein, layouts corresponding to the semiconductor devices disclosed herein, etc.

[0242] Storage medium 804 storage layout diagram 811, such as the layout diagram disclosed herein.

[0243] Processor 802 is electrically coupled to storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in storage medium 804 to make EDA system 800 available for performing part or all of the processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0244] In one or more embodiments, storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, storage medium 804 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0245] In one or more embodiments, storage medium 804 stores instructions, i.e., computer program code 806, configured to enable EDA system 800 (where such execution represents (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 also stores information that facilitates the execution of some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 stores a standard cell library 807, including standard cells corresponding to components of the layout diagrams disclosed herein. Storage medium 804 stores one or more layout diagrams 816, such as one or more layout diagrams corresponding to the layout diagrams disclosed herein, layout diagrams corresponding to the semiconductor devices disclosed herein, one or more compiler macros 817 based on these layout diagrams, etc.

[0246] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0247] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with a network 814 to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 800.

[0248] EDA system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. This information is transmitted to processor 802 via bus 808. EDA system 800 is also configured to receive information related to the user interface (UI) via I / O interface 810. This information is stored as UI 842 on computer-readable medium 804.

[0249] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 800. In some embodiments, a layout including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0250] In some embodiments, these processes are implemented as the functions of a program stored in a non-transient computer-readable recording medium. Examples of non-transient computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0251] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to some embodiments.

[0252] In some embodiments, based on Figure 6 The layout diagram generated by block 602 is implemented in IC manufacturing system 900. Figure 6 Block 604, wherein manufacturing system 900 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in an early semiconductor integrated circuit layer. In some embodiments, IC manufacturing system 900 implements Figure 6 Flowcharts, etc.

[0253] exist Figure 9In this IC manufacturing system 900, entities such as design studio 920, mask room 930, and IC manufacturing plant / manufacturer (“Fab”) 950 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 920, mask room 930, and IC manufacturing plant 950 are owned by a single, larger company. In some embodiments, two or more of the design studio 920, mask room 930, and IC manufacturing plant 950 coexist in a shared facility and use shared resources.

[0254] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 960 to be manufactured. The layers combine to form various IC features. For example, a portion of IC design layout 922 includes various IC features such as active regions, gate terminals, source and drain terminals, metal lines or vias for interlayer interconnects, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Depending on the context, source / drain regions may be referred to individually or collectively as source or drain. Design company 920 implements appropriate design processes to form IC design layout 922. The design process includes one or more of logic design, physical design, or location and routing. IC design layout 922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 922 is represented in GDSII file format or DFII file format.

[0255] Mask chamber 930 includes data preparation 932 and mask fabrication 934. Mask chamber 930 uses IC design layout 922 to fabricate one or more masks 935 for fabricating various layers of IC device 960 according to IC design layout 922. Mask chamber 930 performs mask data preparation 932, where IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF to mask fabrication 934. Mask fabrication 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) or semiconductor wafer. The design layout is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication plant 950. Figure 9In this embodiment, mask data preparation 932, mask manufacturing 934, and mask 935 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0256] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is further used, treating OPC as an inverse imaging problem.

[0257] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout processed by OPC. This set of mask generation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 934, which may undo some modifications performed by OPC to satisfy the mask creation rules.

[0258] In some embodiments, mask data preparation 932 includes a lithography process check (LPC), which simulates a process performed by an IC fabrication plant 950 to manufacture an IC device 960. The LPC simulates this process based on an IC design layout 922 to manufacture a simulated fabricated device, such as IC device 960. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after the LPC has manufactured the simulated fabricated device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further optimize the IC design layout 922.

[0259] For clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, mask data preparation 932 includes additional features, such as logical operations (LOPs) that modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0260] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a set of masks 935 is fabricated based on a modified IC design layout. In some embodiments, a pattern is formed on the mask (photomask or mask stencil) using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified IC design layout. The mask is formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shifting mask (PSM), various features in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and image quality. In various examples, the phase-shifting mask is an attenuated PSM or an alternating PSM. The masks produced by mask manufacturing 934 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0261] IC Manufacturing Plant 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Manufacturing Plant 950 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) fabrication) for the interconnection and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0262] IC manufacturing plant 950 uses a mask 935, manufactured by mask chamber 930, and manufacturing tool 952 to manufacture IC device 960. Therefore, IC manufacturing plant 950 uses IC design layout 922 at least indirectly to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is manufactured by IC manufacturing plant 950 using mask 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0263] In some embodiments, the semiconductor device includes: in a first metallization (M_1st) layer, M_1st segments extending in a first direction and having a first pitch, wherein each M_1st segment substantially has a first width and a substantially uniform first gap therebetween, relative to a second direction perpendicular to the first direction; and capacitor cell regions arranged in an array, the capacitor cell regions being capacitor cells, including one or more first capacitor cells and one or more second capacitor cells, wherein each capacitor cell has a first number of corresponding M_1st segments in the M_1st segments and a substantially uniform physical arrangement; and wherein, for each capacitor cell, the coupling between the M_1st segments and a corresponding first voltage or second voltage is arranged such that: each first voltage... A capacitor cell substantially provides a first capacitance; and each second capacitor cell substantially provides a non-zero second capacitance less than the first capacitance; wherein the electrical arrangement of the M_1st segments differs for the second capacitor cell from that for the first capacitor cell; and wherein, for each capacitor cell: the first end of the odd-numbered M_1st segments and the second end of the even-numbered M_1st segments are substantially aligned with each other and are respectively adjacent to the opposing first and second boundaries of the capacitor cell; and with respect to the second direction, the opposing third and fourth boundaries of the capacitor cell are located in the respective outermost second and third gaps adjacent to the respective outermost M_1st segments; each of the second and third gaps is larger than the first gap.

[0264] In some embodiments, the first number of corresponding M_1st segments in the M_1st segment of each capacitor cell is N; each capacitor cell has at most N-1 capacitor pairs; in each capacitor cell, a capacitor pair is the case where adjacent first and second M_1st segments in the M_1st segment are correspondingly coupled to different voltages in a first voltage or a second voltage, such that each capacitor pair provides a third capacitance less than or equal to the second capacitance; for each capacitor cell, the arrangement of coupling between the M_1st segment and the corresponding first voltage or second voltage relative to a second direction from the first side to the second side defines a binary code, wherein the first voltage represents a logic value of one, and the second voltage represents a logic value of zero; each of the two α values ​​of the binary code corresponds to the first capacitor; and N is a positive integer.

[0265] In some embodiments, each of the two or more β values ​​of the binary code corresponds to the second capacitor.

[0266] In some embodiments, the second capacitor is essentially half the size of the first capacitor; the binary code is Gray code; for each of the two α values ​​of the binary code, the corresponding one of the two or more β values ​​of the binary code differs from the α value by one bit.

[0267] In some embodiments, the capacitor unit further includes one or more pseudo capacitor units; in each pseudo capacitor unit, each of the M_1st segments is coupled to a first voltage, or each of the M_1st segments is coupled to a second voltage; each of the two γ values ​​of the binary code corresponds to one or more pseudo capacitor units.

[0268] In some embodiments, in the second metallization (M_2nd) layer, the M_2nd segments extend in a third direction and have a second pitch, wherein each M_2nd segment has a substantially second width and a substantially uniform fourth gap therebetween relative to a fourth direction perpendicular to the third direction; and wherein: for each capacitor cell, each M_2nd segment is correspondingly coupled to a first voltage or a second voltage; and each capacitor cell has a second number of corresponding M_2nd segments and a substantially uniform physical arrangement.

[0269] In some embodiments, the third direction is parallel to the first direction; the fourth direction is parallel to the second direction; the second pitch is smaller than the first pitch; and the second width is smaller than the first width.

[0270] In some embodiments, the third direction is parallel to the second direction; the fourth direction is parallel to the first direction; the second pitch is greater than the first pitch; and the second width is greater than the first width.

[0271] In some embodiments, in a first interconnect (V_1st) layer between the M_1st layer and the M_2nd layer, V_1st vias are coupled to corresponding M_1st segments in the M_1st segment and corresponding M_2nd segments in the M_2nd segment; and wherein, relative to the first direction, the second direction, the third direction, and the fourth direction: each first capacitor unit has a first arrangement (first via arrangement) of corresponding V_1st vias in the V_1st vias; and each second capacitor unit has a second arrangement (second via arrangement) of corresponding V_1st vias in the V_1st vias; and the first via arrangement is different from the second via arrangement.

[0272] In some embodiments, in each first capacitor cell, according to the first via arrangement: the V_1st via is substantially covered by a first overlapping portion of the corresponding M_1st segment and substantially covered by a second overlapping portion of the corresponding M_1st segment; and in each second capacitor cell, according to the second via arrangement: the V_1st via is substantially covered by a first overlapping portion of the corresponding M_1st segment and substantially covered by a second overlapping portion of the corresponding M_1st segment.

[0273] In some embodiments, in each first capacitor cell, according to the first via arrangement: the V_1st via is substantially not covered by the first overlapping portion of the corresponding M_1st segment, and is substantially not covered by the second overlapping portion of the corresponding M_1st segment; and in each second capacitor cell, according to the second via arrangement: the V_1st via is substantially not covered by the first overlapping portion of the corresponding M_1st segment, and is substantially not covered by the second overlapping portion of the corresponding M_1st segment.

[0274] In some embodiments, a method (for manufacturing a semiconductor device) includes: forming an array of capacitor cell regions, the capacitor cell regions being capacitor cells, each capacitor cell including one or more first capacitor cells and one or more second capacitor cells; and forming the array of capacitor cell regions includes: forming M_1st segments in a first metallization (M_1st) layer, the formation of the M_1st segments including: depositing a first layer of metallized first material as a precursor of the M_1st segments; etching the first layer to produce: first strips of first material extending in a first direction and having a first pitch relative to a second direction perpendicular to the first direction; and each first strip having a substantially first width relative to the first direction and having a substantially uniform first gap therebetween; for each capacitor cell, etching the first strips to produce M_1st segments such that: each capacitor cell has a first number of corresponding M_1st segments in the M_1st segments and a basic This uniform physical arrangement; relative to the second direction, the outermost M_1st segment of the M_1st segment is adjacent to the corresponding outer second gap and third gap, each of the second gap and third gap being larger than the first gap, and the relative first and second boundaries of the capacitor cells are respectively located in the third and fourth gaps; and, relative to the first direction, the relative third and fourth boundaries of each capacitor cell are respectively adjacent to (i) one or more substantially aligned first ends and (i) one or more substantially aligned second ends of the M_1st segments; and for each capacitor cell, the M_1st segment is correspondingly coupled to a first voltage or a second voltage such that: each first capacitor cell substantially provides a first capacitance; each second capacitor cell substantially provides a non-zero second capacitance different from the first capacitance; and the electrical arrangement of the M_1st segments is different for the second capacitor cells than for the first capacitor cells.

[0275] In some embodiments, the array forming the capacitor cell regions further includes: depositing a second layer of metallized second material as a precursor for the M_2nd segments; etching the second layer to produce: second strips of the second material extending in a third direction and having a second pitch relative to a vertical fourth direction; and each second strip having a substantially second width and a substantially uniform fourth gap between them relative to the third direction; for each capacitor cell, etching the second strips to produce the M_2nd segments such that: each capacitor cell has a second number of corresponding M_2nd segments and a substantially uniform physical arrangement; and for each capacitor cell, correspondingly coupling the M_2nd segments to a first voltage or a second voltage.

[0276] In some embodiments, the third direction is parallel to the first direction; the fourth direction is parallel to the second direction; the second pitch is smaller than the first pitch; and the second width is smaller than the first width.

[0277] In some embodiments, the third direction is parallel to the second direction; the fourth direction is parallel to the first direction; the second pitch is greater than the first pitch; and the second width is greater than the first width.

[0278] In some embodiments, the array forming the capacitor cell regions further includes: forming V_1st vias in a first interconnect (V_1st) layer above the M_1st layer, located on and electrically coupled to the corresponding M_1st segment of the M_1st segment; an M_2nd layer is located above the V_1st layer; etching a second layer further produces: a second strip located on and coupled to the corresponding M_2nd segment of the M_2nd segment; and forming V_1st vias relative to a first direction, a second direction, a third direction, and a fourth direction such that: each first capacitor cell has a first arrangement (first via arrangement) corresponding to the V_1st via; and each second capacitor cell has a second arrangement (second via arrangement) corresponding to the V_1st via; and the first via arrangement is different from the second via arrangement.

[0279] In some embodiments, forming a V_1st via further produces:

[0280] In each first capacitor cell, according to the first via arrangement, the V_1st via is substantially covered by the first overlapping portion of the corresponding M_1st segment and substantially covered by the second overlapping portion of the corresponding M_1st segment; and in each second capacitor cell, according to the second via arrangement, the V_1st via is substantially covered by the first overlapping portion of the corresponding M_1st segment and substantially covered by the second overlapping portion of the corresponding M_1st segment.

[0281] In some embodiments, the formation of the V_1st via is further produced as follows: in each first capacitor cell, according to the first via arrangement, the V_1st via is substantially not covered by the first overlapping portion of the corresponding M_1st segment, and substantially not covered by the second overlapping portion of the corresponding M_1st segment; and in each second capacitor cell, according to the second via arrangement, the V_1st via is substantially not covered by the first overlapping portion of the corresponding M_1st segment, and substantially not covered by the second overlapping portion of the corresponding M_1st segment.

[0282] In some embodiments, the semiconductor device includes: in a first metallization (M_1st) layer, M_1st segments extending in a first direction and having a first pitch, wherein each M_1st segment substantially has a first width and a substantially uniform first gap therebetween relative to a second direction perpendicular to the first direction; in a second metallization (M_2nd) layer, M_2nd segments extending in a third direction and having a second pitch, wherein each of the M_2nd segments substantially has a second width relative to a fourth direction perpendicular to the third direction; and capacitor cell regions (capacitor cells) arranged in an array, including one or more first capacitor cells and one or more second capacitor cells, wherein each capacitor cell has (i) a first number and substantially uniform physical arrangement of corresponding M_1st segments in the M_1st segments, and (ii) a second number of corresponding M_2nd segments in the M_2nd segments; and wherein, for each capacitor cell, The coupling between (A) the M_1st segment and the corresponding first or second voltage and (B) the coupling between the M_2nd segment and the corresponding first or second voltage are arranged such that: each first capacitor cell substantially provides a first capacitance; and each second capacitor cell substantially provides a non-zero second capacitance different from the first capacitance; wherein the electrical arrangement of the M_1st segments is different for the second capacitor cells than for the first capacitor cells; and wherein, for each capacitor cell: the first end of the odd-numbered M_1st segments and the second end of the even-numbered M_1st segments are substantially aligned with each other and are respectively adjacent to the opposing first and second boundaries of the capacitor cell; and relative to the second direction, the opposing third and fourth boundaries of the capacitor cell are located in the corresponding outermost M_1st segments in the adjacent M_1st segments; each of the second and third gaps is larger than the first gap.

[0283] In some embodiments, the semiconductor device further includes: in a first interconnect (V_1st) layer between the M_1st layer and the M_2nd layer, a V_1st via is coupled to a corresponding M_1st segment in the M_1st segment and a corresponding M_2nd segment in the M_2nd segment; and wherein, relative to the first direction, the second direction, the third direction, and the fourth direction: each first capacitor cell has a first arrangement (first via arrangement) of a corresponding V_1st via in the V_1st via; and each second capacitor cell has a second arrangement (second via arrangement) of a corresponding V_1st via in the V_1st via; and the first via arrangement is different from the second via arrangement.

[0284] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. Having read the foregoing specification, those skilled in the art will be able to influence various variations, equivalent substitutions, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: In the first metallization layer, first metallization segments extend in a first direction and have a first pitch, wherein, relative to a second direction perpendicular to the first direction, each first metallization segment substantially has a first width and a substantially uniform first gap between the first metallization segments; and A capacitor cell region arranged in an array, wherein the capacitor cell region is a capacitor cell, comprising one or more first capacitor cells and one or more second capacitor cells, wherein each capacitor cell has a first number of corresponding first metallized segments in the first metallized segments and a substantially uniform physical arrangement; and Wherein, for each of the capacitor cells, the coupling between the first metallization segment and the corresponding first voltage or second voltage is arranged such that: each of the first capacitor cells substantially provides a first capacitance; and each of the second capacitor cells substantially provides a non-zero second capacitance less than the first capacitance; The electrical arrangement of the first metallized section differs for the second capacitor cell from that for the first capacitor cell; and Wherein, for each of the capacitor cells: the first ends of the odd-numbered first metallized segments and the second ends of the even-numbered first metallized segments in the first metallized segments are substantially aligned with each other and are correspondingly adjacent to the opposing first and second boundaries of the capacitor cell; and with respect to the second direction, the opposing third and fourth boundaries of the capacitor cell are located in the corresponding outermost second and third gaps adjacent to the corresponding outermost first metallized segments in the first metallized segments; each of the second gap and the third gap is larger than the first gap.

2. The semiconductor device according to claim 1, wherein: The first number of the corresponding first metallized segments in the first metallized segment of each capacitor unit is N; Each capacitor unit has at most N-1 capacitor pairs; In each capacitor cell, the capacitor pair is a case where adjacent first metallized segments and second metallized segments in the first metallized segment are correspondingly coupled to different voltages of the first voltage or the second voltage, such that each capacitor pair provides a third capacitance less than or equal to the second capacitance. For each capacitor cell, the arrangement of the coupling between the first metallization segment and the corresponding first voltage or second voltage, relative to the second direction from the first side to the second side, defines a binary code, wherein the first voltage represents a logic value of one and the second voltage represents a logic value of zero. Each of the two α values ​​of the binary code corresponds to the first capacitor; and N is a positive integer.

3. The semiconductor device according to claim 2, wherein: The capacitor unit also includes one or more pseudo-capacitor units; In each of the pseudo-capacitor units, each of the first metallized segments is coupled to the first voltage, or each of the first metallized segments is coupled to the second voltage; Each of the two γ values ​​of the binary code corresponds to one or more pseudo-capacitor units.

4. The semiconductor device according to claim 1, further comprising: In the second metallization layer, the second metallization segments extend in a third direction and have a second pitch, wherein, relative to a fourth direction perpendicular to the third direction, each second metallization segment has a substantially second width and a substantially uniform fourth gap between the second metallization segments; and Wherein: for each of the capacitor cells, each of the second metallization segments is correspondingly coupled to the first voltage or the second voltage; and each of the capacitor cells has a second number of corresponding second metallization segments in the second metallization segments and a substantially uniform physical arrangement.

5. The semiconductor device according to claim 4, further comprising: In the first interconnect layer between the first metallization layer and the second metallization layer, a first interconnect via is coupled to a corresponding first metallization segment in the first metallization segment and a corresponding second metallization segment in the second metallization segment; and Wherein, relative to the first direction, the second direction, the third direction and the fourth direction: each of the first capacitor units has a first via arrangement of the corresponding first interconnect via in the first interconnect via; and each of the second capacitor units has a second via arrangement of the corresponding first interconnect via in the first interconnect via; and the first via arrangement is different from the second via arrangement.

6. The semiconductor device according to claim 5, wherein: In each of the first capacitor cells, according to the arrangement of the first via: the first interconnect via is substantially covered by a first overlapping portion of the corresponding first metallized segment, and substantially covered by a second overlapping portion of the corresponding first metallized segment; and In each of the second capacitor cells, according to the second via arrangement: the first interconnect via is substantially covered by the first overlapping portion of the corresponding first metallized segment, and substantially covered by the second overlapping portion of the corresponding first metallized segment.

7. The semiconductor device according to claim 6, wherein: In each of the first capacitor cells, according to the arrangement of the first via: the first interconnect via is substantially not covered by the first overlapping portion of the corresponding first metallized segment, and substantially not covered by the second overlapping portion of the corresponding first metallized segment; and In each of the second capacitor cells, according to the second via arrangement: the first interconnect via is substantially not covered by the first overlapping portion of the corresponding first metallized segment, and substantially not covered by the second overlapping portion of the corresponding first metallized segment.

8. A method for manufacturing a semiconductor device, the method comprising: An array of capacitor cell regions is formed, wherein the capacitor cell region is a capacitor cell, and the capacitor cell includes one or more first capacitor cells and one or more second capacitor cells; and, The array of capacitor cell regions includes forming a first metallization segment in a first metallization layer, wherein forming the first metallization segment includes: The first layer of the first material deposited and metallized serves as the precursor of the first metallized segment; The first layer is etched to produce: first strips of the first material extending in a first direction and having a first pitch relative to a second direction perpendicular to the first direction; and each of the first strips having a substantially first width relative to the first direction and a substantially uniform first gap between the first strips; For each capacitor cell, the first strip is etched to produce the first metallized segment, such that: each capacitor cell has a first number of corresponding first metallized segments in the first metallized segment and a substantially uniform physical arrangement; relative to the second direction, the outermost first metallized segment in the first metallized segment is adjacent to a correspondingly outer second gap and a third gap, each of the second gap and the third gap being larger than the first gap, and the opposing first and second boundaries of the capacitor cell are respectively located in the third and fourth gaps; and, relative to the first direction, the opposing third and fourth boundaries of each capacitor cell are correspondingly adjacent to (i) one or more substantially aligned first ends and (i) one or more substantially aligned second ends of the first metallized segments; and For each capacitor cell, the first metallization segment is correspondingly coupled to a first voltage or a second voltage such that: each of the first capacitor cells substantially provides a first capacitance; each of the second capacitor cells substantially provides a non-zero second capacitance different from the first capacitance; and the electrical arrangement of the first metallization segment is different for the second capacitor cell than for the first capacitor cell.

9. The method according to claim 8, wherein, The array forming the capacitor cell region further includes forming a second metallization segment in the second metallization layer, wherein forming the second metallization segment includes: The second layer of the deposited metallized second material serves as a precursor to the second metallized segment; The second layer is etched to produce: second strips of the second material extending upward in a third direction and having a second pitch relative to a vertical fourth direction; and each of the second strips having a substantially second width and a substantially uniform fourth gap between the second strips relative to the third direction; For each capacitor cell, the second strip is etched to create a second metallization segment, such that: each capacitor cell has a second number of corresponding second metallization segments in the second metallization segment and a substantially uniform physical arrangement; and For each capacitor cell, the second metallized segment is correspondingly coupled to the first voltage or the second voltage.

10. A semiconductor device, comprising: In the first metallization layer, first metallization segments extend in a first direction and have a first pitch, wherein, relative to a second direction perpendicular to the first direction, each first metallization segment has a substantially first width and a substantially uniform first gap between the first metallization segments. In the second metallization layer, the second metallization segments extend in a third direction and have a second pitch, wherein each of the second metallization segments has a substantially second width relative to a fourth direction perpendicular to the third direction; and A capacitor cell region arranged in an array, the capacitor cell region being a capacitor cell, includes one or more first capacitor cells and one or more second capacitor cells, wherein each capacitor cell has (i) a first number and substantially uniform physical arrangement of corresponding first metallized segments in the first metallized segment, and (ii) a second number of corresponding second metallized segments in the second metallized segment; and Wherein, for each of the capacitor cells, (A) the coupling between the first metallized segment and the corresponding first voltage or second voltage and (B) the coupling between the second metallized segment and the corresponding first voltage or second voltage are arranged such that: each of the first capacitor cells substantially provides a first capacitance; and each of the second capacitor cells substantially provides a non-zero second capacitance different from the first capacitance; The electrical arrangement of the first metallized section is different for the second capacitor cell than for the first capacitor cell; and Wherein, for each of the capacitor cells: the first ends of the odd-numbered first metallized segments and the second ends of the even-numbered first metallized segments in the first metallized segments are substantially aligned with each other and are correspondingly adjacent to the opposing first and second boundaries of the capacitor cell; and with respect to the second direction, the opposing third and fourth boundaries of the capacitor cell are located in the corresponding outermost first metallized segments in the first metallized segments in the corresponding outermost first metallized segments in the first metallized segments in the corresponding outermost first metallized segments in the first metallized segments in the first metallized segments in the second metallized segments in the second metallized segments in the second metallized segments in the third metallized segments in the second metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the second metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the third metallized segments in the fourth metallized segments in the fifth metallized segments in the third metallized segments in the fourth metallized segments in the fifth metallized segments in the third metallized segments in the fourth metallized segments in the fifth metallized segments in the third metallized segments in the fourth metallized segments in the fifth metallized segments in the fifth metallized segments in the third metallized segments in the fourth metallized segments in the fifth metallized segments in the fifth metallized segments in the first metallized segments in the second ...

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