A common-source common-gate device and a current detection method

Abstract

The application provides a common-source common-gate device and a current detection method, and relates to the technical field of semiconductors, and comprises a monolithic integrated junction field effect tube, a first transistor, a second transistor and a third transistor, wherein the first transistor, the second transistor and the third transistor are all insulated gate field effect tubes; the drain of the junction field effect tube forms a drain terminal of the common-source common-gate device; the source of the junction field effect tube is connected in series with the first transistor and the third transistor in parallel; the gate of the first transistor is interconnected with the drain of the second transistor and the gate of the third transistor to form a gate terminal of the common-source common-gate device; the source of the first transistor, the source of the second transistor and the source of the third transistor are interconnected to form a source terminal of the common-source common-gate device and serve as the gate of the junction field effect tube; a resistor is connected between the source of the third transistor and the source terminal, and the gate and the source of the second transistor are connected to opposite ends of the resistor, so that the device is automatically turned off when overcurrent occurs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a common-source cascode device and a current detection method. Background Technology

[0002] Silicon carbide (SiC), a wide-bandgap semiconductor material, possesses excellent properties such as high breakdown electric field strength, high carrier saturation drift velocity, high thermal conductivity, and good thermal stability, making it particularly suitable for high-voltage, high-power, high-temperature, and radiation-resistant power electronic devices. Among SiC power devices, metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are the most widely used voltage-controlled devices. Currently, planar SiC MOSFETs are the mainstream structure for commercial applications.

[0003] However, planar SiC MOSFETs suffer from a significant problem of excessive saturation current, which often reaches several times the rated current. Under load short-circuit conditions, the drain current rises sharply, and conventional overcurrent protection circuits, due to inherent delays in signal detection and turn-off drive, have slow response speeds and are unable to turn off the device in time before thermal damage occurs. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a common-source cascode device and a current detection method that can ensure device performance through overcurrent self-turn-off functionality.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: One aspect of this application provides a common-source cascode device, comprising: The monolithically integrated junction field-effect transistor, first transistor, second transistor, and third transistor are all insulated-gate field-effect transistors. The drain of the junction field-effect transistor forms the drain terminal of the common-source cascode device; The source of the junction field-effect transistor is connected in series with the first transistor and the third transistor, which are connected in parallel, respectively. The gate of the first transistor is interconnected with the drain of the second transistor and the gate of the third transistor to form the gate terminal of the common-source common-gate device; The source terminals of the first transistor, the second transistor, and the third transistor are interconnected to form the source terminal of the common-source common-gate device, and serve as the gate of the junction field-effect transistor. A resistor is connected between the source and the source terminal of the third transistor, and the gate and source of the second transistor are respectively connected to the opposite ends of the resistor.

[0006] Optionally, the first transistor, the second transistor, and the third transistor are all stacked on the junction field-effect transistor, and an insulating dielectric layer is provided between the first transistor and the junction field-effect transistor, the second transistor and the junction field-effect transistor, and the third transistor and the junction field-effect transistor.

[0007] Optionally, the junction field-effect transistor is a normally open device, and the first transistor, the second transistor, and the third transistor are normally closed devices.

[0008] Optionally, the junction field-effect transistor includes: The back metal, the first substrate, and the first epitaxial layer are stacked sequentially. A first ohmic contact area and a second ohmic contact area are provided on the surface of the first epitaxial layer. A connecting metal is provided on the first ohmic contact area, and a front metal is provided on the second ohmic contact area. The back metal serves as the drain of the junction field-effect transistor (JFET), the connecting metal serves as the source of the JFET, and the front metal serves as the gate of the JFET.

[0009] Optionally, a buried layer is provided in the first epitaxial layer, and the buried layer is provided at intervals from the first ohmic contact region and the second ohmic contact region, respectively; When the common source cascode device is in the off state, the depletion regions formed by the buried layer and the second ohmic contact region are connected.

[0010] Optionally, the first ohmic contact area is an N-type contact area, and the second ohmic contact area is a P-type contact area.

[0011] Optionally, the first epitaxial layer is a silicon carbide epitaxial layer.

[0012] Optionally, the first transistor and / or the second transistor includes: A silicon epitaxial layer having a third ohmic contact region and a fourth ohmic contact region, and a channel located between the third ohmic contact region and the fourth ohmic contact region; A gate oxide layer is disposed on the silicon epitaxial layer; A gate polysilicon is disposed on the gate oxide layer; The third ohmic contact area is in ohmic contact with the connecting metal, and the fourth ohmic contact area is in ohmic contact with the front metal.

[0013] Optionally, the connecting metal is a floating metal.

[0014] One aspect of this application provides a current detection method applied to the aforementioned common-source cascode device, comprising: Obtain the voltage information of the resistor of the common source cascode device; The first current information is obtained based on the voltage information, and the first current information is the current information between the drain terminal of the common source and common gate device and the source terminal of the third transistor. Based on the multiple relationship between the first current information and the second current information, the second current information is obtained. The second current information is the current information between the drain terminal of the common source and common gate device and the source terminal of the first transistor.

[0015] The beneficial effects of this application include: This application provides a common-source cascode device and a current detection method. It achieves monolithic integration of a low-voltage three-transistor and a high-voltage junction field-effect transistor using a heterojunction. Furthermore, it achieves overcurrent self-turn-off by monolithically integrating the third and second transistors. In the event of an overcurrent, the device automatically turns off without external circuitry, preventing damage due to overcurrent. The voltage drop across the external resistor Rext can be applied to the gate and source terminals of the second transistor. When the device's on-state current is too large, the voltage drop across Rext increases, and the second transistor gradually turns on. Since the drain and source terminals of the second transistor are connected to the gate and source terminals of the first transistor, the conducting second transistor pulls down the gate and source voltage of the first transistor, forcing the device to turn off, achieving overcurrent protection and ensuring device performance. Attached Figure Description To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a common-source, common-gate device provided in an embodiment of this application; Figure 2 This is a schematic diagram of a chip layout corresponding to a common source and common gate device provided in an embodiment of this application; Figure 3 This is an equivalent circuit diagram of a common-source cascode device provided in an embodiment of this application.

[0017] Icons: 1-Back metal; 2-First substrate; 3-First epitaxial layer; 4-Buried layer; 5-First ohmic contact region; 6-Second ohmic contact region; 7-Connecting metal; 8-Sidewall insulating layer; 9-Insulating dielectric layer; 10-Silicon epitaxial layer; 12-Gate oxide layer; 13-Gate polysilicon; 14-Interlayer dielectric; 15-Front metal; 21-First transistor; 22-Second transistor; 23-Third transistor; 110-Third ohmic contact region; 111-Fourth ohmic contact region. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Current planar SiC MOSFETs suffer from four main problems: 1) The channel mobility of SiC MOSFETs using existing processes is too low, severely impacting the device's turn-on capability; 2) The drive voltage of existing SiC MOSFETs is too high, typically requiring a gate voltage greater than 18V to drive them, making it impossible to directly use SiC MOSFETs in many applications originally designed for Si devices; 3) The reliability of the gate oxide layer in SiC MOSFETs is poor, mainly due to the large tunneling current between SiC and SiO2; 4) The saturation current of SiC MOSFETs is excessive, resulting in slow overcurrent protection response, especially under short-circuit conditions where timely turn-off is difficult, leading to device damage.

[0020] One aspect of the embodiments of this application refers to... Figure 1 A common-source cascode device is provided, comprising: The monolithically integrated junction field-effect transistor, first transistor 21, second transistor 22 and third transistor 23, all of which are insulated-gate field-effect transistors; The drain of a junction field-effect transistor forms the drain terminal of a cascode device; The source of the junction field-effect transistor is connected in series with the first transistor 21 and the third transistor 23, which are connected in parallel, respectively; The gate of the first transistor 21 is interconnected with the drain of the second transistor 22 and the gate of the third transistor 23 to form the gate terminal of the common source and common gate device. The source of the first transistor 21, the source of the second transistor 22, and the source of the third transistor 23 are interconnected to form the source terminal of the common-source common-gate device and serve as the gate of the junction field-effect transistor. A resistor is connected between the source and source terminals of the third transistor 23, and the gate and source terminals of the second transistor 22 are respectively connected to the opposite ends of the resistor.

[0021] The first transistor 21, the second transistor 22, and the third transistor 23 are all stacked on a junction field-effect transistor. The first transistor 21, the second transistor 22, and the third transistor 23 are all insulated-gate field-effect transistors. For example, the gate of the first transistor 21, the second transistor 22, and the third transistor 23 are all made of gate polysilicon 13. A vertical electric field is generated by the gate voltage to attract the induced charge in the semiconductor substrate to the surface to form a conductive channel, thereby controlling the on / off state and magnitude of the drain current.

[0022] The first transistor 21 and the third transistor 23 are symmetrically arranged on the junction field-effect transistor. The third transistor 23 has the same structure as the first transistor 21. The third transistor 23 acts as a current sensor and is formed using a small number of cells of the first transistor 21. Whether it is turned on or off, the first transistor 21 as the main device and the third transistor 23 as the current sensor are synchronized. Therefore, the currents of the first transistor 21 and the third transistor 23 have a definite multiple relationship N. An external resistor Rext is connected to the source port of the third transistor 23, such as... Figure 3 As shown, the actual current of the third transistor 23 can be calculated by testing the voltage across the external resistor Rext and by using Ohm's law. The current of the first transistor 21 can be calculated by using the multiple relationship N.

[0023] The second transistor 22 acts as a control transistor, controlling the turn-off of the first transistor 21 to achieve overcurrent self-turn-off functionality. Specifically, refer to... Figure 3 The voltage drop across the external resistor Rext can be applied to the gate and source terminals of the second transistor 22. When the device conduction current is too large, the voltage drop across Rext increases, and the second transistor 22 will gradually turn on. Since the drain and source terminals of the second transistor 22 are connected to the gate and source terminals of the first transistor 21, the turned-on second transistor 22 will pull down the gate and source voltage of the first transistor 21, forcing the device to turn off, thus achieving the effect of overcurrent protection.

[0024] In addition, the junction field-effect transistor is a normally open device, while the first transistor 21, the second transistor 22, and the third transistor 23 are normally closed devices.

[0025] The first transistor 21, the second transistor 22, and the third transistor 23 are normally closed devices. The second transistor 22 is a control transistor. When the conduction current is too large, the voltage drop of the gate-source voltage of the second transistor 22 increases, and the second transistor 22 turns on, so that the gate-source voltage of the first transistor 21 decreases and turns off.

[0026] The first transistor 21 and the third transistor 23 can only conduct when the gate-source voltage drop increases. When the first transistor 21 is on, the junction field-effect transistor is on; when the first transistor 21 is off, the junction field-effect transistor is off.

[0027] When a positive voltage is applied to the gate of a common-source cascode device, a high potential is applied to the drain, and a low potential is applied to the source, the MOS transistor below the first transistor 21 (or the third transistor 23) is turned on. Since the junction field-effect transistor above is a normally open device, the device enters the conducting state at this time. Current flows from the drain through the junction field-effect transistor above and the MOS below into the source to form a current, thereby turning on the device.

[0028] Specifically, junction field-effect transistors include: The back metal 1, the first substrate 2, and the first epitaxial layer 3 are stacked sequentially; the first substrate 2 is an N-type silicon carbide substrate, and the first epitaxial layer 3 is an N-type silicon carbide epitaxial layer. A first ohmic contact region 5 and a second ohmic contact region 6 are provided on the surface of the first epitaxial layer 3. A connecting metal 7 is provided on the first ohmic contact region 5, and a front metal 15 is provided on the second ohmic contact region 6. The first ohmic contact region 5 is an N-type silicon carbide ohmic contact region, the second ohmic contact region 6 is a P-type silicon carbide ohmic contact region, the connecting metal 7 is formed by Al metal filling or tungsten plug, and the front metal 15 is formed by AlCu or other metal materials. The back metal 1 serves as the drain of the junction field-effect transistor and as the drain terminal of the cascode device; the connecting metal 7 serves as the source of the junction field-effect transistor and is connected to the drain of the first transistor 21 (third ohmic contact region 110) and the drain of the third transistor 23 (third ohmic contact region 110); and the front metal 15 serves as the gate of the junction field-effect transistor.

[0029] Connecting metal 7 is a floating metal, which does not form a direct electrical connection with the power supply, ground, external pins or other active devices.

[0030] A buried layer 4 is provided in the first epitaxial layer 3, and the buried layer 4 is provided at intervals with the first ohmic contact region 5 and the second ohmic contact region 6 respectively; wherein, the buried layer 4 is a P-type silicon carbide buried layer.

[0031] When the cascode device is in the off state, the depletion regions formed by the buried layer 4 and the second ohmic contact region 6 are connected.

[0032] The buried layer 4 is specifically a P-type silicon carbide buried layer, which is formed by high-energy ion implantation or multilayer epitaxy. In the multilayer epitaxy method, the P-type buried layer is formed by ion implantation after the first epitaxy is completed, and then the second epitaxy is performed.

[0033] When the gate is connected to a negative voltage or no bias voltage is set, the drain is connected to a high potential and the source is connected to a low potential. At this time, the MOS below the first transistor 21 (or current sensor) is blocked. The blocking voltage of the MOS will be applied to the gate and source ends of the junction field-effect transistor (between the first ohmic contact region 5 and the second ohmic contact region 6) to form a reverse bias, forcing the junction field-effect transistor to turn off (the depletion region of the buried layer 4 and the second ohmic contact region 6 is connected) and bear the voltage. At this time, the junction field-effect transistor will bear most of the voltage, and the MOS will bear a small part of the voltage. The device enters the blocking state.

[0034] The first transistor 21 and / or the second transistor 22 include: The silicon epitaxial layer 10 has a third ohmic contact region 110 and a fourth ohmic contact region 111, and a channel located between the third ohmic contact region 110 and the fourth ohmic contact region 111; the third ohmic contact region 110 and the fourth ohmic contact region 111 are N-type silicon ohmic contact regions. Gate oxide layer 12 is disposed on silicon epitaxial layer 10; Gate polysilicon 13 is disposed on gate oxide layer 12, and gate polysilicon 13 serves as the gate of first transistor 21 and gate of second transistor 22; The third ohmic contact area 110 (the drain of the first transistor 21 and the drain of the second transistor 22) is in 7-ohm contact with the connecting metal, and the fourth ohmic contact area 111 (the source of the first transistor 21 and the source of the second transistor 22) is in 15-ohm contact with the front metal.

[0035] The structure of the third transistor 23 is the same as that of the first transistor 21, and will not be described in detail here.

[0036] An insulating dielectric layer 9 is provided between the first transistor 21 and the junction field-effect transistor (JFET), the second transistor 22 and the JFET, and the third transistor 23 and the JFET. The dielectric layer 9 can be made of silicon dioxide or other insulating materials. By providing the insulating dielectric layer 9, parasitic transistor effects between transistors are avoided, signal crosstalk is prevented, and each transistor can operate independently.

[0037] In addition, a sidewall insulating layer 8, made of silicon dioxide or other insulating material, is provided between the first ohmic contact area 5 and the third ohmic contact area 110, and between the second ohmic contact area 6 and the fourth ohmic contact area 111. An interlayer dielectric 14, made of silicon dioxide or other insulating material, is also provided between the connecting metal 7 and the front metal 15, both serving an isolation function.

[0038] Correspondingly, its corresponding chip schematic diagram is as follows: Figure 2As shown, the front side of the chip includes a first transistor 21 (gate PAD), a source PAD, a second transistor 22 (drain PAD), a second transistor 22 (gate PAD), and a third transistor 23 (source PAD). The back side of the chip is the drain. These PADs are connected to... Figure 1 There is a corresponding relationship between the electrodes with the same name in the model.

[0039] The gate PAD of the first transistor 21 and the drain PAD of the second transistor 22 are shorted together by interconnecting the leads, and the gate PAD of the second transistor 22 and the source PAD of the third transistor 23 are shorted together by interconnecting the leads.

[0040] Finally, after packaging, the device will have leads such as Figure 2 The gate port, source port, drain port, and source port of the third transistor 23 are shown in the diagram.

[0041] Optionally, the gate of the first transistor 21 and the drain of the second transistor 22 are shorted together by the internal metal of the chip through the layout design, and the gate of the second transistor 22 and the source of the third transistor 23 are shorted together by the internal metal of the chip through the layout design.

[0042] In summary, the common-source cascode device provided in this application realizes the monolithic integration of a low-voltage SiMOSFET (three transistors) and a high-voltage SiC JFET (junction field-effect transistor) through a heterojunction. Furthermore, the device achieves overcurrent self-turn-off by monolithically integrating the third transistor 23 and the second transistor 22. When an overcurrent occurs, the device automatically turns off without the need for external circuitry, preventing damage to the device due to overcurrent.

[0043] Furthermore, the use of Si MOSFET (gate polysilicon 13) for current conduction avoids the high interface state density problem of existing SiC MOS channels and improves the channel mobility of the device; at the same time, the use of Si MOS for switching the device is fully compatible with the Si MOSFET driving scheme; and the use of Si MOS for switching the device means that the part directly driven by voltage is Si MOS, thus avoiding the problem of low gate oxide reliability of existing SiC MOS.

[0044] When the current is forward-conducting, it passes sequentially through the back metal 1, the first substrate 2, the first epitaxial layer 3, through the buried layer 4 and the second ohmic contact region 6, through the first ohmic contact region 5, the connecting metal 7, the third ohmic contact region 110, the silicon epitaxial layer 10, the fourth ohmic contact region 111, and the front metal 15. Since the first substrate 2, the first epitaxial layer 3, the first ohmic contact region 5, and the third ohmic contact region 110 are all N-type, there is no PN junction. This ensures that the forward-conducting current does not cross the heterojunction (PN junction) barrier, thus avoiding the influence of the heterojunction on the conduction characteristics. Similarly, the reverse current does not pass through the heterojunction epitaxial layer, thus avoiding the problem of increased leakage current caused by lattice mismatch.

[0045] On the other hand, embodiments of this application also provide a current detection method applied to the aforementioned common-source cascode device, the method comprising: Step 300: Obtain the voltage information of the resistor of the common source cascode device.

[0046] Reference Figure 3 Test the voltage across the external resistor Rext.

[0047] Step 301: Obtain the first current information based on the voltage information. The first current information is the current information between the drain terminal of the common source and common gate device and the source terminal of the third transistor 23.

[0048] The actual current of the third transistor 23 was calculated using Ohm's law.

[0049] Step 302: Based on the multiple relationship between the first current information and the second current information, the second current information is obtained. The second current information is the current information between the drain terminal of the common source and common gate device and the source terminal of the first transistor 21.

[0050] Since the currents of the first transistor 21 and the third transistor 23 have a definite multiple relationship N, the current on the first transistor 21 can be calculated through the multiple relationship N.

[0051] This current detection method incorporates the same structure and beneficial effects as the cascode device in the foregoing embodiments. The structure and beneficial effects of the cascode device have been described in detail in the foregoing embodiments and will not be repeated here.

[0052] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A common-source, common-gate device, characterized in that, include: The monolithically integrated junction field-effect transistor, first transistor (21), second transistor (22) and third transistor (23) are all insulated-gate field-effect transistors; The drain of the junction field-effect transistor forms the drain terminal of the common-source cascode device; The source of the junction field-effect transistor is connected in series with the first transistor (21) and the third transistor (23) which are connected in parallel, respectively; The gate of the first transistor (21) is interconnected with the drain of the second transistor (22) and the gate of the third transistor (23) to form the gate terminal of the common source cascode device; The source of the first transistor (21), the source of the second transistor (22) and the source of the third transistor (23) are interconnected to form the source terminal of the common source cascode device and serve as the gate of the junction field-effect transistor. A resistor is connected between the source and the source terminal of the third transistor (23), and the gate and source of the second transistor (22) are respectively connected to the opposite ends of the resistor.

2. The cascode device as described in claim 1, characterized in that, The first transistor (21), the second transistor (22) and the third transistor (23) are all stacked on the junction field-effect transistor. An insulating dielectric layer (9) is provided between the first transistor (21) and the junction field-effect transistor, the second transistor (22) and the junction field-effect transistor, and the third transistor (23) and the junction field-effect transistor.

3. The common-source, common-gate device as described in claim 1 or 2, characterized in that, The junction field-effect transistor is a normally open device, and the first transistor (21), the second transistor (22), and the third transistor (23) are normally closed devices.

4. The common-source, common-gate device as described in claim 3, characterized in that, The junction field-effect transistor includes: The back metal (1), the first substrate (2) and the first epitaxial layer (3) are stacked in sequence. A first ohmic contact area (5) and a second ohmic contact area (6) are provided on the surface of the first epitaxial layer (3). A connecting metal (7) is provided on the first ohmic contact area (5), and a front metal (15) is provided on the second ohmic contact area (6). The back metal (1) serves as the drain of the junction field-effect transistor, the connecting metal (7) serves as the source of the junction field-effect transistor, and the front metal (15) serves as the gate of the junction field-effect transistor.

5. The common-source, common-gate device as described in claim 4, characterized in that, A buried layer (4) is provided in the first epitaxial layer (3), and the buried layer (4) is provided at intervals from the first ohmic contact area (5) and the second ohmic contact area (6); When the common source cascode device is in the off state, the depletion regions formed by the buried layer (4) and the second ohmic contact region (6) are connected.

6. The common-source, common-gate device as described in claim 4, characterized in that, The first ohmic contact area (5) is an N-type contact area, and the second ohmic contact area (6) is a P-type contact area.

7. The common-source, common-gate device as described in claim 4, characterized in that, The first epitaxial layer (3) is a silicon carbide epitaxial layer.

8. The common-source, common-gate device as described in claim 4, characterized in that, The first transistor (21) and / or the second transistor (22) include: The silicon epitaxial layer (10) has a third ohmic contact region (110) and a fourth ohmic contact region (111), and a channel located between the third ohmic contact region (110) and the fourth ohmic contact region (111); A gate oxide layer (12) is disposed on the silicon epitaxial layer (10); A gate polysilicon (13) is disposed on the gate oxide layer (12); The third ohmic contact area (110) is in ohmic contact with the connecting metal (7), and the fourth ohmic contact area (111) is in ohmic contact with the front metal (15).

9. The common-source, common-gate device as described in claim 4, characterized in that, The connecting metal (7) is a floating metal.

10. A current detection method, characterized in that, The method, applied to the common-source cascode device according to any one of claims 1 to 9, comprises: Obtain the voltage information of the resistor of the common source cascode device; The first current information is obtained based on the voltage information. The first current information is the current information between the drain terminal of the common source and common gate device and the source terminal of the third transistor (23). Based on the multiple relationship between the first current information and the second current information, the second current information is obtained. The second current information is the current information between the drain terminal of the common source and common gate device and the source terminal of the first transistor (21).

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