Integrated circuit device

Abstract

An integrated circuit device and a manufacturing method thereof are provided, in which, in the integrated circuit device, a curved channel layer is arranged to improve electrical characteristics, and a gate insulating material is not formed in an inner spacer formed on a sidewall of a source / drain region, thereby reducing a parasitic capacitance.

Description

Cross-reference to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0044274, filed on April 4, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application discloses an integrated circuit device. More specifically, this disclosure relates to an integrated circuit device comprising a nanosheet field-effect transistor. Background Technology

[0003] Due to advancements in electronic technology, the size of integrated circuit devices is rapidly shrinking. Therefore, it is essential to maintain high operating speeds and minimize leakage current to ensure operational accuracy. Various studies are underway to provide integrated circuit devices with structures that reduce leakage current and improve electrical reliability. Summary of the Invention

[0004] This disclosure provides an integrated circuit device having an all-ring gate (GAA) structure including a curved channel, wherein the curved channel has a transition metal dichalcogenide (TMD).

[0005] Furthermore, the problems to be solved by one or more technical ideas disclosed herein are not limited to those mentioned above, and other problems will be clearly understood by those skilled in the art from the following description.

[0006] An integrated circuit device is provided below: According to one or more aspects of this disclosure, an integrated circuit device is provided, comprising: an active region extending on a substrate in a first horizontal direction; a plurality of channel layers disposed on the active region, vertically separated from each other, and extending in the first horizontal direction; oxide layers disposed below the plurality of channel layers; gate lines extending on the active region in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers and the oxide layers; source / drain regions disposed on the active region and contacting the plurality of channel layers; and an inner spacer, wherein the inner spacer includes a sidewall contacting a sidewall of the source / drain region, another sidewall opposite to the sidewall and covering a sidewall of the gate line, and upper and lower surfaces respectively contacting the plurality of channel layers, wherein the plurality of channel layers comprise transition metal dichalcogenide (TMD) compounds, and wherein each of the plurality of channel layers includes a plurality of convex bending units in a vertical direction.

[0007] According to one or more aspects of this disclosure, an integrated circuit device is provided, comprising: an active region extending on a substrate along a first horizontal direction; a plurality of channel layers disposed vertically apart from each other on the active region and extending along the first horizontal direction; a first oxide layer and a second oxide layer disposed apart from each other, each of the plurality of channel layers being located between the first oxide layer and the second oxide layer; a gate line extending on the active region along a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, the first oxide layer and the second oxide layer; a source / drain region disposed on the active region and contacting the plurality of channel layers; and an inner spacer, wherein the inner spacer includes a sidewall contacting a sidewall of the source / drain region, another sidewall opposite to the sidewall and covering the sidewall of the gate line, and an upper surface and a lower surface each contacting the plurality of channel layers, wherein the plurality of channel layers comprise a transition metal dichalcogenide (TMD) compound, and wherein each of the plurality of channel layers includes a plurality of convex bending units in a vertical direction.

[0008] According to one or more aspects of this disclosure, an integrated circuit device is provided, comprising: an active region extending on a substrate along a first horizontal direction; a nanosheet stack including the plurality of nanosheets facing the upper surface of the active region at locations where the nanosheets are separated from the upper surface of the active region in a vertical direction; a gate line extending on the active region in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of nanosheets, the gate line including sub-gates disposed between the plurality of nanosheets adjacent to each other in the vertical direction, the sub-gates being positioned at the lowest nanosheets and the active region. The system comprises: a nanosheet covering the topmost nanosheet; a source / drain region in contact with the nanosheets; an insulating spacer covering the sidewalls of the main gate; an inner spacer disposed between the sub-gate and the source / drain region; and a first oxide layer disposed between the lower surface of the nanosheets and the gate line, wherein the first oxide layer is separated from the source / drain by the inner spacer, and wherein the nanosheets comprise transition metal dichalcogenide (TMD) compounds, and the upper and lower surfaces of the nanosheets comprise a plurality of raised, uneven units in the vertical direction. Attached Figure Description

[0009] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is the layout of the integrated circuit device according to the embodiment; Figure 2A It is the edge of integrated circuit device Figure 1 A cross-sectional view taken by line X1-X1' in the diagram; Figure 2B It is the edge of integrated circuit device Figure 1 A cross-sectional view taken from line Y1-Y1' in the diagram; Figure 2C It is the edge of integrated circuit device Figure 1 A cross-sectional view taken from line Y2-Y2' in the middle; Figures 3 to 14 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment; Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 11 , Figure 12 , Figure 13 and Figure 14 It is an integrated circuit device and along Figure 1 The area corresponding to the cross-section intercepted by line X1-X1' in the diagram is based on the cross-sectional diagram of the corresponding process step. Figure 10B yes Figure 10A Enlarged view of part of the image; Figures 15 to 17 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment; and Figure 18 It is the edge of integrated circuit device Figure 1 Another cross-sectional view taken from line X1-X1' in the diagram. Specific Implementation

[0010] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same constituent parts, and repeated descriptions thereof are omitted.

[0011] Because various modifications can be applied to the embodiments and this disclosure can have various embodiments, specific embodiments are shown and described in detail in the accompanying drawings. However, this is not intended to limit this disclosure to a particular mode of practice, and it should be understood that all modifications, equivalents, and substitutions without departing from the spirit and scope of this disclosure are included herein. In the description of the embodiments, certain detailed descriptions of the related technologies may be omitted where it is thought that certain detailed descriptions of the related technologies may unnecessarily obscure the nature of the embodiments.

[0012] Figure 1 This is the layout of the integrated circuit device 100 according to the embodiment. Figure 2A It is the edge of integrated circuit device 100 Figure 1 The cross-sectional view taken by line X1-X1' in the diagram. Figure 2B It is the edge of integrated circuit device 100 Figure 1 The cross-sectional view taken from line Y1-Y1' in the diagram. Figure 2C It is the edge of integrated circuit device 100 Figure 1The cross-sectional view taken from line Y2-Y2' in the diagram.

[0013] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C According to this disclosure, the integrated circuit device 100 can refer to an integrated circuit device that includes nanowire or nanosheet-shaped active regions and has an all-around gate (GAA) structure surrounding the nanowire or nanosheet-shaped active regions. For example, the integrated circuit device 100 may include a multi-bridge channel field-effect transistor (MBCFET) device. However, this disclosure is not limited thereto, and the integrated circuit device 100 may also include a planar field-effect transistor (FET) device, a fin-type FET (FinFET) device, etc.

[0014] In some embodiments, the integrated circuit device 100 may include an active region F1 protruding from a substrate 102 to define a trench region T1 on the substrate 102. A plurality of active regions F1 may extend parallel to each other on the substrate 102 along a first horizontal direction (X direction) and may be arranged separately from each other along a second horizontal direction (Y direction).

[0015] In some embodiments, the integrated circuit device 100 may include an active region F1 protruding from the substrate 102 to define a trench region T1 on the substrate 102.

[0016] In some embodiments, substrate 102 may include semiconductors (such as Si and Ge) or compound semiconductors (such as SiGe, SiC, GaAs, InAs, InGaAs, and InP). The terms SiGe, SiC, GaAs, InAs, InGaAs, and InP as used in this disclosure may refer to materials comprising the elements included in each term, but may not be referred to as chemical formulas representing stoichiometric relationships. Substrate 102 may include conductive regions comprising, for example, impurity-doped wells or impurity-doped structures.

[0017] In some embodiments, the device separation layer 112 may be disposed in a trench region T1 defining an active region F1. The device separation layer 112 may cover a portion of the sidewall of the active region F1 in the trench region T1 and may be separated from the substrate 102 in the vertical direction (Z direction). The device separation layer 112 may include a silicon oxide layer.

[0018] In some embodiments, a plurality of gate lines 160 may be arranged on an active region F1. Each of the plurality of gate lines 160 may extend longitudinally in a second horizontal direction (Y direction). A plurality of nanosheet stacks NSS may be arranged on the upper fin surface FT of the active region F1 in the region where the active region F1 intersects with the plurality of gate lines 160. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the upper fin surface FT in a vertical direction (Z direction) at a location separated from the upper fin surface FT of the active region F1. As used in this disclosure, the term "nanosheet" may refer to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. Nanosheets should be understood to include nanowires.

[0019] In some embodiments, each of the plurality of nanosheet stacks NSS may include a plurality of nanosheet channel layers N1, N2, and N3 that overlap each other in the vertical direction (Z direction) on the active region F1. The vertical direction (Z direction) distances from the upper fin surface FT of the active region F1 to the plurality of nanosheet channel layers N1, N2, and N3 may be different from each other. Each of the plurality of gate lines 160 may surround the nanosheet channel layers N1, N2, and N3 that overlap each other in the vertical direction (Z direction) included in the nanosheet stack NSS.

[0020] exist Figure 1 In this embodiment, the nanosheet stack NSS has a generally rectangular planar shape, but the embodiments are not limited to this. The nanosheet stack NSS can have various planar shapes depending on the planar shape of each of the active region F1 and the gate line 160. In the embodiment, multiple nanosheet stack NSSs and multiple gate lines 160 can be arranged on one of the active regions F1, and a configuration in which multiple nanosheet stack NSSs are arranged in rows on one of the active regions F1 in a first horizontal direction (X direction) is shown. However, the number of each of the nanosheet stack NSSs and gate lines 160 arranged on the active region F1 is not particularly limited.

[0021] In some embodiments, each of the plurality of nanosheet channel layers N1, N2, and N3 may have a thickness ranging from about 0.6 nm to about 3 nm, but is not limited thereto. For example, in some embodiments, the plurality of nanosheet channel layers N1, N2, and N3 may have a thickness of about 1.2 nm. In this case, the thickness of each of the plurality of nanosheet channel layers N1, N2, and N3 may refer to the dimension in the vertical direction (Z direction). In some embodiments, the plurality of nanosheet channel layers N1, N2, and N3 may have substantially the same thickness in the vertical direction (Z direction). In some other embodiments, at least some of the plurality of nanosheet channel layers N1, N2, and N3 may have different thicknesses in the vertical direction (Z direction).

[0022] In some embodiments, the plurality of nanosheet channel layers N1, N2, and N3 included in one of the nanosheet stacks NSS may have the same or similar dimensions in a first horizontal direction (X direction). In some other embodiments, with Figure 2A Unlike the examples shown, at least some of the multiple nanosheet channel layers N1, N2, and N3 included in one of the nanosheet stacks NSS can have different dimensions from each other in the first horizontal direction (X direction). Figure 2A In this embodiment, each of the plurality of nanosheet stacks NSS includes three nanosheet channel layers (e.g., a first nanosheet channel layer N1, a second nanosheet channel layer N2, and a third nanosheet channel layer N3), but this disclosure is not limited thereto. For example, the nanosheet stack NSS may include at least one channel layer, and the number of channel layers constituting the nanosheet stack NSS is not particularly limited.

[0023] In some embodiments, the plurality of nanosheet channel layers N1, N2, and N3 may comprise two-dimensional semiconductor materials. In this case, the two-dimensional material may represent a material with a layered structure in which the constituent atoms are bonded in a two-dimensional manner. Two-dimensional materials with semiconductor properties exhibit excellent electrical properties, and their properties do not change significantly even when the thickness is reduced to the nanometer scale, and they can maintain high mobility. For example, the plurality of nanosheet channel layers N1, N2, and N3 may comprise transition metal dichalcogenides (TMDs).

[0024] In some embodiments, the TMD can be a two-dimensional material with semiconductor properties and can be a compound of transition metals and chalcogenides. In this case, the transition metal can include at least one of, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re, and the chalcogenides can include at least one of, for example, S, Se, and Te. The TMD can include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, etc., but this disclosure is not limited thereto.

[0025] In some embodiments, the cross-sections of the plurality of nanosheet channel layers N1, N2, and N3 may have curvature. The cross-sections of the plurality of nanosheet channel layers N1, N2, and N3 may have an upwardly convex arc or semi-circular shape. In this case, the curvatures of the plurality of nanosheet channel layers N1, N2, and N3 may be consistent with each other, such as... Figure 2A As shown, but this is just an example. The curvature of one or more of the multiple nanosheet channel layers N1, N2, and N3 can also be different from each other, and Figure 2A The illustrations do not limit this disclosure.

[0026] In some embodiments, a gate dielectric layer 152 may be disposed between a plurality of nanosheet channel layers N1, N2, and N3 and a gate line 160. The gate dielectric layer 152 may be formed at the interface between the plurality of nanosheet channel layers N1, N2, and N3 and the gate line 160. The gate dielectric layer 152 may be disposed between an oxide layer 105 formed on the side surfaces, top surfaces, and bottom surfaces of the plurality of nanosheet channel layers N1, N2, and N3 and the gate line 160. The gate dielectric layer 152 may be formed surrounding the plurality of nanosheet channel layers N1, N2, and N3 and the oxide layer 105. For example, the gate dielectric layer 152 may cover the upper surface of the plurality of nanosheet channel layers N1, N2 and N3, the lower surface of the oxide layer 105, and the sidewalls of the plurality of nanosheet channel layers N1, N2 and N3 and the oxide layer 105 in the second horizontal direction (Y direction), and may extend in the first horizontal direction (X direction).

[0027] In some embodiments, the plurality of nanosheet channel layers N1, N2 and N3 may have a single-layer or multi-layer structure, wherein each layer may have an atomic-level thickness.

[0028] In the case of the integrated circuit device according to the comparative example, the insulating layer can be arranged between the gate line and the inner spacer. On the other hand, in the integrated circuit device 100 of this disclosure, since the gate insulating material is not formed at the location where the inner spacer 150 is formed, the parasitic capacitance can be reduced by reducing the area of ​​the unnecessary insulating layer.

[0029] In some embodiments, oxide layer 105 may be disposed between each of the plurality of sub-gates 160S and the plurality of nanosheet channel layers N1, N2, and N3. Oxide layer 105 may support the plurality of nanosheet channel layers N1, N2, and N3 beneath each of the plurality of nanosheet channel layers N1, N2, and N3. Oxide layer 105 may be formed to have a conformal thickness, and may also have a curved shape due to the curved upper surfaces of the plurality of sub-gates 160S. Figure 2A The oxide layer 105 is shown to be disposed only beneath the plurality of nanosheet channel layers N1, N2, and N3, but this disclosure is not limited thereto. (See also...) Figure 18 In the integrated circuit device 100a, an oxide layer 105 can be formed on both the upper and lower portions of multiple nanosheet channel layers N1, N2, and N3. A first oxide layer 105_1 can be disposed below the multiple nanosheet channel layers N1, N2, and N3, and a second oxide layer 105_2 can be disposed on the multiple nanosheet channel layers N1, N2, and N3. Because the first oxide layer 105_1 and the second oxide layer 105_2 can also be used as gate dielectric layers, when... Figure 18 When both the upper and lower parts of the sub-gate 160S are covered by the first oxide layer 105_1 and the second oxide layer 105_2, the gate dielectric layer 152 can be omitted.

[0030] In some embodiments, each of the plurality of gate lines 160 may include a main gate 160M and a plurality of sub-gates 160S. The main gate 160M may cover the upper surface of the nanosheet stack NSS and may extend in a second horizontal direction (Y direction). The plurality of sub-gates 160S may be integrally connected to the main gate 160M and may be respectively arranged between each of the plurality of nanosheet channel layers N1, N2 and N3 and between the active region F1 and the nanosheet channel layer N3 arranged at the bottommost end. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gates 160S may be less than the thickness of the main gate 160M.

[0031] In some embodiments, each of the plurality of gate lines 160 may comprise a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may include one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may include one of TiN and TaN. The metal carbide may include TiAlC. However, the materials constituting the plurality of gate lines 160 are not limited to the examples described above.

[0032] In some embodiments, a plurality of active region recesses R1 may be formed on the active region F1. The vertical level of the lowermost surface of each of the plurality of active region recesses R1 may be lower than the vertical level of the upper surface FT of the fin of the active region F1.

[0033] In some embodiments, a plurality of source / drain regions 130 may be arranged between each of a plurality of gate lines 160. Each of the plurality of source / drain regions 130 may be arranged at a position adjacent to at least one of the plurality of gate lines 160. Each of the plurality of source / drain regions 130 may have a surface facing a plurality of nanosheet channel layers N1, N2 and N3 adjacent thereto.

[0034] In some embodiments, each of the plurality of inner spacers 150 may be disposed between the plurality of sub-gates 160S and the plurality of source / drain regions 130. One sidewall of an inner spacer 150 may contact a sub-gate 160S, and the other sidewall opposite to that sidewall may contact a source / drain region 130. Additionally, each of the upper and lower surfaces of the inner spacers 150 may contact the plurality of nanosheet channel layers N1, N2, and N3. The plurality of inner spacers 150 may cover the sidewalls of the sub-gates 160S in a first horizontal direction (X direction). Pairs of inner spacers 150 may be separated from each other in the first horizontal direction (X direction), with the sub-gates 160S between the pairs of inner spacers 150. In this case, the inner spacers 150 may comprise silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof.

[0035] In some embodiments, some of the sidewalls of the plurality of source / drain regions 130 may contact the inner spacer 150, while other sidewalls may contact the plurality of nanosheet channel layers N1, N2, and N3. In other words, the plurality of source / drain regions 130 may not be in direct contact with the oxide layer 105. In some embodiments, instead of the oxide layer 105, the inner spacer 150 may be disposed below the plurality of nanosheet channel layers N1, N2, and N3 in a region adjacent to the plurality of source / drain regions 130, which is the region where the inner spacer 150 is disposed. This may be the result of a process that removes a portion of the oxide layer 105 to form the inner spacer 150, as will be referred to below. Figure 10A and Figure 10B Described.

[0036] In some embodiments, each of the plurality of source / drain regions 130 may include an epitaxially grown semiconductor layer. In some embodiments, each of the plurality of source / drain regions 130 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers. When the source / drain region 130 comprises an NMOS transistor, the source / drain region 130 may include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant. The n-type dopant may include phosphorus (P), arsenic (As), or antimony (Sb). When the source / drain region 130 comprises a PMOS transistor, the source / drain region 130 may include a SiGe layer doped with a p-type dopant. The p-type dopant may include boron (B) or gallium (Ga).

[0037] In some embodiments, multiple nanosheet stacks (NSS) can be arranged on the fin surface FT of each of the multiple active regions F1 in the regions where the multiple active regions F1 intersect with the multiple gate lines 160, and multiple FETs can be formed on the substrate 102 in the regions where the multiple active regions F1 intersect with the multiple gate lines 160.

[0038] In some embodiments, a capping insulating pattern 168 may be disposed on the gate line 160. The capping insulating pattern 168 may cover the upper surface of the main gate 160M. The capping insulating pattern 168 may include a silicon nitride layer and a silicon oxide layer.

[0039] In some embodiments, the two sidewalls of the main gate 160M can be covered by a first insulating spacer 118. The first insulating spacer 118 can be formed on the two sidewalls of the main gate 160M on the upper surface of the plurality of nanosheet stacks NSS, and a capping insulating pattern 168 can be disposed on the first insulating spacer 118 and the gate line 160.

[0040] In some embodiments, a plurality of second insulating spacers 119 covering each of one sidewall of the source / drain region 130 and the other sidewall facing that sidewall may be arranged on the upper surface of the device separation layer 112. In some embodiments, each of the plurality of second insulating spacers 119 may be integrally connected to an adjacent first insulating spacer 118. In some other embodiments, at least some of the plurality of second insulating spacers 119 may be omitted.

[0041] In some embodiments, each of the plurality of first insulating spacers 118 and the plurality of second insulating spacers 119 may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof. The terms “SiCN,” “SiBN,” “SiON,” “SiOCN,” “SiBCN,” and “SiOC” as used herein may refer to materials comprising the elements included in each term, but may not be referred to as chemical formulas representing stoichiometric relationships.

[0042] In some embodiments, a metal silicide layer 172 may be disposed on the upper surface of each of the plurality of source / drain regions 130. The metal silicide layer 172 may comprise a metal containing Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide layer 172 may comprise titanium silicide, but is not limited thereto.

[0043] In some embodiments, the insulating pad 142 and the gate-to-gate insulating layer 144 may be sequentially disposed on a plurality of source / drain regions 130 and a plurality of metal silicide layers 172. The first insulating spacer 118 and the plurality of source / drain regions 130 may be covered by the insulating pad 142. In some embodiments, the insulating pad 142 may include, but is not limited to, silicon nitride (SiN), SiCN, SiBN, SiON, SiOCN, SiBCN, or combinations thereof. The gate-to-gate insulating layer 144 may include, but is not limited to, a silicon oxide layer.

[0044] In some embodiments, a plurality of source / drain contacts CA may be disposed on a plurality of source / drain regions 130. Each of the plurality of source / drain contacts CA may penetrate the insulating pad 142 and the gate insulating layer 144 in the vertical direction (Z direction) and may be configured to be electrically connected to at least one of the plurality of source / drain regions 130. Each of the plurality of source / drain contacts CA may contact a metal silicide layer 172 formed on the source / drain region 130. Each of the plurality of source / drain contacts CA may be configured to be electrically connected to the source / drain region 130 via the metal silicide layer 172. Each of the plurality of source / drain contacts CA may be separated from the main gate 160M of the gate line 160 in a first horizontal direction (X direction), with a first insulating spacer 118 between each of the source / drain contacts CA and the main gate 160M.

[0045] In some embodiments, each of the plurality of source / drain contacts CA may include a conductive barrier layer 174 and a contact plug 176. The lower surface and sidewalls of the contact plug 176 may be covered by the conductive barrier layer 174. The conductive barrier layer 174 may include a metal or a conductive metal nitride. For example, the conductive barrier layer 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, but is not limited thereto. The contact plug 176 may include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), or combinations thereof, or alloys thereof, but is not limited thereto. In other embodiments, the conductive barrier layer 174 may be omitted from each of the plurality of source / drain contacts CA.

[0046] In some embodiments, the upper surface of each of the source / drain contacts CA, the capping insulating pattern 168, the insulating pad 142, and the gate insulating layer 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop layer 182 and an interlayer insulating layer 184, which are sequentially stacked on each of the plurality of source / drain contacts CA, the plurality of capping insulating patterns 168, and the gate insulating layer 144. The etch stop layer 182 may include SiC, SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or combinations thereof. The interlayer insulating layer 184 may include an oxide layer, a nitride layer, an ultra-low k (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4, or combinations thereof. For example, the interlayer insulating layer 184 may include, but is not limited to, a tetraethyl orthosilicate (TEOS) layer, a high-density plasma (HDP) layer, a borosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiOC layer, a SiCOH layer, or a combination thereof.

[0047] In some embodiments, a plurality of source / drain via contacts VA may be disposed on a plurality of source / drain contacts CA. Each of the plurality of source / drain via contacts VA may penetrate the upper insulating structure 180 and contact the source / drain contact CA. Each of the plurality of source / drain regions 130 may be configured to be electrically connected to the source / drain via contact VA via a metal silicide layer 172 and the source / drain contact CA. The lower surface of each of the plurality of source / drain via contacts VA may contact the upper surface of the source / drain contact CA. Each of the plurality of source / drain via contacts VA may include, but is not limited to, Mo or W.

[0048] In some embodiments, the upper surface of each of the upper insulating structure 180 and the plurality of source / drain via contacts VA may be covered by the upper insulating layer 192. The material of the upper insulating layer 192 may be substantially the same as the material of the interlayer insulating layer 184 described above.

[0049] In some embodiments, a plurality of upper wiring layers M1 may be arranged to penetrate the upper insulating layer 192. Each of the plurality of upper wiring layers M1 may be electrically connected to one of the source / drain via contacts VA below it, selected from a plurality of source / drain via contacts VA. The plurality of upper wiring layers M1 may include, but are not limited to, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof.

[0050] Figures 3 to 14 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device 100 according to an embodiment. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 11 , Figure 12 , Figure 13 and Figure 14 It is the integrated circuit device 100 and its edge Figure 1 The area corresponding to the cross-section intercepted by line X1-X1' in the diagram is based on the cross-sectional diagram of the corresponding process step. Figure 10B yes Figure 10A A partially enlarged image. (Refer to...) Figures 3 to 14 It describes the manufacturing reference. Figures 1 to 2C An example method of describing the integrated circuit device 100. The following is related to... Figures 1 to 2C The same reference numerals may denote the same components, and repeated descriptions thereof are omitted.

[0051] Reference Figure 3 A sacrificial layer 104 can be formed on the substrate 102. The sacrificial layer 104 may include a bottom unit 104B and an upper surface unit 104T, and the bottom unit 104B and the upper surface unit 104T may include the same material. The lower surface of the sacrificial layer 104 may be formed as flat and coplanar with the upper surface of the substrate 102, and the upper surface of the sacrificial layer 104 may include a plurality of protrusions. In other words, the upper surface unit 104T of the sacrificial layer 104 may not be parallel to the upper surface of the substrate 102 and may be formed as a curved shape.

[0052] The bottom unit 104B and the top surface unit 104T of the sacrificial layer 104 can also be formed integrally or sequentially. When the bottom unit 104B and the top surface unit 104T of the sacrificial layer 104 are formed sequentially, the bottom unit 104B can be conformally formed on the top surface of the substrate 102 with a certain thickness. Then, a plurality of nanocrystals can be arranged on the top surface of the bottom unit 104B. Subsequently, a plurality of nanocrystals can be grown to form upwardly convex protrusions on the bottom unit 104B. In this case, the size and / or density of the nanocrystals arranged on the bottom unit 104B can vary according to the user's settings, and therefore this disclosure is not limited thereto. The bottom unit 104B and the top surface unit 104T of the sacrificial layer 104 may include Si.

[0053] In some embodiments, substrate 102 may include elemental semiconductors such as Si and Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, InGaAs, and InP. Substrate 102 may include a first surface 102_1 and a second surface 102_2 opposite to the first surface 102_1. A plurality of active regions F1 may extend on the first surface 102_1 of substrate 102 along a first horizontal direction (X direction). Sacrificial layer 104 may be disposed on the fin surface FT of each of the plurality of active regions F1.

[0054] Reference Figure 4 , can Figure 3 An oxide layer 105 is formed on the resulting product. In some embodiments, the oxide layer 105 may also be formed naturally, but it may also be obtained by oxidizing the surface of the sacrificial layer 104. The oxide layer 105 may be formed on the upper surface of the sacrificial layer 104 with a conformal thickness, and since the upper surface unit 104T of the sacrificial layer 104 has a curved upper surface, the oxide layer 105 may also be deposited on the sacrificial layer 104 in a curved shape.

[0055] Reference Figure 5 and Figure 6 A nanosheet layer NS of a certain thickness can be formed on the oxide layer 105. In this case, the nanosheet layer NS can be transferred from the carrier substrate CS and attached to the oxide layer 105.

[0056] After the nanosheets NS are formed on the carrier substrate CS, the carrier substrate CS can be flipped so that the nanosheets NS face the upper surface of the substrate 102, and the carrier substrate CS can be attached to the substrate 102 (see reference). Figure 5 In this case, in order to attach the nanosheet layer NS to the substrate 102, a process of applying heat and / or pressure can be performed additionally.

[0057] In some embodiments, the sacrificial layer 104 and the nanosheet layer NS may comprise semiconductor materials with different etch selectivity. In some embodiments, the nanosheet layer NS may comprise a TMD.

[0058] In some embodiments, the thickness of the nanosheet NS in the vertical direction (Z direction) can be approximately 1.2 nm. However, the embodiments are not limited to this. For example, the thickness of the nanosheet NS can range from approximately 0.6 mm to approximately 3 mm.

[0059] The type of carrier substrate CS is not limited, but the carrier substrate CS can include flexible materials. This is likely because the oxide layer 105 has a curved shape; therefore, in the process of attaching the carrier substrate CS to the oxide layer 105, all surfaces of the oxide layer 105 may need to be in contact with the nanosheet layer NS of the carrier substrate CS. When the nanosheet layer NS is attached to the oxide layer 105, the carrier substrate CS can be removed, thus, as... Figure 6 As shown, a curved nanosheet layer NS can be formed. The upper surface NS_S of the nanosheet layer NS may not be parallel to the upper surface of the substrate 102, and may have an upwardly convex shape similar to the upper surface unit 104T of the sacrificial layer 104. In some embodiments, an oxide layer 105 may support the nanosheet layer NS beneath it.

[0060] Reference Figure 7 A sacrificial layer 104 can be formed again on the nanosheet layer NS. The sacrificial layer 104 may include a bottom unit 104B and an upper surface unit 104T. (See reference...) Figure 3 The bottom unit 104B and the upper surface unit 104T of the sacrificial layer 104 can be formed simultaneously or sequentially.

[0061] although Figure 7 The convex bending units of the sacrificial layer 104, which are separated from each other in the vertical direction (Z direction) (with nanosheet layers NS located therebetween), may include substantially the same curvature, but the embodiments are not limited thereto, and the individual convex bending units may have different curvatures from each other.

[0062] Reference Figure 8 , can be Figure 7 The resulting products and stacked structures are sequentially executed using reference. Figures 3 to 7 The described process involves multiple sacrificial layers 104, multiple oxide layers 105, and multiple nanosheets NS that can be alternately stacked in a stacked structure SS. The multiple nanosheets NS can have a single-layer or multi-layer structure. Figure 8 In this invention, three of the nanosheets NS are included in the stacked structure SS, but this is merely an example and does not limit this disclosure.

[0063] In some embodiments, such as Figure 8 As shown, the bending patterns on the upper and lower surfaces of the multiple nanosheets NS can be identical. However, the embodiments are not limited to this, and the bending patterns on the upper and lower surfaces of the multiple nanosheets NS can be different from each other.

[0064] Reference Figure 9 Multiple pseudo-gate structures (DGS) can be formed on a stacked structure of multiple sacrificial layers 104 and multiple nanosheet layers NS.

[0065] Each of the plurality of dummy gate structures DGS can be formed to extend in a second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS can have a structure in which an oxide layer D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked. In some embodiments, the dummy gate layer D124 may comprise polysilicon, and the capping layer D126 may comprise a silicon nitride layer.

[0066] Reference Figure 10A After forming a plurality of first insulating spacers 118 covering the two sidewalls of each of the plurality of dummy gate structures DGS, portions of the plurality of sacrificial layers 104 and the plurality of nanosheet layers NS (see reference) can be etched by using the plurality of dummy gate structures DGS and the plurality of first insulating spacers 118 as an etching mask. Figure 9 The result is that multiple nanosheet layers NS can be divided into multiple nanosheet stacks NSS, each nanosheet stack NSS including multiple nanosheet channel layers N1, N2 and N3. By using an etching process, a stacked pattern SP including multiple sacrificial layers 104 and multiple nanosheet channel layers N1, N2 and N3 can be formed.

[0067] By using an etching process, multiple active region recesses R1 and multiple source / drain spaces SDS can be formed to expose the sidewalls of the stacked pattern SP. To form multiple active region recesses R1 and multiple source / drain spaces SDS, the etching process can be performed using a dry etching process, a wet etching process, or a combination thereof.

[0068] Reference Figure 10B Each of the plurality of active region recesses R1 may further include a plurality of active region sidewall recesses R1_S. The plurality of active region sidewall recesses R1_S can be obtained by further removing portions of the sidewalls of the sacrificial layer 104 and oxide layer 105 with a specific thickness relative to the plurality of active region recesses R1. Because the plurality of nanosheet channel layers N1, N2, and N3 are not removed during this process, the ends of the plurality of nanosheet channel layers N1, N2, and N3 can protrude from the sacrificial layer 104 and oxide layer 105 due to the plurality of active region sidewall recesses R1_S.

[0069] Reference Figure 11 It can form an inner spacer 150 that fills multiple active region sidewall recesses R1_S, and can form multiple source / drain regions 130 that fill multiple active region recesses R1.

[0070] In some embodiments, the inner spacer 150 may cover the sidewalls of a plurality of sacrificial layers 104 and oxide layers 105 in a first horizontal direction (X direction). Pairs of inner spacers 150 may be formed to be separated from each other in the first horizontal direction (X direction), with the sacrificial layers 104 and oxide layers 105 between the pairs of inner spacers 150. Additionally, each of the upper and lower surfaces of the inner spacer 150 may contact a plurality of nanosheet channel layers N1, N2, and N3. In this case, the inner spacer 150 may comprise silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof.

[0071] In some embodiments, in order to form a plurality of source / drain regions 130, semiconductor materials can be epitaxially grown from the sidewalls of each of a plurality of nanosheet channel layers N1, N2 and N3 exposed at a plurality of active region recesses R1 and from the surface of a plurality of active regions F1.

[0072] Insulating pads 142 can be deposited on multiple source / drain regions 130, and then an inter-gate insulating layer 144 can be formed on the insulating pads 142. Then, by etching corresponding portions of the insulating pads 142 and corresponding portions of the inter-gate insulating layer 144, multiple capping layers D126 can be exposed (see reference). Figure 10A The upper surface of the gate layer D124 can then be removed to expose the dummy gate layer D124, and the insulating pad 142 and the inter-gate insulating layer 144 can be partially removed so that the upper surface of the inter-gate insulating layer 144 and the upper surface of the dummy gate layer D124 are approximately at the same level.

[0073] Reference Figure 12 , through from Figure 11 Removing the pseudo-gate layer D124 and pseudo-oxide layer D122 from the obtained product can provide the gate space GS.

[0074] Reference Figure 13 By using the gate space GS from Figure 12 The resulting product selectively removes multiple sacrificial layers 104 retained on substrate 102, and the gate space GS can extend to the space between each of the multiple nanosheet channel layers N1, N2 and N3 and the space between the first nanosheet channel layer N1 and the upper surface of the fin FT.

[0075] Reference Figure 14 A gate dielectric layer 152 can be formed covering the exposed surfaces of each of multiple nanosheet channel layers N1, N2, and N3, multiple oxide layers 105, and multiple active regions F1. An atomic layer deposition (ALD) process can be used to form the gate dielectric layer 152. Subsequently, a gate-filled space GS (refer to...) can be formed on the gate dielectric layer 152. Figure 13The gate line 160. Then, a portion of the gate line 160 and the first insulating spacer 118 can be removed from the upper surface of each of the gate line 160 and the first insulating spacer 118 to reduce their respective heights, and a plurality of capping insulating patterns 168 can be formed covering the upper surface of each of the gate line 160 and the first insulating spacer 118.

[0076] In some embodiments, gate line 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. An ALD process or a chemical vapor deposition (CVD) process may be used to form gate line 160. Gate line 160 may be formed separately from a plurality of nanosheet channel layers N1, N2, and N3 and a plurality of oxide layers 105, with gate dielectric layer 152 located between the plurality of nanosheet channel layers N1, N2, and N3 and oxide layers 105.

[0077] In some embodiments, each of the plurality of gate lines 160 may include a main gate 160M and a plurality of sub-gates 160S.

[0078] Refer again Figure 2A Multiple source / drain contact holes can be formed, which penetrate the insulating structure including the insulating pad 142 and the gate inter-insulator layer 144, and expose multiple source / drain regions 130. Through the source / drain contact holes, specific areas of the multiple source / drain regions 130 can be removed using an anisotropic etching process, so that the multiple source / drain contact holes can further extend toward the substrate 102.

[0079] Subsequently, a portion of the source / drain regions 130 exposed through multiple source / drain contact holes can be processed, and thus, a metal silicide layer 172 can be formed. In some embodiments, to form the metal silicide layer 172, a metal pad conformally covering the exposed surfaces of the source / drain regions 130 can be formed, and a process can be included to initiate a reaction between the source / drain regions 130 and the metal constituting the metal pad by applying a heat treatment. After forming the metal silicide layer 172, the remaining portion of the metal pad can be removed. In some embodiments, when the metal silicide layer 172 comprises titanium silicide, the metal pad may comprise a titanium layer. Source / drain contacts CA comprising a conductive barrier layer 174 and contact plugs 176 can be formed on the metal silicide layer 172.

[0080] Subsequently, an upper insulating structure 180 can be formed by sequentially forming an etch stop layer 182 and an interlayer insulating layer 184 covering the upper surfaces of each of the gate inter-insulating layer 144, the plurality of source / drain contacts CA, and the plurality of capping insulating patterns 168. A plurality of source / drain via contacts VA can be formed that penetrate the upper insulating structure 180 in the vertical direction (Z direction) and are respectively connected to the plurality of source / drain contacts CA.

[0081] Subsequently, an upper insulating layer 192 can be formed covering the upper surface of the upper insulating structure 180 and each of the multiple source / drain via contacts VA, and multiple upper wiring layers M1 can be formed penetrating the upper insulating layer 192 in the vertical direction (Z direction) and respectively connected to the multiple source / drain via contacts VA.

[0082] The process described above can be used to manufacture Figure 1 and Figures 2A to 2C Integrated circuit device 100.

[0083] In the integrated circuit device 100 according to the present disclosure, a sacrificial layer 104 having a curved upper surface may be disposed on a substrate 102 to induce local strain. In this case, for example, the upper surface of the sacrificial layer 104 can be formed with an overall curved shape by growing a plurality of nanocrystals separated from each other, and the curvature can be adjusted by controlling the size and / or density of the nanocrystals. Next, a plurality of nanosheet channel layers N1, N2, and N3 comprising a TMD material may be sequentially formed between the plurality of sacrificial layers 104. Before forming each of the plurality of nanosheet channel layers N1, N2, and N3 on the sacrificial layer 104, an oxide layer 105 may be formed on the upper surface of the sacrificial layer 104, and the oxide layer 105 may support each of the plurality of nanosheet channel layers N1, N2, and N3, and may also serve as a gate dielectric together with a gate dielectric layer 152. Because the integrated circuit device 100 according to this disclosure has a curved channel layer as a result of the above-described process, the electrical characteristics of the integrated circuit device 100 can be improved, and because gate insulating material does not need to be deposited in the inner spacer 150, the parasitic capacitance of the integrated circuit device 100 can be reduced.

[0084] Figures 15 to 17 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit apparatus 100a according to an embodiment. Figure 18 It is an integrated circuit device 100a along Figure 1 The cross-sectional view taken by line X1-X1' in the diagram. This will be understood. Figures 15 to 18 Integrated circuit device 100a and reference Figure 1 , Figures 2A to 2B , Figures 3 to 9 , Figures 10A to 10B as well as Figures 11 to 14 The integrated circuit devices 100 described herein are not mutually exclusive, and components having the same reference numerals may be identical. Hereinafter, repeated descriptions of identical components are omitted, and the description is consistent with the references. Figure 1 , Figures 2A to 2B , Figures 3 to 9 , Figures 10A to 10B and Figures 11 to 14The differences in the description of the given integrated circuit device 100.

[0085] Reference Figure 15 A sacrificial layer 104 can be formed on the upper surface FT of the active region F1 of the substrate 102, and a first oxide layer 105_1, a nanosheet layer NS, and a second oxide layer 105_2 can be sequentially formed on the sacrificial layer 104.

[0086] In some embodiments, the sacrificial layer 104 may include a bottom unit 104B and an upper surface unit 104T, and the nanosheet layer NS may include a TMD material. The oxide layer 105 may include a first oxide layer 105_1 and a second oxide layer 105_2. The first oxide layer 105_1 and the second oxide layer 105_2 may include substantially the same material. In some embodiments, the first oxide layer 105_1 and the second oxide layer 105_2 may have the same thickness, but this is only an example, and the first oxide layer 105_1 and the second oxide layer 105_2 may also have different thicknesses.

[0087] The processes for forming the sacrificial layer 104 and the nanosheet layer NS can be compared with those for reference. Figure 3 and Figure 5 The process described is the same. The process for forming the first oxide layer 105_1 can be the same as the one described above. Figure 4 The processes described are the same, and the process for forming the second oxide layer 105_2 can be the same as the process for forming the first oxide layer 105_1.

[0088] Reference Figure 16 , can Figure 15 A sacrificial layer 104 is formed on the resulting product. (Refer to...) Figure 16 The described process can be compared with the reference. Figure 7 The process is the same, except that the nanosheets NS can be formed on the second oxide layer 105_2 instead of directly on the sacrificial layer 104.

[0089] Reference Figure 17 This allows for the formation of a stacked structure SS, where the sacrificial layer 104, the first oxide layer 105_1, the nanosheet layer NS, and the second oxide layer 105_2 are alternately stacked on the substrate 102. This can be achieved by repeatedly performing the reference... Figure 15 and Figure 16 The described process is used to form the stacked structure SS. Figure 17 In this example, the stacked structure SS includes three nanosheet layers NS, but this is merely an example and does not limit this disclosure.

[0090] Next, in the execution reference Figure 9 , Figure 10A , Figure 11 , Figure 12 , Figure 13 and Figure 14 Following the same process described, a metal silicide layer 172, multiple source / drain contacts CA including a conductive barrier layer 174 and contact plugs 176, an upper insulating structure 180 including an etch stop layer 182 and an interlayer insulating layer 184, multiple source / drain via contacts VA, an upper insulating layer 192, and an upper wiring layer M1 can be formed. Figure 18 Integrated circuit device 100a.

[0091] exist Figure 18 In the integrated circuit device 100a, with Figure 2A The integrated circuit device 100 differs from the previous one because the first oxide layer 105_1 is formed on the upper part of the plurality of nanosheet channel layers N1, N2 and N3, and the second oxide layer 105_2 is formed below the lower part of the plurality of nanosheet channel layers N1, N2 and N3. Therefore, in reference... Figure 10A and Figure 10B In the described process, when the sacrificial layer 104 is removed from the sidewall recesses R1_S of multiple active regions with a certain thickness, two portions of the first oxide layer 105_1 and the second oxide layer 105_2 can also be removed together with the sacrificial layer 104 with a certain thickness.

[0092] Refer again Figure 18 Since the first oxide layer 105_1 and the second oxide layer 105_2 can also be used together with the gate dielectric layer 152 as the gate dielectric layer, the gate dielectric layer 152 can surround the sub-gate 160S because both the upper and lower portions of the sub-gate 160S can be covered by the first oxide layer 105_1 and the second oxide layer 105_2. However, in some other embodiments, the gate dielectric layer 152 surrounding the sub-gate 160S can be omitted.

[0093] As described above with reference to integrated circuit device 100, according to the present disclosure, an integrated circuit device 100a may deposit a sacrificial layer 104 having a curved upper surface on a substrate 102 to induce local strain. In this case, for example, the upper surface of the sacrificial layer 104 may be formed in an overall curved shape by growing a plurality of nanocrystals that are separated from each other, and the curvature may be adjusted by controlling the size and / or density of the nanocrystals. Next, a plurality of nanosheet channel layers N1, N2, and N3 comprising a TMD material may be sequentially formed between the plurality of sacrificial layers 104. Before forming each of the plurality of nanosheet channel layers N1, N2, and N3 on the sacrificial layer 104, a first oxide layer 105_1 may be formed on the upper surface of the sacrificial layer 104, and after forming each of the plurality of nanosheet channel layers N1, N2, and N3, a second oxide layer 105_2 may be formed on the upper surface of the plurality of nanosheet channel layers N1, N2, and N3. The oxide layer 105 can support each of the plurality of nanosheet channel layers N1, N2, and N3, and can also be used as a gate dielectric together with the gate dielectric layer 152. Because the integrated circuit device 100a according to this disclosure has a curved channel layer as a result of the above-described process, the electrical characteristics of the integrated circuit device 100a can be improved, and because the gate insulating material is not deposited in the inner spacer 150, the parasitic capacitance of the integrated circuit device 100a can be reduced.

[0094] As described above, embodiments have been disclosed in the accompanying drawings and this disclosure. While embodiments have been described herein with reference to specific terminology, it should be understood that they are for illustrative purposes only and not for limiting the scope of the disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments are possible without departing from the scope of this disclosure. Consequently, the true scope of this disclosure should be determined by the appended claims.

Claims

1. An integrated circuit device, comprising: An active region extending along a first horizontal direction on a substrate; Multiple channel layers, which are separated from each other in the active region in a vertical direction and extend in the first horizontal direction; Oxide layers respectively beneath the plurality of channel layers; A gate line extends over the active region in a second horizontal direction that intersects the first horizontal direction and surrounds the plurality of channel layers and the oxide layer; Source / drain regions that are located on the active region and in contact with the plurality of channel layers; as well as An inner spacer, wherein the inner spacer comprises: A sidewall that contacts the sidewall of the source / drain region; Another sidewall, which is opposite to said one sidewall and on the sidewall of the gate line; and Upper and lower surfaces, each of which is in contact with the plurality of channel layers. The plurality of channel layers include transition metal dichalcogenide (TMD) compounds, and Each of the plurality of channel layers includes a plurality of convex bending units in the vertical direction.

2. The integrated circuit device according to claim 1, wherein, The thickness of each of the plurality of channel layers is in the range of 0.6 nm to 3 nm.

3. The integrated circuit device according to claim 1, wherein, The oxide layer is separated from the source / drain region in the first horizontal direction, and the inner spacer is located between the oxide layer and the source / drain region.

4. The integrated circuit device according to claim 1, wherein, The gate line includes: The sub-gate, located between adjacent channel layers in the vertical direction and between the lowest channel layer and the active region in the plurality of channel layers. The sub-gate surrounds the upper surface of the plurality of channel layers, the side surfaces of the plurality of channel layers, the side surface of the oxide layer, and the lower surface of the oxide layer.

5. The integrated circuit device according to claim 1, further comprising: A gate dielectric layer is present on the sidewalls of the gate lines, the surfaces of the plurality of channel layers, and the surface of the oxide layer.

6. The integrated circuit device according to claim 1, wherein, At least two of the plurality of convex bending units include substantially the same curvature.

7. The integrated circuit device according to claim 1, wherein, At least two of the plurality of convex bending units have different curvatures.

8. The integrated circuit device according to claim 1, wherein, The width of the plurality of channel layers extending in the first horizontal direction is greater than the width of each of the oxide layers in the first horizontal direction.

9. The integrated circuit device according to claim 1, wherein, The bending pattern on the upper surface of the plurality of channel layers corresponds to the bending pattern on the lower surface of the plurality of channel layers.

10. The integrated circuit device according to claim 1, wherein, The lower surfaces of the plurality of channel layers are coplanar with the upper surface of the oxide layer.

11. An integrated circuit device, comprising: The active region extends along a first horizontal direction on the substrate; Multiple channel layers, which are separated from each other in the active region in a vertical direction and extend in the first horizontal direction; A first oxide layer and a second oxide layer are separated from each other, and the plurality of channel layers are located between the first oxide layer and the second oxide layer; A gate line extends over the active region along a second horizontal direction that intersects the first horizontal direction and surrounds the plurality of channel layers, the first oxide layer and the second oxide layer; Source / drain regions are located on the active region and are in contact with the plurality of channel layers; as well as Internal spacer, comprising: A sidewall that contacts the sidewall of the source / drain region; Another sidewall, which is opposite to and covers the sidewall of the gate line; and Upper and lower surfaces, each of which is in contact with the plurality of channel layers. The plurality of channel layers include transition metal dichalcogenide (TMD) compounds, and Each of the plurality of channel layers includes a plurality of convex bending units in the vertical direction.

12. The integrated circuit device according to claim 11, wherein, The first oxide layer is below the plurality of channel layers, and the second oxide layer is on the plurality of channel layers.

13. The integrated circuit device according to claim 11, wherein, The upper surface of the first oxide layer is coplanar with the lower surface of the plurality of channel layers, and the lower surface of the second oxide layer is coplanar with the upper surface of the plurality of channel layers.

14. The integrated circuit device according to claim 11, wherein, The gate line includes: The sub-gate, located between adjacent channel layers in the vertical direction and between the lowest channel layer and the active region in the plurality of channel layers. The sub-gate surrounds the upper surface of the second oxide layer, the side surfaces of the plurality of channel layers, the side surfaces of the first oxide layer and the second oxide layer, and the lower surface of the first oxide layer.

15. The integrated circuit device according to claim 11, wherein, The thickness of each of the plurality of channel layers is in the range of 0.6 nm to 3 nm.

16. The integrated circuit device according to claim 11, wherein, The width of the plurality of channel layers extending in the first horizontal direction is greater than the width of the first oxide layer in the first horizontal direction.

17. The integrated circuit device according to claim 11, wherein, The bending pattern on the upper surface of the plurality of channel layers corresponds to the bending pattern on the lower surface of the plurality of channel layers.

18. An integrated circuit device, comprising: An active region extending along a first horizontal direction on a substrate; A nanosheet stack comprising a plurality of nanosheets separated in the vertical direction from the upper surface of the active region; A gate line extends over the active region in a second horizontal direction intersecting the first horizontal direction and surrounds the plurality of nanosheets. The gate line includes a sub-gate between adjacent nanosheets in the vertical direction, between the lowermost nanosheet and the active region, and on the uppermost nanosheet. The source / drain region is in contact with the plurality of nanosheets; An insulating spacer is located on the sidewall of the gate line; An inner spacer is located between the sub-gate and the source / drain regions; as well as A first oxide layer is formed between the lower surface of the plurality of nanosheets and the gate line. The inner spacer is located between the first oxide layer and the source / drain region, and The plurality of nanosheets comprises transition metal dichalcogenide (TMD) compounds, and the upper and lower surfaces of the plurality of nanosheets comprise a plurality of raised, uneven units in the vertical direction.

19. The integrated circuit device of claim 18, further comprising a second oxide layer between the upper surface of the plurality of nanosheets and the gate line.

20. The integrated circuit device according to claim 18, wherein, The thickness of each of the plurality of nanosheets is in the range of 0.6 nm to 3 nm.

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