Backside contacts for devices with wide source / drain regions

Abstract

Techniques are provided herein for forming integrated circuits having semiconductor devices with source or drain regions formed using different epitaxial growth profiles. An integrated circuit includes a first semiconductor region extending from a first source or drain region in a first direction, and a second semiconductor region extending from a second source or drain region in the first direction. The second source or drain region can be wider than the first source or drain region along the first direction. The second source or drain region includes a first epitaxial region having one or more epitaxial layers and a second epitaxial region having one or more additional epitaxial layers on the first epitaxial region. Each of the first and second epitaxial regions can include at least one epitaxial layer doped with one or more n-type or p-type dopants and at least one layer that is substantially undoped.

Description

Background Technology

[0001] As integrated circuits continue to shrink in size, numerous challenges arise. For example, reducing the size of memory and logic cells within interconnect structures becomes increasingly difficult due to the reduction in device spacing at device layers. The small size of transistor elements such as gates, sources, or drains makes it challenging to provide efficient contact while maintaining desired operating speeds and power requirements. Therefore, many significant challenges remain in forming such high-density semiconductor devices. Attached Figure Description

[0002] Figure 1A and Figure 1B These are cross-sectional views of different semiconductor devices in an integrated circuit including different source or drain widths and different epitaxial regions, according to embodiments of the present disclosure.

[0003] Figure 2A and Figure 2B This is a cross-sectional view illustrating a stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to an embodiment of the present disclosure.

[0004] Figure 3A and Figure 3B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0005] Figure 4A and Figure 4B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0006] Figure 5A and Figure 5B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0007] Figure 6A and Figure 6B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0008] Figure 7A and Figure 7B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0009] Figure 8A and Figure 8B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0010] Figure 9A and Figure 9B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0011] Figure 10A and Figure 10B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0012] Figure 10B 'This is an example illustrating an embodiment according to this disclosure.' Figure 10B A cross-sectional view of the alternative epitaxial growth profile of a semiconductor device.

[0013] Figure 11A and Figure 11B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0014] Figure 12A and Figure 12B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0015] Figure 13A and Figure 13B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0016] Figure 14A and Figure 14B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0017] Figure 15A and Figure 15B This is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit with different semiconductor devices having source or drain regions with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0018] Figure 16 A cross-sectional view of a chip package comprising one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0019] Figure 17 This is a flowchart of a manufacturing process for forming different semiconductor devices with different epitaxial growth profiles, according to embodiments of the present disclosure.

[0020] Figure 18 A computing system comprising one or more integrated circuits as described in various ways herein is illustrated according to embodiments of the present disclosure.

[0021] Although the following detailed description is based on illustrative embodiments, many alternatives, modifications, and variations will be apparent from the present disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For example, while some drawings generally indicate perfect straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines and right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topology or otherwise be unsmooth, given the real-world limitations of the processing devices and technologies used. Detailed Implementation

[0022] This document provides techniques for forming integrated circuits having semiconductor devices with source or drain regions of different sizes (e.g., different widths) formed using different epitaxial growth profiles. This technique can be used in any number of integrated circuit applications and is particularly useful for logic and memory cells, such as those using fin field-effect transistors (FINFETs) or all-around gate transistors (e.g., stripe FETs and nanowire FETs) or forked-plate transistors. In one such example, the integrated circuit may include a first device having a first semiconductor region extending from a first source or drain region in a first direction, and a second device having a second semiconductor region extending from a second source or drain region in the first direction. The second source or drain region may be wider along the first direction than the first source or drain region, such as at least twice as wide. Epitaxial growth of semiconductor material to form the first source or drain region may be insufficient to form enough semiconductor material for the second source or drain region. According to some embodiments, additional epitaxial growth processes are performed to form another epitaxial region in the second source or drain region. Therefore, a first epitaxial region having one or more epitaxial layers can be formed first, and then a second epitaxial region having one or more epitaxial layers can be formed on the first epitaxial region. Each of the first and second epitaxial regions may include at least one epitaxial layer doped with one or more n-type or one or more p-type dopants and at least one layer that is substantially undoped (e.g., no n-type or p-type dopants deposited). According to some embodiments, a more robust epitaxial profile of the second source or drain region allows for better contact between the back-side contact and the second source or drain region. Many variations and embodiments will be apparent from this disclosure. General Overview

[0023] As mentioned above, many significant challenges remain regarding integrated circuit manufacturing. As devices become smaller and more densely packaged, the contact area to transistor elements such as source or drain regions also decreases. Furthermore, integrated devices of varying sizes present their own set of design challenges. In some examples, logic and memory devices may have a first width, while analog mixed-signal (AMS) devices may have a wider second width. Forming the source or drain regions of a wider AMS device can make it challenging to actually fill the wider source / drain trenches. Wide source or drain regions that do not fill the trenches can result in higher contact resistance with the back-side contacts. Some integrated circuit designs use back-side contacts that rest against the bottom surface of the source or drain regions to provide power or signals to them. However, the back-side contacts may penetrate the thickness of the wide source or drain regions, leading to increased contact resistance and reduced device yield.

[0024] Therefore, and according to embodiments of this disclosure, this document provides techniques for providing different epitaxial growth profiles for devices with different source or drain widths. According to some embodiments, some devices of a given integrated circuit may have a source or drain region of a first width, while other devices may have a source or drain region of a second width greater than the first width, for example, at least 1.5 times, 2 times, 2.5 times, or 3 times the first width. In some examples, the second width may be greater than 50 nm, such as between 50 nm and 60 nm. To form a more robust source or drain region, a source or drain region having a second width may be formed by at least two epitaxial regions, each region comprising one or more epitaxial layers. According to embodiments, a given source or drain region having a second width comprises a first epitaxial region of silicon (Si) for an n-channel device or a silicon-germanium (SiGe) p-channel device. The first epitaxial region has at least a first epitaxial layer and a second epitaxial layer located on the first epitaxial layer. According to some embodiments, a given source or drain region having a second width further includes a second epitaxial region (of Si or SiGe) on the first epitaxial region. In the above example, the first epitaxial layer may be substantially undoped, while the second epitaxial layer is doped with one or more n-type dopants (for n-channel devices) or one or more p-type dopants (for p-channel devices). In this case, substantially undoped means that no n-type or p-type dopants are deposited in the first epitaxial layer. According to some examples, after a given source or drain region is formed, some dopant may diffuse into the first epitaxial layer, but the concentration of n-type or p-type dopants in the first epitaxial layer will be at least two orders of magnitude lower than the concentration of n-type or p-type dopants in the second epitaxial layer.

[0025] According to some embodiments, the second epitaxial region may comprise a single epitaxial layer having n-type or p-type dopant, or it may comprise a third epitaxial layer on the second epitaxial layer and a fourth epitaxial layer on the third epitaxial layer. In such an example, the third epitaxial layer may be substantially undoped, while the fourth epitaxial layer is doped with n-type or p-type dopant (e.g., the same as the second epitaxial layer). The back-side contact may be formed below a given source or drain region and extend through any number of epitaxial layers, for example, extending into at least the third epitaxial layer or into the fourth epitaxial layer.

[0026] According to an embodiment, an integrated circuit includes a semiconductor device having a semiconductor region extending from a source or drain region along a first direction and a gate structure extending over the semiconductor region along a second direction. The source or drain region has a width greater than 50 nm along the first direction and includes a first epitaxial region on at least a portion of the semiconductor region and a second epitaxial region on the first epitaxial region. Each of the first and second epitaxial regions includes one or more n-type dopants or one or more p-type dopants.

[0027] According to an embodiment, the electronic device includes a chip package having one or more dies. At least one of the one or more dies includes a plurality of semiconductor nanoribbons extending from a source or drain region along a first direction, a gate structure extending along a second direction over the plurality of semiconductor nanoribbons, and a back-side contact extending through a bottom surface of the source or drain region. The source or drain region has a width greater than 50 nm along the first direction and includes a first epitaxial region on at least a portion of the plurality of semiconductor nanoribbons and a second epitaxial region on the first epitaxial region. Each of the first epitaxial region and the second epitaxial region includes one or more n-type dopants or one or more p-type dopants.

[0028] According to another embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction; and a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in a second direction. Along the first direction, the width of the second source or drain region is at least twice the width of the first source or drain region. The second source or drain region includes a first epitaxial region on at least a portion of the second semiconductor region and a second epitaxial region on the first epitaxial region. Each of the first epitaxial region and the second epitaxial region includes one or more n-type dopants or one or more p-type dopants.

[0029] According to an embodiment, a method of forming an integrated circuit includes: forming a first fin and a second fin, each comprising semiconductor material, the first fin and the second fin extending over a substrate; forming a sacrificial gate and a spacer structure on the first fin and the second fin; removing portions of the first fin and the second fin not covered by the sacrificial gate and the spacer structure; forming a first epitaxial region at an exposed end of the semiconductor material of the first fin, and forming a second epitaxial region at an exposed end of the semiconductor material of the second fin; forming a dielectric liner on the top surfaces of the first epitaxial region and the second epitaxial region; removing the dielectric liner from the top surface of the second epitaxial region; forming a third epitaxial region on the second epitaxial region after removing the dielectric liner from the top surface of the second epitaxial region; and removing the dielectric liner from the top surface of the first epitaxial region.

[0030] These techniques can be used with any type of nonplanar transistor, including finFETs (sometimes called dual-gate transistors or tri-gate transistors), nanowire and nanoribbon transistors (sometimes called all-to-the-loop gate transistors), or forked transistors, to name just a few. The source and drain regions can be, for example, epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented using a gate-before process or a gate-after process (sometimes called a replacement metal gate or RMG process) or any other gate formation process. Any number of semiconductor materials can be used to form the transistor, such as group IV materials (e.g., silicon, germanium, silicon-germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide, indium phosphide).

[0031] The techniques and structures described herein can be detected using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), electron energy loss spectroscopy, scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional analysis; X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name just a few suitable examples of analytical tools. In some embodiments, such tools can indicate the presence of multiple epitaxial regions within a given source or drain region. For example, seams can be seen between the epitaxial regions, each region having one or more epitaxial layers having one or more n-type or one or more p-type dopants. In some embodiments, such tools can indicate the presence of back-side contacts of multiple such epitaxial layers extending through a given source or drain region; however, the back-side contacts do not penetrate the entire thickness of the source or drain region.

[0032] It should be readily understood that the meanings of “above” and “on top” in this disclosure should be interpreted in the broadest possible sense, such that “above” and “on top” not only mean “directly on something” but also include the meaning of being above something with intermediate features or layers in between. Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” and “bottom” may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0033] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A monolayer is a layer composed of atoms of a single layer of a given material. A layer may extend over the entire lower or upper layer structure, or it may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, wherein the thickness of the layer is less than the thickness of the continuous structure. For example, a layer may lie between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A layer may conform to a given surface (whether flat or curved) and have a relatively uniform thickness throughout the layer.

[0034] As used herein, “materials that are “different in composition” or “different in composition” refer to two materials that have different chemical compositions. This difference in composition can be, for example, by means of elements present in one material but not in the other (e.g., SiGe is different in composition from silicon), or by means of one material having all the same elements as the second material but at least one of those elements being intentionally provided in one material at a different concentration relative to the other (e.g., SiGe with 70 atomic percent germanium is different in composition from SiGe with 25 atomic percent germanium). In addition to this chemical composition diversity, materials can also have different dopants (e.g., gallium and magnesium) or the same dopants but at different concentrations. In other embodiments, materials that are different in composition can also refer to two materials that have different crystal orientations. For example, (110) silicon is different in composition from (100) silicon. For example, stacks with different orientations can be created by transferring uniform thickness wafer layers. If the two materials are different in elements, one material has elements not present in the other material. Architecture

[0035] Figure 1A This is a cross-sectional view taken along the direction of the fins through the semiconductor device 101 according to an embodiment of the present disclosure, showing the semiconductor body extending between the source or drain regions of each semiconductor device. Figure 1BA cross-sectional view is shown, taken through a different semiconductor device 103 on the same die as semiconductor device 101. Semiconductor device 103 may further extend along the same fins as semiconductor device 101, or may be part of a different fin extending parallel to the fins of semiconductor device 101. Each semiconductor device may be, for example, a non-planar metal-oxide-semiconductor (MOS) transistor, such as a tri-gate (e.g., finFET) or gate-all-around (GAA) transistor, but other transistor topologies and types may also benefit from the techniques provided herein. Examples herein illustrate semiconductor devices having a GAA structure (e.g., having nanoribbons, nanowires, or nanosheets extending between source and drain regions). Other examples may have a forked structure having p-type and n-type devices separated by a dielectric ridge or structure.

[0036] According to some embodiments, semiconductor device 103 has a wider gate than semiconductor device 101. In the example, semiconductor device 103 may be an AMS device, while semiconductor device 103 may be a logic or memory device.

[0037] The semiconductor material used in each semiconductor device may be formed from or on a semiconductor substrate. According to some embodiments, after all top-side processing is completed, the substrate is removed and replaced with a substrate dielectric structure 102. The substrate dielectric structure 102 may represent any number of dielectric layers and / or materials. In some examples, the substrate dielectric structure 102 comprises one or more silicon dioxide layers.

[0038] One or more semiconductor regions of the device may include, for example, substrate-native fins (formed by the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins may be formed from a material deposited on the substrate. In one such example, a uniform-thickness layer of SiGe may be deposited on a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In other embodiments, the fins comprise alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires, nanoribbons, and nanosheets during the gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region, allowing a full-around gate process or a forked gate process to then be performed. Similarly, in some examples, the alternating layers may be uniformly deposited and then etched into fins or deposited into fin trenches.

[0039] Each semiconductor device 101 includes one or more semiconductor regions (also referred to as channel regions), such as one or more nanoribbons 104a extending in a first direction between epitaxial source or drain regions 106. Similarly, each semiconductor device 103 includes one or more semiconductor nanoribbons 104b extending in a first direction between epitaxial source or drain regions 107. A given device channel region may include a combination of channel geometries (e.g., both nanowire and nanoribbon geometries within the same device channel region). A first gate structure 108a extends over the nanoribbons 104a of semiconductor device 101 in a second direction (e.g., in / out) to form the transistor gate of semiconductor device 101, and a second gate structure 108b extends over the nanoribbons 104b of semiconductor device 103 in a second direction to form the transistor gate of semiconductor device 103. As described above, the second gate structure 108b is wider than the first gate structure 108a along the first direction. Furthermore, the source or drain regions 107 are wider along the first direction than the source or drain regions 106. In some examples, the source or drain region 107 has a total width of at least 50 nm along the first direction, or a width between about 50 nm and about 60 nm. The source or drain region 106 may have a total width between about 20 nm and about 40 nm along the first direction. In some examples, the width of the source or drain region 107 is at least 1.5 times, at least 2 times, at least 2.5 times, or at least 3 times the width of the source or drain region 106.

[0040] Depending on the application and dopant profile, either the source or drain region 106 / 107 can serve as a source or drain region. Any semiconductor material suitable for the source and drain regions (e.g., group IV and III-V semiconductor materials) can be used for any of the shown source or drain regions 106 / 107. In any such case, the overall doping profile of the source or drain regions 106 and 107 can vary in part due to differences in the geometry between the source or drain regions 106 and 107, as will be discussed in more detail herein. Semiconductor devices 101 and 103 can be n-channel devices of silicon (Si) having a certain concentration of one or more n-type dopants in the associated source or drain regions 106 and 107, or semiconductor devices 101 and 103 can be p-channel devices of silicon germanium (SiGe) having a certain concentration of one or more p-type dopants in the associated source or drain regions 106 and 107. Example p-type dopants include boron or aluminum, and example n-type dopants include phosphorus or arsenic.

[0041] According to some embodiments, gate structures 108a / 108b may each include a gate electrode comprising a conductive filler and one or more metal work function layers. Gate structures 108a / 108b also include a gate dielectric that may represent any number of dielectric layers. The conductive filler may include any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some examples, the conductive filler includes tungsten (W), but other metals or conductive materials such as aluminum (Al), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or doped polysilicon may be used. Semiconductor devices 101 and 103 may be n-channel devices having gate structures 108a / 108b having one or more work function layers of titanium aluminum carbide. Other metal work function layers of the n-channel device may include tantalum nitride (TaN). In some embodiments, semiconductor devices 101 and 103 are p-channel devices having gate structures 108a / 108b having one or more tungsten work function layers. Other metal work function layers in p-channel devices may include tantalum nitride (TaN) and titanium nitride (TiN).

[0042] The gate dielectric of each gate structure 108a / 108b may include any suitable gate dielectric material. In some embodiments, the gate dielectric includes a native oxide material (e.g., silicon dioxide, germanium dioxide, or SiGe oxide) layer on the nanoribbon 104a / 104b, and a high-k dielectric material (e.g., hafnium oxide or aluminum oxide) layer on the native oxide. According to some embodiments, spacer structures 110 and internal spacers 112 are present along the sidewalls of the gate structures 108a / 108b. Spacer structures 110 and internal spacers 112 may be any suitable dielectric material, such as silicon nitride, and provide separation between a given gate structure 108a / 108b and adjacent source or drain regions 106 / 107. The internal spacers 112 may separate adjacent nanoribbons 104a / 104b from each other along a third direction (e.g., a vertical direction).

[0043] According to some embodiments, a dielectric filler 114 is provided over source or drain regions 106 and 107. The dielectric filler 114 can be used to fill any remaining portion of a source / drain trench including source or drain regions 106 and 107 and extending in a second direction (e.g., in / out of a page). Therefore, the dielectric filler 114 can extend over the top surface of source or drain regions 106 and 107, and can also extend over the side surfaces of source or drain regions 106 and 107 (e.g., between source or drain regions along the second direction). In some embodiments, one or more top-side conductive contacts extend through the dielectric filler 114 to contact at least a portion of the top surface of a given source or drain region 106 or 107. The top-side conductive contacts can also extend into at least a portion of a given source or drain region 106 or 107.

[0044] According to some embodiments, the source or drain region 106 includes an epitaxial region comprised of one or more epitaxial layers. For example, a first epitaxial layer 116 may be grown from the end of the nanoribbon 104a (and possibly from the semiconductor substrate before removal of the semiconductor substrate), while a second epitaxial layer 118 may be grown on the first epitaxial layer 116. According to some embodiments, the first epitaxial layer 116 comprises undoped Si (n-type) or undoped SiGe (p-type), and the second epitaxial layer 118 comprises phosphorus- or arsenic-doped Si (n-type) or boron-doped SiGe (p-type). The first epitaxial layer 116 may have a thickness of less than 15 nm, less than 10 nm, or less than 5 nm. In some embodiments, the first epitaxial layer 116 and the second epitaxial layer 118 are formed at different times, such that there is a significant step discontinuity in doping concentration between the zero dopant concentration in the first epitaxial layer 116 and the doping concentration found in the second epitaxial layer 118. In some embodiments, there is a dopant concentration gradient at the boundary between the first epitaxial layer 116 and the second epitaxial layer 118, such that the doping concentration gradually increases from the zero dopant concentration in the first epitaxial layer 116 to the dopant concentration in the second epitaxial layer 118.

[0045] According to some embodiments, the source or drain region 107 includes more than one epitaxial region, wherein each region is constituted by one or more epitaxial layers. In the illustrated example, the first epitaxial region includes a third epitaxial layer 120 and a fourth epitaxial layer 122 on the third epitaxial layer 120. According to some embodiments, the third epitaxial layer 120 is formed simultaneously with the first epitaxial layer 116 and therefore has substantially the same characteristics as the first epitaxial layer 116. Furthermore, the fourth epitaxial layer 122 may be formed simultaneously with the second epitaxial layer 118 and therefore has substantially the same characteristics as the second epitaxial layer 118. According to some embodiments, the source or drain region 107 includes a second epitaxial region, which includes a fifth epitaxial layer 124 on the fourth epitaxial layer 122 and a sixth epitaxial layer 126 on the fifth epitaxial layer 124. In some examples, the fifth epitaxial layer 124 comprises undoped Si (n-type) or undoped SiGe (p-type), and the sixth epitaxial layer 126 comprises phosphorus- or arsenic-doped Si (n-type) or boron-doped SiGe (p-type). Therefore, the fifth epitaxial layer 124 can be substantially similar to the third epitaxial layer 120, and the sixth epitaxial layer 126 can be substantially similar to the fourth epitaxial layer 122. In some embodiments, a visible seam exists between the first and second epitaxial regions (e.g., at the boundary between the fourth epitaxial layer 122 and the fifth epitaxial layer 124).

[0046] Including a second epitaxial region (e.g., having a fifth epitaxial layer 124 and a sixth epitaxial layer 126) effectively increases the volume of the source or drain region 107 and prevents the contacts from penetrating the thickness of a region in a long-channel device such as semiconductor device 103. Any number of back-side contacts can be provided to contact any number of source or drain regions from below. For example, a first back-side contact 128 can be provided to contact the source or drain region 106 from below, and a second back-side contact 130 can be provided to contact the source or drain region 107 from below. According to some embodiments, each of the back-side contacts 128 and 130 extends through at least a portion of the substrate dielectric structure 102 and through at least a portion of the source or drain region 106 and the source or drain region 107, respectively. In the example shown, the second back-side contact 130 extends through the entire thickness of at least each of the third epitaxial layer 120 and the fourth epitaxial layer 122. Either or both of the first back-side contact 128 and the second back-side contact 130 can provide a conductive path between their respective source or drain regions 106 or 107 and a buried conductive wire serving as a power rail or ground rail. The back-side contacts 128 and 130 can comprise any suitable conductive material, such as tungsten, cobalt, ruthenium, or molybdenum. Manufacturing method

[0047] Figure 2A-15A and Figure 2B-15BThe accompanying cross-sectional view illustrates an example process for forming integrated circuits with different semiconductor devices according to embodiments of the present disclosure, the different semiconductor devices having different source / drain widths and different epitaxial growth profiles. Figures 2A to 15A Indicates the relationship across a series of semiconductor devices 101 Figure 1A Similar cross-sectional views, and Figures 2B to 15B Indicates the relationship across a series of semiconductor devices 103 Figure 1B Similar cross-sectional diagrams. Each group of diagrams sharing the same letters shows an example structure resulting from the process flow up to that point in time; therefore, the structure shown evolves as the process continues, eventually forming... Figure 15A and Figure 15B The structure shown is similar to Figure 1A and Figure 1B The structure shown is a subset of an overall integrated circuit (e.g., a processor or memory chip) that includes, for example, digital logic units and / or memory units, as well as analog mixed-signal circuitry. Therefore, the illustrated integrated circuit structure may be a portion of a larger integrated circuit that includes other integrated circuits not depicted. Example materials and process parameters are given, but other materials and process parameters may also be used, as will be understood from this disclosure.

[0048] Figure 2A and Figure 2B Each of the illustrations shows a cross-sectional view taken through a substrate 201 having a series of material layers formed on it, according to an embodiment of the present disclosure. Alternating material layers, including sacrificial layers 202 alternating with semiconductor layers 204, can be deposited on the substrate 201. The alternating layers are used to form a GAA transistor structure. Any number of alternating sacrificial layers 202 and semiconductor layers 204 can be deposited on the substrate 201.

[0049] Substrate 201 may be a bulk substrate comprising, for example, group IV semiconductor materials (such as silicon, germanium, or SiGe), group III-V semiconductor materials (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, substrate 201 may be a semiconductor-on-insulator substrate having a desired semiconductor layer (e.g., silicon over silicon dioxide) over a buried insulating layer. Alternatively, substrate 201 may be a multilayer substrate or superlattice suitable for forming nanowires, nanoribbons, and / or nanosheets (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates may be used, and a given die may comprise any combination of nanowires (e.g., circular or square cross-sections), nanoribbons (e.g., strip-shaped cross-sections), and nanosheets (e.g., sheet-shaped cross-sections).

[0050] According to some embodiments, semiconductor layer 204 has a different material composition than sacrificial layer 202. In some embodiments, semiconductor layer 204 comprises a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or III-V materials such as indium phosphide (InP) or gallium arsenide (GaAs). Sacrificial layer 202 comprises a material that can be selectively removed relative to semiconductor layer 204. In some examples, for instance, semiconductor layer 204 is silicon and sacrificial layer 202 is SiGe, or vice versa. In some other examples where SiGe is used in both semiconductor layer 204 and sacrificial layer 202, the germanium concentrations between semiconductor layer 204 and sacrificial layer 202 differ to allow for etching selectivity. For example, semiconductor layer 204 may include a higher germanium content compared to sacrificial layer 202.

[0051] While the dimensions can vary from one example embodiment to the next, in some examples, the thickness of each semiconductor layer 204 can be between about 5 nm and about 20 nm. In some embodiments, the thickness of each semiconductor layer 204 is substantially the same (e.g., within 1-2 nm). The thickness of each sacrificial layer 202 can be substantially the same as the thickness of each semiconductor layer 204 (e.g., about 5-20 nm). Each of the semiconductor layers 204 and the sacrificial layers 202 can be deposited using any material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) or epitaxial growth.

[0052] Figure 3A and Figure 3B The following are shown, according to an embodiment, after the formation of the capping layer 302 and subsequently the formation of fins below the capping layer 302. Figure 2A and Figure 2B The diagram shows a cross-sectional view of the structure. The capping layer 302 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The capping layer 302 is patterned into rows to form corresponding rows of fins from the alternating stack of sacrificial layer 202 and semiconductor layer 204. The capping layer 302 extends along the top of each fin in a first direction. In some embodiments, Figure 3A and Figure 3B Different portions of the same fin are shown (e.g., patterned below the same stripe of capping 302). In some embodiments, Figure 3A and Figure 3B The portions of different parallel fins are shown (e.g., below different parallel stripes of cap 302).

[0053] According to some embodiments, an anisotropic etching process continues through the stacked layers to at least a portion of the substrate 201. The portion of substrate 201 located below the fins is not etched and creates a sub-fin region 304. The etched portion of substrate 201 not below the fins can be filled with a dielectric filler, which serves as shallow trench isolation (STI) between adjacent fins. The dielectric filler is not shown in these cross-sections because it extends along the sides of the sub-fin region 304 in the first direction of the entry and exit of the page. The dielectric filler can be any suitable dielectric material, such as silicon dioxide. According to some embodiments, the sub-fin region 304 represents the remaining portion of substrate 201 flanked by dielectric fillers.

[0054] Figure 4A and Figure 4B The diagram illustrates the process after the formation of the sacrificial gates 402 / 403 and the spacer structure 404, according to some embodiments. Figure 3A and Figure 3B The diagram shows a cross-sectional view of the structure. The gate mask layer can initially be patterned as strips extending orthogonally (e.g., in a second direction) across each fin to form corresponding sacrificial gates 402 / 403 in the strips beneath the gate mask layer. The gate mask layer can then be removed or may remain as a capping layer over each sacrificial gate 402 / 403. According to some embodiments, sacrificial gate material is removed in all areas not protected by the gate mask layer. The sacrificial gates 402 / 403 can be any suitable material that can be selectively removed without damaging the semiconductor material of the fins. In some examples, the sacrificial gates 402 / 403 comprise polysilicon.

[0055] The sacrificial gate 402 may have a first width w1 along a first direction, which is smaller than a second width w2 of the sacrificial gate 403 along the first direction. In some examples, the second width w2 is at least 15%, at least 25%, at least 30%, at least 40%, or at least 50% larger than the first width w1.

[0056] According to some embodiments, a spacer structure 404 is formed along the sidewalls of the sacrificial gates 402 / 403. The spacer structure 404 may be conformally deposited (e.g., CVD or ALD) and then etched back from the horizontal surface or otherwise removed (e.g., via anisotropic or directional etching), such that the spacer structure 404 is largely retained only on the sidewalls of any exposed structure. The width of the spacer structure 404 (along the first direction) can vary from one example to the next, but in some cases ranges from 3 nm to 20 nm. According to some embodiments, the spacer structure 404 can be any suitable dielectric material, such as silicon nitride, silicon carbonitride, or silicon carbonitride oxide. In one such embodiment, the spacer structure 404 comprises a nitride, and the dielectric filler adjacent to the sub-fin region 304 comprises an oxide to provide a degree of etch selectivity during final gate processing.

[0057] Figure 5A and Figure 5B The image shows, according to some embodiments, the exposed portion of the fins not protected by the sacrificial gates 402 / 403 and the spacer structure 404 after removal. Figure 4A and Figure 4B A cross-sectional view of the structure shown. Any anisotropic etching process, such as reactive ion etching (RIE) or other directional etching processes, can be used to remove the exposed fin portions. According to some embodiments, the removal of the exposed fin portions creates source or drain trenches alternating with the gate trenches (currently filled with sacrificial gates 402 / 403) along a first direction. In some embodiments, at least a portion of the sub-fin region 304 is also removed such that the top surface of the sub-fin region 304 is recessed below the top surface of the adjacent dielectric filler.

[0058] Figure 6A and Figure 6B The diagram illustrates, according to some embodiments, the process after removing a portion of the sacrificial layer 202 and forming the internal spacer 602 within the transverse groove. Figure 5A and Figure 5B The cross-sectional view of the structure shown is illustrated. An isotropic etching process can be used to selectively recess the exposed ends of each sacrificial layer 202 (e.g., while etching a relatively small number of semiconductor layers 204).

[0059] The internal spacer 602 may have a similar or identical material composition to the spacer structure 404. Therefore, the internal spacer 602 may be any suitable dielectric material exhibiting high etch selectivity to semiconductor materials such as silicon and / or silicon-germanium. The internal spacer 602 may be conformally deposited on the sides of the fin structure, for example, using a conformal deposition process such as CVD or ALD, and then etched back using an isotropic etching process to expose the ends of the semiconductor layer 204. According to some embodiments, the internal spacer 602 has a width similar to that of the spacer structure 404 (e.g., along a first direction).

[0060] Figure 7A and Figure 7B The following are examples illustrating the use of various embodiments. Figure 7A The first epitaxial layer 702 is formed in the source / drain trench of the device and in Figure 7B After the second epitaxial layer 704 is formed in the source / drain trench of the device. Figure 6A and Figure 6B The diagram shows a cross-sectional view of the structure. The first epitaxial layer 702 and the second epitaxial layer 704 can be grown substantially simultaneously from the exposed ends of the semiconductor layer 204 and any exposed portions of the sub-fin 304. According to some embodiments, both the first epitaxial layer 702 and the second epitaxial layer 704 are undoped semiconductor materials, such as undoped Si for n-type devices or undoped SiGe for p-type devices. It should be noted that the materials of the first epitaxial layer 702 and the second epitaxial layer 704 are grown from exposed semiconductor surfaces in the source / drain trench, and the growth can be combined to form a continuous layer over the sidewalls and bottom surface of the source / drain trench. Due to the growth process, discontinuities may exist in the first epitaxial layer 702 and the second epitaxial layer 704.

[0061] Figure 8A and Figure 8B The following are examples illustrating the use of various embodiments. Figure 8A A third epitaxial layer 802 is formed on the first epitaxial layer 702 within the source / drain trench of the device, and on... Figure 8B After the fourth epitaxial layer 804 is formed on the second epitaxial layer 704 within the source / drain trench of the device. Figure 7A and Figure 7B The diagram shows a cross-sectional view of the structure. The third epitaxial layer 802 and the fourth epitaxial layer 804 can be grown substantially simultaneously from the exposed surfaces of the first epitaxial layer 702 and the second epitaxial layer 704, respectively. According to some embodiments, both the third epitaxial layer 802 and the fourth epitaxial layer 804 are doped semiconductor materials, such as phosphorus- or arsenic-doped Si for n-type devices or boron-doped SiGe for p-type devices.

[0062] In some embodiments, the first epitaxial layer 702 and the third epitaxial layer 802 are formed at different times, resulting in a significant step discontinuity in doping concentration between the zero dopant concentration in the first epitaxial layer 702 and the doping concentration found in the third epitaxial layer 802. In some embodiments, a doping concentration gradient exists at the boundary between the first epitaxial layer 702 and the third epitaxial layer 802, such that the doping concentration gradually increases from the zero dopant concentration in the first epitaxial layer 702 to the doping concentration in the third epitaxial layer 802. Regardless of the doping scheme used, according to some embodiments, the same doping scheme will also be observed on the second epitaxial layer 704 and the fourth epitaxial layer 804.

[0063] The growth of the first epitaxial layer 702 and the third epitaxial layer 802 has been completed. Figure 8A The formation of the first source or drain region 805 in the device, however, the second epitaxial layer 704 and the fourth epitaxial layer 804 only provide Figure 8B The first epitaxial region 806 of the second source or drain region of the device. According to some embodiments, the remaining portion of the source / drain trench outside the first epitaxial region 806 has no material. In this example, the first epitaxial region 806 includes both a second epitaxial layer 704 and a fourth epitaxial layer 804.

[0064] Figure 9A and Figure 9B The following are shown respectively according to some embodiments after the formation of the liner 902. Figure 8A and Figure 8B The diagram shows a cross-sectional view of the structure. The liner 902 can be any suitable dielectric material, such as silicon dioxide. In some examples, the liner 902 comprises any dielectric material that has sufficient etch selectivity with the spacer structure 404 to reduce damage to the spacer structure 404 during the removal of the liner 902.

[0065] According to some embodiments, the liner 902 is deposited using any suitable conformal deposition technique such as CVD, PECVD, or ALD. The liner 902 can be deposited on all exposed surfaces and subsequently patterned using a suitable photolithography technique to remove the liner from the first epitaxial region 806 while retaining the liner 902 on the top surface of the source or drain region 805. The liner 902 can have a thickness between about 2 nm and about 5 nm, or up to 10 nm.

[0066] Figure 10A and Figure 10B The diagrams illustrate the process after the second epitaxial region 1001 is formed on the first epitaxial region 806 according to some embodiments. Figure 9A and Figure 9B A cross-sectional view of the structure shown. (It can be found in...) Figure 10BThe device shown grows one or more additional epitaxial layers within the source / drain trench, wherein a liner 902 protects the source or drain region 805 from any further material growth.

[0067] In the illustrated example, a fifth epitaxial layer 1002 is grown on a fourth epitaxial layer 804, and a sixth epitaxial layer 1004 is grown on the fifth epitaxial layer 1002. According to some embodiments, the fifth epitaxial layer 1002 is substantially similar to the second epitaxial layer 704, and the sixth epitaxial layer 1004 is substantially similar to the fourth epitaxial layer 804. Therefore, the fifth epitaxial layer 1002 may comprise a substantially undoped semiconductor material (e.g., Si or SiGe), and the sixth epitaxial layer 1004 may comprise a doped semiconductor material (e.g., having one or more dopants similar to those in the fourth epitaxial layer 804). In some examples, the fourth epitaxial layer 804 and the sixth epitaxial layer 1004 have the same concentration of n-type or p-type dopants.

[0068] According to some embodiments, due to one or more additional fabrication operations performed between the formation of the fourth epitaxial layer 804 and the formation of the fifth epitaxial layer 1002, an observable seam exists along the boundary between the fourth epitaxial layer 804 and the fifth epitaxial layer 1002. The doping scheme between the fifth epitaxial layer 1002 and the sixth epitaxial layer 1004 can be similar to the doping scheme between the second epitaxial layer 704 and the fourth epitaxial layer 804 described above (e.g., a step discontinuity or gradient doping across the boundary between the fifth epitaxial layer 1002 and the sixth epitaxial layer 1004).

[0069] According to some embodiments, the formation of the second epitaxial region 1001 completes the formation of the source or drain region 1006. Due to the geometry of the source / drain trench, the source or drain region 805 has a smaller width w3 compared to the width w4 of the source or drain region 1006. For example, the source or drain region 1006 may have a width w4 that is at least 1.5 times, at least 2 times, at least 2.5 times, or at least 3 times the width w3 of the source or drain region 805. In some examples, the width w4 is at least 50 nm or between 50 nm and 60 nm.

[0070] The second extensional region 1001 may include different arrangements of the extensional layers. Figure 10B' Another embodiment is shown, wherein the second epitaxial region 1001 includes a single epitaxial layer 1008 grown on the fourth epitaxial layer 804. The epitaxial layer 1008 may have a similar material composition to the fourth epitaxial layer 804. Therefore, the epitaxial layer 1008 may be a doped semiconductor material that matches the fourth epitaxial layer 804.

[0071] Figure 11A and Figure 11BThe following are shown after the dielectric filler 1102 is formed on the source or drain regions 805 and 1006, respectively. Figure 10A and Figure 10B The diagram shows a cross-sectional view of the structure. In some examples, the dielectric filler 1102 occupies the remaining volume within the source / drain trench surrounding and above portions of the source or drain regions 805 and 1006. The dielectric filler 1102 can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler 1102 extends upward to the top surface of the spacer structure 404 and is flush with the top surface of the spacer structure 404 (e.g., after a polishing process). One or more top-side conductive contacts can be formed through the dielectric filler 1102 to contact the top surface of either the source or drain regions 805 / 1006.

[0072] Figure 12A and Figure 12B The following are shown, according to some embodiments, after the removal of the sacrificial gate 402 and the sacrificial layer 202. Figure 11A and Figure 11B The diagram shows a cross-sectional view of the structure. In the example where the gate mask layers are still present, they can be removed at this point. Once the sacrificial gate 402 is removed, the remaining fin portions extending between the spacer body structures 404 are exposed.

[0073] In an example where the fins include alternating sacrificial layers 202 and semiconductor layers 204, sacrificial layers 202 are selectively removed to leave nanoribbons 1202 extending between source or drain regions 805 and nanoribbons 1204 extending between source or drain regions 1006. Each vertical set of nanoribbons 1202 / 1204 represents a semiconductor region (also referred to as a channel region) of a different semiconductor device. It should be understood that any nanoribbon in nanoribbons 1202 / 1204 can also be a nanowire or a nanosheet (e.g., all of 1202 can be nanowires and all of 1204 can be nanoribbons, or vice versa, or all of 1202 and 1204 can be nanowires, nanoribbons, or nanosheets, or some of 1202 can be nanowires and other nanoribbons in 1202 can be nanoribbons and / or some of 1204 can be nanowires and other of 1204 can be nanoribbons). Channel shaping techniques can be used to provide desired channel geometries and diversity, such as, for example, forming some, but not all, of the nanoribbons 1202 and / or 1204 in a given channel region by thinning nanowires, making them more ribbon-like, while others in the same channel region remain as nanowires. More generally, channel shaping can provide any number of different channel configurations. The sacrificial gate 402 and sacrificial layer 202 can be removed using the same or different isotropic etching processes. Any channel shaping can be performed using isotropic and / or anisotropic etching processes configured to remove unmasked or otherwise exposed channel semiconductor material within the gate trenches of 1202 and / or 1204 until the desired channel configuration is achieved.

[0074] Figure 13A and Figure 13B The images respectively illustrate embodiments of the present disclosure after forming a first gate structure 1302 around a suspended nanoribbon 1202 and a second gate structure 1304 around a suspended nanoribbon 1204. Figure 12A and Figure 12B The diagram shows a cross-sectional view of the structure. As described above, gate structures 1302 / 1304 each include a gate dielectric and a gate electrode.

[0075] A gate dielectric can be conformally deposited around the nanoribbon 1202 / 1204 using any suitable deposition process, such as ALD. The gate dielectric can include any suitable dielectric (such as silicon dioxide and / or high-k dielectric materials). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric is hafnium oxide with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric can include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some examples, the gate dielectric can be a multilayer structure. For example, the gate dielectric can include a first layer on the nanoribbon 1202 / 1204 and a second layer on top of the first layer. The first layer may be an oxide (e.g., silicon dioxide) for example, a semiconductor layer, and the second layer may be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, when using a high-k dielectric material, an annealing process may be performed on the gate dielectric to improve its quality. In some embodiments, the high-k material may be nitrided to improve its anti-aging properties.

[0076] The gate electrode can be deposited on the gate dielectric and can be any standard or proprietary conductive material that may include any number of gate nicks. In some embodiments, the gate electrode comprises doped polysilicon, a metal, or a metal alloy. Suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate electrode may include, for example, one or more work function layers, resistance reduction layers, and / or barrier layers. In an example, the first gate structure 1302 and / or the second gate structure 1304 comprises an n-type work function material, such as aluminum titanium carbide or tantalum nitride. In an example, the first gate structure 1302 and / or the second gate structure 1304 comprises a p-type work function material, such as tungsten.

[0077] Figure 14A and Figure 14B The following are shown, according to some embodiments, after removing the back side portion of substrate 201. Figure 13A and Figure 13B A cross-sectional view of the structure shown. Any number of polishing, grinding, or etching processes (e.g., CMP) can be used to remove the main portion of substrate 201. According to some embodiments, substrate 201 is removed until the bottom surface of sub-fin region 304 and / or the dielectric layer adjacent to sub-fin region 304 are exposed.

[0078] According to some embodiments, the exposed sub-fin region 304 is removed and replaced with a substrate dielectric structure 1402. The sub-fin region 304 can be removed using a suitable isotropic etching process, after which the substrate dielectric structure 1402 is formed on the back side. According to some embodiments, the substrate dielectric structure 1402 includes any number of dielectric layers. In some examples, the substrate dielectric structure 1402 includes a silicon dioxide layer. The substrate dielectric layer may have a polished bottom surface.

[0079] Figure 15A and Figure 15B The following are shown respectively after the back contact portions 1502 and 1504 are formed in the respective back cavities according to some embodiments. Figure 14A and Figure 14B A cross-sectional view of the structure shown. Back-side contacts 1502 and 1504 may comprise any suitable conductive material, such as tungsten, ruthenium, molybdenum, or cobalt. Prior to depositing the conductive material to form the back-side contacts 1502 / 1504, directional etching (e.g., RIE) is performed to form a back-side cavity extending through the thickness of the substrate dielectric structure 1402 and through at least a portion of the respective source or drain regions 805 and 1006. According to some embodiments, as a result of the etching process, the back-side cavity has a tapered profile with a width decreasing from the opening of the cavity (e.g., at the bottom surface of the substrate dielectric structure 1402). Back-side contacts 1502 and 1504 are formed by depositing conductive material within the back-side cavity, and thus exhibit the tapered shape of the back-side cavity. According to some embodiments, back-side contact 1504 extends through at least the entire thickness of the second epitaxial layer 704 and the fourth epitaxial layer 804. In the example shown, back-side contact 1504 extends into at least a portion of the sixth epitaxial layer 1004. One or more additional back-side interconnect layers may be formed beneath the substrate dielectric structure 1402. In some embodiments, one of these layers includes a conductive power rail or ground rail that is conductively coupled to one or both of the back-side contacts 1502 and 1504.

[0080] Figure 16 An example embodiment of a chip package 1600 according to embodiments of the present disclosure is shown. It can be seen that the chip package 1600 includes one or more dies 1602. The one or more dies 1602 may include at least one integrated circuit having a semiconductor device (such as any semiconductor device disclosed herein). In some example configurations, the one or more dies 1602 may include any additional circuitry for interfacing with other devices formed on the die or connected to the chip package 1600.

[0081] As can be further seen, the chip package 1600 includes a housing 1604 bonded to a package substrate 1606. The housing 1604 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for components of the chip package 1600. One or more dies 1602 can be electrically coupled to the package substrate 1606 using connectors 1608, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGAs), pins, or wire bonding, to name just a few. The package substrate 1606 can be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between or at different locations on each face of the package substrate 1606. In some embodiments, the package substrate 1606 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), but any number of package geometries can be used. Additional conductive contacts 1612 may be disposed on opposite sides of the package substrate 1606 for conductive contact, such as a printed circuit board (PCB). One or more vias 1610 extend through the thickness of the package substrate 1606 to provide a conductive path between one or more connections 1608 and one or more contacts 1612. For ease of illustration, the vias 1610 are shown as a single line through the package substrate 1606, but other configurations (e.g., damascene, dual damascene, through-silicon vias, or meandering through the thickness of the substrate 1606 to contact interconnect structures at one or more intermediate locations) may be used. In other embodiments, the vias 1610 are fabricated from a plurality of smaller stacked vias, or staggered at different locations on the package substrate 1606. In the illustrated embodiment, the contacts 1612 are solder balls (e.g., for bump-based connections or ball grid array arrangements), but any suitable package bonding mechanism (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement) may be used. In some embodiments, solder resist is disposed between the contacts 1612 to suppress short circuits.

[0082] In some embodiments, molding material 1614 may be disposed around one or more dies 1602 included within housing 1604 (e.g., as an underfill material between die 1602 and encapsulation substrate 1606, and as an overfill material between die 1602 and housing 1604). While the size and weight of molding material 1614 can vary from one embodiment to the next, in some embodiments, the thickness of molding material 1614 is less than 1 mm. Example materials that can be used for molding material 1614 include suitable epoxy molding materials. In some cases, molding material 1614 is thermally conductive in addition to electrical insulation. method

[0083] Figure 17 This is a flowchart of a method 1700 for forming at least a portion of an integrated circuit according to an embodiment. Various operations of method 1700 can be performed... Figure 2A-15A and Figure 2B-15B The figures are shown in the foregoing figures. However, the relevance of the various operations of method 1700 to the specific components shown in the foregoing figures is not intended to imply any structural and / or usage limitations. Rather, the foregoing figures provide an example embodiment of method 1700. Other operations may be performed before, during, or after any operation of method 1700. For example, method 1700 does not explicitly describe the various standard processes typically performed to form a transistor structure. Some operations of method 1700 may be performed in a different order than that shown.

[0084] According to some embodiments, method 1700 begins at operation 1702, in which at least one semiconductor fin is formed. In examples, first and second semiconductor fins may be formed. The semiconductor material in the fins may be formed from a substrate such that the fins are part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins may be formed from a material deposited on an underlying substrate. In one such example, a uniform-thickness layer of silicon germanium (SiGe) may be deposited on a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins may be formed in a so-called aspect ratio-based trapping process, in which native fins are etched away to leave fin trenches, which can then be filled with an alternative semiconductor material (e.g., a group IV or group III-V material). In other embodiments, the fins comprise alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires, nanoribbons, and nanosheets during the gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region, allowing a full-around gate (GAA) or fork-die process to then be performed. Similarly, the alternating layers can be deposited at a uniform thickness and then etched into the fins, or deposited into fin trenches. The fins may also include a cap structure located above the top surface, which defines the location of the fins during, for example, a RIE process. The cap structure can be a dielectric material, such as silicon nitride.

[0085] According to some embodiments, a dielectric layer is formed around the sub-fin portions of the fin. In some examples, the anisotropic etching process used to form the fin continues into at least a portion of the underlying substrate. Etched portions of the substrate not beneath any fin can be filled with a dielectric filler to form a dielectric layer serving as an STI between adjacent fins. The dielectric layer can be any suitable dielectric material, such as silicon dioxide. According to some embodiments, the sub-fins represent the remaining portion of the substrate flanked by the dielectric layer beneath each fin.

[0086] Method 1700 continues to operation 1704, wherein a sacrificial gate is formed over the fin. Any number of sacrificial gates can be patterned into strips extending orthogonally and parallel to each other over the fin (e.g., forming a crosshair pattern) using a gate mask layer. The gate mask layer can be any suitable hard mask material, such as a hard carbon mask (CHM) or silicon nitride. The sacrificial gate itself can be formed of any suitable material that can be selectively removed at a later time without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon.

[0087] According to some embodiments, spacer structures are also formed on at least the sidewalls of the sacrificial gate. The spacer structures can be deposited and then etched back, such that the spacer structures remain mostly on the sidewalls of any exposed structures. In some cases, spacer structures can also be formed along the sidewalls of exposed fins extending orthogonally between the sacrificial gate strips. According to some embodiments, the spacer structures can be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0088] Method 1700 continues with operation 1706, wherein a portion of the fin adjacent to the sacrificial gate and spacer structure (e.g., not covered by the sacrificial gate and spacer structure) is removed to create a source / drain trench. Any exposed portion of the fin not covered by the sacrificial gate or spacer structure can be removed using any anisotropic etching process such as RIE. According to some embodiments, etching continues through the height of the fin into a sub-fin, such that a groove is etched into the sub-fin adjacent to the remaining portion of the fin (and possibly further etched into the body substrate). According to some embodiments, a first source / drain trench through the first fin has a first width, and a second source / drain trench through the second fin has a second width greater than the first width, such as at least 1.5 times, at least 2 times, at least 2.5 times, or at least 3 times the first width.

[0089] Method 1700 continues to operation 1708, wherein a first epitaxial region is formed at the end of the semiconductor material of the first fin, and a second epitaxial region is formed at the end of the semiconductor material of the second fin. According to some embodiments, the first and second epitaxial regions comprise any number of epitaxial layers. The first epitaxial region may be formed within a first source / drain trench, and the second epitaxial region may be formed within a second source / drain trench. The first and second epitaxial regions may have the same layer structure and material composition as they are formed simultaneously. For example, an undoped semiconductor material is epitaxially grown from the ends of the semiconductor material of the first and second fins to form the first epitaxial layer along the sidewall portions of the first and second source / drain trenches. Additionally, a second epitaxial layer may be formed on the first epitaxial layer to complete the formation of the first and second epitaxial regions. According to some embodiments, each of the first and second epitaxial regions comprises the same first and second epitaxial layers.

[0090] According to some embodiments, the second epitaxial layer is grown from all exposed surfaces of the first epitaxial layer and comprises a doped semiconductor material (e.g., Si doped with an n-type dopant or SiGe doped with a p-type dopant). According to some embodiments, the second epitaxial layer substantially fills any remaining space within the first source / drain trench between adjacent fins. However, at least in part due to the larger width of the second source / drain trench, the second epitaxial layer does not fill the space within the second source / drain trench between adjacent fins.

[0091] In some embodiments, the first epitaxial layer and the second epitaxial layer are formed at separate times, resulting in a significant step discontinuity in doping concentration between the zero dopant concentration in the first epitaxial layer and the doping concentration present in the second epitaxial layer. In some embodiments, a doping concentration gradient exists at the boundary between the first epitaxial layer and the second epitaxial layer, such that the doping concentration gradually increases from the zero dopant concentration in the first epitaxial layer to the doping concentration in the second epitaxial layer.

[0092] Method 1700 continues to operation 1710, wherein a dielectric liner is formed over at least the top surfaces of the first and second epitaxial regions. According to some embodiments, the dielectric liner can be any suitable dielectric material, such as silicon dioxide. In some examples, any suitable conformal deposition technique (such as CVD, PECVD, or ALD) is used to deposit the dielectric liner. The dielectric liner can have a thickness between about 2 nm and about 5 nm, or a thickness up to 10 nm. In some examples, the dielectric liner is formed on any exposed surface of the first and second epitaxial regions, including any exposed side surfaces of the first and second epitaxial regions.

[0093] Method 1700 continues with operation 1712, wherein a dielectric liner on the second epitaxial region is selectively removed. According to some embodiments, a suitable photolithography technique is used to pattern the dielectric liner to remove the liner on the second epitaxial region while retaining the dielectric liner on the first epitaxial region. Thus, the second epitaxial region is exposed within the second source / drain trench.

[0094] Method 1700 continues to operation 1714, wherein a third epitaxial region is formed on the second epitaxial region within the second source / drain trench. According to some embodiments, the third epitaxial region comprises any number of epitaxial layers and substantially fills any remaining space within the second source / drain trench between adjacent fins. According to some embodiments, a visible seam exists at the boundary between the second and third epitaxial regions. In some examples, the third epitaxial region comprises a third epitaxial layer and a fourth epitaxial layer located on the third epitaxial layer. The third epitaxial layer may be substantially similar to the first epitaxial layer described above, and the fourth epitaxial layer may be substantially similar to the second epitaxial layer described above. Thus, the third epitaxial layer may comprise a substantially undoped semiconductor material (e.g., Si or SiGe), and the fourth epitaxial layer may comprise a doped semiconductor material (e.g., having the same dopant as the second epitaxial layer). In some examples, the second and fourth epitaxial layers have the same dopant concentration of n-type or p-type dopant.

[0095] In some embodiments, the third and fourth epitaxial layers are formed at different times, resulting in a significant step discontinuity in doping concentration between the zero dopant concentration in the third epitaxial layer and the doping concentration present in the fourth epitaxial layer. In some embodiments, a doping concentration gradient exists at the boundary between the third and fourth epitaxial layers, such that the doping concentration gradually increases from the zero dopant concentration in the third epitaxial layer to the doping concentration in the fourth epitaxial layer. Example System

[0096] Figure 18 This is an example computing system implemented using one or more of the integrated circuit structures disclosed herein, according to some embodiments of this disclosure. As can be seen, the computing system 1800 houses a motherboard 1802. The motherboard 1802 may include multiple components, including but not limited to a processor 1804 and at least one communication chip 1806, each component may be physically and electrically coupled to the motherboard 1802, or otherwise integrated therein. As will be understood, the motherboard 1802 may be, for example, any printed circuit board (PCB), whether it is a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 1800, etc.

[0097] Depending on its application, computing system 1800 may include one or more other components that may or may not be physically and electrically coupled to motherboard 1802. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, optical discs (CDs), digital multifunction discs (DVDs), etc.). Any component included in computing system 1800 may include one or more integrated circuit structures or devices configured according to example embodiments (e.g., modules comprising integrated circuits configured with different semiconductor devices having source or drain regions with different epitaxial growth profiles, as provided herein in various ways). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communication chip 1806 may be part of or otherwise integrated into processor 1804).

[0098] Communication chip 1806 implements wireless communication for transmitting data to and from computing system 1800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data using modulated electromagnetic radiation through a non-solid-state medium. This term does not imply that the associated device does not contain any wires, although they may not in some embodiments. Communication chip 1806 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and above. Computing system 1800 may include multiple communication chips 1806. For example, the first communication chip 1806 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 1806 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0099] The processor 1804 of the computing system 1800 includes an integrated circuit die packaged within the processor 1804. In some embodiments, the processor's integrated circuit die includes onboard circuitry implemented using one or more semiconductor devices as described herein in various ways. The term "processor" can refer to any device or part of a device that processes, for example, electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0100] The communication chip 1806 may also include an integrated circuit die packaged within the communication chip 1806. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described in various ways herein. As will be appreciated from this disclosure, note that multi-standard wireless capabilities may be directly integrated into the processor 1804 (e.g., where the functionality of any chip 1806 is integrated into the processor 1804, rather than having separate communication chips). Further note that the processor 1804 may be a chipset with such wireless capabilities. In short, any number of processors 1804 and / or communication chips 1806 can be used. Similarly, any chip or chipset may have multiple functions integrated therein.

[0101] In various embodiments, the computing system 1800 may be a laptop computer, netbook, notebook computer, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as described herein in various ways.

[0102] It should be understood that, in some embodiments, various components of the computing system 1800 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software. Further example embodiments

[0103] The following examples relate to further embodiments, according to which many permutations and configurations will be apparent.

[0104] Example 1 is an integrated circuit including a semiconductor device having a semiconductor region extending from a source or drain region in a first direction and a gate structure extending over the semiconductor region in a second direction. The source or drain region has a width greater than 50 nm along the first direction and includes a first epitaxial region on at least a portion of the semiconductor region and a second epitaxial region on the first epitaxial region. Each of the first and second epitaxial regions includes an n-type or p-type dopant.

[0105] Example 2 includes the integrated circuit of Example 1, wherein the width of the source or drain region is between 50 nm and 60 nm.

[0106] Example 3 includes the integrated circuit of Example 1 or 2, wherein the first epitaxial region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer.

[0107] Example 4 includes the integrated circuit of Example 3, wherein a first epitaxial layer contacts at least a portion of a semiconductor region, and a second epitaxial layer includes an n-type or p-type dopant.

[0108] Example 5 includes the integrated circuit of Example 4, wherein the first epitaxial layer is substantially undoped.

[0109] Example 6 includes the integrated circuit of Example 4 or 5, wherein the second epitaxial region includes a third epitaxial layer and a fourth epitaxial layer on the third epitaxial layer.

[0110] Example 7 includes the integrated circuit of Example 6, wherein the third epitaxial layer is on the second epitaxial layer, and the fourth epitaxial layer includes an n-type or p-type dopant.

[0111] Example 8 includes the integrated circuit of Example 7, wherein the first epitaxial layer and the third epitaxial layer are each substantially undoped.

[0112] Example 9 includes an integrated circuit of any of Examples 1-8, and further includes a back-side contact extending through the bottom surface of the source or drain region.

[0113] Example 10 includes an integrated circuit of any of Examples 1-9, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons. In other examples, the semiconductor region comprises a plurality of semiconductor nanowires or a combination of nanowires and nanoribbons.

[0114] Example 11 includes the integrated circuit of Example 10, wherein a plurality of semiconductor nanoribbons (and / or other semiconductor regions) include germanium, silicon, or a combination thereof.

[0115] Example 12 includes an integrated circuit of any of Examples 1-11, wherein a visible seam exists between a first epitaxial region and a second epitaxial region.

[0116] Example 13 is a die that includes an integrated circuit from any of Examples 1-12.

[0117] Example 14 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies includes a plurality of semiconductor nanoribbons extending from a source or drain region along a first direction, a gate structure extending over the plurality of semiconductor nanoribbons along a second direction, and a back-side contact extending through a bottom surface of the source or drain region. The source or drain region has a width greater than 50 nm along the first direction and includes a first epitaxial region on at least a portion of the plurality of semiconductor nanoribbons and a second epitaxial region on the first epitaxial region. Each of the first epitaxial region and the second epitaxial region includes an n-type or p-type dopant.

[0118] Example 15 includes the electronic device of Example 14, wherein the width of the source or drain region is between 50 nm and 60 nm.

[0119] Example 16 includes the electronic device of Example 14 or 15, wherein the first epitaxial region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer.

[0120] Example 17 includes the electronic device of Example 16, wherein a first epitaxial layer contacts at least a portion of a plurality of semiconductor nanoribbons, and a second epitaxial layer comprises an n-type or p-type dopant.

[0121] Example 18 includes the electronic device of Example 17, wherein the first epitaxial layer is substantially undoped.

[0122] Example 19 includes the electronic device of Example 17 or 18, wherein the second epitaxial region includes a third epitaxial layer and a fourth epitaxial layer on the third epitaxial layer.

[0123] Example 20 includes the electronic device of Example 19, wherein the third epitaxial layer is on the second epitaxial layer, and the fourth epitaxial layer includes an n-type or p-type dopant.

[0124] Example 21 includes the electronic device of Example 20, wherein the first epitaxial layer and the third epitaxial layer are each substantially undoped.

[0125] Example 22 includes an electronic device of any one of Examples 14-21, wherein the back contact extends through the entire thickness of the first epitaxial region and extends into at least a portion of the second epitaxial region.

[0126] Example 23 includes an electronic device of any one of Examples 14-22, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0127] Example 24 includes an electronic device of any of Examples 14-23, wherein a visible seam exists between a first extensional region and a second extensional region.

[0128] Example 25 includes an electronic device comprising any one of Examples 14-24, and further includes a printed circuit board, wherein a chip package is coupled to the printed circuit board.

[0129] Example 26 is a method of forming an integrated circuit. The method includes: forming a first fin and a second fin, both comprising semiconductor material, extending over a substrate; forming a sacrificial gate and spacer structure on the first fin and the second fin; removing portions of the first fin and the second fin not covered by the sacrificial gate and spacer structure; forming a first epitaxial region at an exposed end of the semiconductor material of the first fin and forming a second epitaxial region at an exposed end of the semiconductor material of the second fin; forming a dielectric liner on the top surfaces of the first epitaxial region and the second epitaxial region; removing the dielectric liner from the top surface of the second epitaxial region; forming a third epitaxial region on the second epitaxial region after removing the dielectric liner from the top surface of the second epitaxial region; and removing the dielectric liner from the top surface of the first epitaxial region.

[0130] Example 27 includes the method of Example 26, wherein the width of the first extension region is at most half the width of the second extension region.

[0131] Example 28 includes the method of Example 26 or 27, and further includes: removing at least a portion of the substrate; and forming a back-side contact portion through the bottom surface of the second epitaxial region.

[0132] Example 29 includes the method of Example 28, wherein the dorsal contact extends through the second extensional region and through at least a portion of the third extensional region.

[0133] Example 30 includes a method of any one of Examples 26-29, wherein forming the first extensional region and the second extensional region includes forming the extensional region simultaneously.

[0134] Example 31 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction; and a second semiconductor device having a second semiconductor region extending from a second source or drain region in a first direction and a second gate structure extending over the second semiconductor region in a second direction. Along the first direction, the width of the second source or drain region is at least twice the width of the first source or drain region. The second source or drain region includes a first epitaxial region on at least a portion of the second semiconductor region and a second epitaxial region on the first epitaxial region. Each of the first and second epitaxial regions includes an n-type or p-type dopant.

[0135] Example 32 includes the integrated circuit of Example 31, wherein the width of the second source or drain region is between 50 nm and 60 nm.

[0136] Example 33 includes the integrated circuit of Example 31 or 32, wherein the first epitaxial region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer.

[0137] Example 34 includes the integrated circuit of Example 33, wherein a first epitaxial layer contacts at least a portion of a second semiconductor region, and the second epitaxial layer includes an n-type or p-type dopant.

[0138] Example 35 includes the integrated circuit of Example 34, wherein the first epitaxial layer is substantially undoped.

[0139] Example 36 includes the integrated circuit of Example 34 or 35, wherein the second epitaxial region includes a third epitaxial layer and a fourth epitaxial layer on the third epitaxial layer.

[0140] Example 37 includes the integrated circuit of Example 36, wherein the third epitaxial layer is on the second epitaxial layer, and the fourth epitaxial layer includes an n-type or p-type dopant.

[0141] Example 38 includes the integrated circuit of Example 37, wherein the first epitaxial layer and the third epitaxial layer are each substantially undoped.

[0142] Example 39 includes an integrated circuit of any of Examples 31-38, and further includes a back-side contact extending through the bottom surface of the second source or drain region.

[0143] Example 40 includes the integrated circuit of Example 39, wherein the back-side contact extends through the entire thickness of the first epitaxial region and extends into at least a portion of the second epitaxial region.

[0144] Example 41 includes an integrated circuit of any of Examples 31-40, wherein a first semiconductor region includes a first plurality of semiconductor nanoribbons, and a second semiconductor region includes a second plurality of semiconductor nanoribbons. In other examples, one or each of the first and second semiconductor regions includes a combination of nanowires and nanoribbons, or a plurality of semiconductor nanowires.

[0145] Example 42 includes the integrated circuit of Example 41, wherein the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons comprise germanium, silicon, or a combination thereof. As described above, similar components can be applied to other channel feature geometries, such as nanowires.

[0146] Example 43 includes an integrated circuit of any of Examples 31-42, wherein a visible seam exists between a first epitaxial region and a second epitaxial region.

[0147] Example 44 is a die that includes an integrated circuit from any of Examples 31-43.

[0148] The foregoing description of embodiments of this disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Many modifications and variations are possible based on this disclosure. The scope of this disclosure is intended to be limited not by this detailed description, but by the appended claims.

Claims

1. An integrated circuit, comprising: A semiconductor device having a semiconductor region extending from a source or drain region in a first direction and a gate structure extending over the semiconductor region in a second direction. The source or drain region has a width greater than 50 nm along the first direction and includes a first epitaxial region on at least a portion of the semiconductor region and a second epitaxial region on the first epitaxial region, each of the first epitaxial region and the second epitaxial region including an n-type or p-type dopant.

2. The integrated circuit according to claim 1, wherein, The width of the source or drain region is between 50 nm and 60 nm.

3. The integrated circuit according to claim 1, wherein, The first epitaxial region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer.

4. The integrated circuit according to claim 3, wherein, The first epitaxial layer contacts at least a portion of the semiconductor region, and the second epitaxial layer includes the n-type or p-type dopant.

5. The integrated circuit according to claim 4, wherein, The first epitaxial layer is essentially undoped.

6. The integrated circuit according to claim 4, wherein, The second epitaxial region includes a third epitaxial layer and a fourth epitaxial layer on the third epitaxial layer.

7. The integrated circuit according to claim 6, wherein, The third epitaxial layer is on the second epitaxial layer, and the fourth epitaxial layer includes the n-type or p-type dopant.

8. The integrated circuit according to claim 7, wherein, The first epitaxial layer and the third epitaxial layer are each substantially undoped.

9. The integrated circuit according to any one of claims 1-8, further comprising a back-side contact extending through the bottom surface of the source or drain region.

10. The integrated circuit according to any one of claims 1-8, wherein, The semiconductor region includes multiple semiconductor nanoribbons, multiple semiconductor nanowires, or a combination of nanowires and nanoribbons.

11. The integrated circuit according to any one of claims 1-8, wherein, There is a visible seam between the first epitaxial region and the second epitaxial region.

12. A die comprising an integrated circuit according to any one of claims 1-8.

13. An electronic device comprising: A chip package includes one or more dies, at least one of the one or more dies comprising: Multiple semiconductor nanoribbons extend from the source or drain region in a first direction; A gate structure extending over the plurality of semiconductor nanoribbons in a second direction; and The back contact portion extends through the bottom surface of the source or drain region; The source or drain region has a width greater than 50 nm along the first direction and includes a first epitaxial region on at least a portion of the plurality of semiconductor nanoribbons and a second epitaxial region on the first epitaxial region, each of the first epitaxial region and the second epitaxial region including an n-type or p-type dopant.

14. The electronic device according to claim 13, wherein, The width of the source or drain region is between 50 nm and 60 nm.

15. The electronic device according to claim 13, wherein, The first epitaxial region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer.

16. The electronic device according to claim 15, wherein, The first epitaxial layer contacts at least a portion of the plurality of semiconductor nanoribbons, and the second epitaxial layer includes the n-type or p-type dopant.

17. The electronic device according to claim 16, wherein, The first epitaxial layer is essentially undoped.

18. The electronic device according to any one of claims 13-17, wherein, The back contact portion extends through the entire thickness of the first epitaxial region and into at least a portion of the second epitaxial region.

19. An integrated circuit, comprising: A first semiconductor device has a first semiconductor region extending from a first source or drain region in a first direction, and a first gate structure extending over the first semiconductor region in a second direction. as well as The second semiconductor device has a second semiconductor region extending from a second source or drain region in a first direction, and a second gate structure extending over the second semiconductor region in a second direction, wherein, along the first direction, the width of the second source or drain region is at least twice the width of the first source or drain region. The second source or drain region includes a first epitaxial region on at least a portion of the second semiconductor region and a second epitaxial region on the first epitaxial region, each of the first epitaxial region and the second epitaxial region including an n-type or p-type dopant.

20. The integrated circuit according to claim 19, wherein, The first epitaxial region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer.

21. The integrated circuit according to claim 20, wherein, The first epitaxial layer contacts at least a portion of the second semiconductor region, and the second epitaxial layer includes the n-type or p-type dopant.

22. The integrated circuit according to claim 21, wherein, The first epitaxial layer is essentially undoped.

23. The integrated circuit of claim 19, further comprising a back-side contact extending through the bottom surface of the second source or drain region.

24. The integrated circuit according to claim 23, wherein, The back contact portion extends through the entire thickness of the first epitaxial region and into at least a portion of the second epitaxial region.

25. The integrated circuit according to any one of claims 19-24, wherein, There is a visible seam between the first epitaxial region and the second epitaxial region.

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