Integrated circuit device

Abstract

An integrated circuit device includes a plurality of channel layers extending in a first horizontal direction and including a first channel layer and a second channel layer, a gate line surrounding the plurality of channel layers, wherein the gate line includes a first sub-gate arranged between the first channel layer and the second channel layer, a source / drain pattern arranged on a sidewall of the gate line, and a channel passivation layer including a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed between the first sub-gate and the first channel layer, and the second passivation layer is arranged between the first sub-gate and the second channel layer. The plurality of channel layers protrude in the first horizontal direction from the sidewall of the gate line, and the plurality of channel layers include a transition metal dichalcogenide (TMD).

Description

Technical Field

[0001] The present invention relates to integrated circuit devices, and more specifically, to an integrated circuit device comprising a nanosheet field-effect transistor (FET). Background Technology

[0002] Due to advancements in electronic technology, the scaling down of integrated circuit devices is progressing rapidly. Therefore, it is necessary to ensure operational accuracy while maintaining the high operating speed of integrated circuit devices by minimizing leakage current. Consequently, various research efforts are underway to provide integrated circuit devices with structures that reduce leakage current and improve reliability. Summary of the Invention

[0003] The present invention relates to an integrated circuit device comprising a transition metal dichalcogenide (TMD), wherein the mobility of charge carriers is improved by a channel layer having a single crystal structure, and the quality of multiple channel layers is improved.

[0004] The technical problems addressed by this invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art based on the following description.

[0005] According to one aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a plurality of channel layers extending in a first horizontal direction and including a first channel layer and a second channel layer; a gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, wherein the gate line includes a first sub-gate disposed between the first channel layer and the second channel layer; a source / drain pattern disposed on the sidewall of the gate line and connected to the plurality of channel layers; and a channel passivation layer including a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed between the first sub-gate and the first channel layer, and the second passivation layer is disposed between the first sub-gate and the second channel layer. The plurality of channel layers protrude from the sidewall of the gate line in the first horizontal direction, and the plurality of channel layers include a transition metal dichalcogenide (TMD).

[0006] According to another aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a plurality of channel layers extending in a first horizontal direction and including a first channel layer and a second channel layer; a gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, wherein the gate line includes a first sub-gate disposed between the first channel layer and the second channel layer and a second sub-gate disposed on an opposite side of the first sub-gate relative to the first channel layer; a source / drain pattern disposed on a sidewall of the gate line and connected to the plurality of channel layers; a channel passivation layer including a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed between the first sub-gate and the first channel layer, and the second passivation layer is disposed between the first sub-gate and the second channel layer; an insulating spacer disposed between the sidewall of the gate line and the source / drain pattern; and a gate dielectric layer surrounding the first sub-gate. The plurality of channel layers protrude from the insulating spacer in the first horizontal direction. No channel passivation layer is disposed between the first channel layer and the second sub-gate. The first passivation layer is disposed between the gate dielectric layer and the first channel layer, and the gate dielectric layer is in direct contact with the first passivation layer. The plurality of channel layers comprise transition metal dichalcogenides (TMD).

[0007] According to another aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a plurality of channel layers extending in a first horizontal direction and including a first channel layer and a second channel layer; a gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, wherein the gate line includes a first sub-gate disposed between the first channel layer and the second channel layer and a second sub-gate disposed on an opposite side of the first sub-gate relative to the first channel layer; a source / drain pattern disposed on a sidewall of the gate line and connected to the plurality of channel layers; a channel passivation layer including a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed between the first sub-gate and the first channel layer, and the second passivation layer is disposed between the first sub-gate and the second channel layer; an insulating spacer disposed between the sidewall of the gate line and the source / drain pattern; and a gate dielectric layer surrounding the first sub-gate. The plurality of channel layers protrude from the insulating spacer in the first horizontal direction. No channel passivation layer is disposed between the first channel layer and the second sub-gate. The first passivation layer is disposed between the gate dielectric layer and the first channel layer, and the gate dielectric layer is in direct contact with the first passivation layer. The plurality of channel layers comprise transition metal dichalcogenides (TMD). The plurality of channel layers comprise an even number of channel layers. The thickness of each of the plurality of channel layers in a third direction is substantially the same, and the third direction is perpendicular to the first horizontal direction and the second horizontal direction. The plurality of channel layers have a single-crystal structure. The source / drain pattern comprises at least one of a metal, a half-metal, a metal oxide, or a combination thereof. The channel passivation layer comprises at least one of a thiol or S. The channel passivation layer comprises trifluoromethanesulfonylimide (TFSI). The thickness of each of the plurality of channel layers in the third direction is in the range of 0.3 nanometers (nm) to 2.0 nm, and the thickness of the channel passivation layer in the third direction is in the range of 0.1 nm to 0.5 nm.

[0008] According to another aspect of the present invention, an integrated circuit device manufacturing method is provided, the method comprising: alternately stacking a first sacrificial layer and a second sacrificial layer; forming a first opening through at least a portion of the first sacrificial layer and the second sacrificial layer; selectively removing a portion of the second sacrificial layer exposed by the first opening to form a second opening; forming a channel structure on the surface of the first sacrificial layer exposed by the second opening; forming a channel passivation structure; forming a third sacrificial layer to fill the first opening and the second opening; forming a channel passivation layer from the channel passivation structure; forming a plurality of channel layers from the channel structure and forming a source / drain space; removing a portion of the first sacrificial layer and a portion of the third sacrificial layer to form a dummy gate structure; and forming an insulating spacer on the sidewall of the dummy gate structure.

[0009] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein the first sacrificial layer and the second sacrificial layer comprise materials having different nucleation rates for the TMD, and the first sacrificial layer comprises alumina (Al₂O₃). x Zirconium oxide (ZrO) x ) and titanium dioxide (TiO2) x The second sacrificial layer comprises at least one of the following materials, and the second sacrificial layer comprises silicon nitride (SiN). x ) and silicon dioxide (SiO) x At least one of the following materials.

[0010] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein the channel structure comprises a TMD having a single-crystal structure.

[0011] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein a channel structure is formed on the top and bottom surfaces of the first sacrificial layer.

[0012] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein the channel passivation structure comprises at least one of thiol or sulfur (S), and the channel passivation structure comprises TFSI.

[0013] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein, during the formation of the insulating spacer, the channel passivation layer and the plurality of channel layers protrude laterally from the insulating spacer.

[0014] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein a channel passivation layer is alternately disposed between the plurality of channel layers, and the plurality of channel layers includes an even number of channel layers.

[0015] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein the channel passivation layer includes a plurality of passivation layers disposed between a first sacrificial layer and the plurality of channel layers, and the plurality of passivation layers are not disposed between the third sacrificial layer and the plurality of channel layers.

[0016] According to another aspect of the present invention, an integrated circuit device manufacturing method is provided, the method further comprising: forming an insulating layer in the source / drain space; forming a gate dielectric layer and a gate line; and removing the insulating layer to form a plurality of source / drain patterns. When removing the insulating layer, portions at both ends of the channel passivation layer are removed.

[0017] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, wherein, when removing the insulating layer, portions of both ends of the channel passivation layer are removed such that both ends of the channel passivation layer extend to a surface formed by a second surface of the insulating spacer, a first surface of the insulating spacer facing the gate line, and the second surface of the insulating spacer opposite to the first surface of the insulating spacer. Attached Figure Description

[0018] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view of some components of an integrated circuit device according to an embodiment; Figure 2A It shows along Figure 1 A cross-sectional view of the section formed by the section cut by line X1-X1'; Figure 2B yes Figure 2A Enlarged cross-sectional views of some of the components included; Figure 3 It shows along Figure 1 A cross-sectional view of the section formed by the section cut by line Y1-Y2'; Figure 4 It shows along Figure 1 A cross-sectional view of the section formed by the section intercepted by line Y2-Y2'; Figure 5A This is a cross-sectional view showing a portion of the structure of an integrated circuit device according to an embodiment; Figure 5B yes Figure 5A Enlarged cross-sectional views of some of the components included; Figure 6A This is a cross-sectional view showing a portion of the structure of an integrated circuit device according to an embodiment; Figure 6Byes Figure 6A Enlarged cross-sectional views of some of the components included; Figure 7 This is a cross-sectional view showing a portion of the structure of an integrated circuit device according to an embodiment; Figure 8 This is a flowchart illustrating an integrated circuit device manufacturing method according to an embodiment; Figures 9A to 9N This is a view used to sequentially describe an integrated circuit device manufacturing method according to an embodiment. Detailed Implementation

[0019] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0020] Embodiments of the inventive concept are provided to illustrate the inventive concept more fully to those skilled in the art. These embodiments can be modified in various ways, and the scope of the inventive concept is not limited to them. The embodiments are provided so that the inventive concept will be more thorough and complete, and will fully convey the spirit of the inventive concept to those skilled in the art. Furthermore, for ease of explanation and clarity, the thickness and dimensions of each layer in the drawings are exaggerated.

[0021] Figure 1 This is a plan view of some components of the integrated circuit device 100 according to an embodiment. Figure 2A It shows along Figure 1 A cross-sectional view of the section formed by the line X1-X1'. Figure 2B yes Figure 2A Enlarged cross-sectional views of some of the components included. Figure 3 It shows along Figure 1 A cross-sectional view of the section formed by the line Y1-Y2'. Figure 4 It shows along Figure 1 A cross-sectional view constructed from the section intercepted by line Y2-Y2'. More specifically, Figure 2B yes Figure 2A Enlarged cross-sectional view of the first part A1.

[0022] refer to Figures 1 to 4 The present invention will describe an integrated circuit device 100, which includes an active region in the shape of a nanowire or nanosheet and a field-effect transistor (FET) having a gate-all-around structure including a gate surrounding the active region. For example, the integrated circuit device 100 may include a multi-bridge channel FET (MBCFET) device. However, the inventive concept is not limited thereto, and the integrated circuit device 100 may include a planar FET device or a finFET device.

[0023] In an embodiment, the integrated circuit device 100 of the present invention may include a plurality of active regions F1 protruding from a substrate 102 to define a trench region T1 on the substrate 102. The plurality of active regions F1 may extend parallel to each other in a first horizontal direction (X direction) on the substrate 102 and may be spaced apart from each other in a second horizontal direction (Y direction).

[0024] The substrate 102 may include a first surface 102_1 and a second surface 102_2 opposite to the first surface 102_1. A plurality of active regions F1 may extend on the first surface 102_1 of the substrate 102 in a first horizontal direction (X direction).

[0025] In embodiments, substrate 102 may include a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. The terms “SiGe,” “SiC,” “GaAs,” “InAs,” “InGaAs,” and “InP” as used in this specification refer to materials including the elements included in each term and are not chemical formulas representing stoichiometric relationships. Substrate 102 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0026] In one embodiment, device isolation layer 112 may be disposed in trench region T1 defining active region F1. Device isolation layer 112 may cover a portion of the sidewall of active region F1 in trench region T1 and may be spaced apart from substrate 102 in the vertical direction (Z direction). Device isolation layer 112 may include silicon oxide layer.

[0027] In an embodiment, multiple gate lines 160 may be arranged on the active region F1. Each of the multiple gate lines 160 may extend in a second horizontal direction (Y direction). Multiple nanosheet stacks NSS may be arranged on the fin top surface FT of the active region F1 in the region where the active region F1 and the multiple gate lines 160 intersect. Each of the multiple nanosheet stacks NSS may include at least one nanosheet facing the fin top surface FT at a location separated from the fin top surface FT of the active region F1 in a vertical direction (Z direction). As used in this specification, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. Nanosheets should be understood to include nanowires.

[0028] Gate line 160 may include a main gate 160M and a first sub-gate 160SA and a second sub-gate 160SB. The main gate 160M may cover the top surface of the nanosheet stack NSS and may extend in a second horizontal direction (Y direction). The first sub-gate 160SA and the second sub-gate 160SB may be integrally connected to the main gate 160M and may be disposed between the first channel layer N1, the second channel layer N2, the third channel layer N3 and the fourth channel layer N4, and between the active region F1 and the first channel layer N1, respectively.

[0029] The first sub-gate 160SA may be partially disposed between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4. In an embodiment, the first sub-gate 160SA may be disposed between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, wherein a channel passivation layer 122 is disposed. The second sub-gate 160SB may be disposed between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, wherein a channel passivation layer 122 is not disposed.

[0030] In an embodiment, the first sub-gate thickness SG1, which is the thickness of the first sub-gate 160SA in the vertical direction, may be less than the second sub-gate thickness SG2, which is the thickness of the second sub-gate 160SB in the vertical direction.

[0031] Gate line 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from TiN and TaN. The metal carbide may include TiAlC. In embodiments, gate line 160 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal layer are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from Ti, tantalum (Ta), W, Ru, Nb, Mo, and Hf. The gap-filling metal layer may include a W layer or an aluminum (Al) layer. Multiple gate lines 160 may include at least one work function metal layer. At least one work function metal layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In some embodiments, the gate line 160 may include a TiAlC / TiN / W stacked structure, a TiN / TaN / TiAlC / TiN / W stacked structure, or a TiN / TaN / TiN / TiAlC / TiN / W stacked structure. However, the inventive concept is not limited thereto.

[0032] In an embodiment, each of the plurality of nanosheet stacks NSS may include a first channel layer N1, a second channel layer N2, a third channel layer N3, and a fourth channel layer N4 that overlap each other in the vertical direction (Z direction) on the active region F1. The vertical distance (Z direction) from the fin top surface FT of the active region F1 to the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 may be different. Each of the plurality of gate lines 160 may surround the channel layers included in the nanosheet stacks NSS that overlap in the vertical direction (Z direction).

[0033] The number of channel layers included in a nanosheet stack NSS is not limited to this.

[0034] Despite Figure 1 The planar shape of the nanosheet stack NSS shown is approximately square, but the inventive concept is not limited thereto. The nanosheet stack NSS can have various planar shapes depending on the planar shape of each of the active region F1 and the gate lines 160. In the current example, multiple nanosheet stacks NSS and multiple gate lines 160 are arranged on an active region F1, and the multiple nanosheet stacks NSS are arranged in rows on the active region F1 in a first horizontal direction (X direction). However, the number of nanosheet stacks NSS and gate lines 160 arranged on an active region F1 is not particularly limited.

[0035] In an embodiment, the channel thickness TC1, which is the thickness in the vertical direction of each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 included in the nanosheet stack NSS, can have a thickness selected in the range of about 0.3 nanometers (nm) to about 2.0 nm. For example, the channel thickness TC1 can have a thickness selected in the range of about 0.2 nm to about 3.0 nm. However, the inventive concept is not limited thereto. In this case, the thickness of each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 refers to the dimension in the vertical direction (Z direction). In an embodiment, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can have substantially the same thickness in the vertical direction (Z direction). Each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can have a substantially uniform thickness relative to the region of each channel layer.

[0036] As used herein, the expression “substantially the same” can mean having the same value relative to other values ​​compared with it, as those skilled in the art will understand, and allows for approximations, inaccuracies, and limitations in the relevant context. In one or more respects, the terms “substantially,” “approximately,” and “approximately” can provide industry-accepted tolerances for the relativity between their corresponding terms and / or items, such as tolerances of ±1%, ±5%, or ±10% of the stated actual value, and other suitable tolerances.

[0037] In an embodiment, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 included in a nanosheet stack NSS can have substantially the same dimensions in a first horizontal direction (X direction). Although in Figure 2A The illustration shows multiple nanosheet stacks (NSS), each comprising four channel layers, but the inventive concept is not limited thereto. For example, due to the method 1000 for manufacturing an integrated circuit device described below, the nanosheet stack NSS may include at least two channel layers, or the number of channel layers constituting the nanosheet stack NSS may be an even number. For example, the number of channel layers constituting the nanosheet stack NSS may be an even number such as 2, 4, 6, or greater, because in the method 1000 for manufacturing an integrated circuit device described below, the channel layers may be formed in units of two.

[0038] In an embodiment, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 included in a nanosheet stack NSS can be spaced apart from each other by equal spacing. For example, the first gap G1, which is the vertical distance between the first channel layer N1 and the second channel layer N2, the second gap G2, which is the vertical distance between the second channel layer N2 and the third channel layer N3, and the third gap G3, which is the vertical distance between the third channel layer N3 and the fourth channel layer N4, can be substantially the same.

[0039] In this embodiment, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 may comprise two-dimensional semiconductor materials. Here, two-dimensional material can refer to a material having a layered structure in which the constituent atoms are bonded two-dimensionally. Two-dimensional materials with semiconductor properties exhibit excellent electrical properties and can maintain high mobility without significantly altering their properties even when the thickness is reduced to the nanoscale. For example, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 may comprise transition metal dichalcogenides (TMDs). In other embodiments, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 may comprise graphene.

[0040] In embodiments, the TMD, as a two-dimensional material with semiconductor properties, can refer to a compound of a transition metal and a chalcogenide. Here, the transition metal can include at least one of, for example, Mo, W, Nb, vanadium (V), Ta, Ti, zirconium (Zr), Hf, Co, technetium (Tc), or rhenium (Re), and the chalcogenide can include at least one of, for example, sulfur (S), selenium (Se), or tellurium (Te). As a specific example, the TMD can include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, and ReSe2. However, the inventive concept is not limited thereto.

[0041] In an embodiment, each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 included in the nanosheet stack NSS may comprise a single-crystal TMD. For example, each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 included in the nanosheet stack NSS may comprise a single-crystal MoS2, WS2, or WSe2.

[0042] Unlike polycrystalline TMDs, monocrystalline TMDs lack grain boundaries, and therefore the charge carrier (electron and hole) mobility in each of the first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 of a monocrystalline TMD can be relatively high. Consequently, the performance of an integrated circuit comprising the first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 of a monocrystalline TMD can be higher than that of an integrated circuit comprising the first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 of a polycrystalline TMD.

[0043] Furthermore, in the integrated circuit device 100 according to the embodiment, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, which include a single crystal TMD, are not generated separately, but are formed in the integrated circuit device manufacturing method 1000 by a single process as described below.

[0044] Unlike conventional processes that perform deposition processes on each channel layer, the integrated circuit device 100 according to the embodiment may include a channel comprising a single-crystal TMD having a uniform thickness through a single process. After forming the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, the formation of possible oxides can be prevented by the channel passivation layer 122 described below, and simultaneously, doping of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be performed by the channel passivation layer 122.

[0045] The first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 of the single-crystal TMD can be formed by selective region growth in the integrated circuit device manufacturing method 1000 described below, which will be described in detail below. The single-crystal ratio of the first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 can be, for example, in the range of 95% to 99.9%, or in the range of 99% to 100%. However, the inventive concept is not limited to these numerical ranges.

[0046] The channel passivation layer 122 may be disposed on one surface of each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4. In an embodiment, the channel passivation layer 122 may be partially disposed between two adjacent channel layers of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4. In an embodiment, the channel passivation layer 122 may be alternately disposed between two adjacent channel layers of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4. For example, the channel passivation layer 122 may be disposed between the first channel layer N1 and the second channel layer N2, the channel passivation layer 122 may not be disposed between the second channel layer N2 and the third channel layer N3, and the channel passivation layer 122 may be disposed between the third channel layer N3 and the fourth channel layer N4.

[0047] The first passivation layer 122A may be disposed on one surface of the first channel layer N1. The second passivation layer 122B may be disposed on one surface of the second channel layer N2 adjacent to the first channel layer N1. The first passivation layer 122A and the second passivation layer 122B may be included in the channel passivation layer 122.

[0048] The first passivation layer 122A can directly contact the top surface of the first channel layer N1. The length of the first passivation layer 122A in the first horizontal direction can be less than the length of the first channel layer N1 in the first horizontal direction. The first passivation layer 122A can overlap with the first channel layer N1 in the vertical direction. In an embodiment, the entire first passivation layer 122A can overlap with the first channel layer N1 in the vertical direction. That is, the first passivation layer 122A can be included in the first channel layer N1 in the first horizontal direction.

[0049] The second passivation layer 122B can be in direct contact with the bottom surface of the second channel layer N2. The length of the second passivation layer 122B in the first horizontal direction can be less than the length of the second channel layer N2 in the first horizontal direction. The second passivation layer 122B can overlap with the second channel layer N2 in the vertical direction. In an embodiment, the entire second passivation layer 122B can overlap with the second channel layer N2 in the vertical direction. That is, the second passivation layer 122B can be included in the second channel layer N2 in the first horizontal direction.

[0050] For example, the channel passivation layer 122 may have a thickness of 0.1 nm to 0.5 nm in the vertical direction. That is, each of the first passivation layer 122A and the second passivation layer 122B may have a thickness of 0.1 nm to 0.5 nm in the vertical direction. For example, the channel passivation layer 122 may have a thickness of 0.1 nm to 1.0 nm in the vertical direction.

[0051] The channel passivation layer 122 may include a chemical material comprising thiols or sulfur. In embodiments, the channel passivation layer 122 may include 3-octyl mercaptan, ethanethiol, and diphenyl sulfide. In addition to 3-octyl mercaptan, ethanethiol, or diphenyl sulfide, the channel passivation layer 122 may also include trifluoromethanesulfonylimide (TFSI).

[0052] The channel passivation layer 122, having such a material composition, can control the charge carrier concentration at each surface of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, including the TMD, thereby generating a doping effect for the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4. Additionally, the channel passivation layer 122 can prevent oxidation of the surfaces of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 that may occur during the manufacturing process.

[0053] The two sidewalls of gate line 160 may be covered on the active region F1 by insulating spacer 120. Insulating spacer 120 may cover the two sidewalls of the main gate 160M, the two sidewalls of each of the plurality of sub-gates 160SA and 160SB, and the two sidewalls of the covering insulating pattern 168. Insulating spacer 120 may be spaced apart from gate line 160, and gate dielectric layer 152 is interposed between insulating spacer 120 and gate line 160. Insulating spacer 120 may comprise silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof. The terms “SiCN,” “SiBN,” “SiON,” “SiOCN,” “SiBCN,” and “SiOC” as used in this specification refer to materials including the elements included in each term and are not chemical formulas representing stoichiometric relationships.

[0054] The insulating spacer 120 may include a first spacer 120A and a second spacer 120B. Each of the first spacer 120A and the second spacer 120B may be disposed between two adjacent channel layers.

[0055] The first spacer 120A may be disposed between the first passivation layer 122A and the second passivation layer 122B. In an embodiment, the upper end and the lower end of the first spacer 120A may contact the first passivation layer 122A and the second passivation layer 122B, respectively.

[0056] The first sidewall of the first spacer 120A may face the first sub-gate 160SA, and the gate dielectric layer 152 may be located between the first spacer 120A and the first sub-gate 160SA. The second sidewall of the first spacer 120A may contact the source / drain pattern 130. The first sidewall and the second sidewall of the first spacer 120A may be opposite sides of each other.

[0057] One end of the first passivation layer 122A may extend to the second sidewall of the first spacer 120A. Or, as Figure 2B As shown in the partially enlarged circular view, one end of the first passivation layer 122C may protrude beyond the second sidewall of the first spacer 120A. In other words, one end of the first passivation layer 122C may extend beyond the second sidewall of the first spacer 120A.

[0058] One end of the first passivation layer 122A may extend to the second sidewall of the first spacer 120A, or one end of the first passivation layer 122A may extend beyond the second sidewall of the first spacer 120A, such that one end of the first passivation layer 122A may extend to the surface formed by the second sidewall of the first spacer 120A.

[0059] like Figure 2B As shown in the enlarged circular view of a portion, the first passivation layer 122C may have a shape in which the width of the first passivation layer 122C decreases as the first passivation layer 122C moves away from the first channel layer N1 in the portion adjacent to the first channel layer N1.

[0060] In an embodiment, at least a portion of the upper and lower ends of the second spacer 120B may contact the channel layer. The second spacer 120B may be disposed on the opposite side of the first spacer 120A based on the first channel layer N1. For example, the second spacer 120B disposed on the opposite side of the first spacer 120A based on the first channel layer N1 may have an upper end that contacts the bottom surface of the first channel layer N1.

[0061] The second spacer 120B disposed between the second channel layer N2 and the third channel layer N3 may have an upper end and a lower end that respectively contact the third channel layer N3 and the second channel layer N2.

[0062] The first sidewall of the second spacer 120B may face the second sub-gate 160SB, and the gate dielectric layer 152 may be located between the second spacer 120B and the second sub-gate 160SB. The second sidewall of the second spacer 120B may contact the source / drain pattern 130. The first sidewall and the second sidewall of the first spacer 120A may be opposite sides of each other.

[0063] The insulating spacer 120 can be provided as a single body up to the top of a nanosheet stack NSS that includes a first spacer 120A and a second spacer 120B adjacent to the first channel layer N1, the second channel layer N2, the third channel layer N3 and the fourth channel layer N4, the main gate 160M and the nanosheet stack NSS covering the insulating pattern 168.

[0064] The gate dielectric layer 152 may be located between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 and the gate line 160. The gate dielectric layer 152 may include a portion of the surface covering the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, a portion of the sidewall covering the main gate 160M, a portion of the fin top surface FT covering the active region F1, and a portion of the top surface covering the device isolation layer 112.

[0065] In an embodiment, for example, the gate dielectric layer 152 may include a high-k dielectric layer. The high-k dielectric layer may include a material having a higher dielectric constant than the silicon oxide layer. For example, the high-k dielectric layer may have a dielectric constant of about 10 to about 25. The high-k dielectric layer may include hafnium oxide. However, the inventive concept is not limited thereto.

[0066] In this embodiment, a plurality of source / drain patterns 130 may be arranged between the plurality of gate lines 160. Each of the plurality of source / drain patterns 130 may be positioned adjacent to at least one gate line 160 selected from the plurality of gate lines 160. Each of the plurality of source / drain patterns 130 may have a surface facing an adjacent channel layer.

[0067] Each portion of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 that protrudes from the sidewall of the insulating spacer 120 in the first horizontal direction can be surrounded by the source / drain pattern 130. For example, the sidewall, top surface, and bottom surface of the first channel layer N1 can be surrounded by the source / drain pattern 130 and can be in direct contact with the source / drain pattern 130. The portions of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 that protrude from the sidewall of the insulating spacer 120 ensure a contact area between the source / drain pattern 130 and the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4.

[0068] The source / drain pattern 130 may include a metallic material. In embodiments, the source / drain pattern 130 may include a half-metallic material. The half-metallic material may include bismuth (Bi), arsenic (As), and antimony (Sb). However, the inventive concept is not limited thereto. Because the source / drain pattern 130 includes a metallic material, ohmic contacts can be formed between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 and the source / drain pattern 130. Hereinafter, the source / drain pattern 130 is described as including a metallic material.

[0069] For example, the source / drain pattern 130 may include an alloy comprising at least one or a combination of metallic materials including Ti, Ni, Pd, gold (Au), Pt, W, Mo, Co, chromium (Cr), and silver (Ag). For example, the source / drain pattern 130 may include multiple layers comprising metallic materials.

[0070] In an embodiment, such as Figure 3 As shown, the source / drain pattern 130 may have substantially vertically extending sidewalls and a flat top surface, and the two sidewalls of the source / drain pattern 130 may be continuously connected to the first surface 102_1 of the substrate 102. However, the shape of the source / drain pattern 130 is not limited to this.

[0071] However, it is not excluded that each of the plurality of source / drain patterns 130 includes an epitaxially grown semiconductor layer. In embodiments, each of the plurality of source / drain patterns 130 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers. When the source / drain pattern 130 constitutes an n-channel metal-oxide-semiconductor (NMOS) field-effect transistor (MOSFET), the source / drain pattern 130 may include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb).

[0072] In an embodiment, a plurality of recesses R1 may be formed in the active region F1. The vertical height of the lowermost surface of each of the plurality of recesses R1 may be lower than the vertical height of the fin top surface FT of the active region F1. Each of the plurality of source / drain patterns 130 may have a complementary shape along the shape formed by the plurality of recesses R1 and the fin top surface FT.

[0073] In some embodiments, each of the plurality of source / drain patterns 130 may contact at least a portion of the plurality of recesses R1 and the fin top surface FT. Each of the plurality of source / drain patterns 130 may have a shape that fills each of the plurality of recesses R1. In addition, each of the plurality of source / drain patterns 130 may fill the region between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 protruding from the insulating spacer 120 toward the source / drain pattern 130, and may fill the region between the first channel layer N1 and the active region F1.

[0074] In an embodiment, the insulating pad 142 and the gate-to-gate insulating layer 144 may be sequentially arranged on a plurality of source / drain patterns 130. The insulating spacer 120 and the plurality of source / drain patterns 130 may be covered by the insulating pad 142. In an embodiment, the insulating pad 142 may comprise SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, or combinations thereof. However, the inventive concept is not limited thereto. The gate-to-gate insulating layer 144 may comprise a silicon oxide layer. However, the inventive concept is not limited thereto.

[0075] In an embodiment, a plurality of source / drain contacts CA can be arranged on a plurality of source / drain patterns 130. Each of the plurality of source / drain contacts CA can penetrate the insulating pad 142 and the gate-to-gate insulating layer 144 in the vertical direction (Z direction) and can be electrically connected to at least one source / drain pattern 130 selected from the plurality of source / drain patterns 130. The plurality of source / drain contacts CA can contact the plurality of source / drain patterns 130 respectively.

[0076] Multiple source / drain contacts CA can be electrically connected to multiple source / drain patterns 130, respectively. Each of the multiple source / drain contacts CA can be spaced apart from the main gate 160M of the gate line 160 in a first horizontal direction (X direction), with insulating spacers 120 located between them.

[0077] In an embodiment, each of the plurality of source / drain contacts CA may include a conductive barrier layer 174 and a contact plug 176. The bottom surface and sidewalls of the contact plug 176 may be covered by the conductive barrier layer 174. The conductive barrier layer 174 may include a metal or a conductive metal nitride. For example, the conductive barrier layer 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof. However, the inventive concept is not limited thereto. The contact plug 176 may include Mo, W, Co, Ru, manganese (Mn), Ti, Ta, Al, Cu, combinations thereof, or alloys thereof. However, the inventive concept is not limited thereto. In some embodiments, the conductive barrier layer 174 may be omitted from each of the plurality of source / drain contacts CA.

[0078] In one embodiment, the top surface of each of the source / drain contact CA, the overlay insulating pattern 168, the insulating pad 142, and the gate inter-insulating layer 144 may be covered by the upper insulating structure 180. The upper insulating structure 180 may include an etch stop layer 182 and an interlayer insulating layer 184 sequentially stacked on each of the plurality of source / drain contacts CA, the plurality of overlay insulating patterns 168, and the gate inter-insulating layer 144.

[0079] The etch stop layer 182 may include SiC, SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or combinations thereof.

[0080] Interlayer insulating layer 184 may include an oxide layer, a nitride layer, an ultra-low k (ULK) layer with an ultra-low dielectric constant K of about 2.2 to about 2.4, or combinations thereof. For example, interlayer insulating layer 184 may include a tetraethyl orthosilicate (TEOS) layer, a high-density plasma (HDP) oxide layer, a borosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiN layer, a SiOC layer, a SiCOH layer, or combinations thereof. However, the inventive concept is not limited thereto.

[0081] In an embodiment, multiple source / drain path contacts VA can be arranged on multiple source / drain contacts CA. Each of the multiple source / drain path contacts VA can contact the source / drain contact CA through the upper insulating structure 180. Each of the multiple source / drain patterns 130 can be electrically connected to the source / drain path contact VA through the metal silicide layer 172 and the source / drain contact CA. The bottom surface of each of the multiple source / drain path contacts VA can contact the top surface of the source / drain contact CA. Each of the multiple source / drain path contacts VA can include Mo or W. However, the inventive concept is not limited thereto.

[0082] In this embodiment, the top surface of the upper insulating structure 180 and each of the plurality of source / drain path contacts VA may be covered by the upper insulating layer 192. The material constituting the upper insulating layer 192 is substantially the same as that described above for the material constituting the interlayer insulating layer 184.

[0083] In an embodiment, a plurality of upper wiring layers M1 may be arranged through the upper insulating layer 192. Each of the plurality of upper wiring layers M1 may be electrically connected to one of a plurality of source / drain path contacts VA selected below it. The plurality of upper wiring layers M1 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof. However, the inventive concept is not limited thereto.

[0084] In the integrated circuit device 100 according to an embodiment, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 may comprise a single-crystal TMD, thereby improving the charge carrier mobility in the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4. Because the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 are formed through a single process, it is possible to form the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 with consistent quality. Furthermore, oxidation of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be prevented by the channel passivation layer 122. These features can improve the performance and quality of the integrated circuit device.

[0085] Figure 5A This is a cross-sectional view showing a portion of the structure of the integrated circuit device 100A according to an embodiment. Figure 5B yes Figure 5A Enlarged cross-sectional views of some of the components included. More specifically, Figure 5B yes Figure 5A The enlarged cross-sectional view of Part A2. Anything not described below may be substantially the same as what is described above.

[0086] refer to Figure 5A and Figure 5B In the integrated circuit device 100A according to an embodiment, the first sub-gate thickness SG1, which is the thickness of the first sub-gate 160SA in the vertical direction, can be substantially equal to the second sub-gate thickness SG2, which is the thickness of the second sub-gate 160SB in the vertical direction. The first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 included in a nanosheet stack NSS can have alternating spacing between adjacent channel layers.

[0087] For example, the first gap G1, which is the vertical distance between the first channel layer N1 and the second channel layer N2, can be different from the second gap G2, which is the vertical distance between the second channel layer N2 and the third channel layer N3. The second gap G2 can be different from the third gap G3, which is the vertical distance between the third channel layer N3 and the fourth channel layer N4. Furthermore, the first gap G1 can be substantially the same as the third gap G3.

[0088] Because the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 are formed in a single manufacturing process, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can have substantially the same thickness in the vertical direction (Z direction).

[0089] Figure 6A This is a cross-sectional view showing a portion of the structure of the integrated circuit device 100B according to an embodiment. Figure 6B yes Figure 6A Enlarged cross-sectional views of some of the components included. More specifically, Figure 6B yes Figure 6A Part A3 is an enlarged cross-sectional view. Anything not described below may be substantially the same as what is described above.

[0090] refer to Figure 6A and Figure 6B The integrated circuit device 100B according to an embodiment may include a plurality of channel barriers 124, each surrounding two lateral ends of each of the first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 included in the nanosheet stack NSS. For example, each of the plurality of channel barriers 124 may be disposed at two lateral ends of each of the first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4.

[0091] Multiple channel barriers 124 can be disposed between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 and multiple source / drain patterns 130. The first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be spaced apart from the multiple source / drain patterns 130, and the multiple channel barriers 124 can be disposed between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 and the multiple source / drain patterns 130, respectively. In an embodiment, the lateral ends of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be completely surrounded by the multiple channel barriers 124.

[0092] The plurality of channel barriers 124 may be in direct contact with the channel passivation layer 122 and may also be in contact with the second spacer 120B. In other embodiments, the plurality of channel barriers 124 may be in contact with the channel passivation layer 122 and the adjacent first spacer 120A.

[0093] The plurality of channel barriers 124 may include transition metals. Specifically, the transition metals included in the plurality of channel barriers 124 may be group IV transition metals. For example, the plurality of channel barriers 124 may include at least one of Ti, Zr, or Hf. However, the inventive concept is not limited thereto. In embodiments, the plurality of channel barriers 124 may include TMDs.

[0094] By using multiple channel barriers 124, after the formation of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be protected during the process. For example, as shown below... Figure 9M In the process of forming the source / drain pattern 130 of the filled source / drain region SDS as described herein, damage to the first channel layer N1, the second channel layer N2, the third channel layer N3 and the fourth channel layer N4 that may occur during the process of forming the source / drain pattern 130 by deposition can be prevented by multiple channel barriers 124.

[0095] For example, in the process of forming the source / drain pattern 130, metal deposition can be performed at high temperatures or in a plasma state. The first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 of the TMD exposed to such conditions may contain S and / or selenium (Se) that may escape at high temperatures. Alternatively, during the process of forming the source / drain pattern 130, the surfaces of the first channel layer N1, second channel layer N2, third channel layer N3, and fourth channel layer N4 may be oxidized or subject to unintended recombination reactions. Potential problems can be prevented by multiple channel barriers 124.

[0096] Furthermore, the contact resistance between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 and the source / drain pattern 130 can be reduced by using multiple channel barriers 124. For example, ohmic contact between the source / drain pattern 130 and the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be achieved by using multiple channel barriers 124. That is, by using multiple channel barriers 124 of the integrated circuit device 100B according to the embodiment, the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be protected, and at the same time, the contact quality between the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 and the source / drain pattern 130 can be improved.

[0097] Figure 7 This is a cross-sectional view showing a portion of the construction of the integrated circuit device 100C according to an embodiment. Anything not described below may be substantially the same as that described above.

[0098] refer to Figure 7The source / drain pattern 130 constituting the integrated circuit device 100C according to the embodiment can extend from the fin top surface FT and the recess R1 on the top surface of the substrate 102 to the etch stop layer 182. The source / drain pattern 130 can be in integral contact with the sidewalls of two adjacent insulating spacers 120 facing each other, wherein the source / drain pattern 130 is located between two adjacent insulating spacers 120 facing each other. That is, unlike the integrated circuit device 100 described above, Figure 7 The integrated circuit device 100C may not include the insulating pad 142, the gate-to-gate insulating layer 144, and multiple source / drain contacts CA.

[0099] The source / drain pattern 130 may include metal and / or half-metal, and the source / drain path contact VA may be in direct contact with the top surface of the source / drain pattern 130. The source / drain path contact VA may have a conductive barrier layer disposed on its surface.

[0100] The source / drain pattern 130 can directly contact the source / drain path contact VA, allowing the source / drain pattern 130 to be electrically connected to the source / drain path contact VA. Because the source / drain pattern 130 includes metal and / or half-metal, the contact resistance between the source / drain pattern 130 and the source / drain path contact VA can be reduced, thereby improving the performance of the integrated circuit device 100C according to the embodiment.

[0101] Figure 8 This is a flowchart illustrating an integrated circuit device manufacturing method 1000 according to an embodiment. Figures 9A to 9N This is a view used to sequentially describe an integrated circuit device manufacturing method 1000 according to an embodiment. Anything not described below may be substantially the same as that described above.

[0102] refer to Figure 8 You can refer to this. Figures 9A to 9N Specifically, a flowchart illustrating an integrated circuit device manufacturing method 1000 according to an embodiment is given.

[0103] refer to Figure 9A Multiple first sacrificial layers 104 and multiple second sacrificial layers 106 can be stacked alternately on the substrate 102. The first sacrificial layers 104 stacked on top can be formed to have a thickness greater than the other first sacrificial layers 104 in the vertical direction, which can be used to form the main gate 160M and the cover insulating pattern 168 to be formed in subsequent processes.

[0104] In an embodiment, the plurality of first sacrificial layers 104 and the plurality of second sacrificial layers 106 may comprise materials with different nucleation rates for the TMD. In an embodiment, the first sacrificial layers 104 may be directly disposed on the top surface of the substrate 102, and the plurality of first sacrificial layers 104, alternately stacked with the plurality of second sacrificial layers 106, may comprise alumina (Al₂O₃). x Zirconium oxide (ZrO) x ) and titanium dioxide (TiO2) x At least one of the following materials. The plurality of second sacrificial layers 106 disposed on a first sacrificial layer 104 directly disposed on the substrate 102 and stacked alternately with the plurality of first sacrificial layers 104 may include silicon nitride (SiN). x ) and silicon dioxide (SiO) x At least one of the following materials.

[0105] For example, when molybdenum disulfide (MoS2) is used as the material to form the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, which will be described below, the nucleation rate is in the range of AlO. x Multiple first sacrificial layers 104 can be high, and include SiN x or SiO x The multiple second sacrificial layers 106 can be low. Therefore, selective region growth is performed such that the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 of the single-crystal TMD can be formed in a flat plate shape including a uniform thickness, with reference... Figure 9D This will be described in detail.

[0106] refer to Figure 9B A process can be performed to remove multiple first sacrificial layers 104 and multiple second sacrificial layers 106 in the vertical direction to form a first opening OP1 reaching the active region F1. For example, the multiple first sacrificial layers 104 and multiple second sacrificial layers 106 can be sequentially removed from the top using reactive ion etching (RIE) or inductively coupled plasma (ICP) etching to form the first opening OP1. Although in Figure 9B The diagram shows that the first opening OP1 is formed only in one location, but in reality, the first opening OP1 can be formed repeatedly at specific intervals in the horizontal direction.

[0107] refer to Figure 9CThe cross-sections of the plurality of second sacrificial layers 106 exposed through the first opening OP1 can be selectively removed. For example, by using a wet etchant such as an HF series or a buffered oxide etchant (BOE), the plurality of first sacrificial layers 104 can be left unremoved, and only the plurality of second sacrificial layers 106 can be removed. Therefore, the cross-sections of the plurality of second sacrificial layers 106 exposed through the first opening OP1 can be selectively etched in the horizontal direction. A portion of the plurality of second sacrificial layers 106 can be removed, such that a plurality of second openings OP2 can be formed between the plurality of first sacrificial layers 104. Because the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, as well as the channel passivation layer 122, are formed in the plurality of second openings OP2 by the subsequent processes described below, it is necessary to appropriately control the degree of etching of the plurality of second sacrificial layers 106.

[0108] refer to Figure 9D The channel structure 108 can be formed in the second opening OP2 formed in the previous process. In an embodiment, the channel structure 108 may include a single-crystal TMD. The channel structure 108 can be formed by chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

[0109] For example, the TMD deposited by the deposition process described above has a high nucleation rate on multiple first sacrificial layers 104 and a low nucleation rate on multiple second sacrificial layers 106, so that the channel structure 108 can grow on multiple first sacrificial layers 104 at a relatively high growth rate.

[0110] TMD has a plate-like crystal structure, making it more likely to bond in a plane. Because the nucleation rate is high on the multiple first sacrificial layers 104, TMD nuclei are formed on the multiple first sacrificial layers 104 at the start of the deposition process, and then TMD layers can be formed planarly on the multiple first sacrificial layers 104.

[0111] Due to the formation characteristics of this TMD, such as Figure 9D As shown, a first channel structure 108A is formed on the top surface of the first sacrificial layer 104 in the second opening OP2, and a second channel structure 108B is formed on the bottom surface of the first sacrificial layer 104 to face the first channel structure 108A. However, TMD formation does not occur or hardly occurs on the side surfaces of the plurality of first sacrificial layers 104 introduced into the first opening OP1.

[0112] In this embodiment, compared to the first channel structure 108A or the second channel structure 108B, a relatively small number of third channel structures 108S can be formed on the sidewall of the second sacrificial layer 106, such as... Figure 9DAs shown. In this case, a first channel structure 108A, a second channel structure 108B, and a third channel structure 108S can be formed along the first sacrificial layer 104 and the second sacrificial layer 106 exposed to the second opening OP2.

[0113] In other embodiments, a channel structure may not be formed on the sidewalls of the second sacrificial layer 106 exposed to the second opening OP2. In some embodiments, a TMD layer may be formed on the first sacrificial layer 104 stacked on top. The TMD layer can be removed by performing an additional process.

[0114] refer to Figure 9E A channel passivation structure 122E can be formed in one of the multiple channel structures 108 formed in the second opening OP2. The channel passivation structure 122E with a substantially uniform thickness can be formed on the exposed surfaces of the multiple channel structures 108 facing the second opening OP2. The channel passivation structure 122E can be formed by deposition or immersion. However, the inventive concept is not limited thereto.

[0115] Here, the channel passivation structure 122E may include thiols or S, and may also include TFSI. In embodiments, the channel passivation structure 122E may include 3-octyl mercaptan, ethanethiol, and diphenyl sulfide.

[0116] refer to Figure 9F A third sacrificial layer 104F can be formed to fill the first opening OP1 and the plurality of second openings OP2. The third sacrificial layer 104F may comprise the same material as the first sacrificial layer 104. However, the inventive concept is not limited thereto. Along Figure 9F The dotted lines shown can be removed in subsequent processes. Figure 9F It is part of the structure. In embodiments, chemical mechanical polishing (CMP) can be performed on the uppermost surface exposed to the outside as needed. In the present specification, Figure 9F The process structure can be referred to as a stacked structure.

[0117] refer to Figure 9G It can remove Figure 9F A portion of the structure is used to form multiple source / drain spaces (SDS). In an embodiment, portions of the second sacrificial layer 106, the first channel structure 108A, the second channel structure 108B, the third channel structure 108S, and the channel passivation structure 122E formed on the third channel structure 108S can be removed. Furthermore, portions of the third sacrificial layer 104F and the adjacent portions of the multiple first sacrificial layers 104, a portion of the first channel structure 108A, a portion of the second channel structure 108B, and a portion of the channel passivation structure 122E can be removed.

[0118] Multiple source / drain space SDSs can be formed by dry etching, and during the formation process, a portion of the active region F1 can be etched to form multiple recesses R1. The vertical height of the lowermost surface of each of the multiple recesses R1 can be lower than the vertical height of the fin top surface FT of the active region F1. However, the formation of multiple source / drain space SDSs is not limited to dry etching.

[0119] Due to the formation of multiple source / drain spaces (SDS), the following structure can be formed: multiple first sacrificial layers 104, a first channel layer N1, a second channel layer N2, a third channel layer N3 and a fourth channel layer N4, a channel passivation layer 122, and multiple third sacrificial layers 104F having substantially the same planar area to interact with... Figure 9G Stacked in the same order.

[0120] In the method 1000 for manufacturing an integrated circuit device according to an embodiment, due to, in particular, as shown in the example Figure 9D The above-described process, which results in forming multiple channel structures 108 serving as the basis for the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 on the plane of the first sacrificial layer 104 exposed to the second opening OP2, can form an even number of channel layers included in a nanosheet stack NSS. Additionally, as shown... Figure 9D As shown, multiple channel structures 108, which serve as the basis for the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 of the integrated circuit device 100, are formed by a single recovery process. Therefore, the thickness of each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 formed by subsequent processes is more consistent than the thickness of an integrated circuit device manufactured by sequentially stacking integrated circuit devices in a conventional manner, and the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be manufactured with a consistently high level of quality.

[0121] refer to Figure 9H A portion of each of the plurality of first sacrificial layers 104A and the plurality of third sacrificial layers 104F exposed in each of the plurality of source / drain spaces SDS is removed, such that the plurality of source / drain spaces SDS can extend laterally. The structure in which the plurality of source / drain spaces SDS extend laterally and the plurality of first sacrificial layers 104A and the plurality of third sacrificial layers 104F are partially removed can be referred to as a dummy gate structure.

[0122] refer to Figure 9IAn insulating spacer 120 can be formed. In an embodiment, the insulating spacer 120 can be formed on the sidewalls of a plurality of first sacrificial layers 104A and a plurality of third sacrificial layers 104F exposed in each of the plurality of source / drain spaces SDS. The first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, as well as the channel passivation layer 122, can protrude laterally from the insulating spacer 120.

[0123] The insulating spacer 120 may cover the sidewalls of a plurality of first sacrificial layers 104A and a plurality of third sacrificial layers 104F in the first horizontal direction. Pairs of insulating spacers 120 may be formed on the sidewalls of the plurality of first sacrificial layers 104A and the plurality of third sacrificial layers 104F, with the plurality of first sacrificial layers 104A and the plurality of third sacrificial layers 104F stacked therebetween. The insulating spacer 120 may comprise silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof.

[0124] refer to Figure 9J An insulating layer 132 can be formed to fill multiple active region recesses R1 and multiple source / drain spaces SDS located between mutually facing insulating spacers 120. The insulating layer 132 can cover the sidewalls of the multiple insulating spacers 120, the sidewalls of the first channel layer N1, the sidewalls of the second channel layer N2, the sidewalls of the third channel layer N3 and the fourth channel layer N4, and the sidewalls of the channel passivation layer 122. The insulating layer 132 may include silicon oxide (SiO2). However, the inventive concept is not limited thereto.

[0125] After forming the insulating layer 132, a plurality of dummy gate structures disposed between the insulating spacers 120 can be removed. A sub-gate space GSS and a main gate space GMS defined by the insulating spacers 120, the fin top surface FT, and the channel layer can be formed. The plurality of dummy gate structures may include a plurality of first sacrificial layers 104A and a plurality of third sacrificial layers 104F. In some embodiments, the main gate space GMS can be formed first, and then the sub-gate space GSS can be formed.

[0126] refer to Figure 9K , can Figure 9J The process results in the formation of a high-k dielectric layer to form a gate dielectric layer 152 covering the exposed surfaces of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4, multiple active regions F1, and the exposed surface of the channel passivation layer 122. After forming a conductive layer to fill the remaining sub-gate space GSS and main gate space GMS after forming the gate dielectric layer 152, the conductive layer can be etched back to make the upper part of the main gate space GMS empty again.

[0127] As a result, a gate line 160 covering the gate dielectric layer 152 can be formed. The gate line 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The gate line 160 can be formed using an ALD process or a CVD process.

[0128] Subsequently, an insulating pattern 168 can be formed on the gate line 160 to fill the space between the upper part of the main gate 160M and the insulating spacer 120.

[0129] refer to Figure 9L The insulating layer 132 can be removed to form the source / drain space SDS. In the process of removing the insulating layer 132, portions of the channel passivation layer 122 that protrude laterally from the insulating spacer 120 can be removed. As a result, the top or bottom surface of each of the first channel layer N1, the second channel layer N2, the third channel layer N3, and the fourth channel layer N4 can be exposed to the source / drain space SDS.

[0130] refer to Figure 9M Multiple source / drain patterns 130 can be formed to occupy at least a portion of the source / drain space SDS. The multiple source / drain patterns 130 can comprise metals or half-metals and can be formed by deposition. Here, physical vapor deposition (PVD), CVD, or ALD can be used as the deposition process. In some embodiments, heat treatment can be performed to provide ohmic contact with other components of the multiple source / drain patterns 130.

[0131] refer to Figure 9N After forming an insulating pad 142 covering multiple source / drain patterns 130 and forming an inter-gate insulating layer 144 on the insulating pad 142, a process for planarizing the insulating pad 142 and the inter-gate insulating layer 144 can be performed.

[0132] Refer again Figure 2A , Figure 2B , Figure 3 and Figure 4 Multiple source / drain contact holes (not shown) can be formed to expose multiple source / drain patterns 130 through an insulating structure including an insulating pad 142 and an inter-gate insulating layer 144. Partial areas of the multiple source / drain patterns 130 can be removed through the source / drain contact holes (not shown) by an anisotropic etching process, so that the multiple source / drain contact holes (not shown) can extend further toward the substrate 102.

[0133] Subsequently, source / drain contacts CA can be formed, including a conductive barrier layer 174 formed in the space of a plurality of source / drain contact holes (not shown) and in contact with a portion of the exposed source / drain pattern 130 and contact plugs 176.

[0134] Subsequently, an etch stop layer 182 and an interlayer insulating layer 184 covering the top surface of the gate inter-insulating layer 144, the top surface of the plurality of source / drain contacts CA, and the top surface of the plurality of insulating patterns 168 can be sequentially formed to form an upper insulating structure 180, and a plurality of source / drain path contacts VA connected to the plurality of source / drain contacts CA can be formed through the upper insulating structure 180 in the vertical direction.

[0135] Subsequently, an upper insulating layer 192 can be formed covering the top surface of the upper insulating structure 180 and the top surface of the multiple source / drain path contacts VA, and multiple upper wiring layers M1 connected to the multiple source / drain path contacts VA can be formed through the upper insulating layer 192 in the vertical direction.

[0136] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: A plurality of channel layers, the plurality of channel layers extending in a first horizontal direction and including a first channel layer and a second channel layer; A gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, the gate line including a first sub-gate disposed between the first channel layer and the second channel layer; Source / drain patterns are arranged on the sidewalls of the gate lines and connected to the plurality of channel layers; as well as A channel passivation layer, comprising a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed between the first sub-gate and the first channel layer, and the second passivation layer is disposed between the first sub-gate and the second channel layer. The plurality of channel layers protrude from the sidewalls of the gate lines in the first horizontal direction, and The plurality of channel layers include transition metal dichalcogenides.

2. The integrated circuit device according to claim 1, in, The thickness of each of the plurality of channel layers is substantially the same in the third direction. Wherein, the distance between adjacent channel layers in the plurality of channel layers is substantially the same, and Wherein, the third direction is perpendicular to the first horizontal direction and the second horizontal direction.

3. The integrated circuit device according to claim 2, in, The gate line also includes a second sub-gate. Wherein, the second sub-gate is located on the opposite side of the first sub-gate relative to the first channel layer, and The thickness of the second sub-gate in the third direction is greater than the thickness of the first sub-gate in the third direction.

4. The integrated circuit device according to claim 1, wherein, The plurality of channel layers includes an even number of channel layers.

5. The integrated circuit device according to claim 1, wherein, The source / drain pattern includes at least one of a metal, a half-metal, a metal oxide, or a combination thereof, and The channel passivation layer includes at least one of thiol or sulfur.

6. The integrated circuit device according to claim 1, wherein, The multiple channel layers have a single-crystal structure.

7. The integrated circuit device according to claim 1, in, The first passivation layer is in direct contact with the top surface of the first channel layer, and The second passivation layer is in direct contact with the bottom surface of the second channel layer.

8. The integrated circuit device according to claim 1, in, One end of the first passivation layer and one end of the second passivation layer are in contact with the source / drain pattern.

9. The integrated circuit device according to claim 1, wherein, The passivation layers are alternately arranged between adjacent channel layers in the plurality of channel layers.

10. The integrated circuit device according to claim 1, in, The gate line also includes a second sub-gate. Wherein, the first channel layer is disposed between the first sub-gate and the second sub-gate, and In this case, no channel passivation layer is provided between the first channel layer and the second sub-gate.

11. The integrated circuit device according to claim 1, further comprising: An insulating spacer is disposed between the sidewall of the gate line and the source / drain pattern. The insulating spacer includes a first spacer disposed between the first channel layer and the second channel layer, wherein the first passivation layer is disposed between the first spacer and the first channel layer.

12. The integrated circuit device according to claim 11, wherein, The first spacer is spaced apart from the first channel layer and the second channel layer.

13. The integrated circuit device according to claim 11, in, The first surface of the first spacer faces the first sub-gate, and the second surface of the first spacer is in contact with the source / drain pattern. Wherein, one end of the first passivation layer extends from the top surface of the first channel layer to the surface formed by the second surface of the first spacer, and Wherein, the second surface of the first spacer is the opposite surface of the first surface of the first spacer.

14. The integrated circuit device according to claim 1, further comprising: An insulating spacer is disposed between the sidewall of the gate line and the source / drain pattern; as well as An insulating cover pattern is disposed on the side of the insulating spacer on the main gate. The gate line includes the main gate disposed above the plurality of channel layers, and The insulating spacer extends integrally on the sidewall of the first sub-gate, the sidewall of the main gate, and the sidewall of the covering insulating pattern.

15. An integrated circuit device, the integrated circuit device comprising: A plurality of channel layers, the plurality of channel layers extending in a first horizontal direction and including a first channel layer and a second channel layer; A gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, wherein the gate line includes a first sub-gate disposed between the first channel layer and the second channel layer and a second sub-gate disposed on the opposite side of the first sub-gate relative to the first channel layer. Source / drain patterns are disposed on the sidewalls of the gate lines and connected to the plurality of channel layers; A channel passivation layer, the channel passivation layer including a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed between the first sub-gate and the first channel layer, and the second passivation layer is disposed between the first sub-gate and the second channel layer; An insulating spacer disposed between the sidewall of the gate line and the source / drain pattern; and A gate dielectric layer, the gate dielectric layer surrounding the first sub-gate, The plurality of channel layers protrude from the insulating spacer in the first horizontal direction. Wherein, no channel passivation layer is provided between the first channel layer and the second sub-gate. The first passivation layer is disposed between the gate dielectric layer and the first channel layer, and the gate dielectric layer is in direct contact with the first passivation layer. The plurality of channel layers include transition metal dichalcogenides.

16. The integrated circuit device according to claim 15, in, The plurality of channel layers includes an even number of channel layers. In this embodiment, the thickness of each of the plurality of channel layers is substantially the same in a third direction, and the third direction is perpendicular to the first horizontal direction and the second horizontal direction. Among them, the plurality of channel layers have a single-crystal structure, and The source / drain pattern includes at least one of a metal, a half-metal, a metal oxide, or a combination thereof.

17. The integrated circuit device according to claim 15, in, The insulating spacer includes a first spacer disposed between the first channel layer and the second channel layer, and the first passivation layer is disposed between the first spacer and the first channel layer. In this configuration, the first spacer is spaced apart from the first channel layer and the second channel layer. The first surface of the first spacer faces the first sub-gate, and the second surface of the first spacer contacts the source / drain pattern. Furthermore, the second surface of the first spacer is the opposite surface of the first surface of the first spacer. One end of the first passivation layer extends to the second surface of the first spacer.

18. The integrated circuit device according to claim 17, in, The ends of each of the plurality of channel layers are surrounded by channel barriers. The ends of each of the plurality of channel layers are spaced apart from the source / drain pattern by the channel barrier. The channel barrier includes at least one of titanium, zirconium, or hafnium. The channel barrier is in contact with the channel passivation layer.

19. The integrated circuit device according to claim 15, in, The thickness of each of the plurality of channel layers in the third direction is in the range of 0.3 nanometers to 2.0 nanometers. The thickness of the channel passivation layer in the third direction is in the range of 0.1 nanometers to 0.5 nanometers, and Wherein, the third direction is perpendicular to the first horizontal direction and the second horizontal direction.

20. An integrated circuit device, the integrated circuit device comprising: Multiple channel layers, the multiple channel layers extending in a first horizontal direction and including a first channel layer and a second channel layer; A gate line extends in a second horizontal direction intersecting the first horizontal direction and surrounds the plurality of channel layers, wherein the gate line includes a first sub-gate disposed between the first channel layer and the second channel layer and a second sub-gate disposed on the opposite side of the first sub-gate relative to the first channel layer. Source / drain patterns are disposed on the sidewalls of the gate lines and connected to the plurality of channel layers; A channel passivation layer, the channel passivation layer including a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed between the first sub-gate and the first channel layer, and the second passivation layer is disposed between the first sub-gate and the second channel layer; An insulating spacer disposed between the sidewall of the gate line and the source / drain pattern; and A gate dielectric layer, the gate dielectric layer surrounding the first sub-gate, The plurality of channel layers protrude from the insulating spacer in the first horizontal direction. Wherein, no channel passivation layer is provided between the first channel layer and the second sub-gate. The first passivation layer is disposed between the gate dielectric layer and the first channel layer, and the gate dielectric layer is in direct contact with the first passivation layer. The plurality of channel layers include transition metal dichalcogenides. The plurality of channel layers includes an even number of channel layers. In this embodiment, the thickness of each of the plurality of channel layers is substantially the same in a third direction, and the third direction is perpendicular to the first horizontal direction and the second horizontal direction. The plurality of channel layers have a single-crystal structure. The source / drain pattern includes at least one of a metal, a half-metal, a metal oxide, or a combination thereof. The channel passivation layer includes at least one of thiol or sulfur. The channel passivation layer comprises trifluoromethanesulfonylimide, and The thickness of each of the plurality of channel layers in the third direction is in the range of 0.3 nm to 2.0 nm, and the thickness of the channel passivation layer in the third direction is in the range of 0.1 nm to 0.5 nm.

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