Semiconductor device

Abstract

A semiconductor device is provided, including: first active patterns spaced apart from each other in a first direction; a first device isolation layer between the first active patterns adjacent to each other; first channel patterns on the first active patterns; and a cut pattern extending perpendicularly between the first channel patterns. The cut pattern includes a first portion and a second portion on the first portion. At a boundary between the first portion and the second portion, a width of the first portion is greater than a width of the second portion.

Description

Technical Field

[0001] This disclosure relates to semiconductors and methods of manufacturing the same, and more specifically, to a semiconductor device including a field-effect transistor and a method of manufacturing the same. Background Technology

[0002] Semiconductor devices can include integrated circuits containing metal-oxide-semiconductor field-effect transistors (MOSFETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and scaled-down design rules, MOSFETs have also been scaled down. This scaling down of MOSFETs can lead to a degradation in the operating characteristics of semiconductor devices. Various studies are underway to overcome the technological limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the Invention

[0003] Embodiments of the present disclosure provide semiconductor devices with improved reliability and electrical characteristics.

[0004] Embodiments of the present disclosure provide methods for manufacturing semiconductor devices with improved reliability and electrical characteristics.

[0005] According to embodiments of the present disclosure, a semiconductor device may include: a first active pattern spaced apart from each other in a first direction; a first device isolation layer between adjacent first active patterns; a first channel pattern located on the first active patterns; and a dicing pattern extending perpendicularly between the first channel patterns. The dicing pattern includes a first portion and a second portion located on the first portion, wherein at the boundary between the first portion and the second portion, the width of the first portion is greater than the width of the second portion.

[0006] According to embodiments of the present disclosure, a semiconductor device may include: a substrate including a first active region and a second active region; a first active pattern located on the first active region and spaced apart from each other in a first direction; a first device isolation layer between adjacent first active patterns; a first gate electrode located on the first active pattern; and a first dicing pattern extending through the first gate electrode into the first device isolation layer. The first dicing pattern includes a first portion and a second portion located on the first portion, wherein the first portion includes a first dicing layer and a second dicing layer located on the first dicing layer, wherein the first dicing layer and the second dicing layer have different etch selectivity with respect to at least one etch process, and wherein the sidewalls of the first portion are spaced apart from the sidewalls of the second portion in the first direction.

[0007] According to embodiments of the present disclosure, a semiconductor device may include: a substrate including an active pattern; a device isolation layer defining the active pattern; a first channel pattern located on the active pattern and spaced apart from each other in a first direction; a first source / drain pattern connected to the first channel pattern; a diced pattern extending perpendicularly between adjacent first channel patterns; a first gate electrode connected to the first source / drain pattern; and a gate insulating layer between the first gate electrode and each of the first channel patterns. The diced pattern comprises: a gate spacer located on a sidewall of the first gate electrode; a gate overlay pattern located on the upper surface of the first gate electrode; an interlayer insulating layer located on the first source / drain pattern and the gate overlay pattern; an active contact connected to each of the first source / drain patterns through the interlayer insulating layer; a gate contact connected to the first gate electrode through the gate overlay pattern and the interlayer insulating layer; and a first metal layer located on the interlayer insulating layer and including a first wiring connected to the active contact and the gate contact. The diced pattern comprises a first portion and a second portion located on the first portion, wherein the first portion includes an upper surface exposed by the second portion, and wherein the horizontal height of the upper surface of the first portion is lower than the horizontal height of the upper surface of the active pattern.

[0008] According to embodiments of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first active pattern on a substrate, the first active patterns being spaced apart from each other in a first direction; forming a device isolation layer between adjacent first active patterns; forming a first channel pattern on the first active pattern; forming a sacrificial pattern covering the first channel pattern and extending in a second direction intersecting the first direction; forming a dicing hole by performing a patterning process on the sacrificial pattern; forming a first preliminary dicing layer on the inner wall of the dicing hole; forming a second preliminary dicing layer on the first preliminary dicing layer; removing the sacrificial pattern to expose a portion of the sidewall of the first preliminary dicing layer; and removing the exposed portion of the first preliminary dicing layer.

[0009] In a method for manufacturing a semiconductor device according to the present disclosure, the first preliminary dicing layer and the second preliminary dicing layer have different etch selectivity relative to at least one etch process.

[0010] The method for manufacturing a semiconductor device according to the present disclosure further includes, prior to forming the sacrificial pattern, sequentially forming a gate insulating film and a first metal pattern on the first channel pattern.

[0011] In a method of manufacturing a semiconductor device according to the present disclosure, the dicing hole extends into the device isolation layer; and removing the sacrificial pattern does not remove the first preliminary dicing layer formed in the device isolation layer.

[0012] In a method for manufacturing a semiconductor device according to the present disclosure, the first preliminary dicing layer and the second preliminary dicing layer are formed by different deposition processes. Attached Figure Description

[0013] Figures 1 to 3 This is a conceptual diagram used to describe an embodiment of a semiconductor device based on the concept of this disclosure.

[0014] Figure 4 It is a plan view used to describe a semiconductor device according to an embodiment of the concept of this disclosure.

[0015] Figure 5A It is along Figure 4 The cross-sectional view taken by line A-A' in the diagram.

[0016] Figure 5B It is along Figure 4 The cross-sectional view taken by line B-B'.

[0017] Figure 5C It is along Figure 4 A cross-sectional view taken from line C-C'.

[0018] Figure 5D It is along Figure 4 The cross-sectional view taken by line D-D'.

[0019] Figure 6A It is shown Figure 5D An enlarged view of an embodiment of part M.

[0020] Figure 6B It is shown Figure 5D An enlarged view of an embodiment of part N.

[0021] Figure 7A and Figure 7B It is shown Figure 5D An enlarged view of an embodiment of part N.

[0022] Figure 7C It is shown Figure 5D An enlarged view of an embodiment of part M.

[0023] Figure 7D , Figure 7E and Figure 7F Each is shown Figure 5D An enlarged view of an embodiment of part N.

[0024] Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of this disclosure.

[0025] Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B and Figure 19C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of this disclosure.

[0026] Figures 20 to 24 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of this disclosure. Detailed Implementation

[0027] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are illustrated.

[0028] Figures 1 to 3 This is a conceptual diagram used to describe the logic unit of a semiconductor device according to an embodiment of the present disclosure.

[0029] refer to Figure 1 A single-height cell (SHC) can be provided. For example, a first power trace M1_R1 and a second power trace M1_R2 can be provided on substrate 100. The first power trace M1_R1 can be a path for providing the drain voltage VDD (e.g., power supply voltage). The second power trace M1_R2 can be a path for providing the source voltage VSS (e.g., ground voltage).

[0030] A single-height cell SHC can be defined between a first power trace M1_R1 and a second power trace M1_R2. The single-height cell SHC may include a PMOSFET region PR and an NMOSFET region NR. That is, the single-height cell SHC can be a CMOS structure disposed between the first power trace M1_R1 and the second power trace M1_R2. The first active region can be the PMOSFET region PR, and the second active region can be the NMOSFET region NR. Conversely, the second active region can be the PMOSFET region PR, and the first active region can be the NMOSFET region NR.

[0031] Each of the PMOSFET region PR and the NMOSFET region NR may have a first width WI1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as the first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first power wiring M1_R1 and the second power wiring M1_R2.

[0032] A single-height SHC can constitute a logic unit. In this document, a logic unit can refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic unit can include transistors for configuring logic elements and wiring that connects the transistors to each other (e.g., electrical connections).

[0033] refer to Figure 2A dual-height cell (DHC) can be provided. For example, a first power trace M1_R1, a second power trace M1_R2, and a third power trace M1_R3 can be provided on substrate 100. The first power trace M1_R1 can be disposed between the second power trace M1_R2 and the third power trace M1_R3. The third power trace M1_R3 can be used to provide a path for the source voltage VSS.

[0034] The dual-height cell (DHC) can be defined between the second power wiring M1_R2 and the third power wiring M1_R3. The dual-height cell (DHC) may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0035] A first NMOSFET region NR1 may be adjacent to a second power wiring M1_R2. A second NMOSFET region NR2 may be adjacent to a third power wiring M1_R3. Another second NMOSFET region NR2 may be adjacent to a first NMOSFET region NR1, with a second power wiring M1_R2 situated between them. A first PMOSFET region PR1 and a second PMOSFET region PR2 may be adjacent to a first power wiring M1_R1. In a plan view, the first power wiring M1_R1 may be positioned between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0036] The length of the dual-height unit DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be... Figure 1 The first height HE1 is approximately twice that of the second height. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the dual-height cell DHC can be combined to operate as a single PMOSFET region.

[0037] Therefore, the channel size of the PMOS transistor in a dual-height cell DHC can be larger than the above. Figure 1 The diagram shows the channel dimensions of a PMOS transistor in a single-height cell SHC. For example, the channel dimensions of a PMOS transistor in a dual-height cell DHC can be approximately twice that of a PMOS transistor in a single-height cell SHC. As a result, a dual-height cell DHC can operate at a higher speed compared to a single-height cell SHC. In this disclosure, Figure 2 The dual-height cell (DHC) shown can be defined as a multi-height cell. A multi-height cell can include cells with a height of... Figure 1 The single-height unit SHC has a unit height approximately three times that of the three-height unit.

[0038] refer to Figure 3 A first single-height unit SHC1, a second single-height unit SHC2, and a double-height unit DHC can be two-dimensionally disposed on the substrate 100. The first single-height unit SHC1 can be disposed between the first power wiring M1_R1 and the second power wiring M1_R2. The second single-height unit SHC2 can be disposed between the first power wiring M1_R1 and the third power wiring M1_R3. The second single-height unit SHC2 can be adjacent to the first single-height unit SHC1 in the first direction D1.

[0039] The dual-height unit DHC can be positioned between the second power cabling M1_R2 and the third power cabling M1_R3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second direction D2.

[0040] A separation structure DB can be provided between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The active region of the dual-height unit DHC can be electrically separated from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2 through the separation structure DB.

[0041] Figure 4 It is a plan view used to describe a semiconductor device according to an embodiment of the concept of this disclosure. Figure 5A , Figure 5B , Figure 5C and Figure 5D They are along Figure 4 Cross-sectional views of lines A-A', B-B', C-C', and D-D'. Figure 4 as well as Figure 5A , Figure 5B , Figure 5C and Figure 5D The semiconductor device shown is illustrated in more detail therein. Figure 2 An example of a dual-height unit (DHC).

[0042] refer to Figure 4 as well as Figure 5A , Figure 5B , Figure 5C and Figure 5D A dual-height cell (DHC) can be disposed on the substrate 100. Logic transistors constituting logic circuits can be disposed on the dual-height cell (DHC). The substrate 100 can be a semiconductor substrate comprising, for example, silicon, germanium, silicon-germanium, and / or the like, or a compound semiconductor substrate. For example, the substrate 100 can be a silicon substrate.

[0043] A first active pattern AP1 and a second active pattern AP2 may be defined by a trench TR formed on the substrate 100. The first active pattern AP1 may be disposed on a first PMOSFET region PR1 and a second PMOSFET region PR2, and the second active pattern AP2 may be disposed on a first NMOSFET region NR1 and a second NMOSFET region NR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertical protrusions of the substrate 100.

[0044] A device isolation layer ST may be provided on the substrate 100. The device isolation layer ST may fill the trench TR. A spacer layer OLI may be provided between the trench TR and the device isolation layer ST. The device isolation layer ST may be provided between the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2, which will be described later.

[0045] A first channel pattern CH1 may be disposed on a first active pattern AP1. A second channel pattern CH2 may be disposed on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction (e.g., in the third direction D3).

[0046] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon. In some embodiments of the present disclosure, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be stacked nanosheets.

[0047] Multiple first source / drain patterns SD1 can be disposed on the first active pattern AP1. Multiple first recesses RS1 can be formed on the first active pattern AP1. The first source / drain patterns SD1 can be disposed in the first recesses RS1 respectively. The first source / drain patterns SD1 can be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be located between pairs of first source / drain patterns SD1. That is, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can connect the pairs of first source / drain patterns SD1 to each other.

[0048] Multiple second source / drain patterns SD2 can be formed on the second active pattern AP2. Multiple second recesses RS2 can be formed on the second active pattern AP2. The second source / drain patterns SD2 can be respectively disposed in the second recesses RS2. The second source / drain patterns SD2 can be impurity regions of a second conductivity type (e.g., n-type). The second channel pattern CH2 can be located between pairs of second source / drain patterns SD2. That is, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can connect the pairs of second source / drain patterns SD2 to each other.

[0049] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the upper surface of the third semiconductor pattern SP3. In some embodiments, the upper surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at substantially the same horizontal height as the upper surface of the third semiconductor pattern SP3.

[0050] In embodiments of the present disclosure, the first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the semiconductor material of the substrate 100. Therefore, the paired first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 therebetween. The second source / drain pattern SD2 may comprise the same semiconductor material as the substrate 100 (e.g., Si).

[0051] The sidewalls of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a non-uniform imprinted shape. That is, the sidewalls of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a wavy profile. The sidewalls of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may protrude toward the first inner portion PO1, the second inner portion PO2, and the third inner portion PO3 of the gate electrode GE, as will be described later.

[0052] A gate electrode GE can be provided, extending across a first channel pattern CH1 and a second channel pattern CH2 in a first direction D1. The gate electrode GE can be arranged in a second direction D2 according to a first pitch. Each gate electrode GE can overlap perpendicularly with the first channel pattern CH1 and the second channel pattern CH2.

[0053] The gate electrode GE may include a first inner portion PO1 between the first active pattern AP1 or the second active pattern AP2 and the first semiconductor pattern SP1, a second inner portion PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner portion PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth inner portion PO4 located on the third semiconductor pattern SP3.

[0054] refer to Figure 5D The gate electrode GE can be disposed on the upper surface, lower surface, and two sidewalls of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. That is, the transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., a multi-bridge channel (MBC) FET or a gate-all-around (GAA) FET), wherein the gate electrode GE surrounds the channel (e.g., the first channel pattern CH1 and the second channel pattern CH2) in three dimensions.

[0055] refer to Figure 4 , Figure 5A , Figure 5B , Figure 5C and Figure 5D A pair of gate spacers GS can be disposed on the two sidewalls of the fourth inner portion PO4 of the gate electrode GE. The gate spacers GS can extend along the gate electrode GE in the first direction D1. The upper surface of the gate spacers GS can be higher than the upper surface of the gate electrode GE. In some embodiments, the gate spacers GS can include at least one of SiCN, SiCON, or SiN. In some embodiments, the gate spacers GS can include a multilayer composed of at least two of SiCN, SiCON, or SiN.

[0056] A gate cover pattern GP may be formed on the gate electrode GE. The gate cover pattern GP may extend along the gate electrode GE in a first direction D1. The gate cover pattern GP may include a material that has etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described later. For example, the gate cover pattern GP may include SiON, SiCN, SiCON and / or SiN.

[0057] A gate insulating layer GI can be inserted between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI can be located on the upper surface, bottom surface, and two sidewalls of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI can be located on the upper surface of the device isolation layer ST below the gate electrode GE.

[0058] In embodiments of the present disclosure, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high dielectric layer HK. The high dielectric layer HK may be situated between the gate electrode GE and the gate insulating layer GI. The high dielectric layer HK may surround the inner gate electrodes IGE1, IGE2, and IGE3 of the gate electrode GE with a uniform thickness. The high dielectric layer HK may extend from the lower surface of the outer gate electrode OGE of the gate electrode GE to the sidewall. For example, the gate insulating layer GI may be in a structure stacked on the high dielectric layer HK.

[0059] The high dielectric layer HK may include a high dielectric constant material having a higher dielectric constant than that of the silicon oxide layer. For example, the high dielectric layer HK may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium dioxide, zirconium silicon dioxide, tantalum dioxide, titanium dioxide, barium strontium titanium oxide, barium titanium oxide, strontium aluminum oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0060] refer to Figure 4 , Figure 5A , Figure 5B , Figure 5C and Figure 5DThe gate electrode GE may include a first metal pattern MP1 and a second metal pattern MP2 located on the first metal pattern MP1. The first metal pattern MP1 may be disposed on the gate insulating layer GI to be adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern MP1 may include a work function metal that adjusts the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern MP1, the desired threshold voltage of the transistor can be achieved. For example, the first inner portion PO1, the second inner portion PO2, and the third inner portion PO3 of the gate electrode GE may be formed by the first metal pattern MP1 as the work function metal. The fourth inner portion PO4 of the gate electrode GE may also include the first metal pattern MP1.

[0061] The first metal pattern MP1 may include a metal nitride layer. For example, the first metal pattern MP1 may include at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and / or molybdenum (Mo) and nitrogen (N). Furthermore, the first metal pattern MP1 may also include carbon (C). The first metal pattern MP1 may include multiple stacked work function metal layers.

[0062] Compared to the first metal pattern MP1, the second metal pattern MP2 may include a metal with lower resistance. For example, the second metal pattern MP2 may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and / or tantalum (Ta). For example, the fourth inner portion PO4 of the gate electrode GE may include the first metal pattern MP1 and the second metal pattern MP2 located on the first metal pattern MP1.

[0063] refer to Figure 4 , Figure 5A , Figure 5B and Figure 5D A single-height element SHC may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in a second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. A single-height element SHC may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0064] A cutting pattern CT can be provided on the boundary parallel to the second direction D2 of each of the first single-height unit SHC1 and the second single-height unit SHC2. For example, the cutting pattern CT can be provided on the third boundary BD3 and the fourth boundary BD4 of the first single-height unit SHC1. The cutting pattern CT can be arranged along the third boundary BD3 at a first pitch. The cutting pattern CT can be arranged along the fourth boundary BD4 at a first pitch. In a plan view, the cutting pattern CTs located on the third boundary BD3 and the fourth boundary BD4 can be arranged to overlap on the gate electrode GE, respectively.

[0065] The diced pattern CT can extend from the device isolation layer ST to the gate overlay pattern GP on the third-direction D3. The horizontal height of the upper surface of the diced pattern CT can be the same as or higher than the horizontal height of the upper surface of the gate electrode GE. The diced pattern CT may include insulating materials such as silicon nitride layers, silicon oxide layers, and / or combinations thereof.

[0066] The grid electrode GE located on the first single-height unit SHC1 can be separated from the grid electrode GE located on the second single-height unit SHC2 by a cutting pattern CT. The cutting pattern CT can be located between the grid electrode GE located on the first single-height unit SHC1 and the grid electrode GE located on the second single-height unit SHC2 that is aligned with it in the first direction D1. That is, the grid electrode GE extending in the first direction D1 can be divided into multiple grid electrodes GE by the cutting pattern CT.

[0067] The dicing pattern CT may include a first dicing pattern CT1 located on the PMOSFET region PR and a second dicing pattern CT2 located on the NMOSFET region NR. The first dicing pattern CT1 may be located between the first PMOSFET region PR1 and the second PMOSFET region PR2. The second dicing pattern CT2 may be located between the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0068] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may extend around the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. A second interlayer insulating layer 120 covering the gate cover pattern GP may be disposed on the first interlayer insulating layer 110. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. For example, the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140 may include silicon oxide layers.

[0069] A pair of partition structures DB facing each other in the second direction D2 may be provided on both sides of each of the first single-height unit SHC1 and the second single-height unit SHC2. For example, the pair of partition structures DB may be provided on the first boundary BD1 and the second boundary BD2 of the first single-height unit SHC1 and the second single-height unit SHC2, respectively. The partition structure DB may extend parallel to the gate electrode GE in the first direction D1. The pitch between the partition structure DB and its adjacent gate electrode GE may be the same as the first pitch.

[0070] The separator structure DB can extend through the first interlayer insulation layer 110 into the first active pattern AP1 and the second active pattern AP2. The separator structure DB can penetrate the upper part of each of the first active pattern AP1 and the second active pattern AP2. The separator structure DB can electrically separate the active region of a single-height cell SHC from the active region of another adjacent cell.

[0071] Active contacts AC can be provided, which penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. Pairs of active contacts AC can be provided on both sides of the gate electrode GE. In a plan view, the active contacts AC can be in the shape of a strip extending in the first direction D1.

[0072] The active contact AC can be a self-aligned contact. That is, the active contact AC can be formed in a self-aligned manner using a gate cover pattern GP and a gate spacer GS. For example, the active contact AC can be located on at least a portion of the sidewall of the gate spacer GS. The active contact AC can be located on a portion of the upper surface of the gate cover pattern GP.

[0073] A metal-semiconductor compound layer SC (e.g., a silicide layer) can be inserted between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and / or cobalt silicide.

[0074] The gate contact GC can electrically penetrate or extend into the second interlayer insulating layer 120 and the gate cover pattern GP to connect to the gate electrode GE. In a plan view, the gate contact GC can be configured to overlap with the PMOSFET region PR and the NMOSFET region NR, respectively. For example, the gate contact GC can be located on the first active pattern AP1.

[0075] In some embodiments of the present disclosure, reference is made to Figure 5A The upper portion of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. The lower surface of the upper insulating pattern UIP can be lower than the lower surface of the gate contact GC. That is, the upper surface of the active contact AC adjacent to the gate contact GC can be lower than the lower surface of the gate contact GC through the upper insulating pattern UIP. Therefore, it is possible to prevent a short circuit when the gate contact GC comes into contact with the adjacent active contact AC.

[0076] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include aluminum, copper, tungsten, molybdenum, and / or cobalt. The barrier pattern BM may be located on the sidewalls and lower surface of the conductive pattern FM. The barrier pattern BM may include a metal layer / metal nitride layer. The metal layer may include titanium, tantalum, tungsten, nickel, cobalt, and / or platinum. The metal nitride layer may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and / or a platinum nitride (PtN) layer.

[0077] A first metal layer M1 may be provided in the third interlayer insulation layer 130. For example, the first metal layer M1 may include a first power wiring M1_R1, a second power wiring M1_R2, and a first wiring M1_I. Each of the wirings M1_R1, M1_R2, and M1_I in the first metal layer M1 may extend parallel to each other in the second direction D2.

[0078] Specifically, the first power wiring M1_R1 and the second power wiring M1_R2 can be respectively disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height unit SHC1. The first power wiring M1_R1 can extend along the third boundary BD3 in the second direction D2. The second power wiring M1_R2 can extend along the fourth boundary BD4 in the second direction D2. The third power wiring M1_R3 can extend along the second direction D2 on the second single-height unit SHC2 to be parallel to the first power wiring M1_R1 and the second power wiring M1_R2.

[0079] A first wiring M1_I of the first metal layer M1 can be disposed between a first power wiring M1_R1 and a second power wiring M1_R2. The first wiring M1_I of the first metal layer M1 can be arranged along a first direction D1 at a second pitch. The second pitch can be smaller than the first pitch. The line width of each first wiring M1_I can be smaller than the line width of each of the first power wiring M1_R1 and the second power wiring M1_R2.

[0080] The first metal layer M1 may further include a first path VI1. The first path VI1 may be disposed below the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1, respectively. The active contact AC and the wirings of the first metal layer M1 may be electrically connected to each other through the first path VI1. The gate contact GC and the wirings of the first metal layer M1 may be electrically connected to each other through the first path VI1.

[0081] The wiring of the first metal layer M1 and the first path VI1 beneath it can each be formed in separate processes. In some embodiments, each of the wiring of the first metal layer M1 and the first path VI1 can be formed in a single damascene process. The semiconductor device according to this embodiment can be formed using a process of less than 20 nm.

[0082] A second metal layer M2 may be provided in the fourth interlayer insulating layer 140. The second metal layer M2 may include multiple second wirings M2_I. Each second wiring M2_I of the second metal layer M2 may be in the shape of a line or a strip extending in the first direction D1. That is, the second wirings M2_I may extend parallel to each other in the first direction D1.

[0083] The second metal layer M2 may further include a second path VI2 disposed below the second wiring M2_I. The wiring of the first metal layer M1 and the wiring of the second metal layer M2 can be electrically connected to each other through the second path VI2. For example, the wiring of the second metal layer M2 and the second path VI2 below it can be formed together by a dual damascene process.

[0084] The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include the same or different conductive materials. For example, the wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include at least one metallic material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and / or cobalt. Metal layers (e.g., M3, M4, M5...) stacked on the fourth interlayer insulating layer 140 may be further provided. Each stacked metal layer may include wiring for routing between cells. Figure 6A It is shown Figure 5D An enlarged view of an embodiment of part M. Figure 6B It is shown Figure 5D An enlarged view of an embodiment of part N. (Refer to...) Figure 6A and Figure 6B A more detailed description of the cutting pattern CT.

[0085] refer to Figure 6AThe first cut pattern CT1 may include a first portion PT1 and a second portion PT2 located on the first portion PT1. Based on the boundary where the width of the first cut pattern CT1 suddenly changes, the lower part of the boundary may be the first portion PT1 and the upper part of the boundary may be the second portion PT2. For example, the first portion PT1 may be the portion of the first cut pattern CT1 embedded in the device isolation layer ST, and the second portion PT2 may be the portion other than the first portion PT1, but is not limited thereto.

[0086] The device isolation layer ST can cover the sidewalls and lower surface of the first portion PT1. The gate insulating layer GI can be disposed on the first upper surface TS1 and the second upper surface TS2 of the first portion PT1, as described later, and on the sidewalls of the second portion PT2. A high dielectric layer HK can be disposed on the gate insulating layer GI. Since the first diced pattern CT1 is located on the PMOSFET region PR, a first metal pattern MP1 can be further disposed on the high dielectric layer HK. The first metal pattern MP1 can extend along the first direction D1 on the high dielectric layer HK. The first metal pattern MP1 is disposed only on the lower portion of the sidewalls of the second portion PT2 and may not extend along the third direction D3.

[0087] At the boundary between the first part PT1 and the second part PT2, the first width WD1 of the first part PT1 can be greater than the second width WD2 of the second part PT2. At the boundary between the second part PT2 and the first part PT1, the width of the first cutting pattern CT1 can change discontinuously. The width of the first cutting pattern CT1 can suddenly decrease from the first width WD1 of the first part PT1 to the second width WD2 of the second part PT2.

[0088] The upper width of the first part PT1 can be greater than the lower width of the second part PT2. Therefore, the sidewall SW1 of the first part PT1 can be spaced apart from the sidewall SW2 of the second part PT2 in the first direction D1. The sidewall SW1 of the first part PT1 can be offset relative to the sidewall SW2 of the second part PT2 in the first direction D1.

[0089] The first portion PT1 may include a first upper surface TS1 and a second upper surface TS2 exposed by the second portion PT2. The second portion PT2 may be located between the first upper surface TS1 and the second upper surface TS2. The first upper surface TS1 and the second upper surface TS2 may be spaced apart from each other in a first direction D1, with the second portion PT2 interposed therebetween. The first upper surface TS1 and the second upper surface TS2 may be the upper surfaces of the first diced layer CL1, which will be described later. The first upper surface TS1 and the second upper surface TS2 may extend in a direction parallel to the substrate 100 (e.g., the first direction D1), but are not limited thereto.

[0090] The first upper surface TS1 and the second upper surface TS2 can be the stepped surfaces of the first cutting pattern CT1. That is, the width of the first cutting pattern CT1 can be changed by the first upper surface TS1 and the second upper surface TS2. The first upper surface TS1 and the second upper surface TS2 can connect the sidewalls of the first portion PT1 and the second portion PT2. At the boundary between the first portion PT1 and the second portion PT2, the difference between the width of the second portion PT2 and the width of the first portion PT1 can be substantially equal to the sum of the lengths of the first upper surface TS1 and the second upper surface TS2.

[0091] The gate insulating layer GI and the high dielectric layer HK can be sequentially disposed on the first upper surface TS1 and the second upper surface TS2. The first upper surface TS1 and the second upper surface TS2 can be in contact with the gate insulating layer GI. The first upper surface TS1 and the second upper surface TS2 can face the gate electrode GE.

[0092] refer to Figure 5D and Figure 6A The horizontal height of the first upper surface TS1 and the horizontal height of the second upper surface TS2 can be a first horizontal height Lv1. The first horizontal height Lv1 can be lower than the horizontal height of the upper surface of the first active pattern AP1. In some embodiments, the horizontal height of the first upper surface TS1 and the horizontal height of the second upper surface TS2 can be different from each other. For example, the horizontal height of the first upper surface TS1 can be higher than the horizontal height of the second upper surface TS2.

[0093] The first part PT1 may include a first dicing layer CL1 and a second dicing layer CL2 located on the first dicing layer CL1. The first dicing layer CL1 may cover the two sidewalls and the lower surface of the second dicing layer CL2. The first dicing layer CL1 may be located between the second dicing layer CL2 and the device isolation layer ST. The third width WD3 of the first dicing layer CL1 in the first direction D1 may be smaller than the width of the second dicing layer CL2 in the first direction D1.

[0094] The first dicing layer CL1 and the second dicing layer CL2 may have different etch selectivity for at least one etching process. The etching process may be, but is not limited to, wet etching. For example, the first dicing layer CL1 and the second dicing layer CL2 may include silicon nitride (SiN), but may have different etch selectivity for wet etching. The first dicing layer CL1 and the second dicing layer CL2 may be formed by different deposition processes. The first dicing layer CL1 and the second dicing layer CL2 may include the same material, but may have different etch selectivity for etching processes depending on different deposition processes, differences in chemical composition, whether heat treatment is performed, etc.

[0095] For example, the first cleaving layer CL1 and the second cleaving layer CL2 may comprise silicon nitride (SiN), and the first cleaving layer CL1 may have a lower density or lower crystallinity than the second cleaving layer CL2. For this reason, the first cleaving layer CL1 may be etched more by a wet etching process than the second cleaving layer CL2.

[0096] The first dicing layer CL1 and the second dicing layer CL2 may comprise materials having different etch selectivity relative to the etching process. The first dicing layer CL1 and the second dicing layer CL2 may comprise different materials. The first dicing layer CL1 and the second dicing layer CL2 may comprise insulating materials, such as silicon nitride layers, silicon oxide layers, and / or combinations thereof.

[0097] The upper surface of the first diced layer CL1 can be the first upper surface TS1 and the second upper surface TS2 of the first portion PT1. The horizontal height of the upper surface of the first diced layer CL1 can be lower than the horizontal height of the upper surface of the first active pattern AP1. The upper surface of the first diced layer CL1 can be located at a lower horizontal height than the upper surface of the second diced layer CL2. The first diced layer CL1 can include the upper surface exposed by the second diced layer CL2. The upper surface of the first diced layer CL1 can face the gate electrode GE.

[0098] At the boundary between the first portion PT1 and the second portion PT2, the difference between the width of the second portion PT2 and the width of the first portion PT1 can be substantially equal to the length of the upper surface of the first cutting layer CL1. The second width WD2 of the second portion PT2 can differ from the first width WD1 of the first portion PT1 by virtue of the first cutting layer CL1.

[0099] refer to Figure 6B The second dicing pattern CT2 can be substantially the same as the first dicing pattern CT1. However, since the second dicing pattern CT2 is disposed on the NMOSFET region NR, the gate electrode GE may not include the first metal pattern MP1. Therefore, the first metal pattern MP1 can be omitted on the high dielectric layer HK.

[0100] Figure 7A and Figure 7B It is shown Figure 5D An enlarged view of an embodiment of part N. (Except for the reference...) Figure 6A and Figure 6B Beyond the overlapping technical features described, the differences will be described in detail. Except for the absence of a first metal pattern MP1, according to... Figure 7A and Figure 7B The second cutting pattern CT2 can be applied equally. Figure 6A The first cutting pattern CT1.

[0101] refer to Figure 7A The first upper surface TS1 and the second upper surface TS2 can be inwardly recessed curved surfaces of the first portion PT1. The first upper surface TS1 and the second upper surface TS2 can be concave curved surfaces. This is because, in the manufacturing method described later, the first dicing layer CL1 is etched deeper than the upper surface of the device isolation layer ST. The horizontal height of the first upper surface TS1 and the second upper surface TS2 can be a second horizontal height Lv2, which can be lower than... Figure 6A and Figure 6B The first horizontal height Lv1. Therefore, the second horizontal height Lv2 of each of the first upper surface TS1 and the second upper surface TS2 can be lower than the horizontal height of the upper surface of the device isolation layer ST.

[0102] The gate insulating layer GI and the high dielectric layer HK can be disposed on the first upper surface TS1 and the second upper surface TS2. The bottom surface of the gate insulating layer GI that contacts the first upper surface TS1 and the second upper surface TS2 can be located at a lower horizontal height than the upper surface of the device isolation layer ST.

[0103] refer to Figure 7B The first upper surface TS1 and the second upper surface TS2 of the first part PT1 can be located at a third horizontal height Lv3, and the third horizontal height Lv3 can be higher than the first horizontal height Lv1. The first upper surface TS1 and the second upper surface TS2 can be located at a higher horizontal height than the upper surface of the device isolation layer ST. That is, the horizontal height of the upper surface of the first dicing layer CL1 can be higher than the horizontal height of the upper surface of the device isolation layer ST.

[0104] The gate insulating layer GI and the high dielectric layer HK can contact the sidewalls of the first portion PT1. That is, the gate insulating layer GI and the high dielectric layer HK can contact the sidewalls of the first cleavage layer CL1. The gate insulating layer GI may not be disposed on the first upper surface TS1 and the second upper surface TS2 of the first portion PT1. Therefore, the first upper surface TS1 and the second upper surface TS2 can be in direct contact with the gate electrode GE. The gate insulating layer GI may not be disposed on the sidewalls of the second portion PT2.

[0105] In some embodiments, the first upper surface TS1 and the second upper surface TS2 may be located at a higher horizontal level than the upper surface of the gate insulating layer GI and the upper surface of the high dielectric layer HK. Therefore, a portion of the sidewall of the first cleavage layer CL1 may contact the gate electrode GE.

[0106] Figure 7C It is shown Figure 5D An enlarged view of an embodiment of part M. (Except for the reference...) Figure 6A In addition to the overlapping technical features described, the differences are also described in detail.

[0107] refer to Figure 7C The first upper surface TS1 and the second upper surface TS2 can be located at a fourth horizontal height Lv4, and the fourth horizontal height Lv4 can be higher than the first horizontal height Lv1 and the third horizontal height Lv3. The first upper surface TS1 and the second upper surface TS2 can be located at a higher horizontal height than the upper surface of the device isolation layer ST, the upper surface of the gate insulating layer GI, and the upper surface of the high dielectric layer HK. That is, the horizontal height of the upper surface of the first dicing layer CL1 can be located at a higher horizontal height than the upper surface of the device isolation layer ST, the upper surface of the gate insulating layer GI, and the upper surface of the high dielectric layer HK. This is because in the manufacturing process described later, the gate insulating layer GI, the high dielectric layer HK, and the first metal pattern MP1 are formed earlier than the first dicing pattern CT1.

[0108] The first upper surface TS1 and the second upper surface TS2 may be substantially coplanar with the upper surface of the first metal pattern MP1, but are not limited thereto. In some embodiments, the upper surfaces of the first upper surface TS1 and the second upper surface TS2 may be located at a lower or higher horizontal level than the upper surface of the first metal pattern MP1. When the first upper surface TS1 and the second upper surface TS2 are located at a higher horizontal level than the upper surface of the first metal pattern MP1, a portion of the sidewall of the first cut layer CL1 may contact the second metal pattern MP2.

[0109] The gate insulating layer GI, the high dielectric layer HK, and the first metal pattern MP1 can contact the sidewall of the first portion PT1. That is, the gate insulating layer GI, the high dielectric layer HK, and the first metal pattern MP1 can contact the first dicing layer CL1. The first dicing layer CL1 can be located between the second dicing layer CL2 and each of the gate insulating layer GI, the high dielectric layer HK, and the first metal pattern MP1.

[0110] Figure 7D , Figure 7E and Figure 7F Each is shown Figure 5D An enlarged view of an embodiment of part N. (Except for the reference...) Figure 6A and Figure 6B In addition to the overlapping technical features described, the differences are also described in detail. Aside from the absence of the first metal pattern MP1, according to... Figure 7D , Figure 7E and Figure 7F The second cutting pattern CT2 can be applied equally. Figure 6A The first cutting pattern CT1.

[0111] refer to Figure 7DThe second part PT2 may further include a first cutting layer CL1 located on the second cutting layer CL2. The first cutting layer CL1 of the second part PT2 may be located on two sidewalls of the second cutting layer CL2 of the second part PT2. The fourth width WD4 of the first cutting layer CL1 of the second part PT2 in the first direction D1 may be smaller than the third width WD3 of the first cutting layer CL1 of the first part PT1. Due to the first cutting layer CL1 of the second part PT2, the length of the first upper surface TS1 and the length of the second upper surface TS2 may be reduced, but are not limited thereto.

[0112] In some embodiments, the first cutting layer CL1 of the second portion PT2 may be disposed only on a portion of the sidewall of the second cutting layer CL2. For this reason, the first cutting layer CL1 may be disposed on any portion of the sidewall of the second cutting layer CL2, and the first cutting layer CL1 may not be disposed on another portion.

[0113] The first dicing layer CL1 of the second part PT2 can be located between the second dicing layer CL2 and the gate electrode GE. The gate insulating layer GI and the high dielectric layer HK can be located between the first dicing layer CL1 and the gate electrode GE, but are not limited thereto. For example... Figure 7B As shown, the gate insulating layer GI and the high dielectric layer HK may not be disposed on the sidewall of the second part PT2.

[0114] refer to Figure 7E The first portion PT1 may further include a third cutting layer CL3 located between the first cutting layer CL1 and the second cutting layer CL2. The third cutting layer CL3 may extend along the sidewall of the second cutting layer CL2 in a third direction D3. For this reason, the second portion PT2 may also include the third cutting layer CL3 located on the sidewall of the second cutting layer CL2. The fifth width WD5 of the third cutting layer CL3 may be less than or greater than the third width WD3 of the first cutting layer CL1, but is not limited thereto. The fifth width WD5 of the third cutting layer CL3 may be the same as the third width WD3 of the first cutting layer CL1.

[0115] refer to Figure 7F The first part PT1 may also include a third cutting layer CL3 located between the first cutting layer CL1 and the second cutting layer CL2, but the second part PT2 may not include the third cutting layer CL3.

[0116] The upper surfaces of the first cutting layer CL1 and the third cutting layer CL3 can be the first upper surface TS1 and the second upper surface TS2 of the first portion PT1. The upper surfaces of the first cutting layer CL1 and the third cutting layer CL3 can be coplanar, but are not limited thereto. In some embodiments, the upper surface of the first cutting layer CL1 can be located at a different horizontal height than the upper surface of the third cutting layer CL3.

[0117] refer to Figure 7E and Figure 7F The third dicing layer CL3 may have different etch selectivity for at least one etch process than at least one of the first dicing layer CL1 or the second dicing layer CL2. According to Figure 7E The third dicing layer CL3 can have different etching selectivity relative to the first dicing layer CL1 compared to the etching process. According to... Figure 7F The third dicing layer CL3 may have a different etch selectivity than the second dicing layer CL2. In some embodiments, the third dicing layer CL3 may have different etch selectivity for each of the first dicing layer CL1 and the second dicing layer CL2.

[0118] For example, the first dicing layer CL1, the second dicing layer CL2, and the third dicing layer CL3 all comprise silicon nitride (SiN) and may have different etch selectivity for wet etching processes. The third dicing layer CL3 may be formed by a deposition process different from that used for at least one of the first dicing layer CL1 or the second dicing layer CL2. The third dicing layer CL3 may comprise the same material as at least one of the first dicing layer CL1 or the second dicing layer CL2, but may have different etch selectivity for etching processes depending on different deposition processes, differences in chemical composition, whether heat treatment is performed, etc.

[0119] According to the present disclosure, a diced pattern CT may include multiple layers, such as a first dicing layer CL1 and a second dicing layer CL2. Since the first dicing layer CL1 and the second dicing layer CL2 have different etch selectivity relative to the etching process, the width of the diced pattern CT can be reduced by removing a portion of the first dicing layer CL1 during the formation of the diced pattern CT. For this reason, a width variation may exist between a first portion PT1 where the first dicing layer CL1 has not been removed and a second portion PT2 where the first dicing layer CL1 has been removed. Therefore, reducing the width of the diced pattern CT enables a reduction in transistor size. As a result, the reliability and electrical characteristics of the semiconductor device can be improved.

[0120] Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A, Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure. In detail, Figure 8A , Figure 9 , Figure 10A , Figure 11A , Figure 16A and Figure 17A It is along Figure 4 A cross-sectional view taken from line A-A'. Figure 11B It is along Figure 4 The cross-sectional view taken by line B-B'. Figure 10B , Figure 11C and Figure 17B It is along Figure 4 The cross-sectional view taken from line C-C'. Figure 8B , Figure 12 , Figure 13 , Figure 14A , Figure 15A , Figure 16B and Figure 17C It is along Figure 4 The cross-sectional view taken by line D-D'. Figure 14B It is shown Figure 14A A magnified view of part M. Figure 15B yes Figure 15A An enlarged view of an embodiment of part M, and Figure 15C It is shown Figure 15A An enlarged view of an embodiment of part M. Figure 16C It is shown Figure 16B A magnified view of part M.

[0121] Reference Figures 8A to 17C The present disclosure describes in detail the method for manufacturing semiconductor devices.

[0122] refer to Figure 8A and Figure 8B A substrate 100 may be provided, comprising a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. An active layer ACL and a sacrificial layer SAL may be alternately stacked on the substrate 100. The active layer ACL may comprise one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layer SAL may comprise another of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0123] The sacrificial layer SAL can comprise a material that can be etch-selective relative to the active layer ACL. For example, the active layer ACL can comprise silicon (Si), and the sacrificial layer SAL can comprise silicon germanium (SiGe). The concentration of germanium (Ge) in each sacrificial layer SAL can be from 10 at% to 30 at%.

[0124] Mask patterns can be formed on the first active pattern AP1 and the second active pattern AP2 of the substrate 100, respectively. The mask patterns can be in the form of a line or a strip extending in the second direction D2.

[0125] The trench TR defining the first active pattern AP1 and the second active pattern AP2 can be formed by performing a patterning process on the mask pattern using an etch mask. The first active pattern AP1 can be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 can be formed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0126] A stacked pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. The stacked pattern STP may include active layers ACL and sacrificial layers SAL that are stacked alternately on top of each other. The stacked pattern STP can be formed together with the first active pattern AP1 and the second active pattern AP2 during the patterning process.

[0127] A padding layer OLI can be formed on the trench TR. The padding layer OLI may include an insulating material, such as a silicon nitride layer, a silicon oxide layer, and / or combinations thereof. A device isolation layer ST can be formed to fill the trench TR. For example, an insulating layer covering a first active pattern AP1 and a second active pattern AP2 and a stacked pattern STP can be formed on the front surface of the substrate 100. The insulating layer is recessed until the stacked pattern STP is exposed, thereby forming the device isolation layer ST.

[0128] The device isolation layer ST may include an insulating material such as silicon oxide. A stacked pattern STP may be exposed on the device isolation layer ST. That is, the stacked pattern STP may protrude vertically from the device isolation layer ST.

[0129] refer to Figure 9 Sacrificial patterns PP intersecting the stacked pattern STP can be formed on the substrate 100. Each sacrificial pattern PP can be formed as a line shape or a strip shape extending in a first direction D1. The sacrificial patterns PP can be arranged along a second direction D2 at a first pitch.

[0130] Specifically, forming the sacrificial pattern PP may include: forming a sacrificial layer on the front surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask. The sacrificial layer may include polysilicon.

[0131] Pairs of gate spacers GS can be formed on the two sidewalls of each sacrificial pattern PP. Forming the gate spacers GS may include: conformally forming a gate spacer layer on the front surface of the substrate 100, and anisotropically etching the gate spacer layer. In some embodiments of the present disclosure, the gate spacers GS may be multilayers comprising at least two layers.

[0132] refer to Figure 10A and Figure 10B A first recess RS1 can be formed in a stacked pattern STP on a first active pattern AP1. A second recess RS2 can be formed in a stacked pattern STP on a second active pattern AP2. Simultaneously with the formation of the first recess RS1 and the second recess RS2, the device isolation layer ST located on either side of each of the first active pattern AP1 and the second active pattern AP2 can be further recessed (see...). Figure 10B ).

[0133] For example, a hard mask pattern MP and a gate spacer GS can be used as an etching mask to etch a stacked pattern STP located on a first active pattern AP1 to form a first recess RS1. The first recess RS1 can be formed between pairs of sacrificial patterns PP.

[0134] In some embodiments of the present disclosure, forming the first recess RS1 may further include performing a selective etching process on the exposed sacrificial layer SAL. Each sacrificial layer SAL can be recessed by the selective etching process to form a recessed region IDE. Therefore, the first recess RS1 may have wavy inner walls. The sidewalls of the sacrificial layer SAL can be recessed by the recessed region IDE. A second recess RS2 located in the stacked pattern STP on the second active pattern AP2 can be formed in the same manner as forming the first recess RS1.

[0135] A first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3, sequentially stacked between adjacent first recesses RS1, can each be formed by an active layer ACL. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 located between adjacent first recesses RS1 can constitute a first channel pattern CH1. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 located between adjacent second recesses RS2 can constitute a second channel pattern CH2.

[0136] refer to Figure 11A , Figure 11B and Figure 11C The first source / drain pattern SD1 can be formed separately in the first recess RS1. For example, the first source / drain pattern SD1 can be formed by performing a first selective epitaxial growth process (e.g., a first SEG process) using the inner wall of the first recess RS1 as a seed layer. The first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0137] The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) whose lattice constant is greater than that of the semiconductor material of the substrate 100. Impurities may be implanted in situ during the first SEG process. As another example, impurities may be implanted into the first source / drain pattern SD1 after its formation. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0138] A second source / drain pattern SD2 can be formed separately in the second recess RS2. For example, the second source / drain pattern SD2 can be formed by performing a second SEG process in which the inner wall of the second recess RS2 is used as a seed layer. For example, the second source / drain pattern SD2 can include the same semiconductor material as the substrate 100 (e.g., Si). The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type). An inner spacer can be formed between the second source / drain pattern SD2 and the sacrificial layer SAL.

[0139] refer to Figure 12 A patterning process involving etching the sacrificial pattern PP and the device isolation layer ST can be performed on the sacrificial pattern PP to form cleaving holes CTH1 and CTH2 extending on the third direction D3. Forming the cleaving holes CTH1 and CTH2 may include: forming a mask pattern on the sacrificial pattern PP, and using the mask pattern as a mask to perform an etching process to etch the sacrificial pattern PP and the device isolation layer ST. The cleaving holes CTH1 and CTH2 may include a first cleaving hole CTH1 between a first PMOSFET region PR1 and a second PMOSFET region PR2, and a second cleaving hole CTH2 between a first NMOSFET region NR1 and a second NMOSFET region NR2.

[0140] A first dicing hole CTH1 and a second dicing hole CTH2 can extend through the sacrificial pattern PP into the device isolation layer ST. The inner walls of the sacrificial pattern PP and the device isolation layer ST can be exposed through the first dicing hole CTH1 and the second dicing hole CTH2. For example, the first dicing hole CTH1 can have a first inner wall IW1 that exposes the sacrificial pattern PP and the device isolation layer ST, and the second dicing hole CTH2 can have a second inner wall IW2 that exposes the sacrificial pattern PP and the device isolation layer ST.

[0141] In some embodiments, the first cleaving hole CTH1 and the second cleaving hole CTH2 can penetrate the device isolation layer ST to expose the substrate 100. The first cleaving hole CTH1 and the second cleaving hole CTH2 can have a high aspect ratio. Therefore, the first cleaving hole CTH1 and the second cleaving hole CTH2 can have a relatively large depth relative to their width. The depth-to-width ratio of the first cleaving hole CTH1 and the second cleaving hole CTH2 can be from 4 to 8, but is not limited thereto.

[0142] refer to Figure 13 A first preliminary cutting layer PCL1 and a second preliminary cutting layer PCL2 can be sequentially formed in the first cutting hole CTH1 and the second cutting hole CTH2, thereby forming a first preliminary cutting pattern PCT1 and a second preliminary cutting pattern PCT2.

[0143] A first preliminary cutting layer PCL1 can be formed on the inner walls of the first cutting hole CTH1 and the second cutting hole CTH2. A second preliminary cutting layer PCL2 can fill the remaining portions of the first cutting hole CTH1 and the second cutting hole CTH2, and can be formed on the first preliminary cutting layer PCL1. The first preliminary cutting layer PCL1 can cover the bottom surface and two sidewalls of the second preliminary cutting layer PCL2.

[0144] The first preliminary cutting layer PCL1 and the second preliminary cutting layer PCL2 can have different etching selectivity for at least one etching process. The first preliminary cutting layer PCL1 and the second preliminary cutting layer PCL2 can be formed by different deposition processes.

[0145] For reference Figure 6AAs described, the first preliminary dicing layer PCL1 and the second preliminary dicing layer PCL2 may comprise the same material or may comprise different materials. Even when both the first preliminary dicing layer PCL1 and the second preliminary dicing layer PCL2 comprise silicon nitride (SiN), they may have different etch selectivity for the etching process described later. This is because the first preliminary dicing layer PCL1 and the second preliminary dicing layer PCL2 may have different physical properties, such as density, crystallinity, and whether a deposition process and / or heat treatment are performed. The first preliminary dicing layer PCL1 and the second preliminary dicing layer PCL2 may comprise insulating materials, such as silicon nitride layers, silicon oxide layers, or combinations thereof.

[0146] A first interlayer insulating layer 110 can be formed on the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS (see Figure 16A For example, the first interlayer insulating layer 110 may include a silicon oxide layer. The first interlayer insulating layer 110 may be planarized until the upper surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back process or a CMP (chemical mechanical polishing) process. During the planarization process, all hard mask patterns MP may be removed.

[0147] refer to Figure 14A and Figure 14B An etching process can be performed to selectively remove the sacrificial pattern PP on the substrate 100. The etching process can be a wet etching process. The first preliminary dicing layer PCL1 and the second preliminary dicing layer PCL2 may comprise materials that are etch-selective relative to the sacrificial pattern PP and may not be removed by the etching process. While the sacrificial pattern PP is being removed, a portion of the sidewalls of the first preliminary dicing layer PCL1 may be exposed. For example, the first preliminary dicing layer PCL1 located in the device isolation layer ST may not be exposed, and the remainder may be exposed.

[0148] The overall structure formed by the first preliminary cutting layer PCL1 and the second preliminary cutting layer PCL2 can have a first width WD1, and the first preliminary cutting layer PCL1 can have a third width WD3. The third width WD3 of the first preliminary cutting layer PCL1 can be smaller than the width of the second preliminary cutting layer PCL2.

[0149] refer to Figure 15A and Figure 15B An etching process can be performed to selectively remove... Figure 14AThe first preliminary dicing layer PCL1 is exposed by the device isolation layer ST. The second preliminary dicing layer PCL2 may not be removed because it has a different etch selectivity relative to the etching process than the first preliminary dicing layer PCL1. Furthermore, portions of the first preliminary dicing layer PCL1 not exposed by the device isolation layer ST may not be removed. The etching process can be a wet etching process. For example, a wet etching process can use, but is not limited to, a hydrofluoric acid (Hf) solution or a phosphoric acid (H3PO4) solution.

[0150] While removing a portion of the first preliminary cutting layer PCL1, a first cutting layer CL1 can be formed. While removing a portion of the first preliminary cutting layer PCL1, an area in which the width of the first preliminary cutting pattern PCT1 changes can be formed. The width of the first preliminary cutting pattern PCT1 can abruptly change from a first width WD1 to a second width WD2 at the boundary between the portion where the first preliminary cutting layer PCL1 has been removed and the portion where the first preliminary cutting layer PCL1 has not been removed. The portion having the first width WD1 can be a first portion PT1, and the portion having the second width WD2 can be a second portion PT2.

[0151] The first cleaving layer CL1 may include a first upper surface TS1 and a second upper surface TS2 as exposed upper surfaces. The first upper surface TS1 and the second upper surface TS2 may be coplanar with the upper surface of the device isolation layer ST, but are not limited thereto. In some embodiments, the first upper surface TS1 and the second upper surface TS2 may be higher or lower than the upper surface of the device isolation layer ST.

[0152] According to the present disclosure, a first preliminary cutting layer PCL1 and a second preliminary cutting layer PCL2 can be formed sequentially. Then, the widths of the cutting patterns CT1 and CT2 can be reduced by removing a portion of the first preliminary cutting layer PCL1.

[0153] refer to Figure 15C The second upper surface TS2 can have a concave profile. This is because, during the etching process, the first preliminary cut layer PCL1 can be etched deeper than the upper surface of the device isolation layer ST. This is because the first upper surface TS1 and the second upper surface TS2, which are the exposed upper surfaces of the first cut layer CL1, can be further etched through the etching process. Therefore, the horizontal height of each of the first upper surface TS1 and the second upper surface TS2 can be lower than the horizontal height of the upper surface of the device isolation layer ST.

[0154] In some embodiments, only one of the first upper surface TS1 and the second upper surface TS2 may have a concave profile. For example, the first upper surface TS1 may be as follows: Figure 15B As shown, it extends in the first direction D1, and the second upper surface TS2 can be shaped as follows. Figure 15CThe inwardly recessed contour of the first cut layer CL1 is shown.

[0155] refer to Figure 16A , Figure 16B and Figure 16C The sacrificial layer SAL can be exposed by removing the sacrificial pattern PP. The exposed sacrificial layer SAL can be selectively removed by an etching process. The etching process can be a wet etching process. The etching material used in the etching process can quickly remove the sacrificial layer SAL with a relatively high germanium concentration. While removing the sacrificial layer SAL, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be exposed.

[0156] A gate insulating layer GI can be formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate insulating layer GI can surround each of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate insulating layer GI can be formed in each of the first inner region IRG1, second inner region IRG2, and third inner region IRG3. The gate insulating layer GI can be formed in the outer region ORG.

[0157] The gate insulating layer GI can be formed on the upper surfaces of the first active pattern AP1 and the second active pattern AP2, as well as on the upper surface of the device isolation layer ST. The gate insulating layer GI can be formed on the exposed first upper surface TS1 and the second upper surface TS2, and can extend in the third direction D3 along the two sidewalls SW2 and SW3 of the first preliminary diced pattern PCT1. That is, the gate insulating layer GI can be formed on the sidewalls SW2 and SW3 of the first preliminary diced pattern PCT1.

[0158] refer to Figure 17A , Figure 17B and Figure 17C A gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE may include a first inner portion PO1, a second inner portion PO2, and a third inner portion PO3 formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, respectively, and a fourth inner portion PO4 formed in the outer region ORG. The gate electrode GE can be recessed to reduce its height. A gate overlay pattern GP can be formed on the recessed gate electrode GE.

[0159] As the gate electrode GE is recessed, the height of the first preliminary dicing pattern PCT1 can be reduced to form the first dicing pattern CT1. Forming the second dicing pattern CT2 can be substantially the same as forming the first dicing pattern CT1 as described above. The gate overlay pattern GP can be formed on the first dicing pattern CT1 and the second dicing pattern CT2. The upper surface of each of the first dicing pattern CT1 and the second dicing pattern CT2 can contact the bottom surface of the gate overlay pattern GP.

[0160] Forming a gate electrode GE on the first PMOSFET region PR1 and the second PMOSFET region PR2 may include sequentially forming a first metal pattern MP1 and a second metal pattern MP2. The first metal pattern MP1 may be formed on the gate insulating layer GI, and the second metal pattern MP2 may be formed on each of the first metal patterns MP1. The first metal pattern MP1 may fill all of the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, and may also be formed in a portion of the outer region ORG. The first metal pattern MP1 may surround the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. (See reference...) Figure 6A The first metal pattern MP1 can also be formed on a portion of the sidewall of the first cut pattern CT1 by extending it onto the device isolation layer ST.

[0161] Refer again Figure 4 as well as Figure 5A , Figure 5B , Figure 5C and Figure 5D A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include silicon oxide. An active contact AC electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 may be formed through the second interlayer insulating layer 120 and the first interlayer insulating layer 110. A gate contact GC electrically connected to the gate electrode GE may be formed through the second interlayer insulating layer 120 and the gate overlay pattern GP.

[0162] Forming each of the active contact AC and the gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may include a metal layer / metal nitride. The conductive pattern FM may include a low-resistance metal.

[0163] A separator structure DB can be formed at the first boundary BD1 and the second boundary BD2 of the single-height cell SHC, respectively. The separator structure DB can extend through the gate cover pattern GP and the gate electrode GE into the first active pattern AP1 and the second active pattern AP2. The separator structure DB may include an insulating material, such as silicon oxide or silicon nitride.

[0164] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0165] Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B and Figure 19C This is a schematic diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. (See reference...) Figures 8A to 17C Overlapping technical features are omitted, and the differences are described in detail.

[0166] Figure 18A and Figure 19A It is along Figure 4 The cross-sectional view taken by line D-D'. Figure 18B It is shown Figure 18A A magnified view of part M. Figure 18C It is an instruction Figure 18A A magnified view of part N. Figure 19B It is shown Figure 19A A magnified view of part M. Figure 19C It is an instruction Figure 19A A magnified view of part N.

[0167] refer to Figure 18A , Figure 18B and Figure 18C According to Figure 11A , Figure 11B and Figure 11C A first source / drain pattern SD1 and a second source / drain pattern SD2 are formed. An etching process can then be performed to selectively remove the sacrificial pattern PP. By removing the sacrificial pattern PP, the outer region ORG can expose the first channel pattern CH1 and the second channel pattern CH2 (see [link to original text]). Figure 16A Removing the sacrificial pattern PP may include wet etching using an etchant that selectively etches polysilicon.

[0168] The sacrificial layer SAL exposed through the outer region ORG can be selectively removed to form the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 (see [link]). Figure 16A For example, an etching process that selectively etches the sacrificial layer SAL can be performed to remove only the sacrificial layer SAL while retaining the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The etching process can achieve high etching rates for silicon-germanium with relatively high germanium concentrations.

[0169] A gate insulating layer GI can be formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate insulating layer GI can surround each of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate insulating layer GI can be formed in each of the first inner region IRG1, second inner region IRG2, and third inner region IRG3. The gate insulating layer GI can be formed in the outer region ORG.

[0170] A first metal pattern MP1 can be formed on the gate insulating layer GI in the first PMOSFET region PR1 and the second PMOSFET region PR2. The first metal pattern MP1 can extend to the upper surface of the device isolation layer ST located in the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0171] A sacrificial insulating layer 111 may be formed on the front surface of the substrate 100. The sacrificial insulating layer 111 may be formed on the device isolation layer ST, the first active pattern AP1 and the second active pattern AP2, and the first semiconductor pattern SP1, the second semiconductor pattern SP2 and the third semiconductor pattern SP3. The sacrificial insulating layer 111 may include an insulating material.

[0172] A patterning process can be performed on the sacrificial insulating layer 111 to form such as Figure 12 The first cut hole CTH1 and the second cut hole CTH2 are shown. The first cut hole CTH1 and the second cut hole CTH2 can extend through the sacrificial insulating layer 111 into the device isolation layer ST. The inner walls of the sacrificial insulating layer 111 and the inner walls of the device isolation layer ST can be exposed through the first cut hole CTH1 and the second cut hole CTH2.

[0173] Then, a first preliminary cutting layer PCL1 and a second preliminary cutting layer PCL2 can be sequentially formed in the first cutting hole CTH1 and the second cutting hole CTH2. The formation of the first preliminary cutting layer PCL1 and the second preliminary cutting layer PCL2 can be related to a reference. Figure 13 The descriptions are essentially the same. However, the reference... Figure 18B and Figure 18C Since the gate insulating layer GI, the high dielectric layer HK, and the first metal pattern MP1 are formed before the first preliminary dicing layer PCL1 and the second preliminary dicing layer PCL2, the gate insulating layer GI, the high dielectric layer HK, and the first metal pattern MP1 can contact the sidewall of the first preliminary dicing layer PCL1.

[0174] refer to Figure 19A , Figure 19B and Figure 19CAn etching process can be performed to selectively remove the sacrificial insulating layer 111. The first preliminary dicing layer PCL1 may include a material that is etch-selective relative to the sacrificial insulating layer 111 and may not be removed by the etching process. While the sacrificial insulating layer 111 is being removed, a portion of the sidewalls of the first preliminary dicing layer PCL1 may be exposed. For example, the first preliminary dicing layer PCL1 located beneath the first metal pattern MP1 of the first PMOSFET region PR1 and the second PMOSFET region PR2 may not be exposed, and the remainder may be exposed. The first preliminary dicing layer PCL1 located beneath the high dielectric layer HK of the first NMOSFET region NR1 and the second NMOSFET region NR2 may not be exposed, and the remainder may be exposed.

[0175] An etching process can be performed to selectively remove the exposed first preliminary cut layer PCL1. The second preliminary cut layer PCL2 may not be removed because it has a different etching selectivity relative to the etching process than the first preliminary cut layer PCL1. Furthermore, portions not exposed by the first metal pattern MP1 or the high dielectric layer HK may not be removed.

[0176] While removing a portion of the first preliminary cutting layer PCL1, a first cutting layer CL1 can be formed. While removing a portion of the first preliminary cutting layer PCL1, an area in which the width of the first preliminary cutting pattern PCT1 changes can be formed. The width of the first preliminary cutting pattern PCT1 can abruptly change from a first width WD1 to a second width WD2 at the boundary between the portion where the first preliminary cutting layer PCL1 has been removed and the portion where the first preliminary cutting layer PCL1 has not been removed.

[0177] The first diced layer CL1 may include a first upper surface TS1 and a second upper surface TS2 as exposed upper surfaces. In the first PMOSFET region PR1 and the second PMOSFET region PR2, the first upper surface TS1 and the second upper surface TS2 may be located at a fourth horizontal height Lv4, and in the first NMOSFET region NR1 and the second NMOSFET region NR2, the first upper surface TS1 and the second upper surface TS2 may also be located at a third horizontal height Lv3. Due to the thickness of the first metal pattern MP1, the fourth horizontal height Lv4 may be higher than the third horizontal height Lv3. Therefore, the horizontal height of the upper surface of the first diced layer CL1 located in the first PMOSFET region PR1 and the second PMOSFET region PR2 may be higher than the horizontal height of the upper surface of the first diced layer CL1 located in each of the first NMOSFET regions NR1 and the second NMOSFET region NR2. That is, the first PMOSFET region PR1 and the second PMOSFET region PR2, as well as the first NMOSFET region NR1 and the second NMOSFET region NR2, may have upper surfaces with different horizontal heights of the first portion PT1.

[0178] Figures 20 to 24 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of this disclosure. Figure 20 It is along Figure 4 The cross-sectional view taken by line D-D'. Figure 21 , Figure 22 , Figure 23 and Figure 24 It is shown Figure 20 A magnified view of part O. (Compared to reference) Figures 8A to 17C Overlapping technical features are omitted, and the differences are described in detail.

[0179] refer to Figure 20 and Figure 21 A patterning process can be performed on the sacrificial pattern PP to form a first dicing hole CTH1 and a second dicing hole CTH2 extending on the third direction D3, in which the sacrificial pattern PP and the device isolation layer ST are etched. However, with Figure 12 Unlike other holes, the inner walls of the first cutting hole CTH1 and the second cutting hole CTH2 can have negative slopes. (Reference) Figure 12 The widths of the first cut hole CTH1 and the second cut hole CTH2 can decrease in the vertical direction (e.g., in the third direction D3) toward the bottom surface of the substrate 100. However, referring to Figure 20 and Figure 21There may be sections where the widths of the first dicing hole CTH1 and the second dicing hole CTH2 increase vertically toward the bottom surface of the substrate 100. If the inner walls of the first dicing hole CTH1 and the second dicing hole CTH2 can have a negative slope, then when insulating material is filled to form dicing patterns CT in the first dicing hole CTH1 and the second dicing hole CTH2 respectively, air gaps or seams can be formed. This is because the first dicing hole CTH1 and the second dicing hole CTH2 have a large aspect ratio. This may lead to the problem of deterioration of the electrical characteristics of the semiconductor device.

[0180] On the other hand, the present invention allows for the initial formation of a first preliminary cutting layer PCL1 in the first cutting hole CTH1 and the second cutting hole CTH2. Since the first preliminary cutting layer PCL1 is formed on the inner walls of the first cutting hole CTH1 and the second cutting hole CTH2, air gaps or seams are not formed even in sections including negative slopes. By forming the first preliminary cutting layer PCL1, negative slope sections of the first cutting hole CTH1 and the second cutting hole CTH2 can be eliminated.

[0181] The thickness of the first preliminary cutting layer PCL1 does not have to be constant. For example, the first thickness TH1 of the first preliminary cutting layer PCL1 in sections other than the negative slope section can be less than the second thickness TH2 of the first preliminary cutting layer PCL1 in the negative slope section.

[0182] refer to Figure 22 After forming the first preliminary cutting layer PCL1, an etching process can be further performed on the first preliminary cutting layer PCL1. However, the etching process can be omitted. The thickness of the first preliminary cutting layer PCL1 can be reduced through the etching process. For example, the second thickness TH2 of the first preliminary cutting layer PCL1 in the negative slope region can be reduced to a fourth thickness TH4. The first thickness TH1 of the first preliminary cutting layer PCL1 in regions other than the negative slope region can be reduced to a third thickness TH3.

[0183] The etching process removes all negative slope sections of the first cut hole CTH1 and the second cut hole CTH2. Therefore, the widths of the first cut hole CTH1 and the second cut hole CTH2 can be reduced in the vertical direction toward the bottom surface of the substrate 100.

[0184] refer to Figure 23 The second preliminary cutting layer PCL2 fills the remaining portions of the first cutting hole CTH1 and the second cutting hole CTH2, and can be formed on the first preliminary cutting layer PCL1. The first preliminary cutting layer PCL1 can be located on the bottom surface and two sidewalls of the second preliminary cutting layer PCL2. When forming the second preliminary cutting layer PCL2 while removing the negative slope section, air gaps or seams can be avoided.

[0185] refer to Figure 24 An etching process can be performed to selectively remove the sacrificial pattern PP on the substrate 100. Removal of the sacrificial pattern PP can be performed in conjunction with a reference... Figure 14A and Figure 14B The descriptions are essentially the same. While removing the sacrificial pattern PP, a portion of the sidewalls of the first preliminary cutting layer PCL1 can be exposed.

[0186] Then, the exposed first preliminary cutting layer PCL1 can be selectively removed. Removal of the first preliminary cutting layer PCL1 can be performed in conjunction with a reference. Figure 15A and Figure 15B The descriptions are essentially the same. While removing the first preliminary dicing layer PCL1, the second preliminary dicing layer PCL2 can be exposed. Since all negative slope segments are removed, the second width WD2 of the second preliminary dicing layer PCL2 can be reduced in the vertical direction toward the bottom surface of the substrate 100.

[0187] according to Figures 20 to 24 The method for manufacturing a diced pattern CT according to the present disclosure may include sequentially forming a first preliminary dicing layer PCL1 and a second preliminary dicing layer PCL2. While forming and etching the first preliminary dicing layer PCL1, negative slope sections formed in the first dicing hole CTH1 and the second dicing hole CTH2 can be removed. Therefore, the diced pattern CT may not include air gaps or seams. As a result, it is possible to manufacture semiconductor devices with improved reliability and electrical characteristics.

[0188] In the three-dimensional field-effect transistor according to the present disclosure, the width of a diced pattern extending vertically through the gate electrode can be varied. The diced pattern may include a first portion and a second portion located on the first portion, wherein at the boundary between the first and second portions, the width of the first portion is greater than the width of the second portion. The first portion may include a first dicing layer and a second dicing layer having different etch selectivity for the etching process. Furthermore, the method for manufacturing the diced pattern according to the present disclosure allows for the sequential formation of the first dicing layer and the second dicing layer. The width of the diced pattern can be reduced by removing a portion of the first dicing layer. Therefore, the size of the transistor in the semiconductor device can be reduced, and reliability and electrical characteristics can be improved.

[0189] While embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of this disclosure. Therefore, the exemplary embodiments of this disclosure should be considered illustrative rather than restrictive in all respects.

Claims

1. A semiconductor device, the semiconductor device comprising: The first active pattern is spaced apart from each other in a first direction; A first device isolation layer is located between adjacent first active patterns; A first channel pattern, wherein the first channel pattern is located on the first active pattern; and A cutting pattern, the cutting pattern extending perpendicularly between the first groove patterns, The cutting pattern includes a first portion and a second portion located on the first portion, and Wherein, at the boundary between the first part and the second part, the width of the first part is greater than the width of the second part.

2. The semiconductor device according to claim 1, wherein, The sidewall of the first portion is spaced apart from the sidewall of the second portion in the first direction, and The upper surface of the first part connects the side wall of the first part and the side wall of the second part.

3. The semiconductor device according to claim 1, further comprising: A gate insulating layer that covers the upper surface of the first device isolation layer. The gate insulating layer is in contact with at least one of the upper surface of the first portion or the sidewall of the first portion.

4. The semiconductor device according to claim 1, further comprising: The gate electrode is located on the first channel pattern. The upper surface of the first portion faces the gate electrode.

5. The semiconductor device according to claim 4, wherein, The gate electrode includes a first metal pattern located on the first active pattern and a second metal pattern located on the first metal pattern, and The sidewall of the first part is in contact with the first metal pattern.

6. The semiconductor device according to claim 1, wherein, The first part includes a first cutting layer and a second cutting layer located on the first cutting layer. The first cutting layer is located on the sidewall of the second cutting layer, and The first cutting layer and the second cutting layer have different etching selectivity relative to at least one etching process.

7. The semiconductor device according to claim 6, wherein, The horizontal height of the upper surface of the first cut layer is lower than the horizontal height of the upper surface of the first active pattern.

8. The semiconductor device according to claim 6, wherein, The first cutting layer and the second cutting layer are formed by different deposition processes.

9. The semiconductor device according to claim 6, wherein, The second part also includes the second cutting layer and the first cutting layer located on the sidewall of the second cutting layer, and Wherein, the width of the first cut layer in the second part is smaller than the width of the first cut layer in the first part.

10. The semiconductor device according to claim 6, wherein, The first portion further includes a third cutting layer, which is located between the first cutting layer and the second cutting layer, and The third cutting layer has different etching selectivity relative to at least one of the first cutting layer or the second cutting layer with respect to at least one etching process.

11. The semiconductor device according to claim 10, wherein, The second part also includes the third cutting layer located on the sidewall of the first cutting layer.

12. A semiconductor device, the semiconductor device comprising: A substrate, the substrate including a first active region and a second active region; A first active pattern, the first active pattern being located on the first active region and spaced apart from each other in a first direction; A first device isolation layer is located between adjacent first active patterns; A first gate electrode, the first gate electrode being located on the first active pattern; and A first diced pattern extends through the first gate electrode into the first device isolation layer. The first cutting pattern includes a first portion and a second portion located on the first portion. The first part includes a first cutting layer and a second cutting layer located on the first cutting layer. Wherein, the first cutting layer and the second cutting layer have different etching selectivity relative to at least one etching process, and The sidewall of the first part is spaced apart from the sidewall of the second part in the first direction.

13. The semiconductor device according to claim 12, wherein, The horizontal height of the upper surface of the second cutting layer is lower than the horizontal height of the upper surface of the first active pattern.

14. The semiconductor device according to claim 12, wherein, The first portion further includes a third cutting layer, which is located between the first cutting layer and the second cutting layer, and The third cutting layer has different etching selectivity relative to at least one of the first cutting layer or the second cutting layer with respect to at least one etching process.

15. The semiconductor device according to claim 12, wherein, The first cutting layer and the second cutting layer are formed by different deposition processes.

16. The semiconductor device according to claim 12, wherein, The first cutting layer includes an upper surface exposed by the second cutting layer, and The upper surface of the first dicing layer faces the gate electrode.

17. The semiconductor device of claim 12, further comprising: The second active pattern is located on the second active region and is spaced apart from each other in the first direction; A second device isolation layer is located between adjacent second active patterns; The second gate electrode is located on the second active pattern and includes a first metal pattern and a second metal pattern located on the first metal pattern; as well as A second dicing pattern extends through the second gate electrode into the second device isolation layer. The second cutting pattern includes a third portion and a fourth portion located on the third portion. The third part includes the first cutting layer and a second cutting layer located on the first cutting layer, and At least a portion of the sidewall of the third part is in contact with the first metal pattern.

18. The semiconductor device of claim 17, wherein, The first active region is an NMOSFET region and the second active region is a PMOSFET region.

19. The semiconductor device according to claim 17, wherein, The third part includes the upper surface exposed by the fourth part, and The upper surface of the third part is higher than the upper surface of the first part.

20. A semiconductor device, the semiconductor device comprising: Substrate, the substrate comprising an active pattern; A device isolation layer that defines the active pattern; A first channel pattern, the first channel pattern being located on the active pattern and spaced apart from each other in a first direction; First source / drain pattern, the first source / drain pattern is connected to the first channel pattern; Cutting patterns, which extend vertically between adjacent first channel patterns; A first gate electrode, the first gate electrode being connected to the first source / drain pattern; A gate insulating layer, wherein the gate insulating layer is disposed between the first gate electrode and each of the first channel patterns; A gate spacer located on the sidewall of the first gate electrode; A gate overlay pattern, the gate overlay pattern being located on the upper surface of the first gate electrode; An interlayer insulating layer is located on the first source / drain pattern and the gate overlay pattern; An active contact is provided, which extends through the interlayer insulation layer and connects to each of the first source / drain patterns; A gate contact that extends through the gate cover pattern and the interlayer insulating layer and connects to the first gate electrode; as well as A first metal layer, situated on the interlayer insulating layer, includes a first wiring connection to the active contact and the gate contact. The cutting pattern includes a first portion and a second portion located on the first portion. The first portion includes the upper surface exposed by the second portion, and Wherein, the horizontal height of the upper surface of the first part is lower than the horizontal height of the upper surface of the active pattern.

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