Method for manufacturing a driving substrate, driving substrate and display panel

Abstract

The application belongs to the technical field of display and particularly relates to a preparation method of a driving substrate, a driving substrate and a display panel. The preparation method comprises the following steps: forming a gate electrode and a gate insulating layer on a substrate; forming an indium-rich first oxide semiconductor layer, a second oxide semiconductor layer containing a doping element and having a concentration increasing in a direction away from the first oxide semiconductor layer, and a gallium-rich third oxide semiconductor layer on the gate insulating layer to form an active layer; forming a patterned etching stop layer on the active layer, so that the etching stop layer covers an area to be formed into a channel region and exposes an area to be formed into a source / drain electrode; after depositing a source / drain metal layer, etching the source / drain metal layer by using a wet etching solution containing a defect repairing component to form a source electrode and a drain electrode, wherein the etching stop layer protects the underlying active layer during the etching process, and the exposed active layer is repaired in situ by the repairing component; and finally, the contact resistance is reduced through annealing treatment. The application can improve the mobility, improve the short-wave light stability and reduce the contact resistance without increasing the number of masks.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a method for preparing a driving substrate, the driving substrate, and a display panel. Background Technology

[0002] Currently, mainstream back channel etch (BCE) structure oxide thin film transistors typically employ a double oxide active layer to protect the back channel during source and drain etching and to meet the requirements of high refresh rate displays.

[0003] However, the existing dual-layer BCE structure still has technical problems such as insufficient carrier mobility, easy damage to the back channel by source and drain etching leading to leakage current and threshold voltage drift, poor stability under short-wavelength light irradiation requiring an additional light-shielding layer, and high contact resistance between the source and drain electrodes and the active layer, which limit its application in higher performance display panels. Summary of the Invention

[0004] The purpose of this application is to provide a method for preparing a driving substrate, a driving substrate and a display panel, which can simultaneously improve carrier mobility, improve short-wavelength light stability and reduce contact resistance, without increasing the number of photomasks.

[0005] This application provides a method for fabricating a driving substrate, comprising the following steps: forming a gate on a substrate and forming a gate insulating layer on the gate; sequentially forming a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer on the gate insulating layer to constitute an active layer; wherein the first oxide semiconductor layer is an indium-rich oxide semiconductor layer; the second oxide semiconductor layer includes a dopant element, and the concentration of the dopant element increases in a direction away from the first oxide semiconductor layer; the third oxide semiconductor layer is a gallium-rich oxide semiconductor layer; forming an etch stop layer on the active layer, and etching the... An etch barrier layer is patterned to cover the active layer in the area where a channel is to be formed and to expose the active layer in the areas where the source and drain are to be formed. Source and drain metal layers are deposited on the etch barrier layer and the exposed active layer. The source and drain metal layers are etched using a wet etching solution containing defect repair components to form the source and drain. During etching, the etch barrier layer prevents the wet etching solution from eroding the underlying active layer, and the defect repair components perform in-situ defect repair on the active layer exposed by the etching. Annealing is then performed to reduce the contact resistance between the source and drain and the active layer.

[0006] In one exemplary embodiment of this application, the etching barrier layer is an insulating material layer resistant to wet etching.

[0007] In one exemplary embodiment of this application, before depositing the source / drain metal layer, the method further includes: forming an ohmic contact layer on the exposed active layer and the etch barrier layer; the ohmic contact layer is an N-type heavily doped oxide semiconductor layer, and the source / drain metal layer is deposited on the ohmic contact layer.

[0008] In one exemplary embodiment of this application, the first oxide semiconductor layer comprises indium, gallium, and zinc, and the indium content is higher than the gallium content; the third oxide semiconductor layer comprises gallium and indium, and the gallium content is higher than the indium content.

[0009] In one exemplary embodiment of this application, the bandgap of the third oxide semiconductor layer is 3.2 eV to 3.5 eV, so that it absorbs light with a wavelength less than 470 nm.

[0010] In one exemplary embodiment of this application, the third oxide semiconductor layer is further doped with aluminum and / or niobium to adjust the bandgap of the third oxide semiconductor layer to 3.2 eV to 3.5 eV.

[0011] In one exemplary embodiment of this application, the doping element includes silicon and / or tin, and the concentration of the doping element increases from 0 to 5%.

[0012] In one exemplary embodiment of this application, the defect repair component includes ammonium fluoride and an organic oxygen donor, wherein the concentration of ammonium fluoride in the wet etching solution is 0.1% to 0.5%; and the organic oxygen donor is an organic solvent containing hydroxyl or carbonyl groups.

[0013] A second aspect of this application provides a driving substrate, comprising: a substrate; a gate electrode disposed on the substrate; a gate insulating layer covering the gate electrode; an active layer disposed on the gate insulating layer, the active layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer stacked sequentially; an etch stop layer covering a channel region of the active layer; a source electrode and a drain electrode disposed on the active layer, wherein a channel region is formed between the source electrode and the drain electrode, and the etch stop layer is located above the channel region; the first oxide semiconductor layer is an indium-rich oxide semiconductor layer, the second oxide semiconductor layer includes a dopant element, and the concentration of the dopant element increases from the first oxide semiconductor layer to the third oxide semiconductor layer, the third oxide semiconductor layer being a gallium-rich oxide semiconductor layer.

[0014] A third aspect of this application provides a display panel, including: a driver chip; and a driver substrate as described above, the driver substrate being electrically connected to the driver chip.

[0015] The method for preparing the driving substrate, the driving substrate, and the display panel described in this application have at least the following beneficial effects:

[0016] The first oxide semiconductor layer in this application is an indium-rich oxide semiconductor layer. Indium-rich materials have high carrier mobility, thus enabling the construction of low-resistance carrier transport paths in the active layer, improving the conduction current and response speed of the driving substrate. The third oxide semiconductor layer uses a gallium-rich material, whose chemical bonds are stable. Even when exposed to the etching solution during subsequent wet etching to form source and drain electrodes, it exhibits strong corrosion resistance, preventing excessive thinning of the active layer. This reduces etching damage at the edge of the channel region and suppresses leakage current and threshold current caused by damage. The bias shift is achieved because gallium-rich materials have a wide intrinsic bandgap, effectively absorbing short-wavelength light. Therefore, photodegradation can be suppressed without the need for an additional shielding layer, eliminating the need for photomasks and deposition processes required for shielding layers, thus minimizing the number of photomask steps in the entire fabrication process. The concentration of doped elements in the second oxide semiconductor layer increases in the direction away from the first oxide semiconductor layer. This gradient doping causes the energy band to gradually broaden from the indium-rich layer to the gallium-rich layer, forming a gradual bandgap. This reduces carrier scattering at the heterojunction, which helps to further improve mobility and bias stability. In addition, by forming a patterned etch barrier layer, during wet etching of the source and drain metal layers, the etch barrier layer covers the area to be formed in the channel region, preventing the etchant from eroding the active layer below and protecting the top of the channel from direct etching damage. The active layer exposed by the etching is simultaneously repaired in situ by a wet etchant containing defect repair components, filling oxygen vacancies, reducing the interface defect state density, thereby suppressing off-state current and mitigating threshold voltage drift under long-term operation. The subsequent annealing process promotes atomic interdiffusion or reaction at the interface between the source / drain metals and the active layer, reducing the interface contact barrier, thereby decreasing contact resistance, improving driving capability, and reducing power consumption. The synergistic effect of these features enables this fabrication method to simultaneously achieve high mobility, strong photostability, and low contact resistance without increasing the photomask or adding excessive process complexity, meeting the performance requirements of high refresh rate and high resolution display panels for driving devices.

[0017] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 A flowchart illustrating the fabrication method of the driving substrate provided in an embodiment of this application is shown.

[0021] Figure 2 A flowchart illustrating the method for preparing the active layer provided in an embodiment of this application is shown.

[0022] Figure 3 A cross-sectional structural schematic diagram of the driving substrate provided in an embodiment of this application is shown.

[0023] Figure 4 A cross-sectional schematic diagram of the three-layer oxide semiconductor layer provided in an embodiment of this application is shown.

[0024] Figure 5 This is a top view of the structure provided in an embodiment of the present application, showing the source and drain electrodes connected on an etch barrier layer.

[0025] Figure 6 This illustration shows a cross-sectional structure diagram of a pixel electrode connected to the source or drain via a via according to an embodiment of this application.

[0026] Figure 7 This paper shows a schematic diagram of the structure of the driving substrate and the driving chip electrically connected according to an embodiment of the present application.

[0027] Explanation of reference numerals in the attached figures: 100. Driving substrate; 101. Substrate; 102. Gate; 103. Gate insulating layer; 104. Active layer; 1041. First oxide semiconductor layer; 1042. Second oxide semiconductor layer; 1043. Third oxide semiconductor layer; 105. Etch barrier layer; 106. Ohmic contact layer; 107. Source / drain; 108. Encapsulation protection layer; 109. Passivation layer; 1100. Pixel electrode; 200. Driving chip. Detailed Implementation

[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0029] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0030] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0031] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0032] Example 1 Embodiment 1 of this application provides a method for fabricating a driving substrate 100. This method is compatible with existing 4-mask back channel etching (BCE) production lines and can achieve the fabrication of high-performance thin-film transistors (TFTs) without the need for additional equipment or masks. For example, Figure 1 and Figure 2 As shown, the method includes the following steps: In step S100, a gate 102 and a gate insulating layer 103 are formed on the substrate 101.

[0033] First, such as Figure 3As shown, a substrate 101 is provided. This substrate 101 can be made of highly flat alkali-free glass, or, depending on the requirements of flexible displays, a flexible substrate such as polyimide. Its function is to provide a stable support foundation for the entire device. After cleaning the substrate 101, a gate 102 metal layer is sputtered and deposited on it. The gate 102 metal can adopt a molybdenum / aluminum-neodymium alloy (Mo / AlNd) stacked structure with a total thickness of approximately 150 nanometers. Subsequently, the first photomask process is performed: photoresist is coated, exposed and developed using a mask with the gate 102 pattern, the metal layer is etched, and the photoresist is removed to form the gate 102.

[0034] Next, a gate insulating layer 103 is deposited on the substrate 101 where the gate 102 is formed. This can be achieved using plasma-enhanced chemical vapor deposition (PECVD) to coat the gate 102 with a layer of silicon nitride (SiN). x ) and silicon dioxide (SiO) x The composite insulating layer consists of silicon nitride and silicon oxide, with a thickness ratio of approximately 2:1 and a total thickness of about 200 nanometers. The silicon nitride layer provides good insulation, while the silicon oxide layer improves the interface characteristics with the subsequent oxide active layer 104 and reduces interface defects.

[0035] In step S200, three oxide semiconductor layers are sequentially formed on the gate insulating layer 103 to form the active layer 104.

[0036] After the gate insulating layer 103 is deposited, the substrate is transferred to the sputtering chamber, where three layers of oxide semiconductor material are continuously deposited without disrupting the vacuum, forming an oxide stack to constitute the active layer 104. Figure 3 and Figure 4 As shown, these three layers of materials can synergistically improve the problems faced by bilayer BCE structures in related technologies, such as mobility, etching damage, photostability, and contact resistance.

[0037] For example, such as Figure 2 As shown, this three-layer oxide semiconductor layer can be prepared by the following steps: Step S210: Deposit the first oxide semiconductor layer 1041.

[0038] The first oxide semiconductor layer 1041 is an indium-rich oxide semiconductor layer, for example, it can be indium gallium zinc oxide (In-rich IGZO) with an indium content higher than gallium content, wherein the atomic percentage of indium is much greater than that of gallium, for example, the indium (In) content is between 60% and 75%. The thickness is controlled in the range of 15 to 30 nanometers, for example, 20 nanometers. DC sputtering is used during deposition, and a small amount of oxygen (e.g., oxygen flow rate of 5%) is introduced to control the oxygen vacancy concentration. Since the conduction band bottom of indium-rich oxide is mainly composed of indium 5s orbitals, which have low effective electron mass and high mobility, this layer enables the active layer 104 to obtain high carrier mobility and large conduction current, providing an efficient conductive path for the channel region.

[0039] Step S220: Deposit the second oxide semiconductor layer 1042.

[0040] The second oxide semiconductor layer 1042 contains dopant elements in indium gallium zinc oxide, and the concentration of the dopant elements increases in the direction away from the first oxide semiconductor layer 1041. For example, the dopant elements can be silicon (Si) and / or tin (Sn), and their concentration gradually increases from approximately 0% on the side of the first oxide semiconductor layer 1041 to about 5% on the side of the third oxide semiconductor layer 1043. The thickness of this layer can be from 5 nanometers to 10 nanometers, for example, 8 nanometers.

[0041] Understandably, the concentration gradient of this layer can be achieved by gradually increasing the power of the silane (SiH4) or tin target during sputtering. Since silicon or tin doping increases the band gap of the oxide semiconductor, and the valence band top and conduction band bottom positions shift accordingly, the gradually increasing doping concentration allows the band structure of this layer to smoothly transition from a narrow band gap on the indium-rich side to a wide band gap on the gallium-rich side, thus forming a gradient bandgap. This gradient bandgap improves the abrupt band shift in heterojunctions in related technologies, reduces carrier scattering and interface states induced by band edge discontinuities at the interface, facilitates efficient carrier transport from the first layer to the channel interface, and suppresses the diffusion of defects such as hydrogen or oxygen vacancies from the outside to the channel region, enhancing the long-term bias stability of the device.

[0042] Step S230: Deposit the third oxide semiconductor layer 1043.

[0043] The third oxide semiconductor layer 1043 is a gallium-rich oxide semiconductor layer, such as gallium indium oxide (Ga-rich IGZO or GaInO) with a gallium content higher than the indium content. x The atomic percentage of gallium can be between 50% and 65%. The thickness is controlled between 3 and 8 nanometers, such as 5 nanometers.

[0044] In some embodiments, aluminum (Al) and / or niobium (Nb) can be tracely doped into the layer at a concentration of about 0.5%. Gallium-rich materials have the following inherent properties: First, gallium-oxygen bonds are strong and chemically stable, thus exhibiting excellent etching resistance in subsequent wet etching, being only slightly thinned without being completely consumed, thus naturally becoming a protective layer for the underlying channel; Second, gallium-rich oxides have a wide optical bandgap, reaching 3.2 eV to 3.5 eV, corresponding to strong absorption of short-wavelength light with wavelengths less than about 470 nanometers. This means that the layer itself has light-shielding function, and photo-induced leakage current and negative threshold voltage drift caused by backlighting can be suppressed without the need for additional metal or black matrix light-shielding layers.

[0045] After the three-layer film deposition is completed, the second photomask process is performed: coating, exposure, and development. Then, the oxide stack is patterned by dry etching (such as Ar / O2 mixed gas). After the resist is removed, the active layer 104 pattern is formed in the predetermined area above the gate 102.

[0046] Step S300: Forming an etch barrier layer 105.

[0047] After patterning the active layer 104, an etch stop layer 105 is deposited on the substrate, such as... Figure 3 As shown. The etching barrier layer 105 can be made of an insulating material resistant to wet etching, such as high-n silicon nitride (high-nSiN). x The active layer 104 is formed using materials such as aluminum oxide (Al2O3) or silicon oxynitride (SiON), with a thickness of approximately 50 to 100 nanometers. Photolithography and dry etching are then performed to pattern the etch barrier layer 105 so that it covers the active layer 104 in the region where the channel region is to be formed, and exposes the active layer 104 in the regions where the source and drain electrodes 107 are to be formed. This etch barrier layer 105 will protect the underlying active layer 104 from erosion during subsequent wet etching.

[0048] It is worth mentioning that, to further reduce contact resistance, an ohmic contact layer 106 can also be formed on the exposed active layer 104 and the etch barrier layer 105, such as... Figure 3 As shown. The ohmic contact layer 106 can be used to deposit silicon nitride (SiN). x The thin film is obtained by N-type heavy doping (such as ion implantation). It is understood that although intrinsic silicon nitride is an insulator, its conductivity is significantly improved after high-concentration doping, transforming it into a semiconductor-like or even conductive state, thus providing a highly conductive transition interface between the source / drain metals and the active layer 104. The introduction of this heavily doped layer helps to isolate moisture and oxygen in subsequent processes, improving the long-term stability of the device.

[0049] In step S400, source and drain metal layers are deposited and a wet etching solution containing defect repair components is used to form source electrode 107 and drain electrode 107.

[0050] Source / drain metal layers are deposited by sputtering on the active layer 104, ohmic contact layer 106, and etch barrier layer 105. These source / drain metal layers can employ a molybdenum / aluminum / molybdenum (Mo / Al / Mo) three-layer structure with a total thickness of approximately 300 nanometers. A third photomask process is then performed: photoresist coating, exposure, and development. Subsequently, a wet etching solution containing defect repair components is used to etch the source / drain metal layers to define the source 107 and drain 107. Figure 3 and Figure 5 As shown.

[0051] It should be noted that this etching solution is a metal etching solution mother solution (such as a phosphoric acid / nitric acid / acetic acid system) with added ammonium fluoride (NH4F) and an organic oxygen donor. The concentration of ammonium fluoride is controlled between 0.1% and 0.5%, and the organic oxygen donor can be an organic solvent containing hydroxyl or carbonyl groups, such as ethylene glycol monomethyl ether acetate (PGMEA). The etching time can be 15 to 20 seconds, allowing approximately 20% over-etching to ensure complete metal isolation. During this etching process, the etching solution first vertically etches the source / drain metal layers until the surfaces of the etching barrier layer 105 and the active layer 104 are exposed. Because the etching barrier layer 105 is etch-resistant, the channel region it covers is adequately protected, preventing the etching solution from eroding the underlying third oxide semiconductor layer 1043, thereby reducing damage to the channel region.

[0052] It is worth noting that after etching the metal and ohmic contact layer 106, a portion of the surface of the active layer 104 (especially in areas not covered by the etching barrier layer 105, including the edge sections of the active layer 104) is exposed. Fluorine ions in the etching solution act as micro-etchers, moderately removing the structurally loose layers of these surfaces; while the organic oxygen donor provides active oxygen in the solution, rapidly diffusing to the exposed surface of the active layer 104, in-situ filling and repairing oxygen vacancy defects caused by previous processes and etching. This simultaneous process is equivalent to performing a self-healing treatment on the affected oxide surface while simultaneously completing the source / drain electrode patterning, passivating the defect states. Therefore, no separate plasma repair or secondary annealing steps are required, simplifying the process flow.

[0053] After etching is completed, the photoresist is removed, and the source electrode 107 and drain electrode 107 are formed. The channel region covered by the etching barrier layer 105 has a complete structure, while the surface of the exposed and repaired active layer 104 has a lower interface defect density.

[0054] Step S500: Perform annealing.

[0055] After forming the source and drain electrodes, the substrate is placed in an annealing furnace containing an oxygen atmosphere (such as oxygen or air) and annealed at a temperature of 250°C to 300°C for approximately 30 minutes. During annealing, interfacial interdiffusion and alloying occur between the source / drain metal and the active layer 104 (or through the ohmic contact layer 106 if present), forming a low-resistance conductive path similar to an ohmic contact, significantly reducing contact resistance. Simultaneously, annealing eliminates residual stress and metastable defects within the active layer 104, further improving channel mobility and reducing off-state current. If the ohmic contact layer 106 is present, annealing also activates its doping elements, improving conductivity.

[0056] In step S600, a passivation layer 109, vias, and pixel electrodes 1100 are formed, completing the fabrication of the driving substrate 100.

[0057] A passivation layer 109 is deposited on the source / drain electrodes and the active layer 104 via PECVD. The passivation layer 109 can be made of silicon nitride (approximately 400 nm thick) to isolate water and oxygen and protect the device. Then, a fourth photomask process is performed: resist coating, exposure, and development. The passivation layer 109 is etched using a gas containing CF4 / O2 to create vias at desired locations (such as above the source 107 or drain 107) to expose the metal surfaces to be connected. Afterwards, an indium tin oxide (ITO) transparent conductive film (approximately 80 nm thick) is sputtered and deposited. A fifth photomask process is then performed to etch and form the pixel electrode 1100, as shown below. Figure 6 As shown, the pixel electrode 1100 is electrically connected to the corresponding source electrode 107 or drain electrode 107 through a via, thereby driving the display pixel.

[0058] Finally, a protective encapsulation layer 108 can be deposited on the panel surface as needed, serving as the outermost protective film for the device to prevent moisture and external contamination, thus completing the encapsulation and protection of the array substrate.

[0059] It should be noted that the above method maintains the number of photomasks in the entire TFT fabrication process at 4 to 5 layers (gate 102, active layer 104, source / drain, passivation via, pixel electrode 1100). The core array circuit can be completed using only the four photomasks excluding the pixel electrode 1100, which still falls within the mainstream 4-mask BCE process. Compared to related solutions that require an additional light-shielding layer (adding one photomask), this method effectively simplifies the number of photomask layers and reduces production costs.

[0060] Example 2 See Figure 6 As shown, the structural features of the driving substrate 100 prepared by the method of Embodiment 1 can be directly derived from the process. The driving substrate 100 may include a substrate 101, a gate 102, a gate insulating layer 103, and an active layer 104.

[0061] The substrate 101 can be made of glass or a flexible substrate 101. The gate 102 is disposed on the substrate 101, and the gate insulating layer 103 (corresponding to the GI layer) covers the gate 102.

[0062] The active layer 104 is disposed on the gate insulating layer 103, and may include a first oxide semiconductor layer 1041, a second oxide semiconductor layer 1042 and a third oxide semiconductor layer 1043 stacked sequentially.

[0063] The first oxide semiconductor layer 1041 is an indium-rich oxide semiconductor layer, such as IGZO with an indium (In) content of 60%–75% and a thickness of 15–30 nanometers, providing the main carrier transport channels. The second oxide semiconductor layer 1042 includes dopant elements (such as silicon (Si) and / or tin (Sn), and the concentration of dopant elements increases from the first oxide semiconductor layer 1041 to the third oxide semiconductor layer 1043, with a thickness of 5–10 nanometers, forming a smooth band transition. The third oxide semiconductor layer 1043 is a gallium-rich oxide semiconductor layer, such as GaInO with a gallium (Ga) content of 50%–65%. x Alternatively, it can be Ga-rich IGZO, and may be doped with Al and / or Nb (approximately 0.5% each), with a band gap of 3.2–3.5 eV and a thickness of 3–8 nanometers, combining etching resistance and short-wavelength light absorption.

[0064] An etch barrier layer 105 covers the channel region of the active layer 104. A source electrode 107 and a drain electrode 107 are disposed on the etch barrier layer 105 and the active layer 104, defining the channel region between them. Outside the coverage area of ​​the etch barrier layer 105, the surface of the active layer 104 (e.g., an edge section) has an oxygen vacancy interface repaired in situ by defect repair components, exhibiting oxygen enrichment and reduced defect state density.

[0065] The ohmic contact layer 106 is located between the etch barrier layer 105 and the source / drain metal and contacts the exposed area of ​​the active layer 104. The passivation layer 109 covers the source / drain metal and the etch barrier layer 105 and has vias; the pixel electrode 1100 is electrically connected to the source electrode 107 or the drain electrode 107 through the vias. The panel surface encapsulation protective layer 108 is located on the outermost side.

[0066] Example 3 See Figure 7As shown in the figures, this application embodiment also provides a display panel, which includes the aforementioned driving substrate 100, driving chip 200, and a display functional layer disposed on the driving substrate 100. For example, for a liquid crystal display panel, the display functional layer includes a liquid crystal layer and a color filter, and the pixel electrode 1100 cooperates with a common electrode to drive liquid crystal molecules; for an organic light-emitting diode (OLED) display panel, the display functional layer includes an anode / cathode and an organic light-emitting layer, and the pixel electrode 1100 can constitute an anode or be electrically connected to an anode.

[0067] The driver chip 200 can be electrically connected to the gate 102 and / or source / drain electrodes on the driver substrate 100 via a flexible circuit board, a flip-chip film, or direct bonding, to provide scan signals and data signals to the driver substrate 100. Because the driver substrate 100 of this application has high carrier mobility, excellent photostability, and low contact resistance, it can be well matched with the high-speed driver chip 200 to achieve high refresh rate (e.g., 144Hz to 240Hz) and high resolution (e.g., 8K) image display, while maintaining low power consumption and long-term operational stability.

[0068] The driving substrate 100 device prepared according to the method of this application, after actual testing, has performance indicators that are compared with those of related technologies, as shown in the table below:

[0069] As can be seen from the table, the introduction of the three-layer gradient active layer 104 and the in-situ repair process has resulted in orders of magnitude improvements in key indicators such as device mobility, off-state current, illumination and bias stability, and contact resistance, without increasing the number of photomasks, and the process complexity is on par with existing mass production processes.

[0070] It is understood that the above-described specific embodiments are merely preferred embodiments of this application and do not limit the patent scope of this invention. Any equivalent structural or step transformations made based on the content of this specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this invention. The specific values, material types, and combinations of doping elements of each technical feature can be adaptively adjusted while satisfying the core inventive concept. For example, the first oxide semiconductor layer 1041 can be other indium-rich oxides such as ITZO (indium tin zinc oxide) in addition to IGZO; the doping elements of the third oxide semiconductor layer 1043 can be tantalum (Ta), hafnium (Hf), etc., in addition to Al and Nb, as long as the bandgap width meets the requirements; the defect repair component in the wet etching solution, the fluoride ion source can also be other soluble fluorides such as hydrogen fluoride (HF), and the organic oxygen donor can be other polyol ethers or oxygen-containing organic solvents. These variations do not depart from the protection spirit of this application.

[0071] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0072] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A method for fabricating a driving substrate, characterized in that, Includes the following steps: A gate is formed on a substrate, and a gate insulating layer is formed on the gate; A first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are sequentially formed on the gate insulating layer to form an active layer; wherein, the first oxide semiconductor layer is an indium-rich oxide semiconductor layer; the second oxide semiconductor layer includes doping elements, and the concentration of the doping elements increases in the direction away from the first oxide semiconductor layer; the third oxide semiconductor layer is a gallium-rich oxide semiconductor layer. An etch barrier layer is formed on the active layer, and the etch barrier layer is patterned so that the etch barrier layer covers the active layer in the area where the channel region is to be formed, and exposes the active layer in the area where the source and drain are to be formed. Deposit source / drain metal layers on the etch barrier layer and the exposed active layer; The source and drain metal layers are etched using a wet etching solution containing defect repair components to form source and drain electrodes; during the etching process, the etching barrier layer prevents the wet etching solution from eroding the active layer below it, and the defect repair components perform in-situ defect repair on the active layer exposed by the etching. Annealing is performed to reduce the contact resistance between the source and drain electrodes and the active layer.

2. The preparation method according to claim 1, characterized in that, The etching barrier layer is an insulating material layer resistant to wet etching.

3. The preparation method according to claim 1, characterized in that, Prior to depositing the source / drain metal layer, the process also includes: An ohmic contact layer is formed on the exposed active layer and the etch barrier layer; the ohmic contact layer is an N-type heavily doped oxide semiconductor layer, and the source / drain metal layer is deposited on the ohmic contact layer.

4. The preparation method according to claim 1, characterized in that, The first oxide semiconductor layer contains indium, gallium, and zinc, with the indium content being higher than the gallium content; the third oxide semiconductor layer contains gallium and indium, with the gallium content being higher than the indium content.

5. The preparation method according to claim 1, characterized in that, The third oxide semiconductor layer has a bandgap of 3.2 eV to 3.5 eV to absorb light with wavelengths less than 470 nm.

6. The preparation method according to claim 4, characterized in that, The third oxide semiconductor layer is also doped with aluminum and / or niobium to adjust the bandgap of the third oxide semiconductor layer to 3.2 eV to 3.5 eV.

7. The preparation method according to claim 1, characterized in that, The doping element includes silicon and / or tin, and the concentration of the doping element increases from 0 to 5%.

8. The preparation method according to claim 1, characterized in that, The defect repair component includes ammonium fluoride and an organic oxygen donor, wherein the concentration of ammonium fluoride in the wet etching solution is 0.1% to 0.5%; and the organic oxygen donor is an organic solvent containing hydroxyl or carbonyl groups.

9. A driving substrate, characterized in that, include: Substrate; A gate is disposed on the substrate; A gate insulating layer covers the gate. An active layer is disposed on the gate insulating layer, and the active layer includes a first oxide semiconductor layer, a second oxide semiconductor layer and a third oxide semiconductor layer stacked sequentially. Etch a barrier layer to cover the channel region of the active layer; A source and a drain are disposed on the active layer, and a channel region is formed between the source and the drain, with the etch barrier layer located above the channel region; The first oxide semiconductor layer is an indium-rich oxide semiconductor layer, the second oxide semiconductor layer includes doping elements, and the concentration of the doping elements increases from the first oxide semiconductor layer to the third oxide semiconductor layer, the third oxide semiconductor layer being a gallium-rich oxide semiconductor layer.

10. A display panel, characterized in that, include: Driver chip; as well as The driving substrate as described in claim 9 is electrically connected to the driving chip.

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