A back contact cell and its preparation method and application

Abstract

The present application relates to the field of photovoltaic cells, and more particularly to a back contact cell and a preparation method and application thereof. The back contact cell, from the front to the back, comprises: a SiNx:H anti-reflection layer, an oxygen-rich SiOx oxygen capture layer, an N-type monocrystalline silicon substrate and a SiO2 tunneling layer which are sequentially stacked; the SiO2 tunneling layer has phosphorus-doped n + polysilicon layer and a boron-doped p + polysilicon layer; a gradient oxygen-rich SiOx tunneling layer is arranged between the boron-doped p + polysilicon layer and the SiO2 tunneling layer. The back contact cell can effectively fix interstitial oxygen atoms in a high-oxygen silicon wafer and reduce interface recombination, and realizes comprehensive improvement of open-circuit voltage, short-circuit current and fill factor of the cell under the premise of adapting to low-cost high-oxygen silicon wafers.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cells, and more specifically, to a back contact cell, its preparation method, and its application. Background Technology

[0002] Back-contact (BC) crystalline silicon solar cells place both positive and negative electrodes entirely on the back of the cell, completely eliminating light-shielding losses from the front-side metal grid lines. Compared to PERC and TOPCon cells, they offer higher photoelectric conversion efficiency and better uniformity. To further reduce photovoltaic cell manufacturing costs, the industry is gradually adopting low-cost, high-oxygen Czochralski-grown N-type monocrystalline silicon wafers to replace traditional low-oxygen N-type silicon wafers. High-oxygen silicon wafers have lower raw material costs and better mass production yield stability, giving them advantages for large-scale industrialization. However, high-oxygen silicon wafers contain a large number of interstitial oxygen atoms and native oxygen precipitation defects. During the high-temperature oxidation, annealing, and metallization processes, these oxygen defects easily diffuse to the silicon wafer surface and interface, forming high-density minority carrier recombination centers. Conventional BC cell structures are not designed to accommodate the inherent defects of high-oxygen silicon wafers, generally resulting in high interface recombination, severe lateral leakage, and significant long-term light decay, severely restricting the mass production efficiency and service stability of high-oxygen silicon-based BC cells.

[0003] The overall structure of the flat laser-isolated tunneling back contact (TBC) solar cell is as follows: a low-oxygen N-type monocrystalline silicon wafer is used as the substrate, with only a single layer of SiNx:H passivation and antireflection layer on the front side of the wafer; a uniformly thick ultrathin SiO2 tunneling layer is fabricated over the entire back side of the wafer, with n-type silicon cells arranged alternately at equal intervals on the tunneling layer. + Polycrystalline silicon electron collection region and p + Polycrystalline silicon hole collection region; adjacent n + Polycrystalline silicon region and p + Physical isolation between polycrystalline silicon regions is achieved by vertically straight rectangular laser grooving. The isolation grooves are rectangular structures with equal width at the top and bottom. Lateral conductivity is blocked only by mechanically cutting the polycrystalline silicon conductive layer. The back P / N doped collection region uses the same homogeneous tunneling oxide layer without partitioned differential passivation design. The isolation grooves only achieve physical isolation function and do not have defect passivation, oxygen capture and thermal stress buffering structures.

[0004] This existing technology is only suitable for the mass production of low-oxygen N-type silicon wafers. When directly applied to the fabrication of BC cells using high-oxygen N-type silicon wafers, it suffers from many unavoidable technical defects, as follows: (1) High oxygen silicon wafers suffer severe interface recombination losses. Existing technologies lack targeted oxygen capture and passivation structures. During the high-temperature fabrication process, a large number of interstitial oxygen atoms diffuse outward from the interior of the high oxygen silicon wafer, forming a large number of oxygen vacancies and oxygen precipitation recombination centers at the interface between the silicon substrate and polycrystalline silicon. This significantly increases the interface state density and causes a surge in minority carrier recombination rate, directly resulting in a substantial decrease in the open-circuit voltage of the battery and a significant reduction in photoelectric conversion efficiency.

[0005] (2) There is a structural contradiction in the flat rectangular isolation trench. The traditional rectangular isolation trench with equal width at the top and bottom cannot achieve both low leakage current and high light-receiving area: reducing the trench width can easily lead to residual doped polysilicon at the laser etching edge, which forms a local conductive channel after high-temperature sintering, causing lateral leakage current in the P / N region and reducing the mass production yield; increasing the trench width can suppress leakage current, but it will significantly reduce the effective carrier collection area, increase the battery series resistance, and reduce the fill factor and output efficiency.

[0006] (3) Passivation layer thermal mismatch, resulting in poor long-term stability. The thermal expansion coefficient of high-oxygen silicon wafers is higher than that of traditional low-oxygen silicon wafers. Existing technologies use a uniform single-layer tunneling oxide layer, which has poor thermal stress adaptability. After multiple high-temperature processes, microcracks are easily generated in the tunneling layer. Metal slurry ions penetrate along the cracks to the silicon substrate, forming local flow channels, which leads to higher annual light decay of the battery and a significant reduction in outdoor service life.

[0007] (4) Poor carrier transport adaptability, photoelectric performance cannot be maximized. The existing P / N collection region uses a tunneling layer with a uniform structure, which cannot differentiate the tunneling barrier according to the transport characteristics of electrons and holes. The hole transport region has an excessively high barrier and serious recombination, which cannot adapt to the carrier movement characteristics of high oxygen silicon wafers. The battery short-circuit current and fill factor have inherent losses.

[0008] In view of this, the present invention is hereby proposed. Summary of the Invention

[0009] To address the inherent technical shortcomings of existing flat laser-isolated TBC solar cells, this invention aims to adapt to the mass production of low-cost, high-oxygen N-type monocrystalline silicon wafers and solve the following four core technical problems: 1. Solve the problem of high interfacial recombination induced by oxygen defects in high-oxygen silicon wafers. Overcome the defects of existing oxygen-free trapping structures, eliminate recombination centers formed by interstitial oxygen and oxygen precipitates, reduce interfacial state density, suppress silicon wafer bulk recombination and interfacial recombination, and improve the open-circuit voltage and photoelectric conversion efficiency of the battery.

[0010] 2. Resolves the structural contradiction between leakage current and effective light-receiving area in traditional flat isolation slots. Abandoning the rectangular isolation structure with equal width at the top and bottom, a gradient wedge isolation design is adopted to completely block lateral leakage current in the P / N region while retaining sufficient effective carrier collection area, thus balancing the battery's low leakage current characteristics and high output performance.

[0011] 3. Solve the problem of thermal mismatch in the passivation layer and long-term light decay of the battery. Address the issues of thermal expansion mismatch between the homogeneous tunneling layer and the high-oxygen silicon wafer, easy cracking at high temperatures, and metal ion penetration and shunting. Optimize the interfacial thermal stress adaptability, significantly reduce the long-term battery degradation rate, and improve the battery's stability during outdoor service.

[0012] 4. Solve the problem of poor carrier transport adaptability in the P / N region. Overcome the limitations of existing global homogeneous tunneling layers, achieve differentiated barrier control in the electron and hole regions, match the transport characteristics of different carriers, reduce carrier recombination losses, and comprehensively improve the battery short-circuit current and fill factor.

[0013] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: A back-contact battery, from front to back, includes: a SiNx:H antireflection layer, an oxygen-rich SiOx oxygen trapping layer, an N-type single-crystal silicon substrate, and a SiO2 tunneling layer stacked sequentially. The SiO2 tunneling layer has phosphorus doped n particles arranged at alternating intervals. + Polycrystalline silicon layer and boron-doped p + Polycrystalline silicon layer; the boron-doped p + A gradient oxygen-rich SiOx tunneling stack is disposed between the polycrystalline silicon layer and the SiO2 tunneling layer.

[0014] A method for preparing the back contact battery includes the following steps: (a) An oxygen-rich SiOx oxygen trapping layer and a SiNx:H antireflection layer are sequentially deposited on the front side of an N-type single-crystal silicon substrate; (b) A tunneling SiOx layer is grown on the back side of the N-type single-crystal silicon substrate; phosphorus-doped n is deposited on the tunneling SiOx layer. + Polycrystalline silicon layer and boron-doped p + Polycrystalline silicon layer; (c) The phosphorus doping n + The polycrystalline silicon layer and the boron-doped p + Etching is performed at the junction of the polycrystalline silicon layers, in the phosphorus-doped n + The polycrystalline silicon layer and the boron-doped p + An isolation region is formed between the polysilicon layers; (d) For the boron-doped p + The polycrystalline silicon layer undergoes plasma oxidation treatment, and the boron-doped p-layer is then subjected to this process. + A gradient oxygen-rich SiOx tunneling stack is formed between the polycrystalline silicon layer and the tunneling SiOx layer; (e) Sintering.

[0015] A photovoltaic module, including the back contact cell described herein.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention, through structural innovation, material system innovation, and process innovation, fundamentally solves the technical shortcomings of existing flat-isolated TBC batteries that cannot be adapted to high-oxygen silicon wafers, and has the following five outstanding advantages: 1. Adapted to low-cost, high-oxygen silicon wafers, significantly improving conversion efficiency. This invention utilizes a multi-layer oxygen capture and passivation system to effectively adsorb and passivate oxygen defects in high-oxygen silicon wafers, drastically reducing the interface state density and significantly suppressing interface-bulk recombination. This results in a 7-10mV increase in open-circuit voltage and a 0.45%-0.6% improvement in mass production conversion efficiency compared to existing technologies, significantly enhancing battery output performance while reducing raw material costs.

[0017] 2. Completely resolves the inherent contradictions of the isolation structure, resulting in higher mass production yield. Adopting a wedge-shaped isolation structure that is wider at the top and narrower at the bottom, the narrow bottom of the tank completely cuts off the lateral conductive path, eliminating leakage in the P / N area; the wide top of the tank buffers high-temperature thermal stress, eliminating the need to reduce the effective light-receiving area. This completely solves the problem of the traditional rectangular tank's inability to balance leakage and efficiency, reducing battery leakage failure rate by 6%~9% and significantly improving mass production yield.

[0018] 3. Precise control of the zoned potential barrier results in superior carrier transport efficiency. The tunneling layer structure is designed differently for the transport characteristics of electrons and holes. The low potential barrier in the electron region ensures high-speed transport, while the oxygen-rich passivation in the hole region reduces recombination losses. This perfectly matches the carrier movement pattern of the high-oxygen silicon wafer, resulting in a simultaneous improvement in the battery's short-circuit current and fill factor.

[0019] 4. Excellent thermal stability and significantly reduced long-term light decay. The wedge-shaped inclined sidewalls can adaptively buffer the thermal deformation of the high-oxygen silicon wafer, and the gradient passivation layer eliminates thermal mismatch microcracks and prevents metal ion penetration and shunting. The annual long-term light decay of the battery is ≤0.4%, which is more than 50% lower than the existing technology, and significantly extends the battery's outdoor service life.

[0020] 5. Excellent mass production compatibility and low industrialization cost. This invention reuses existing picosecond laser, ALD, and PECVD equipment for BC battery mass production throughout the entire process. No new large-scale production lines are required. Only laser etching parameters and passivation processes are optimized, resulting in low modification costs. It can be directly adapted to the large-scale mass production of 182 / 210mm large-size silicon wafers, making it highly feasible to implement. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the back contact battery structure. Detailed Implementation

[0023] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, but not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall be followed. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0024] One aspect of the present invention relates to a back contact battery, such as Figure 1 As shown, from the front to the back, it includes: a SiNx:H antireflection layer, an oxygen-rich SiOx oxygen trapping layer, an N-type single crystal silicon substrate, and a SiO2 tunneling layer stacked sequentially. The SiO2 tunneling layer has phosphorus doped n particles arranged at alternating intervals. + Polycrystalline silicon layer and boron-doped p + Polycrystalline silicon layer; The boron-doped p + A gradient oxygen-rich SiOx tunneling stack is disposed between the polycrystalline silicon layer and the SiO2 tunneling layer.

[0025] The aforementioned back-contact battery features a double-layer passivation structure on the front side, consisting of a SiNx:H antireflection layer and an oxygen-rich SiOx oxygen-capturing layer. On the back side, a gradient oxygen-rich SiOx tunneling stack is positioned between the p-type hole collection region and the SiO2 tunneling layer, constructing an oxygen-capturing passivation system spanning both sides. This effectively adsorbs and immobilizes interstitial oxygen atoms in the high-oxygen silicon wafer, reducing interface state density, suppressing bulk and interface recombination, and improving the battery's open-circuit voltage and photoelectric conversion efficiency. This invention retains a homogeneous thin SiO2 tunneling layer in the electron collection region and sets a gradient oxygen-rich SiOx tunneling stack in the hole collection region, achieving differentiated barrier control in different zones. The electron region maintains a low tunneling barrier to ensure high-speed electron transport, while the hole region is oxygen-rich and passivated to reduce hole recombination losses, which is beneficial for improving the battery's short-circuit current and fill factor.

[0026] SiNx:H refers to hydrogenated amorphous silicon nitride.

[0027] Furthermore, the front side of the N-type single-crystal silicon substrate has a micron-scale pyramid texturing structure to ensure efficient absorption of sunlight. The front micron-scale pyramid texturing structure is formed through alkaline texturing, followed by acid-alkali cleaning and drying to remove surface impurities and mechanical damage layers, ensuring the cleanliness of the silicon wafer surface.

[0028] Furthermore, the thickness of the oxygen-rich SiOx oxygen trapping layer is 2~4nm (for example, it can be a point value of any one of 2nm, 3nm or 4nm or a range of any two values), which can adsorb interstitial oxygen atoms overflowing from the silicon wafer and suppress the generation of oxygen defect recombination centers.

[0029] Furthermore, the thickness of the SiNx:H antireflection layer is 70~90nm (for example, it can be a point value or a range of any one of 70nm, 75nm, 80nm, 85nm or 90nm, for example, or any two of them). This layer has passivation, antireflection and moisture protection functions, which greatly reduces the recombination rate of the front surface.

[0030] Furthermore, the N-type single-crystal silicon substrate has an oxygen content of 12-18 ppma (for example, it can be any one of 12 ppma, 14 ppma, 16 ppma or 18 ppma or any range between two), a thickness of 130-150 μm (for example, it can be any one of 130 μm, 135 μm, 140 μm, 145 μm or 150 μm or any range between two), phosphorus doping, high minority carrier mobility, and is suitable for low-cost mass production.

[0031] Furthermore, the N-type single-crystal silicon substrate includes: an N-type Czochralski single-crystal silicon wafer.

[0032] Furthermore, the thickness of the SiO2 tunneling layer is 1.0~1.5nm (for example, it can be a point value or a range between any one of 1.0nm, 1.1nm, 1.2nm, 1.4nm or 1.5nm, for example, to ensure the overall passivation uniformity of the substrate and provide a basic barrier for carrier tunneling transport).

[0033] Furthermore, the phosphorus doping n + The thickness of the polycrystalline silicon layer (electron collection unit) is 80~120nm (for example, it can be any point value or any range between 80nm, 90nm, 100nm, 110nm or 120nm, for example, it can be any point value or any range between two of them), and it is paired with a homogeneous low oxygen tunneling layer to reduce the electron tunneling barrier and improve the electron transport efficiency.

[0034] Furthermore, the boron-doped p + The thickness of the polysilicon layer (hole collection unit) is 90~130nm (for example, it can be a point value or a range of any one of 90nm, 100nm, 110nm, 120nm or 130nm, or any two of them).

[0035] Furthermore, the thickness of the gradient oxygen-rich SiOx tunneling stack is 1.8~2.5 nm (e.g., it can be any value or a range between any two of 1.8 nm, 2.0 nm, 2.3 nm, or 2.5 nm, for example), and the atomic ratio of O to Si is 1.3~1.5 (e.g., it can be any value or a range between any two of 1.3, 1.4, or 1.5, for example), which can accurately capture interfacial oxygen defects and significantly reduce hole recombination loss. Using n + Homogeneous thin tunneling layer in electron region, p + The asymmetric passivation structure of the gradient oxygen-rich SiOx stack in the hole region enables precise passivation of oxygen defects through an oxygen-rich layer with an O / Si atomic ratio of 1.3 to 1.5, thereby achieving differentiated control of the carrier barrier.

[0036] Furthermore, the adjacent phosphorus doped n + The polycrystalline silicon layer and the boron-doped p + Wedge-shaped isolation trenches are provided between the polycrystalline silicon layers, through which phosphorus doping n is applied. + Polycrystalline silicon layer and boron-doped p + The polycrystalline silicon layers are spaced apart.

[0037] Furthermore, the wedge-shaped isolation groove has a bottom width of 10-15 μm (e.g., it can be any one of 10 μm, 13 μm, or 15 μm, or a range between any two), a top width of 30-40 μm (e.g., it can be any one of 30 μm, 33 μm, 35 μm, 38 μm, or 40 μm, or a range between any two), and a sidewall inclination angle of 12°-18° (e.g., it can be any one of 12°, 14°, 16°, or 18°, or a range between any two). The wedge-shaped isolation groove achieves multiple functions including insulation isolation, thermal stress buffering, and defect passivation.

[0038] Furthermore, an Al-doped SiO2 insulating layer is provided on the inner wall of the wedge-shaped isolation groove.

[0039] Furthermore, the thickness of the Al-doped SiO2 insulating layer is 5~8nm (for example, it can be a point value of any one of 5nm, 6nm, 7nm or 8nm or a range of any two).

[0040] Furthermore, the amount of Al doping in the Al-doped SiO2 insulating layer is 3wt% to 5wt% (for example, it can be any one of 3wt%, 4wt%, or 5wt%, or a range between any two).

[0041] An oxygen-capturing insulating layer of SiO2 with an Al doping mass fraction of 3%~5% and a thickness of 5~8nm is set on the inner wall of the wedge-shaped isolation groove. Combining field passivation and oxygen atom adsorption mechanism, the problem of interface recombination of high oxygen silicon wafers is solved from the root.

[0042] Unlike traditional rectangular trenches, wedge-shaped isolation trenches have a wedge-shaped cross-section that is wider at the top and narrower at the bottom. These trenches can completely cut off the lateral conductive path in the P / N region, preventing leakage, and can also buffer high-temperature thermal stress through their inclined sidewalls, while simultaneously achieving oxygen capture and passivation. Using ALD atomic layer deposition technology, an Al-doped SiO2 insulating layer is uniformly prepared on the inner wall of the wedge-shaped isolation trench, achieving physical isolation, field passivation, and oxygen atom capture functions simultaneously.

[0043] Furthermore, the phosphorus doping n + The polycrystalline silicon layer and the boron-doped p + Metal electrodes are disposed on the polycrystalline silicon layer. Contact holes are selectively formed on the top of the electron collection unit and the hole collection unit, and silver-aluminum composite grid lines are printed to achieve conductive output. The isolation area has no metal covering to ensure insulation effect.

[0044] Another aspect of the present invention relates to a method for preparing the aforementioned back contact battery, comprising the following steps: (a) Using a PECVD device, an oxygen-rich SiOx oxygen trapping layer and a SiNx:H antireflection layer are sequentially deposited on the front side of an N-type single-crystal silicon substrate to complete the passivation and antireflection protection of the front side defects; (b) A tunneling SiOx layer is grown on the back side of the N-type single-crystal silicon substrate by a high-temperature thermal oxidation process; subsequently, phosphorus-doped n-type silicon is deposited on the tunneling SiOx layer in situ in sections. + Polycrystalline silicon layer and boron-doped p + A polycrystalline silicon layer forms the initial carrier collection layer on the back side; (c) The phosphorus doping n + The polycrystalline silicon layer and the boron-doped p + Etching is performed at the junction of the polycrystalline silicon layers, in the phosphorus-doped n + The polycrystalline silicon layer and the boron-doped p + An isolation region is formed between the polysilicon layers; (d) For the boron-doped p + The polycrystalline silicon layer undergoes plasma oxidation treatment, and the boron-doped p-layer is then subjected to this process. + A gradient oxygen-rich SiOx tunneling stack is formed between the polycrystalline silicon layer and the tunneling SiOx layer; (e) Sintering.

[0045] The aforementioned method for fabricating back-contact solar cells utilizes existing picosecond laser, atomic layer deposition, and plasma-enhanced chemical vapor deposition equipment found in BC solar cell mass production lines. Only adjustments to the laser etching energy parameters and plasma oxidation modification process conditions are required; no new large-scale production line equipment is needed. This method is directly adaptable to large-scale production of large-size silicon wafers, resulting in low modification costs and strong industrialization feasibility. It is perfectly compatible with the mass production of 12-18 ppma high-oxygen N-type silicon wafers, achieving a balance of high efficiency, high yield, and high stability.

[0046] Furthermore, a shaped elliptical picosecond pulse laser is used along the phosphorus-doped n... + The polycrystalline silicon layer and the boron-doped p + Gradient energy etching is performed at the interface of the polycrystalline silicon layer. Utilizing the gradient attenuation characteristic of laser energy from top to bottom, a wedge-shaped isolation trench, wider at the top and narrower at the bottom, is etched, completely penetrating the polycrystalline silicon layer without any doping residue or thermal damage. A picosecond-shaped beam gradient energy etching process is employed to achieve integrated molding of the wedge-shaped isolation trench without residue or thermal damage, adapting to the high-temperature processing characteristics of high-oxygen silicon wafers.

[0047] Further, the parameters of the plasma oxidation treatment include: radio frequency power of 80~120W (e.g., any one of 80W, 90W, 100W, 110W or 120W or a range between any two), chamber pressure of 0.15~0.30mbar (e.g., any one of 0.15mbar, 0.20mbar, 0.25mbar or 0.30mbar or a range between any two), and O2 gas flow rate of 80~150sccm (e.g., 80sccm, 90sccm or ... The processing time is 40 to 70 seconds (e.g., any one of 100 sccm, 110 sccm, 120 sccm, 130 sccm, 140 sccm or 150 sccm, or any range between two of these values), the substrate temperature is 220 to 280°C (e.g., any one of 220°C, 230°C, 240°C, 250°C, 260°C, 270°C or 280°C, or any range between two of these values), and the processing time is 40 to 70 seconds (e.g., any one of 40 seconds, 50 seconds, 60 seconds or 70 seconds, or any range between two of these values).

[0048] Phosphorus doping n + The polycrystalline silicon layer is not modified, and a homogeneous thin tunneling layer is retained to achieve differentiated passivation and barrier modulation in the P / N region.

[0049] Furthermore, the sintering temperature is 420~460℃ (for example, it can be any value or a range between any two of 420℃, 430℃, 440℃, 450℃, or 460℃), and the time is 25~40min (for example, it can be any value or a range between any two of 25min, 30min, 35min, or 40min). Sintering and solidifying the electrode at a low temperature eliminates printing stress, improves electrode adhesion and conductivity, and ultimately produces a high-efficiency, high-stability high-oxygen silicon-based BC battery.

[0050] Furthermore, by selectively creating metal contact holes using lasers to precisely correspond to the P / N collection areas, silver-aluminum composite grid lines are screen-printed to form a conductive electrode pattern on the back side.

[0051] Another aspect of the invention relates to a photovoltaic module including the aforementioned back contact battery.

[0052] The embodiments of the present invention will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of the invention. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer are followed. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0053] Example 1 The back contact battery provided in this embodiment includes, from the front to the back, a SiNx:H antireflection layer, an oxygen-rich SiOx oxygen trapping layer, an N-type single crystal silicon substrate, and a SiO2 tunneling layer stacked sequentially. The SiO2 tunneling layer has alternating phosphorus doping n + Polycrystalline silicon layer and boron-doped p + Polycrystalline silicon layer; boron-doped p + A gradient oxygen-rich SiOx tunneling stack is disposed between the polycrystalline silicon layer and the SiO2 tunneling layer; The front side of the N-type single-crystal silicon substrate has a micron-scale pyramid texturing light-trapping structure with an oxygen content of 16 ppma and a thickness of 140 μm. The thickness of the oxygen-rich SiOx oxygen trapping layer is 3 nm; the thickness of the SiNx:H antireflection layer is 80 nm; the thickness of the SiO2 tunneling layer is 1.3 nm; and the thickness of the phosphorus-doped n... + The polycrystalline silicon layer is 100 nm thick; boron-doped p + The thickness of the polycrystalline silicon layer is 110 nm; The thickness of the gradient oxygen-rich SiOx tunneling stack is 2.0 nm, and the atomic ratio of O to Si is 1.4. Adjacent phosphorus doping n + Polycrystalline silicon layer and boron-doped p+ Wedge-shaped isolation trenches are provided between the polycrystalline silicon layers, through which phosphorus doping n is applied. + Polycrystalline silicon layer and boron-doped p + The polycrystalline silicon layers are spaced apart; The wedge-shaped isolation trench has a bottom width of 13 μm, a top width of 35 μm, and a sidewall inclination angle of 14°. An Al-doped SiO2 insulating layer is deposited on the inner wall of the wedge-shaped isolation trench. The thickness of the Al-doped SiO2 insulating layer is 6 nm, and the Al doping content in the Al-doped SiO2 insulating layer is 4 wt%. Phosphorus doping n + Polycrystalline silicon layer and boron-doped p + Metal electrodes are disposed on the polycrystalline silicon layer.

[0054] The method for preparing a back contact battery provided in this embodiment includes the following steps: S1. High-oxygen N-type monocrystalline silicon wafers are texturized with alkali to form a front-side micron pyramid light-trapping structure, and then surface impurities and mechanical damage layers are removed by acid and alkali cleaning and drying.

[0055] S2. Using PECVD equipment, an oxygen-rich SiOx oxygen trapping layer and a SiNx:H anti-reflection passivation layer are sequentially deposited on the front side of the silicon wafer.

[0056] S3. A basic ultrathin tunneling SiOx layer is grown on the back side of the silicon wafer using a high-temperature thermal oxidation process, followed by in-situ deposition of phosphorus-doped n in sections. + Polycrystalline silicon layer, boron-doped p + Polycrystalline silicon layer.

[0057] S4. Employs a picosecond pulse laser with a shaped elliptical spot, along the phosphorus-doped n... + Polycrystalline silicon layer and boron-doped p + Gradient energy etching is performed at the junction of the polysilicon layers to form a wedge-shaped isolation trench that is wider at the top and narrower at the bottom, completely penetrating the polysilicon layers.

[0058] S5. Using ALD atomic layer deposition process, an Al-doped SiO2 insulating layer is uniformly prepared on the inner wall of the wedge-shaped isolation groove.

[0059] S6, boron-doped p + The polycrystalline silicon layer undergoes plasma oxidation treatment. The parameters for plasma oxidation treatment include: RF power of 100W, chamber pressure of 0.25mbar, O2 gas flow rate of 120sccm, substrate temperature of 250℃, and treatment time of 60s, to generate a gradient oxygen-rich SiOx tunneling stack.

[0060] S7. Electrode preparation.

[0061] S8. Sintering at 440℃ for 35 minutes.

[0062] Example 2 The back contact battery provided in this embodiment has the same structure as that in Embodiment 1, with the following differences: The front side of the N-type single-crystal silicon substrate has a micron-scale pyramid texturing light-trapping structure with an oxygen content of 12 ppma and a thickness of 130 μm. The thickness of the oxygen-rich SiOx oxygen trapping layer is 2 nm; the thickness of the SiNx:H antireflection layer is 70 nm; the thickness of the SiO2 tunneling layer is 1.0 nm; and the thickness of the phosphorus-doped n... + The polycrystalline silicon layer is 80 nm thick; boron-doped p + The thickness of the polycrystalline silicon layer is 90 nm; The thickness of the gradient oxygen-rich SiOx tunneling stack is 1.8 nm, and the atomic ratio of O to Si is 1.3. Adjacent phosphorus doping n + Polycrystalline silicon layer and boron-doped p + Wedge-shaped isolation trenches are provided between the polycrystalline silicon layers, through which phosphorus doping n is applied. + Polycrystalline silicon layer and boron-doped p + The polycrystalline silicon layers are spaced apart; The wedge-shaped isolation groove has a bottom width of 10 μm, a top width of 30 μm, and a sidewall inclination angle of 12°. An Al-doped SiO2 insulating layer is disposed on the inner wall of the wedge-shaped isolation groove. The thickness of the Al-doped SiO2 insulating layer is 5 nm, and the Al doping amount in the Al-doped SiO2 insulating layer is 3 wt%.

[0063] The preparation process is the same as in Example 1, with the following differences: The parameters for plasma oxidation treatment include: RF power of 80W, chamber pressure of 0.15mbar, O2 gas flow rate of 80sccm, substrate temperature of 220℃, and treatment time of 40s.

[0064] Example 3 The back contact battery provided in this embodiment has the same structure as that in Embodiment 1, with the following differences: The front side of the N-type single-crystal silicon substrate has a micron-scale pyramid texturing light-trapping structure with an oxygen content of 18 ppma and a thickness of 150 μm. The thickness of the oxygen-rich SiOx oxygen trapping layer is 4 nm; the thickness of the SiNx:H antireflection layer is 90 nm; the thickness of the SiO2 tunneling layer is 1.5 nm; and the thickness of the phosphorus-doped n... + The polycrystalline silicon layer is 120 nm thick; boron-doped p + The thickness of the polycrystalline silicon layer is 130 nm; The thickness of the gradient oxygen-rich SiOx tunneling stack is 2.5 nm, and the atomic ratio of O to Si is 1.5. Adjacent phosphorus doping n +Polycrystalline silicon layer and boron-doped p + Wedge-shaped isolation trenches are provided between the polycrystalline silicon layers, through which phosphorus doping n is applied. + Polycrystalline silicon layer and boron-doped p + The polycrystalline silicon layers are spaced apart; The wedge-shaped isolation groove has a bottom width of 15 μm, a top width of 40 μm, and a sidewall inclination angle of 18°. An Al-doped SiO2 insulating layer is disposed on the inner wall of the wedge-shaped isolation groove. The thickness of the Al-doped SiO2 insulating layer is 8 nm, and the Al doping amount in the Al-doped SiO2 insulating layer is 5 wt%.

[0065] The preparation process is the same as in Example 1, with the following differences: The parameters for plasma oxidation treatment include: RF power of 120W, chamber pressure of 0.30mbar, O2 gas flow rate of 150sccm, substrate temperature of 280℃, and treatment time of 70s.

[0066] Comparative Example 1 The only difference between this comparative example and Example 1 is the boron doping p. + No gradient oxygen-rich SiOx tunneling stack was set between the polycrystalline silicon layer and the SiO2 tunneling layer.

[0067] Comparative Example 2 The only difference between this comparative example and Example 1 is that the atomic ratio of O to Si in the gradient oxygen-rich SiOx tunneling stack is 2.

[0068] Comparative Example 3 The only difference between this comparative example and Example 1 is that the wedge-shaped isolation groove is replaced with a rectangular isolation groove with a width of 15μm.

[0069] Comparative Example 4 The only difference between this comparative example and Example 1 is that the Al-doped SiO2 insulating layer is not provided on the inner wall of the wedge-shaped isolation groove.

[0070] Table 1

[0071] Although the present invention has been illustrated and described with specific embodiments, it should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; those skilled in the art should understand that modifications can be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein, without departing from the spirit and scope of the present invention; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A back-contact battery, characterized in that, From the front to the back, it includes: a SiNx:H antireflection layer, an oxygen-rich SiOx oxygen trapping layer, an N-type single crystal silicon substrate, and a SiO2 tunneling layer stacked sequentially; The SiO2 tunneling layer has phosphorus doped n particles arranged at alternating intervals. + Polycrystalline silicon layer and boron-doped p + Polycrystalline silicon layer; The boron-doped p + A gradient oxygen-rich SiOx tunneling stack is disposed between the polycrystalline silicon layer and the SiO2 tunneling layer.

2. The back contact battery according to claim 1, characterized in that, The oxygen content of the N-type single-crystal silicon substrate is 12~18 ppma.

3. The back contact battery according to claim 1, characterized in that, The thickness of the gradient oxygen-rich SiOx tunneling stack is 1.8~2.5 nm, and the atomic ratio of O to Si is 1.3~1.

5.

4. The back contact battery according to claim 1, characterized in that, The adjacent phosphorus doped n + The polycrystalline silicon layer and the boron-doped p + Wedge-shaped isolation grooves are provided between the polycrystalline silicon layers.

5. The back contact battery according to claim 4, characterized in that, The wedge-shaped isolation groove has a bottom width of 10~15μm, a top width of 30~40μm, and a sidewall inclination angle of 12°~18°.

6. The back contact battery according to claim 5, characterized in that, An Al-doped SiO2 insulating layer is provided on the inner wall of the wedge-shaped isolation groove.

7. The back contact battery according to claim 6, characterized in that, The thickness of the Al-doped SiO2 insulating layer is 5~8 nm; And / or, the amount of Al doping in the Al-doped SiO2 insulating layer is 3wt%~5wt%.

8. The method for preparing a back contact battery according to any one of claims 1 to 7, characterized in that, Includes the following steps: (a) An oxygen-rich SiOx oxygen trapping layer and a SiNx:H antireflection layer are sequentially deposited on the front side of an N-type single-crystal silicon substrate; (b) A tunneling SiOx layer is grown on the back side of the N-type single-crystal silicon substrate; phosphorus-doped n is deposited on the tunneling SiOx layer. + Polycrystalline silicon layer and boron-doped p + Polycrystalline silicon layer; (c) The phosphorus doping n + The polycrystalline silicon layer and the boron-doped p + Etching is performed at the junction of the polycrystalline silicon layers, in the phosphorus-doped n + The polycrystalline silicon layer and the boron-doped p + An isolation region is formed between the polysilicon layers; (d) For the boron-doped p + The polycrystalline silicon layer undergoes plasma oxidation treatment, and the boron-doped p-layer is then subjected to this process. + A gradient oxygen-rich SiOx tunneling stack is formed between the polycrystalline silicon layer and the tunneling SiOx layer; (e) Sintering.

9. The method for preparing a back contact battery according to claim 8, characterized in that, The parameters for the plasma oxidation treatment include: radio frequency power of 80~120W, chamber pressure of 0.15~0.30mbar, O2 gas flow rate of 80~150sccm, substrate temperature of 220~280℃, and treatment time of 40~70s.

10. A photovoltaic module, characterized in that, Includes the back contact battery as described in any one of claims 1 to 7.

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