A photovoltaic cell and method of manufacture, photovoltaic module and photovoltaic system

Abstract

This application relates to the field of photovoltaic cell technology, and discloses a photovoltaic cell and its fabrication method, photovoltaic module, and photovoltaic system. The cell includes: a substrate, which has a front side and a back side disposed opposite to each other along the thickness direction of the cell; in a first direction, the back side of the substrate has an alternately distributed first region and a second region, with an isolation region between the first region and the second region; the first region and the second region have opposite polarities, and the second region includes at least a first dielectric layer, an N-type doped polycrystalline silicon layer, and a second dielectric layer in a direction away from the substrate; a first electrode located in the first region; and a second electrode located in the second region. The second dielectric layer in the N-region can block the diffusion of metal ions to the N-type doped polycrystalline silicon layer and the first dielectric layer during the fabrication of the second electrode, reducing metal-induced recombination, reducing leakage risk, and improving cell reliability and long-term service stability.

Description

Technical Field

[0001] This application relates to the field of photovoltaic cell technology, and more specifically, to a photovoltaic cell and its preparation method, a photovoltaic module and a photovoltaic system. Background Technology

[0002] A back-contact (BC) photovoltaic cell is a type of photovoltaic cell where all the structures, including the positive and negative electrodes and the PN junction, are located on the back of the cell, with no grid lines obstructing the front. Because the front of the cell is unobstructed, it maximizes the use of incident light, reduces optical losses, and improves the cell's conversion efficiency. Furthermore, the absence of grid lines on the front of the cell creates a uniform black appearance, making the cell more aesthetically pleasing.

[0003] The back of a BC battery contains a P-region, an N-region, and an isolation region located between the P-region and the N-region. The isolation region is a trench. Residual metal impurities and diffusion byproducts in the P-region, N-region, and isolation region will seriously degrade the passivation performance and yield of the battery. Wet cleaning after the texturing process affects the appearance of the BC battery's EL (Electroluminescence) and conversion efficiency.

[0004] In existing technologies, the N-region of back-contact batteries has an oxide layer and a doped polycrystalline silicon layer. The electrodes in the N-region are in direct contact with the doped polycrystalline silicon layer, resulting in a high risk of leakage and poor battery stability.

[0005] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention

[0006] This application provides a photovoltaic cell and its preparation method, a photovoltaic module and a photovoltaic system, which reduce the risk of leakage and improve the stability of the cell.

[0007] In a first aspect, a photovoltaic cell is provided, comprising: The substrate has a front side and a back side disposed opposite to each other along the thickness direction of the cell; in a first direction, the back side of the substrate is provided with an alternately distributed first region and a second region, and an isolation region is provided between the first region and the second region; the first region and the second region have opposite polarities, and the second region includes at least a first dielectric layer, an N-type doped polysilicon layer and a second dielectric layer in the direction away from the substrate from the substrate. The first electrode is located in the first region; The second electrode is located in the second region.

[0008] The photovoltaic cell in this embodiment includes a substrate, a first electrode, and a second electrode. The back side of the substrate has alternating first and second regions, with an isolation region between them. The second region includes at least a first dielectric layer, an N-type doped polycrystalline silicon layer, and a second dielectric layer. By providing the second dielectric layer, during the metallization sintering process of the second electrode, metal atoms and ions in the metal slurry tend to penetrate downwards, reaching the ultra-thin first dielectric layer through the polycrystalline silicon grain boundaries, and even invading the substrate to form recombination centers. The second dielectric layer is insulating and dense, forming a physical barrier that prevents metal ions from further diffusing into the N-type doped polycrystalline silicon layer, avoiding direct damage to the interface between the first dielectric layer and the substrate, reducing metal-induced recombination, minimizing leakage risk, and improving cell reliability and long-term service stability.

[0009] In some embodiments, the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

[0010] In some embodiments, the ratio of the thickness of the second dielectric layer to the thickness of the first dielectric layer is 1.5 to 8. In some embodiments, the thickness of the second dielectric layer is 5 nm to 12 nm.

[0011] In some embodiments, the thickness of the first dielectric layer is no greater than 10 nm.

[0012] In some embodiments, the thickness ratio of the N-type doped polysilicon layer to the second dielectric layer is 1.2 to 15.

[0013] In some embodiments, the thickness of the N-type doped polycrystalline silicon layer is 120 nm to 300 nm.

[0014] In some embodiments, the density of the second dielectric layer is greater than the density of the first dielectric layer.

[0015] In some embodiments, it also includes: A passivation layer is located on the front side of the substrate and on one side of the back side of the substrate; An antireflective layer is located on the surface of the passivation layer.

[0016] Secondly, a method for preparing a photovoltaic cell is provided, comprising: Prepare a battery prefabricated structure; the battery prefabricated structure includes a substrate, and along the thickness direction of the battery, the substrate has a front side and a back side disposed opposite to each other; in a first direction, the back side of the substrate is provided with an alternately distributed first region and a second region, and an isolation region is provided between the first region and the second region; the first region and the second region have opposite polarities, and the second region includes a first dielectric layer and an N-type doped polycrystalline silicon layer in the direction away from the substrate; The battery prefabrication structure is cleaned, and a second dielectric layer is formed on the surface of the N-type doped polycrystalline silicon layer; A first electrode is grown in the first region and a second electrode is grown in the second region to obtain a photovoltaic cell.

[0017] Thirdly, a photovoltaic module is provided, comprising any of the photovoltaic cells described above; Fourthly, a photovoltaic system is provided, which includes the photovoltaic modules described above. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a photovoltaic cell provided in this application; Figure 2 This application provides a flowchart of a method for preparing a photovoltaic cell; Figure 3 This is a schematic diagram of the photovoltaic system provided in this application; Figure 4 This is a schematic diagram of the photovoltaic module provided in this application; Figure 5 This is an exploded view of the photovoltaic module provided in this application; The accompanying drawings are not drawn to scale.

[0019] Reference numerals: 10000, photovoltaic system; 1000, photovoltaic module; 100, front cover plate; 200, first encapsulating film; 300, cell string layer; 400, second encapsulating film; 500, back cover plate; 600, frame; 700, junction box; 1, substrate; 2, first type structure; 21, third dielectric layer; 22, P-type doped polycrystalline silicon layer; 3, second type structure; 31, first dielectric layer; 32, N-type polycrystalline silicon layer; 33, second dielectric layer; 4, passivation layer; 5, antireflection layer; 6, first electrode; 7, second electrode. Detailed Implementation

[0020] The descriptions of specific structures or functions implemented according to the concept of this application disclosed in this specification are merely illustrative examples for explaining embodiments based on the concept of this application. Those skilled in the art will understand that embodiments based on the concept of this application can have various variations and forms, and are not limited to the embodiments described in this specification, but also include various modifications, equivalents, or substitutions made within the scope of the purpose, concept, and technology of this application.

[0021] In the description of this application, it should be understood that the use of terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicates the relative orientation or positional relationship between different components, and is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Although the terms "first" or "second" may be used to describe various components or components, the components or components should not be limited by the terms. The terms above are used only for the purpose of distinguishing one component or component from another. For example, without departing from the scope of the claims according to the concept of this application, a first battery cell may be referred to as a second battery cell, and similarly, a second battery cell may be referred to as a first battery cell.

[0023] In this application, unless otherwise expressly specified and limited, the terms "connected," "fixed," "set," etc., should be interpreted broadly. For example, when one component is said to "connect" another component, it should be understood that it can be directly or indirectly connected to the other component, meaning that other components may also be present in between. Similarly, the terms "fixed" and "set" should be interpreted broadly in a similar way. Furthermore, the term "connected" can refer to a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. In this application, unless otherwise expressly specified and limited, the description of "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. The first feature being "below", "under", or "below" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0024] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0025] The researchers who applied for this application discovered that the passivation effect of the N-region in the prior art is poor.

[0026] Based on this, this application provides a photovoltaic cell, please refer to... Figure 1 ,include: Substrate 1, along the thickness direction Y of the cell, has a front side and a back side disposed opposite to each other; in the first direction X, the back side of substrate 1 is provided with an alternately distributed first region S1 and a second region S2, and an isolation region S3 is provided between the first region S1 and the second region S2; the first region S1 and the second region S2 have opposite polarities, and the second region S2 includes at least a first dielectric layer 31, an N-type doped polysilicon layer 32 and a second dielectric layer 33 from the substrate 1 in the direction away from the substrate 1; The first electrode 6 is located in the first region S1; The second electrode 7 is located in the second region S2.

[0027] Substrate 1 can be an N-type silicon wafer.

[0028] The first direction X is perpendicular to the battery thickness direction Y in a two-dimensional plane.

[0029] For ease of description, the entire structure set in the first region is referred to as the first type structure 2, and the entire structure set in the second region is referred to as the second type structure 3. That is, the second type structure 3 includes at least a first dielectric layer 31, an N-type doped polysilicon layer 32, and a second dielectric layer 33.

[0030] The material of the first dielectric layer 31 can be silicon dioxide, which serves to passivate and selectively tunnel through: the first dielectric layer 31 covers the surface of the substrate 1, saturates the silicon wafer surface with dangling bonds, and significantly reduces the interface recombination rate; it allows majority carrier quantum tunneling through while blocking minority carriers from crossing the potential barrier, thus achieving selective contact.

[0031] It should be noted that the thickness of the first dielectric layer 31 is not limited in this application and depends on the specific circumstances.

[0032] In some embodiments of this application, the thickness of the first dielectric layer 31 is no greater than 10 nm.

[0033] For example, the thickness of the first dielectric layer 31 can be 1nm, 2nm, 4nm, 6nm, 8nm or 10nm, etc.

[0034] If the thickness of the first dielectric layer 31 is greater than 10 nm, the selective tunneling conduction effect will decrease due to the excessive thickness, which is not conducive to improving battery efficiency.

[0035] The doping element in the N-type doped polycrystalline silicon layer 32 can be phosphorus or other similar elements.

[0036] The material of the second dielectric layer 33 can be silicon dioxide.

[0037] In some embodiments of this application, the thickness ratio of the N-type doped polysilicon layer 32 to the second dielectric layer 33 can be 1.2 to 15.

[0038] For example, the thickness ratio of the N-type doped polysilicon layer 32 to the second dielectric layer 33 can be 1.2, 4, 6, 8, 10, 12, 14 or 15, etc.

[0039] The thickness of the N-type doped polysilicon layer 32 is not limited in this application and can be set by the user.

[0040] In some embodiments of this application, the thickness of the N-type doped polysilicon layer 32 can be 120 nm to 300 nm.

[0041] For example, the thickness of the N-type doped polysilicon layer 32 can be 120nm, 150nm, 200nm, 250nm or 300nm, etc.

[0042] If the thickness of the N-type doped polycrystalline silicon layer 32 is less than 120 nm, it is too thin and cannot serve as a passivation layer. It may cause the electrode paste to invade and corrode the first dielectric layer 31 during sintering. If the thickness of the N-type doped polycrystalline silicon layer 32 is greater than 300 nm, it is too thick and will increase parasitic absorption, leading to a decrease in battery performance. At the same time, it will also exacerbate the warpage of the substrate 1 due to stress issues.

[0043] The first type structure 2 includes a third dielectric layer 21 and a P-type doped polysilicon layer 22 stacked in the direction away from the substrate 1.

[0044] The material of the third dielectric layer 21 can be silicon dioxide, which serves to passivate and selectively tunnel through: the first dielectric layer 31 covers the surface of the substrate 1, saturates the silicon wafer surface with dangling bonds, and greatly reduces the interface recombination rate; it allows majority carrier quantum tunneling through while blocking minority carriers from crossing the potential barrier, thus achieving selective contact.

[0045] The doping element of the P-type doped polycrystalline silicon layer 22 can be boron or the like.

[0046] In some embodiments of this application, the thickness of the second dielectric layer 33 is greater than the thickness of the first dielectric layer 31. The first dielectric layer 31 is a tunneling oxide layer, made of ultrathin silicon oxide, and its thickness is constrained by the tunneling probability. This thickness is very thin and lacks effective blocking capability. The outer second dielectric layer 33 is set to a greater thickness. This second dielectric layer 33 is thicker than the tunneling oxide layer, providing sufficient film thickness to form a dense hydrogen barrier, suppressing excessive hydrogen diffusion to the tunneling interface, preventing interface degradation of the tunneling oxide layer, and reducing the interface recombination current density. 0sIt stabilizes the open-circuit voltage and improves the thermal stability of the battery. At the same time, when the thickness of the second dielectric layer 33 on the outside of the N-type doped polycrystalline silicon layer 32 is greater than that of the tunneling oxide layer, the sufficient film thickness can form a physical barrier layer, which can block the downward intrusion of metals and metal ions, prevent metals from damaging the tunneling oxide layer, reduce metal-induced recombination centers, reduce leakage risk, and improve the parallel resistance Rsh, which is suitable for the back structure of BC battery with alternating interdigitated arrangement.

[0047] It should be noted that this application does not limit the thickness relationship between the second dielectric layer 33 and the first dielectric layer 31, and can be set by the user.

[0048] In some embodiments of this application, the ratio of the thickness of the second dielectric layer 33 to the thickness of the first dielectric layer 31 is 1.5 to 8. If this thickness ratio is less than 1.5, the thickness of the second dielectric layer 33 is close to the thickness of the tunneling first dielectric layer 31, and the overall film is too thin to form a dense and effective hydrogen barrier. During high-temperature annealing and sintering, hydrogen can easily penetrate the second dielectric layer 33 and diffuse downwards, invading the N-type doped polycrystalline silicon layer 32 and reaching the interface between the first dielectric layer 31 and the substrate 1, causing an increase in interface states and a degradation of passivation contact performance. At the same time, the film has insufficient resistance to metal ion penetration and cannot effectively block the diffusion of metal components downwards along the polycrystalline silicon grain boundaries, which can easily lead to metal-induced recombination and increased leakage current. If the thickness ratio is greater than or equal to 1.5, the second dielectric layer 33 has sufficient film thickness to form a continuous and dense barrier film, achieving hydrogen blocking and metal ion blocking, while effectively covering the surface of the N-type doped polysilicon layer 32, saturating the polysilicon surface dangling bonds, reducing interfacial recombination between the N-type doped polysilicon layer 32 and the upper film, and also withstanding subsequent etching and cleaning processes, thus playing a process protection role.

[0049] This thickness ratio is less than or equal to 8, which can prevent the thickness of the second dielectric layer 33 from increasing excessively. While achieving the barrier protection function, it can control the stress of the film layer, maintain good optical performance, reduce the difficulty of the etching process, and broaden the process window.

[0050] For example, the ratio of the thickness of the second dielectric layer 33 to the thickness of the first dielectric layer 31 can be 1.5, 2.5, 4, 6, 7 or 8, etc.

[0051] It should be noted that the thickness of the second dielectric layer 33 is not limited in this application and depends on the specific circumstances.

[0052] In some embodiments of this application, the thickness of the second dielectric layer 33 is 5nm to 12nm.

[0053] For example, the thickness of the second dielectric layer 33 can be 5nm, 7nm, 9nm, 11nm, or 12nm. If the thickness of the second dielectric layer 33 is too large, on the one hand, the overall stress of the second dielectric layer 33 increases, the risk of thermal stress mismatch in the stacked film system increases, and the film layer is prone to warping, cracking, and delamination under high-temperature processes, reducing the yield and reliability of the battery; on the other hand, an excessively thick second dielectric layer 33 will change the optical interference conditions of the back film system, increase the back optical parasitic loss, which is not conducive to long-wavelength light reflection, resulting in a loss of short-circuit current density Jsc. If the thickness of the second dielectric layer 33 is too small, it is not enough to form a dense and effective hydrogen barrier. During high-temperature annealing and sintering, hydrogen can easily penetrate the second dielectric layer 33 and diffuse downward, invade the N-type doped polycrystalline silicon layer 32 and reach the interface between the first dielectric layer 31 and the substrate 1, causing an increase in interface states and degradation of passivation contact performance; at the same time, the film's resistance to metal ion penetration is insufficient, and it cannot effectively block the diffusion of metal components downward along the polycrystalline silicon grain boundaries, which can easily lead to metal-induced recombination and increased leakage current.

[0054] Meanwhile, if the thickness of the second dielectric layer 33 is too thin (less than 5nm), the passivation effect is too poor; if the thickness of the second dielectric layer 33 is too thick, the density of the second dielectric layer 33 will be aggravated, making it difficult to burn through the screen during sintering and thus having limited effect on improving the problem of EL fogging.

[0055] In some embodiments of this application, the density of the second dielectric layer 33 is greater than that of the first dielectric layer 31. The first dielectric layer 31 is mainly for tunneling and transport, so the first dielectric layer 31 should not be too dense. The second dielectric layer 33 is mainly for barrier protection, so the second dielectric layer 33 should not be too loose and porous.

[0056] Density can be tested by using BET (Brunauer–Emmett–Teller) to determine the specific surface area of ​​the medium layer; the larger the specific surface area, the smaller the density. Alternatively, porosity can be observed using SEM (scanning electron microscope); the larger the porosity, the smaller the density.

[0057] In some embodiments of this application, the front side of the substrate 1 has a textured structure. The textured structure has a light-trapping effect, which can increase the amount of light entering the battery, thereby improving the battery conversion efficiency.

[0058] The photovoltaic cell in this embodiment includes a substrate 1, a first electrode 6, and a second electrode 7. The back surface of the substrate 1 has alternating first and second regions, with an isolation region between them. The second region includes at least a first dielectric layer 31, an N-type doped polycrystalline silicon layer 32, and a second dielectric layer 33. By providing the second dielectric layer 33, during the metallization sintering process of fabricating the second electrode 7, metal atoms and ions in the metal slurry tend to penetrate downwards, reaching the ultra-thin first dielectric layer 31 through the polycrystalline silicon grain boundaries, and even invading the substrate 1 to form recombination centers. The second dielectric layer 33 is insulating and dense, forming a physical barrier that prevents metal ions from further diffusing into the N-type doped polycrystalline silicon layer 32, avoiding direct metal damage to the interface between the first dielectric layer 31 and the substrate 1, reducing metal-induced recombination, minimizing leakage risk, and improving cell reliability and long-term service stability.

[0059] Based on the above embodiments, in one embodiment of this application, the photovoltaic cell may further include: Passivation layer 4 is located on the front side of the substrate 1 and on one side of the back side of the substrate 1; Antireflection layer 5 is located on the surface of the passivation layer.

[0060] On the back side of substrate 1, passivation layers are located on the surfaces of the first type structure 2 and the second type structure 3.

[0061] The passivation layer 4 is used to reduce the carrier recombination rate on the battery surface, and the antireflection layer 5 is used to reduce light reflection. Together, they can significantly improve the photoelectric conversion efficiency and open-circuit voltage of the battery.

[0062] The passivation layer 4 and the antireflection layer 5 can be a single layer or multiple layers.

[0063] The passivation layer 4 may include at least one of an aluminum oxide layer, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a hafnium oxide layer, or a magnesium oxide layer; the antireflection layer 5 may include at least one of a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

[0064] In this embodiment, the second dielectric layer 33 also has the following effects: Firstly, the passivation layer 4 and the antireflection layer 5 (such as SiN) have the following effects: xThe substrate 1 contains a large number of hydrogen atoms. During high-temperature sintering and annealing, hydrogen easily diffuses downward through the N-type doped polycrystalline silicon layer 32 and reaches the interface between the substrate 1 and the first dielectric layer 31, causing an increase in interface states, degradation of passivation contacts, and an increase in minority carrier recombination. The first dielectric layer 31 is a tunneling oxide layer. A second dielectric layer 33 is provided on the outside of the N-type doped polycrystalline silicon layer 32. The second dielectric layer 33 acts as a hydrogen barrier layer, which can block hydrogen from migrating towards the tunneling oxide layer, protect the interface quality between the substrate 1 and the tunneling oxide layer, suppress surface recombination-induced degradation, stabilize passivation contact performance, and improve the thermal process stability of the battery open-circuit voltage. Secondly, the surface of the N-type doped polysilicon layer 32 contains a large number of grain boundaries and dangling bonds, and direct deposition of the passivation layer is prone to generating a high number of interface states. The second dielectric layer 33 covers the surface of the N-type doped polysilicon layer 32, saturates the dangling bonds on the polysilicon surface, reduces the interface state density between the N-type doped polysilicon layer 32 and the passivation layer 4, reduces carrier recombination at the interface of this layer, and synergistically improves the overall passivation effect of the second region S2. At the same time, it can buffer the stress between the upper and lower film layers, alleviate the risk of film warping, cracking and delamination under high temperature process, and improve the process compatibility of the stacked film system.

[0065] This application also provides a method for preparing a photovoltaic cell; please refer to [reference needed]. Figure 2 The method may include: Step S101: Prepare the battery prefabrication structure.

[0066] The battery prefabrication structure includes a substrate, which has a front side and a back side disposed opposite to each other along the thickness direction of the battery. In a first direction, the back side of the substrate is provided with an alternately distributed first region and a second region, and there is an isolation region between the first region and the second region. The first region and the second region have opposite polarities, and the second region includes a first dielectric layer and an N-type doped polycrystalline silicon layer in the direction away from the substrate.

[0067] The substrate can be an N-type silicon wafer.

[0068] In this application, the first area is designated as area P, and the second area is designated as area N.

[0069] The first type of structure includes a third dielectric layer and a P-type doped polysilicon layer 22 stacked in the direction away from the substrate.

[0070] The textured surface of the substrate and the isolation region can be a pyramidal structure.

[0071] This application does not impose any restrictions on the manufacturing process of the battery prefabrication structure; the process can be set independently.

[0072] In some embodiments of this application, preparing the battery prefabricated structure may include: Step S1011: A third dielectric layer and a first intrinsic polysilicon layer are sequentially deposited on the back surface of the substrate.

[0073] The third dielectric layer is a silicon oxide layer. The third dielectric layer and the first intrinsic polycrystalline silicon layer can be formed using methods such as LPCVD (Low Pressure Chemical Vapor Deposition).

[0074] As one possible implementation, before depositing the third dielectric layer and the first intrinsic polycrystalline silicon layer, the substrate can be polished to remove the damaged layer on the substrate surface, thereby improving the photoelectric conversion efficiency of the battery.

[0075] During damage removal, the substrate can be pre-cleaned using a mixture of O3 or NaOH and H2O2. Then, the substrate surface is polished using NaOH and ADD1 (Additive 1, a functional additive for first-alkali polishing). After that, the substrate is post-cleaned using a mixture of O3 or NaOH and H2O2 to remove additive residues. Then, HF and HCl are used for surface dehydration and removal of metal ions. Finally, the substrate is dried.

[0076] Step S1012: Doping the first intrinsic polysilicon layer to form a P-type polysilicon layer; the first type structure includes the third dielectric layer and the P-type polysilicon layer.

[0077] The first intrinsic polysilicon layer can be doped with boron (B), and a layer of borosilicate glass (BSG) can be formed on the surface of the first type of polysilicon layer.

[0078] Step S1013: Remove the first type structure located in the second region.

[0079] First, the BSG in the second region is treated with laser, followed by pre-cleaning with a mixture of O3 or NaOH and H2O2. Then, the laser-treated area is polished with a solution of NaOH and ADD2 (Additive 2, a functional additive for second-alkali polishing) to remove the type I structure in the second region and part of the substrate. Next, a post-cleaning process is performed with a mixture of O3 or NaOH and H2O2 to remove additive residues. Then, a mixture of HF and H2O2 is used to remove the BSG. Finally, a mixture of HF and HCl is used for surface dehydration and removal of metal ions, followed by drying.

[0080] Step S1014: A first dielectric layer and a second intrinsic polysilicon layer are sequentially deposited on one side of the back surface of the substrate.

[0081] The first dielectric layer is a silicon oxide layer. The first dielectric layer and the second intrinsic polycrystalline silicon layer can be formed using methods such as LPCVD.

[0082] The first dielectric layer and the second intrinsic polysilicon layer are deposited across the entire surface, meaning that the first dielectric layer and the second intrinsic polysilicon layer are formed in both the first and second regions.

[0083] Step S1015: Doping the second intrinsic polysilicon layer to form an N-type polysilicon layer; the second type structure includes the first dielectric layer and the N-type polysilicon layer, wherein the N-type polysilicon layer has the opposite electrical properties to the P-type polysilicon layer.

[0084] The second intrinsic polysilicon layer can be doped with phosphorus (P), and a layer of PSG (phosphosilicate glass) will also be formed on the surface of the second type polysilicon layer.

[0085] Step S1016: Process a local area in the second region near the first region to form an opening and obtain the battery structure to be processed.

[0086] The opening corresponds to the subsequent isolation zone, and the second zone no longer includes the opening area.

[0087] A laser can be used to process a local area of ​​the second region close to the first region to remove local PSG in the second region. It should be noted that the laser is also used to process the first region at the same time to remove PSG in the first region so that the first dielectric layer and N-type polysilicon layer of the first region can be removed in the subsequent texturing process.

[0088] Step S1017: Pre-clean the battery structure to be processed.

[0089] Pre-cleaning can be performed using O3 or a mixture of NaOH and H2O2.

[0090] Step S1018: Texturing the battery structure to be processed to form a textured structure on the positive surface of the substrate, while removing the first dielectric layer and N-type polysilicon layer located in the first region and the first dielectric layer and N-type polysilicon layer located in the region where the opening is located to form an isolation region.

[0091] The first dielectric layer and N-type polysilicon layer of the front and back openings and the first region of the silicon wafer are removed using a solution of NaOH and ADD3 (Additive 3, a functional additive for third-alkali polishing). At the same time, a textured structure is formed on the surface of the front surface and the substrate of the isolation region.

[0092] Step S1019: Perform post-cleaning on the texturized battery structure to obtain the battery prefabricated structure.

[0093] The purpose of post-washing is to remove additives remaining from the texturing process. NaOH and H2O2 can be used for post-washing.

[0094] It should be noted that after the post-cleaning process, the process also includes removing PSG from the second zone using HF.

[0095] Step S102: Clean the battery prefabrication structure and form a second dielectric layer on the surface of the N-type doped polycrystalline silicon layer.

[0096] The second dielectric layer can be a silicon dioxide layer.

[0097] In some embodiments of this application, cleaning the battery prefabricated structure includes cleaning the battery prefabricated structure with a mixed cleaning agent of O3, HF and HCl, and the cleaning temperature range is 5°C to 15°C.

[0098] The cleaning process effectively removes residual metal impurities, diffusion byproducts, and other contaminants from the texturing process. During this cleaning, O3 (ozone) oxidizes the surface of the N-type doped polycrystalline silicon layer to form a second dielectric layer, which is then etched by HF (hydrofluoric acid). The etching rate is lower than the oxidation rate. Simultaneously, O3, as a strong oxidant, oxidizes residual metal impurities (such as iron and copper) on the battery surface into higher valence metal ions. HCl (hydrochloric acid) provides chloride ions (Cl... - It possesses excellent complexing ability, rapidly forming complexes with these high-valence metal ions, thereby stably retaining the metal ions in the cleaning solution and effectively preventing them from redepositing onto the silicon surface or oxide layer through electrochemical reactions. This complexing effect hinders abnormal metal deposition, preventing further exacerbation of the unevenness and surface defects in the second dielectric layer, thus improving the uniformity and defect issues of the second dielectric layer.

[0099] The second dielectric layer can provide a good interface morphology for subsequent film deposition, and at the same time play a certain passivation role.

[0100] For example, the cleaning temperature can be 5°C, 10°C, or 15°C, etc.

[0101] The low temperature in this cleaning temperature range suppresses the etching rate of HF while increasing the stability of ozone dissolution, thus matching the HF etching rate with the ozone oxidation rate. This transforms excessive oxidation into an ideal dynamic balance of "oxidation-complexation-etching," preventing abnormal wire mesh sintering while also acting as a passivation layer.

[0102] It should be noted that this application does not limit the concentration of HCl in the mixed cleaning agent; it depends on the specific circumstances.

[0103] In some embodiments of this application, the concentration of HCl ranges from 0.5% to 2%.

[0104] For example, the concentration of HCl can be 0.5%, 1%, 1.5%, or 2%, etc.

[0105] If the hydrochloric acid concentration is too low (less than 0.5%), it cannot effectively complex metal ions; if the concentration is too high (greater than 2%), it will lead to chloride ion residue. Chloride ions are easily adsorbed on the silicon wafer surface, making cleaning difficult and causing reliability issues. Therefore, an HCl concentration between 0.5% and 2% ensures sufficient chloride ions (Cl... - It rapidly forms stable complexes with oxidized metal ions, thereby effectively removing metal impurities and preventing them from depositing on the silicon wafer surface or in the second dielectric layer, while improving the cleaning effect.

[0106] By controlling process conditions (the combination of cleaning temperature and hydrochloric acid concentration), a dynamic balance is achieved between the growth rate and etching rate of the second dielectric layer, thereby avoiding the formation of an excessively thick and difficult-to-remove second dielectric layer due to over-oxidation. Furthermore, compared to a single O3 / HF cleaning method, the hybrid cleaning system in this application has better wettability and penetration, enabling it to more fully penetrate the narrow trench area on the back of the back contact battery, ensuring that residues on the trench bottom and sidewalls are effectively removed.

[0107] It should be noted that this application does not limit the concentration of HF in the mixed cleaning agent; it depends on the specific circumstances.

[0108] In some embodiments of this application, the concentration of HF in the mixed cleaning agent is 0.05% to 0.1%.

[0109] For example, the HF concentration can be 0.05%, 0.08%, or 0.1%, etc.

[0110] HF reacts slowly at low temperatures. If the concentration is too low (less than 0.5%), the cleaning time will be too long and the oxidation rate will be too fast, causing the second medium layer to gradually thicken. If the HF concentration is too high (greater than 2%) (less than 0.5%), the corrosion rate will be much greater than the oxidation rate, damaging the surface of the second type structure and resulting in roughness or micropits.

[0111] Under the synergistic effect of the low-temperature environment, the chemical activity of HF is further suppressed, thereby matching its etching rate with the oxidation rate of ozone. This matching avoids the problem of an excessively thick, dense, and difficult-to-remove second dielectric layer caused by an oxidation rate much greater than the etching rate, effectively preventing appearance and performance defects such as electroluminescent fogging caused by an excessively thick second dielectric layer in subsequent processes.

[0112] It should be noted that after cleaning, the process also includes dehydration and drying of the cleaned battery prefabricated structure. Dehydration can be carried out using HF.

[0113] Step S103: Grow a first electrode in the first region and a second electrode in the second region to obtain a photovoltaic cell.

[0114] The fabrication process of the first and second electrodes is well known to those skilled in the art and will not be described in detail here.

[0115] In this embodiment, a second dielectric layer is formed on the surface of an N-type doped polycrystalline silicon layer. The second dielectric layer has a passivation effect, which can improve the efficiency of the battery.

[0116] Based on the above embodiments, in one embodiment of this application, the method for preparing a photovoltaic cell, before growing a first electrode in the first region and a second electrode in the second region, may further include: A passivation layer is grown in the first region, the second region, and the positive surface of the substrate; An antireflection layer is grown on the surface of the passivation layer.

[0117] The deposition method of the passivation layer and the antireflection layer is not limited in this application. For example, they can be formed by processes such as atomic layer deposition (ALD) and plasma enhanced chemical vapor deposition (PECVD).

[0118] Passivation layers are used to reduce the surface recombination rate and improve the open-circuit voltage of the battery. The passivation layer can be an aluminum oxide layer.

[0119] An antireflection layer is used to reduce the reflection of incident light on the front surface of the battery, increase light absorption, and thus improve the short-circuit current. The antireflection layer can be a silicon nitride layer.

[0120] The preparation method in this embodiment, by preparing a passivation layer and an antireflection layer, can further improve the passivation effect and photoelectric conversion efficiency of photovoltaic cells.

[0121] The performance of the solar cells was tested in the following ways: I. Preparatory work before testing 1. Battery cell cleaning, including: Wipe the surface of the battery cells with ultrapure water, ethanol or isopropanol to remove fingerprints, dust and organic residues; After drying the solar cells with nitrogen, let them stand for 10 minutes to avoid surface contamination affecting their optical properties.

[0122] 2. Electrode contact inspection, including

[0123] Use a four-wire probe (such as the Keithley 2400 series) to perform electrical measurements on the solar cells, ensuring that the contact resistance between the metal electrodes of the solar cells and the probe is <0.1Ω; Use silver paste or spring probes to secure the battery cells and avoid pressure damage.

[0124] 3. Stabilization treatment, including: The solar cells were aged under standard light (1000W / m²) for 1 hour to eliminate light-induced degradation (LID). The temperature of the solar cells was maintained at 25℃±0.5℃ using a constant temperature stage to avoid the impact of thermal effects on carrier mobility.

[0125] 4. Equipment calibration, including: The light source spectrum was calibrated using a standard reference cell to conform to the AM1.5G standard spectral conditions, with a calibration wavelength range of 300 nm to 1200 nm. The irradiance uniformity deviation in the test area does not exceed ±2%, and the measurement error of the temperature sensor used is less than ±0.1℃.

[0126] II. Testing Equipment and Conditions

[0127] 1. Core equipment

[0128] IV tester: Keysight B2900A series, with a voltage resolution of 0.1mV and a current resolution of 0.1μA; Solar simulator: Class AAA compliant, with selectable pulsed or steady-state light source (e.g., Wacom WXS-200S-20). Temperature control console: Temperature regulation is achieved based on a thermoelectric cooling (TEC) module, with a control accuracy of ±0.2℃; Spectral response instrument: equipped with a quantum efficiency (QE) testing system (such as Bentham PVE300).

[0129] 2. Standard Test Conditions (STC)

[0130] Irradiance: 1000W / m² (AM1.5G standard spectrum); Temperature: 25℃±1℃ (monitored in real time via TEC module); Light spot uniformity: The uniformity of the light spot covering the effective area of ​​the battery is >95%.

[0131] III. Key Parameter Testing Procedures

[0132] 1. Conversion efficiency (Eta) and IV characteristics (Voc, Isc, FF) testing

[0133] Test equipment: solar simulator, IV tester and four-wire probe.

[0134] step: (1) Sample placement: Place the battery cell in the center of the light spot of the simulator, and use a light shield to block the edge of the battery cell by 5mm to avoid light leakage at the edge; (2) IV scan: Apply a scan voltage from -0.5V to Voc+0.5V through an IV tester, set the scan step size to 10mV, and record the IV characteristic curve of the battery simultaneously; (3) Parameter extraction: Extract the open-circuit voltage Voc (voltage when current = 0) and short-circuit current Isc (current when voltage = 0) from the IV curve; (4) Calculation of power and fill factor: Calculate the maximum power point (Pmax=Vmpp×Impp) and fill factor FF=Pmax / (Voc×Isc) on the IV curve; (5) Efficiency calculation: The conversion efficiency Eta = (Pmax / Pin) × 100% is calculated, where the incident light power Pin is calibrated by a calibrated standard cell.

[0135] 2. Series resistance (Rs) test

[0136] Method 1: Dual-light illumination method

[0137] (1) Curve measurement: The IV curve of the battery was measured under two irradiance conditions of 1000W / m² and 800W / m² respectively; (2) Resistance calculation: Calculate the slope of ΔV / ΔI of the two IV curves in the region near the short-circuit current Isc, and calculate the series resistance Rs using the formula Rs=(Voc1-Voc2) / (Isc1-Isc2).

[0138] Method 2: Four-wire pulse measurement

[0139] (1) Pulse application: Use an IV tester to apply a short current pulse with a pulse width of 1ms to the battery cell to eliminate the influence of battery self-heating on the measurement.

[0140] (2) Resistance back deduction: According to Ohm's law ΔV=I×Rs, the series resistance Rs=ΔV / I can be deduced from the measured voltage drop ΔV. It should be noted that the inherent contact resistance of the system needs to be deducted during the calculation.

[0141] 3. Parallel Resistance (Rsh) Test

[0142] Method 1: Dark Current Method

[0143] (1) Dark-state bias scanning: Under completely dark conditions, apply a reverse bias voltage from -1V to 0V to the solar cell and perform scanning; (2) Resistance calculation: Measure the slope of the IV characteristic in the reverse saturation current region. The parallel resistance Rsh = ΔV / ΔI. Usually, the data point is taken at a bias voltage of -0.5V.

[0144] Method 2: Low-intensity IV analysis

[0145] (1) Low light measurement: The IV curve of the battery was measured under a low irradiance of 50 W / m²; (2) Resistance estimation: The parallel resistance Rsh can be approximated as the reciprocal of the slope of the IV curve in the region near the open-circuit voltage Voc.

[0146] Example

[0147] Step 1: Remove the mechanical damage layer and metal ions from the surface of the silicon wafer (substrate) using a wet cleaning tank. First, pre-clean the silicon wafer with a mixture of O3 or NaOH and H2O2. Then, polish the surface of the silicon wafer with a mixture of NaOH and ADD1. Next, perform a post-cleaning with a mixture of O3 or NaOH and H2O2 to remove additive residues. Then, dehydrate the surface and remove metal ions with a mixture of HF and HCl. Finally, dry the wafer.

[0148] Step 2: A third dielectric layer and a first intrinsic polysilicon layer are sequentially deposited on the polished back surface using a low-pressure chemical vapor deposition (LPCVD) device.

[0149] Step 3: Use a high-temperature diffusion device to perform double-sided boron diffusion, so that the first intrinsic polycrystalline silicon layer is transformed into a P-type doped polycrystalline silicon layer, and BSG is formed on its surface. BSG will also be formed on the front side of the silicon wafer.

[0150] Step 4: Use a laser device to remove the pattern of BSG on the back side. The laser-treated area is defined as the N area (second area), and the untreated area is defined as the P area (first area).

[0151] Step 5: Use a wet plating tank to remove the remaining BSG on the back side, while simultaneously performing alkaline polishing on the front side. First, pre-clean with a mixture of O3 or NaOH and H2O2. Then, polish the laser-treated area (i.e., the N-region) with a mixture of NaOH and ADD2 to remove the P-type doped polysilicon layer and the third dielectric layer in the N-region, while also etching part of the substrate. Next, remove the BSG with a mixture of HF and H2O2, followed by surface dehydration and metal ion removal with a mixture of HF and HCl, and finally dry the surface.

[0152] Step 6: Deposit a first dielectric layer and a second intrinsic polysilicon layer on the back side (including the P-region and N-region) using an LPCVD device.

[0153] Step 7: Use a high-temperature diffusion device to perform double-sided phosphorus diffusion, so that the second intrinsic polysilicon layer is transformed into an N-type doped polysilicon layer, and a PSG layer is formed on its surface. PSG will also be formed on the front side.

[0154] Step 8: Use a laser device to remove the PSG in the P area on the back side and apply it to a local area in the N area to form an opening in the N area to define the subsequent isolation zone.

[0155] Step 9: Use a chain-type hydrofluoric acid cleaning device to remove the PSG formed by phosphorus diffusion on the positive surface.

[0156] Step 10: Use a tank-type wet process to remove the N-type polysilicon layer in the laser area on the front and back sides to form a textured surface on the front side and an isolation area on the back side.

[0157] Step 11: First, pre-clean using O3 or a mixture of NaOH and H2O2; then, use a mixture of NaOH and ADD3 to remove the N-type polysilicon layer and the first dielectric layer in the laser area on the front and back of the silicon wafer, while simultaneously preparing a textured structure on the front surface of the silicon wafer and the surface of the silicon wafer in the isolation area; then, use a mixture of N-type polysilicon layers for post-cleaning to remove additive residues; subsequently, use hydrofluoric acid to remove PSG in the N-region.

[0158] Step 12: Cleaning is performed in a low-temperature (5℃~15℃) environment using a mixed cleaning agent of O3, HF and HCl to form a second dielectric layer on the surface of the N-type polycrystalline silicon layer, wherein the concentration of HF is 0.05%~0.1% and the concentration of HCl is 0.5%~2%.

[0159] Step 13: Surface dehydration and drying are performed using HF.

[0160] Step 14: Deposit aluminum oxide passivation layers on the front and back sides of the silicon wafer using an ALD device.

[0161] Step 15: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer using a PECVD device.

[0162] Step 16: Print main grid lines and fine grid lines in the P-region and N-region respectively using a metallization device. After sintering, perform photoinjection treatment to form the first electrode and the second electrode.

[0163] Step 17: Use a test sorting machine to perform IV characteristic tests and performance sorting on the manufactured batteries.

[0164] Comparative Example

[0165] The preparation process of the comparative example is similar to that of the example, except that the process of forming the second dielectric layer in step 12 is missing.

[0166] The performance parameters of the back-contact solar cells obtained in the comparative examples and embodiments are shown in Table 1.

[0167] Table 1

[0168] As shown in Table 1, compared with the comparative example, the Voc (open circuit voltage) of the back contact battery in this application embodiment is improved, indicating that the recombination loss of the battery is reduced; Isc (short circuit current) is slightly reduced; FF (fill factor) is improved; the average value eta (average photoelectric conversion efficiency) is improved, indicating that the battery performance is improved; Rs_LfDf (series resistance) is reduced, indicating that the ohmic loss inside the battery is smaller; Rsh_Df (parallel resistance) is significantly improved, indicating that there are fewer bypass leakage paths and the leakage loss is reduced; Irev 12 (reverse leakage current) is reduced, indicating that the insulation effect of the battery isolation area is improved, the leakage paths caused by edge leakage and defects are reduced, and the reliability and safety of the battery are improved.

[0169] like Figure 3 As shown, this application provides a photovoltaic system 10000, which can be applied in photovoltaic power plants, such as ground power plants, rooftop power plants, and water surface power plants, and can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc.

[0170] It is understandable that the application scenarios of the PV system 10000 are not limited to this; that is to say, the PV system 10000 can be applied in all fields that require solar power generation. Taking a PV power generation system as an example, the PV system 10000 may include a PV array, a combiner box, and an inverter. The PV array may be an array combination of multiple PV modules 1000. For example, multiple PV modules 1000 can form multiple PV arrays. The PV array is connected to the combiner box, which can collect the current generated by the PV array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to realize solar power supply.

[0171] A photovoltaic module 1000 is a device that directly converts light energy into electrical energy through the photoelectric effect or photochemical effect. For example... Figure 4 and Figure 5 As shown, the photovoltaic module 1000 is typically a stacked encapsulation structure, which includes at least the following from the light-facing side to the backlight side: a front cover plate 100, a first encapsulation film 200, a cell string layer 300, a second encapsulation film 400, and a back cover plate 500, as well as a frame 600 arranged around the periphery of the stacked structure and a junction box 700 disposed on one side of the back cover plate 500.

[0172] The front cover 100 may be made of a material with excellent light transmittance, impact resistance, corrosion resistance, and weather resistance, and may optionally include at least one of the following materials: tempered glass, plexiglass, transparent ceramics, organic fibers, or polymers. In some embodiments, the front cover 100 may include at least one of an insulating barrier layer, a fluorinated weather-resistant layer, and a transition adhesive layer.

[0173] The back cover 500 typically needs to possess insulation, water resistance, aging resistance, weather resistance, and corrosion resistance. It may optionally include at least one of the following composite back covers as the substrate: tempered glass, plexiglass, metal back cover, or PET film. The PET-based composite back cover may, depending on the needs of different applications, include various types such as composite (e.g., TPT / KPK, TPE / KPE), coated (e.g., TPC, KPC, CPC), and co-extruded (e.g., PO).

[0174] It is understandable that the material selection of the front cover 100 and the back cover 500 does not affect each other, and the same or different materials can be selected according to different application scenarios of the components (such as residential photovoltaics and building-integrated photovoltaics).

[0175] The first encapsulating film 200 and the second encapsulating film 400 may be selected from at least one of ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, EVA-POE-EVA co-extruded film (EPE), PVB (polyvinyl butyral), polyethylene terephthalate (PET) film, or liquid silicone. In some embodiments, the first encapsulating film 200 and the second encapsulating film 400 may further include one or more functional additives selected from the group consisting of crosslinking agents, coupling agents, antioxidants, ultraviolet absorbers, etc., to improve the crosslinking degree, weather resistance, adhesive strength, and anti-aging properties of the film. It is understood that the first encapsulating film 200 and the second encapsulating film 400 may be made of the same or different materials.

[0176] The battery string layer 300 includes multiple battery strings, which can be combined in series, parallel, or series-parallel configurations to achieve current collection and output. Further, each battery string is formed by sequentially connecting multiple battery cells via connectors. In some embodiments, at least a portion of the connector is electrically connected to the back electrode of one battery cell, and at least another portion of the connector is electrically connected to the front or back electrode of another battery cell to form a battery string. The connector may optionally include conductive elements such as solder strips, busbars, or metal clips. In some embodiments, to improve welding performance, oxidation resistance, and weather resistance, the connector material may preferably be a highly conductive metal material, such as at least one of silver, copper, tin, and nickel, or an alloy thereof. In some embodiments, to balance conductivity and cost control, the connector material may also be at least one of metal-clad composite materials such as silver-coated copper, copper-coated silver, copper-coated aluminum, aluminum-coated copper, tin-plated copper, or nickel-plated copper. The electrical connection may be selected from one of the following methods: laser welding, spot welding, bonding, ultrasonic welding, resistance welding, or brazing.

[0177] The solar cell may include a semiconductor substrate, a first emitter of a first conductivity type, and a second emitter of a second conductivity type. It is understood that one of the first and second conductivity types is P-type, and the other is N-type. The semiconductor substrate may include an N-type silicon substrate or a P-type silicon substrate. N-type silicon substrates are typically formed by doping with Group V elements such as phosphorus, arsenic, or antimony, and have the characteristic that the majority charge carriers are electrons; P-type silicon substrates are typically formed by doping with Group III elements such as boron, gallium, or aluminum, and have the characteristic that the majority charge carriers are holes.

[0178] The solar cell can employ a grid line design with no main grid (OBB), multiple main grid (MBB), or super-multiple main grid (SMBB). In some embodiments, the grid line material can be selected as at least one of silver-based conductive paste or silver-coated copper composite paste. The paste uses highly conductive metal powder as the conductive substrate, and the substrate can be at least one of silver powder, copper powder, or silver-coated copper composite powder. To improve the ohmic contact performance, conductivity, and long-term weather resistance of the electrodes, a composite functional layer can be formed on the surface of the substrate or in the grid line structure. The functional layer material includes at least one of glass powder, organic carrier, nickel-based barrier layer, tin-based alloy layer, or anti-oxidation and corrosion-resistant coating.

[0179] It is understood that the solar cell can be the back-contact solar cell prepared in the above embodiments.

[0180] A frame 600 surrounds the periphery of the stacked structure and is typically made of aluminum alloy or steel alloy. In some embodiments, the frame 600 may also be a fiberglass frame 600 or a plastic frame 600. The inner side of the frame 600 usually has grooves for filling with sealant to achieve a sealed bond with the stacked components formed by the front cover plate 100, the first encapsulating film 200, the battery string layer 300, the second encapsulating film 400, and the back cover plate 500, thereby blocking moisture and buffering external impacts. In some embodiments, the frame 600 can be assembled using corner brackets.

[0181] A junction box 700 is located on one side of the back cover 500 and is electrically connected to the terminals of the bus electrodes in the battery string layer 300 via a lead-out busbar for energy extraction. The junction box 700 typically includes a housing and cover made of weather-resistant insulating material, conductive connecting tabs disposed within the housing, and one or more bypass diodes. The bypass diodes are connected in parallel with sub-units of the battery string. The electrical leads of the junction box 700 include photovoltaic-specific connectors and cables. The cables preferably use cross-linked polyethylene insulating sheaths and tinned copper core wires. In some embodiments, the interior of the junction box 700 may also be filled and encapsulated with potting compound to achieve insulation, thermal conductivity, moisture protection, and fixation.

Claims

1. A photovoltaic cell, characterized in that, include: A substrate, along the thickness direction of the battery, has a front side and a back side disposed opposite to each other; In a first direction, the back side of the substrate is provided with alternating first and second regions, with an isolation region between the first and second regions; the first and second regions have opposite polarities, and the second region includes at least a first dielectric layer, an N-type doped polysilicon layer, and a second dielectric layer from the substrate toward the direction away from the substrate. The first electrode is located in the first region; The second electrode is located in the second region.

2. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

3. The photovoltaic cell as described in claim 1, characterized in that, The ratio of the thickness of the second dielectric layer to the thickness of the first dielectric layer is 1.5 to 8.

4. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the second dielectric layer is 5nm~12nm.

5. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the first dielectric layer is no greater than 10 nm.

6. The photovoltaic cell as described in claim 1, characterized in that, The thickness ratio of the N-type doped polycrystalline silicon layer to the second dielectric layer is 1.2 to 15.

7. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the N-type doped polycrystalline silicon layer is 120 nm to 300 nm.

8. The photovoltaic cell as described in claim 1, characterized in that, The density of the second dielectric layer is greater than that of the first dielectric layer.

9. The photovoltaic cell according to any one of claims 1 to 8, characterized in that, Also includes: A passivation layer is located on the front side of the substrate and on one side of the back side of the substrate; An antireflective layer is located on the surface of the passivation layer.

10. A method for preparing a photovoltaic cell, characterized in that, include: Prepare a battery prefabrication structure; the battery prefabrication structure includes a substrate, which has a front side and a back side disposed opposite to each other along the thickness direction of the battery; In a first direction, the back side of the substrate is provided with alternating first and second regions, with an isolation region between the first and second regions; the first and second regions have opposite polarities, and the second region includes a first dielectric layer and an N-type doped polysilicon layer in the direction away from the substrate. The battery prefabrication structure is cleaned, and a second dielectric layer is formed on the surface of the N-type doped polycrystalline silicon layer; A first electrode is grown in the first region and a second electrode is grown in the second region to obtain a photovoltaic cell.

11. A photovoltaic module, characterized in that, Including the photovoltaic cell as described in any one of claims 1 to 9.

12. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 11.

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