A VTG process method

Abstract

The application discloses a VTG process method, and the method comprises the following steps: after the VTG groove is expanded, the silicon nitride layer on the wafer surface is subjected to a nitrogen pretreatment process before the sacrifice oxide film is grown, and the formation of the sacrifice oxide film on the surface of the silicon nitride layer is inhibited. Before the sacrifice oxide film is grown, the N2 is introduced to perform plasma pretreatment, the stability of the N-Si bond is enhanced, the reactivity of the Si atom and the O2 is reduced, the formation of the sacrifice oxide film on the SiN surface is inhibited, and the deposition of the sacrifice oxide film in the VTG groove is not affected. After the deposition of the sacrifice oxide film, the thickness of the deposited sacrifice oxide film on the SiN surface is obviously smaller than the thickness of the deposited sacrifice oxide film in the VTG groove. After the SiN wet etching removal, the residual thickness of the sacrifice oxide film on the surface of the VTG groove can still maintain a sufficient thickness, and the subsequent process requirements can be met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and in particular to a VTG process method. Background Technology

[0002] CMOS image sensors (CIS) are widely used in digital cameras, smartphones and other fields. With the increasing demand for high-speed continuous shooting and high pixel count in CIS, the development of CIS has evolved from front-illuminated (FSI) to back-illuminated (BSI) technology, and back-side wiring technology has been incorporated into the back-illuminated process.

[0003] As the performance requirements of CIS products continue to increase and the chip area continues to shrink, the currently popular CIS chip structure is the STACK structure, which consists of three wafers—logical, pixel, and BSI—stacked together to form a fully functional CIS chip. This achieves both excellent logic performance and meets the requirements for pixel performance.

[0004] Currently, the charge transfer capability of traditional planar polycrystalline silicon (TG) gates is insufficient to meet the performance requirements of higher Full Well Capacity (FWC) and low White Pixel (WP) levels. To improve the performance of CIS products, the next-generation CIS key technology, Vertical Transfer Gate (VTG), is being adopted. This technology significantly improves charge transfer efficiency, eliminates motion distortion, and adapts to the high-performance imaging requirements of high pixel count and low noise. In ordinary planar lateral gate (TG) gates, electrons move horizontally on the silicon surface. As pixels shrink, leakage current, slow transfer speed, and decreased full-well capacity occur. In contrast, VTG gates extend vertically downwards into the silicon wafer, closely adhering to the deep photodiode (PD). Electrons are transferred vertically upwards to the floating diffusion region (FD). Unlike traditional planar lateral gates, VTG is primarily used in small-pixel, high-pixel-density mobile phone sensors. VTG trenches require high aspect ratio etching, necessitating multiple patterning techniques using a hard mask (APF amorphous carbon) + DARC anti-reflective layer. However, the development of VTG requires extremely strict control over the defect source and damage on the substrate surface, which is crucial for WP. During development, an oxide film of approximately 90 Å needs to be formed on the substrate trench surface before SiN removal to meet the requirements of subsequent IMP implantation and to effectively suppress the impact of hot phosphoric acid from subsequent SiN removal on the trench. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a VTG process method to suppress the formation of oxide film on the surface of silicon nitride layer and effectively prevent damage to WP performance.

[0006] To address the aforementioned issues, this invention provides a VTG process method in which, after the VTG trench is enlarged and before the sacrificial oxide film is grown, the silicon nitride layer on the wafer surface is subjected to a nitrogen pretreatment process to suppress the formation of an oxide film on the silicon nitride layer surface.

[0007] Furthermore, the process method includes: The first step involves providing a wafer and sequentially depositing the following film layers on the surface of a semiconductor substrate: plasma-enhanced oxide, plasma-enhanced nitride, APF, and DACK. Finally, a layer of photoresist is coated. After photolithography, the etching windows of the DARC layer, APF layer, and plasma-enhanced nitride layer are opened at once. The semiconductor substrate is etched downwards to form a VTG trench. Then, the photoresist, DACK, and APF are removed until the plasma-enhanced nitride layer is exposed again. The second step is to sequentially perform hole enlargement etching on the plasma-enhanced nitride film and plasma-enhanced oxide film at the opening of the VTG trench to expand the lateral width of the VTG trench opening. The third step is to perform a nitrogen pretreatment process on the wafer; The fourth step is to deposit a sacrificial oxide film on the wafer surface, which covers the TVG trenches; The fifth step is to perform back etching on the sacrificial oxide film to remove the sacrificial oxide film covering the plasma-enhanced nitride film region above the TVG trench, including the inner sidewall of the trench. Step 6: Remove the plasma-enhanced nitride film from the wafer surface; Step 7: Remove all sacrificial oxide film from the wafer surface, including plasma-enhanced oxide film; Step 8: Deposit the gate oxide layer; Step 9: Deposit polysilicon and etch back.

[0008] Furthermore, in the first step, the wafer includes at least a silicon substrate wafer, a germanium silicon substrate wafer, a gallium arsenide substrate wafer, a gallium nitride substrate wafer, and a silicon carbide substrate wafer.

[0009] Furthermore, in the first step, the thickness of the plasma-enhanced oxide film is 100 Å, the thickness of the plasma-enhanced nitride film is 1200 Å, the thickness of the APF is 2000 Å, the thickness of the DACK is 350 Å, and finally a photoresist with a thickness of 1400 Å is coated.

[0010] Furthermore, in the first step, the VTG trench depth is 0.4 μm and the opening width is 0.1 μm.

[0011] Furthermore, in the third step, nitrogen gas is introduced into the process chamber to replace and exhaust all other gases inside the process chamber. Nitrogen plasma pretreatment is then introduced to enhance the stability of N-Si bonds, reduce the reactivity of Si atoms with O2, and inhibit the subsequent formation of oxide film on the silicon nitride surface.

[0012] Furthermore, in the fourth step, the thickness of the sacrificial oxide film is at least 90 Å, which needs to meet the requirements of subsequent ion implantation and rapid thermal annealing activation processes.

[0013] Furthermore, in the fifth step, the thickness of the remaining sacrificial oxide film after the back etching must be no less than 30 Å to ensure that the influence of hot phosphoric acid is effectively blocked in the subsequent wet etching removal process of the plasma-enhanced nitride film.

[0014] Furthermore, in the sixth step, the plasma-enhanced nitride film removal adopts a wet etching process, which utilizes a phosphoric acid solution for removal.

[0015] The VTG process disclosed in this invention involves performing a nitrogen pretreatment process on the silicon nitride layer on the wafer surface after the VTG trench is enlarged and before the sacrificial oxide film is grown. This effectively inhibits the formation of the oxide film on the surface of the silicon nitride layer without affecting the growth of the oxide film on the surface of the silicon trench, thereby improving the performance of CIS. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the existing planar transverse gate (TG) and vertical transmission gate.

[0017] Figure 2 This is a state diagram after the deposition of various film layers on the substrate sub in the first step of the process of this invention.

[0018] Figure 3 This is a state diagram of the first step of the process of this invention, which involves etching VTG trenches using PESiN as a hard mask.

[0019] Figure 4 This is a state diagram of the second step of the process of the present invention, which involves enlarging and etching the opening of the VTG trench.

[0020] Figure 5 This is a state diagram of the third step in the process of this invention, which involves N2 plasma pretreatment of the PESiN surface.

[0021] Figure 6 This is a state diagram of the fourth step in the process of this invention, which involves depositing a sacrificial oxide film (SACOX).

[0022] Figure 7 This is a state diagram of the sacrificial oxide film (SAC OX) after the fifth step of the process of this invention, which is etched back.

[0023] Figure 8 This is a state diagram of the sixth step of the process of the present invention, in which the plasma-enhanced nitride film on the wafer surface is removed by wet etching process, i.e., hot phosphoric acid solution.

[0024] Figure 9 This is a state diagram of the seventh step of the process of the present invention, which involves removing all sacrificial oxide film, including plasma-enhanced oxide film, from the wafer surface.

[0025] Figure 10 This is a state diagram after the second deposition of the gate oxide layer in the eighth step of the process of this invention.

[0026] Figure 11 This is a state diagram of the ninth step of the process of the present invention, which involves depositing a polysilicon layer to fill the VTG trench and then etching back to form the VTG structure.

[0027] Figure 12 This is a flowchart of the process steps of the present invention. Detailed Implementation

[0028] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] This invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] As described in the background section, a key aspect of VTG process development is forming a 90 Å thick oxide film on the surface of the silicon trench before removing the silicon nitride layer to meet the thickness requirements of subsequent ion implantation, and to effectively block the influence of hot phosphoric acid on silicon during subsequent silicon nitride layer removal.

[0031] To effectively suppress the impact of hot phosphoric acid on the silicon substrate surrounding the trench during the subsequent removal of the PESiN layer, this invention proposes a novel process method. Before growing the sacrificial oxide film, the SiN surface is treated with nitrogen (N2) to effectively suppress the formation of the oxide film on the SiN surface without affecting the growth of the oxide film on the silicon trench surface. This satisfies the thickness requirements for subsequent IMP implantation while ensuring that the retained thickness of the sacrificial oxide film in the trench is at least 30 Å, effectively blocking the impact of the hot phosphoric acid solution on the silicon substrate during PESiN removal.

[0032] Specifically, after the normal active area cycling process and pixel IMP injection, the corresponding VTG process is performed: First step, such as Figure 1 As shown, a 100 Å thick plasma-enhanced oxide (PEOX), a 1200 Å thick plasma-enhanced silicon nitride (PESiN), a 2000 Å thick APF, and a 350 Å thick DACK layer are first deposited on a silicon wafer, and finally a 1400 Å thick photoresist (PR) layer is coated.

[0033] The VTG process then proceeds sequentially, including photolithography to sequentially open the DARC layer, APF layer, and plasma-enhanced silicon nitride (PESiN). PESiN primarily serves as a hard mask layer, opening the etching windows for the VTG trenches. The PEOX layer and the silicon substrate are then etched downwards to form the VTG trenches. In one embodiment, the VTG trenches have a depth of 0.4 μm and a width of 0.1 μm.

[0034] The second step involves sequentially enlarging the hole by etching the plasma-enhanced nitride film and the plasma-enhanced oxide film at the opening of the VTG trench, thereby expanding the lateral width of the VTG trench opening. The trench opening is then etched back to approximately 50 Å.

[0035] The third step involves nitrogen (N2) pretreatment, in which nitrogen is introduced into the process chamber to form N plasma, which enhances the stability of the N-Si bond and reduces the reactivity of Si atoms with O2, thereby inhibiting the subsequent formation of oxide films on the SiN surface.

[0036] The fourth step is to deposit a sacrificial oxide film (SAC OX) with a thickness of not less than 90 Å. In the CIS process, an ISG oxide layer is generally used.

[0037] Step 5: Etch back the sacrificial oxide film SAC OX. Remove the sacrificial oxide film SAC OX from the surface of the plasma-enhanced silicon nitride (PESiN), including the sidewalls of the trench region. The remaining sacrificial oxide film SAC OX covering the silicon material in the trench of the substrate must be at least 30 Å thick to ensure that the wet etching of the subsequent plasma-enhanced nitride film can effectively block the influence of hot phosphoric acid.

[0038] The sixth step is to remove the plasma-enhanced nitride (PESiN) film on the wafer surface using a wet etching process with hot phosphoric acid solution.

[0039] Step 7: Remove all sacrificial oxide (SAC OX) from the wafer surface, including the plasma-enhanced oxide film; Step 8: Deposition of the gate oxide layer. The gate oxide layer is deposited in two stages to form GOX1 and GOX2. The first gate oxide layer has a thickness of 58 Å, and the second gate oxide layer has a thickness of 37 Å.

[0040] In the ninth step, a 1000 Å thick polysilicon layer is deposited to fill the VTG trench, and then etched back to form the VTG structure.

[0041] Finally, it also includes conventional fabrication processes required for normal CIS processes, such as source / drain ion implantation, contact hole CT, and interconnect metal.

[0042] Before N2 pretreatment in existing processes, the thickness difference between the oxide film on the nitride film surface and the silicon surface on the trench wall is very small. After the nitride film is removed, the silicon inner wall surface of the VTG trench is almost free of oxide film, which cannot effectively defend against the influence of hot phosphoric acid during subsequent wet etching removal of the nitride film. Correspondingly, the method of this invention pretreatments the sacrificial oxide film by introducing N2 plasma before the growth of the sacrificial oxide film. This enhances the stability of the N-Si bond and reduces the reactivity of Si atoms with O2, thereby inhibiting the subsequent formation of the sacrificial oxide film on the nitride film surface without affecting the deposition of the sacrificial oxide film inside the VTG trench. Thus, after the sacrificial oxide film is deposited, the thickness of the nitride film on the surface is significantly smaller than the thickness of the sacrificial oxide film deposited inside the VTG trench. After the wet etching removal of the nitride film, the remaining thickness of the sacrificial oxide film on the VTG trench surface can still be maintained at no less than 30 Å, meeting the requirements of subsequent processes.

[0043] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A VTG process method, characterized in that: After the VTG trench is enlarged and before the sacrificial oxide film is grown, the silicon nitride layer on the wafer surface is pretreated with nitrogen to inhibit the formation of the oxide film on the silicon nitride layer surface.

2. The VTG process method as described in claim 1, characterized in that: The process method includes: The first step involves providing a wafer and sequentially depositing the following film layers on the surface of a semiconductor substrate: plasma-enhanced oxide, plasma-enhanced nitride, APF, and DACK. Finally, a layer of photoresist is coated. After photolithography, the etching windows of the DARC layer, APF layer, and plasma-enhanced nitride layer are opened at once. The semiconductor substrate is etched downwards to form a VTG trench. Then, the photoresist, DACK, and APF are removed until the plasma-enhanced nitride layer is exposed again. The second step is to sequentially perform hole enlargement etching on the plasma-enhanced nitride film and plasma-enhanced oxide film at the opening of the VTG trench to expand the lateral width of the VTG trench opening. The third step is to perform a nitrogen pretreatment process on the wafer; The fourth step is to deposit a sacrificial oxide film on the wafer surface, the sacrificial oxide film covering the TVG trench; The fifth step is to perform back etching on the sacrificial oxide film to remove the sacrificial oxide film covering the plasma-enhanced nitride film region above the TVG trench, including the inner sidewall of the trench. Step 6: Remove the plasma-enhanced nitride film from the wafer surface; Step 7: Remove all sacrificial oxide film from the wafer surface, including plasma-enhanced oxide film; Step 8: Deposit the gate oxide layer; Step 9: Deposit polysilicon and etch back.

3. The VTG process method as described in claim 2, characterized in that: In the first step, the wafer includes at least a silicon substrate wafer, a germanium silicon substrate wafer, a gallium arsenide substrate wafer, a gallium nitride substrate wafer, and a silicon carbide substrate wafer.

4. The VTG process method as described in claim 2, characterized in that: In the first step, the thickness of the plasma-enhanced oxide film is 100 Å, the thickness of the plasma-enhanced nitride film is 1200 Å, the thickness of the APF is 2000 Å, the thickness of the DACK is 350 Å, and finally a photoresist with a thickness of 1400 Å is coated.

5. The VTG process method as described in claim 2, characterized in that: In the first step, the VTG trench depth is 0.4 μm and the opening width is 0.1 μm.

6. The VTG process method as described in claim 2, characterized in that: In the third step, nitrogen gas is introduced into the process chamber to replace and exhaust all other gases inside the process chamber. Nitrogen plasma pretreatment is then introduced to enhance the stability of N-Si bonds, reduce the reactivity of Si atoms with O2, and inhibit the subsequent formation of oxide films on the silicon nitride surface.

7. The VTG process method as described in claim 2, characterized in that: In the fourth step, the thickness of the sacrificial oxide film must be at least 90 Å to meet the requirements of subsequent ion implantation and rapid thermal annealing activation processes.

8. The VTG process method as described in claim 2, characterized in that: In the fifth step, the thickness of the remaining sacrificial oxide film after the back etching must be no less than 30 Å to ensure that the influence of hot phosphoric acid is effectively blocked in the subsequent wet etching removal process of the plasma-enhanced nitride film.

9. The VTG process method as described in claim 2, characterized in that: In the sixth step, the plasma-enhanced nitride film removal adopts a wet etching process, which uses a phosphoric acid solution for removal.

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