Detector package, photon counting detector and detector module

Abstract

The application provides a detector packaging structure, a photon counting detector and a detector module. The detector packaging structure comprises a crystal, a chip and one or more electrodes. The one or more electrodes are arranged on the crystal. The chip comprises a first region and a second region arranged adjacently. The chip is an integrated structure. The crystal is arranged above the first region. The first region comprises at least a part of one or more adapter channels. The second region comprises a signal processing circuit or comprises the signal processing circuit and another part of the adapter channels. The one or more electrodes are in communication with the one or more adapter channels. The one or more electrodes are connected to the signal processing circuit through the one or more adapter channels. The detector module comprises a substrate and at least one detector packaging structure arranged on the substrate. The structure integrates multiple functional regions on the chip, reduces the multi-layer connection interface inside the detector packaging structure, has a compact structure and high packaging flexibility.

Description

Technical Field

[0001] This invention relates to the field of photon counting detectors, and particularly to a detector packaging structure, a photon counting detector, and a detector module. Background Technology

[0002] Photon counting detectors have broad application prospects in fields such as medical imaging, nuclear detection, and security inspection. Their core performance is related to the packaging method between the crystal (such as cadmium zinc telluride crystal, cadmium telluride crystal, and other CZT-type crystals) and the chip.

[0003] Therefore, a detector packaging structure, a photon counting detector, and a detector module are provided to optimize the core performance of the detector. Summary of the Invention

[0004] This invention provides a detector packaging structure, including a crystal, a chip, and one or more electrodes; the one or more electrodes are disposed on the crystal; the chip includes a first region and a second region disposed adjacent to each other, the chip is an integrated structure, and the crystal is correspondingly disposed above the first region; the first region includes at least a portion of a transition path, and the number of the transition paths is one or more; the second region includes a signal processing circuit or includes the signal processing circuit and another portion of the transition path; the one or more electrodes are connected to one or more of the transition paths, and the one or more electrodes are connected to the signal processing circuit through one or more transition paths.

[0005] In some embodiments, the adapter path includes a first pad, a second pad, and a conductive line, wherein the first pad is conductively connected to the second pad via the conductive line; the first pad is conductively connected to the electrode, and the second pad is conductively connected to the signal processing circuit.

[0006] In some embodiments, the crystal is provided with multiple electrodes, and the number of the first pads and the number of the second pads are both multiple, with the multiple first pads and the multiple second pads respectively arranged in an array.

[0007] In some embodiments, the signal processing circuit includes one or more signal processing channels, each of which corresponds to and is electrically connected to the switching path.

[0008] In some embodiments, the signal processing channel includes an amplifier, a shaper, a comparator, and a counter connected in sequence.

[0009] In some embodiments, the crystal is disposed on one of two surfaces of the chip that are spaced apart along its thickness direction.

[0010] In some embodiments, the absolute value of the difference between the thermal expansion coefficient of the chip substrate and the thermal expansion coefficient of the crystal does not exceed 5.

[0011] The present invention also provides a photon counting detector, characterized in that it comprises: a plurality of crystals, each crystal forming a photon pixel unit, the photon pixel unit being used to receive X-rays and convert them into electrical signals, the crystals being made of zinc cadmium telluride or cadmium telluride; a chip including adjacently arranged switching paths and signal processing circuits, the switching paths and signal processing circuits being packaged into an integrated structure; the plurality of crystals being soldered to the switching paths, the switching paths being capable of transmitting the electrical signal of any one of the crystals to the signal processing circuits.

[0012] The present invention also provides a detector module, characterized in that it includes a substrate and one or more detector packaging structures; the one or more detector packaging structures are disposed on the substrate.

[0013] In some embodiments, the substrate includes a data acquisition circuit, which is signal-connected to a signal processing circuit in the detector packaging structure.

[0014] The beneficial effects of this invention include, but are not limited to: (1) By integrating the first region (which realizes the function of the interposer) and the second region (which realizes the function of the ASIC readout circuit) on the chip, the number of multi-layer connection interfaces inside the detector package structure is reduced, the overall thickness of the detector is reduced, the structure is compact, the reliability of the detector is improved, and the integrated manufacturing of the interposer and the ASIC chip can be realized, which reduces the manufacturing difficulty; (2) By combining the first pad, the second pad and the conductive line to form the transfer path, the flexible transfer between the electrode and the signal processing circuit is realized, which reduces the limitation on the crystal processing accuracy and the chip channel layout, improves the stability of the package structure, and improves the reliability of signal transmission; (3) The one-to-one correspondence and conductive connection between the signal processing channel and the transfer path set an independent signal processing flow for each electrode, which is conducive to eliminating signal crosstalk, realizing parallel processing, and retaining the independent energy spectrum information of each crystal pixel; (4) Integrating more than one detector package structure on the substrate realizes the modularization and miniaturization of the detection unit, thereby improving the yield of the detector module. Attached Figure Description

[0015] The present invention will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same reference numerals denote the same structures, wherein:

[0016] Figure 1 These are exemplary schematic diagrams of detector packaging structures shown in some embodiments of this specification; Figure 2 This is a circuit connection diagram of the detector package structure shown in some embodiments of this specification; Figure 3 This is a schematic diagram of the connection path of the adapter according to some embodiments of this specification; Figure 4 This is a schematic diagram of a signal processing circuit according to some embodiments of this specification; Figure 5 This is a schematic diagram of the detector module according to some embodiments of this specification; Figure 6 This is a schematic diagram of the detector module according to other embodiments shown in this specification; Figure 7 This is a schematic diagram of the detector module according to some embodiments of this specification.

[0017] Explanation of reference numerals in the attached diagram: 1. Crystal; 2. Chip; 21. First region; 210. Adapter path; 211. First pad; 212. Second pad; 213. Conductive line; 22. Second region; 220. Signal processing circuit; 221. Signal processing channel; 222. Amplifier; 223. Shaper; 224. Comparator; 225. Counter; 23. Lead; 3. Electrode; 4. Substrate; 41. Flexible flat cable. Detailed Implementation

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0019] It should be understood that the terms “system,” “device,” “unit,” and / or “module” used herein are one way to distinguish different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0020] As illustrated in this invention, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0021] In related technologies, crystals and chips can be packaged using methods such as direct top-to-bottom connection and interposer packaging. Direct top-to-bottom connection requires a one-to-one correspondence between chip channels and crystal pixels. The chip pads are connected to the readout circuit below via through-silicon vias (TSVs). The packaged structure has good thermal matching and high reliability, but TSV processing is difficult, resulting in low yield and high manufacturing costs. Interposer packaging can also be used, where the crystal and chip are indirectly connected via an interposer. The chip and crystal pads do not need to be strictly geometrically aligned, increasing packaging flexibility and reducing manufacturing costs. However, the thermal expansion coefficients of the interposer, crystal, and chip differ significantly, leading to stress concentration at the solder joints between layers and potentially causing solder joint breakage. This results in poor overall stability and reliability of the packaged structure.

[0022] This invention provides a detector packaging structure to effectively solve the above-mentioned problems.

[0023] Figure 1 This is an exemplary schematic diagram of a detector packaging structure shown according to some embodiments of this specification. Figure 2 This is a circuit connection diagram of the detector package structure shown in some embodiments of this specification.

[0024] In some embodiments, such as Figures 1-2 As shown, the detector package structure includes a crystal 1, a chip 2, and one or more electrodes 3. The one or more electrodes 3 are disposed on the crystal 1. The chip 2 includes a first region 21 and a second region 22 disposed adjacent to each other. The chip 2 is an integrated structure, and the crystal 1 is correspondingly disposed above the first region 21. The first region 21 includes at least a portion of one or more transition paths 210, and the number of transition paths is one or more. The second region 22 includes a signal processing circuit 220. The one or more electrodes 3 are connected to the one or more transition paths 210, and the one or more electrodes 3 are connected to the signal processing circuit 220 through the one or more transition paths 210.

[0025] Crystal 1 refers to a detection medium capable of receiving X-ray radiation and generating corresponding electrical or optical signals. In some embodiments, crystal 1 can be made of semiconductor materials, such as cadmium telluride (CdTe), cadmium zinc telluride (CZT), silicon (Si), etc. When X-rays or high-energy particles strike crystal 1, crystal 1 undergoes a photoelectric effect, generating a microcurrent.

[0026] Electrode 3 refers to a conductive structure disposed on crystal 1 for conducting signals or microcurrents. In some embodiments, the material of electrode 3 may be at least one of aluminum (Al), silver (Ag), gold (Au), indium tin oxide (ITO), etc.

[0027] In some embodiments, the number of electrodes 3 determines the number of pixels in crystal 1. For example, if crystal 1 has N×N electrodes 3, then the number of pixels in crystal 1 is N×N. N is an integer greater than 0, and the value of N can be set according to actual needs.

[0028] In some embodiments, one or more electrodes 3 can be disposed on the crystal 1 in various ways. For example, one or more electrodes 3 can be bonded to the crystal 1 with conductive adhesive. Or, for example, a metal layer can be deposited on one or more surfaces of the crystal 1 using vacuum evaporation or sputtering processes, and an array of electrodes 3 with a predetermined shape and spacing can be formed using photolithography or masking processes.

[0029] In some embodiments, one or more electrodes 3 may also be disposed on the crystal 1 in other feasible ways. For example, one or more electrodes 3 may be fixed on the crystal 1 by pressing to form electrical contact; but this is not the only possibility.

[0030] Chip 2 is an electronic device unit formed by integrating at least one electronic component on a substrate using semiconductor processes. The substrate is used to support the electronic component in chip 2. The substrate material can be a semiconductor material, such as at least one of germanium, GaAs, SiC, etc.

[0031] In some embodiments, chip 2 can be an unpackaged die. In some embodiments, chip 2 can be a packaged chip.

[0032] In some embodiments, the absolute value of the difference between the thermal expansion coefficient of the substrate of chip 2 and the thermal expansion coefficient of crystal 1 does not exceed 5 ppm / °C. The substrate material can be a semiconductor material, such as at least one of germanium, GaAs, SiC, etc.

[0033] The coefficient of thermal expansion is a constant that measures the relative change in the dimensions (such as length and volume) of a material when the temperature changes. It reflects the degree to which a material expands when heated or contracts when cooled.

[0034] In some embodiments, the substrate material of chip 2 is silicon.

[0035] The coefficient of thermal expansion of silicon (Si) is approximately 2.6 ppm / °C. The coefficients of thermal expansion of CZT (cadmium zinc telluride) crystal 1 and cadmium telluride (CdTe) crystal 1 are approximately 5-6 ppm / °C.

[0036] Silicon has a thermal expansion coefficient close to that of common crystal materials, and it also has mature semiconductor processing technology and good thermal conductivity. This reduces the production cost of detectors while improving the thermal stability and structural reliability of the packaging structure.

[0037] In some embodiments of this specification, the thermal expansion coefficient of the substrate of chip 2 is close to that of crystal 1, resulting in good thermal matching. Under temperature changes or vibration conditions, the thermal stress generated at the interface of heterogeneous materials is reduced, the stress concentration phenomenon is significantly alleviated, the solder joint breakage problem is effectively avoided, and the long-term reliability of the packaging structure is greatly improved.

[0038] In some embodiments, the first region and the second region are arranged adjacent to each other along a first direction. The first direction is the arrangement direction of different functional regions on the chip 2. The thickness direction of the chip refers to the direction in which the chip thickness is measured, such as the normal direction of the upper surface (front) or the normal direction of the lower surface (back) of the chip. In some embodiments, the first direction is substantially parallel or approximately parallel to the plane on which the chip is located (such as the upper or lower surface). For example, as shown in the figure... Figures 1-2 As shown, the first direction is the positive X-axis. The area above the first region 21 is the direction when the detector packaging structure is placed horizontally, such as the direction close to the positive Y-axis.

[0039] In some embodiments, the angle between the first direction and the plane where chip 2 is located ranges from 0 to 5°. In some embodiments, the angle between the first direction and the plane where chip 2 is located ranges from 0 to 3°. In some embodiments, the angle between the first direction and the plane where chip 2 is located ranges from 3° to 5°.

[0040] The first region 21 is used for electrical connection switching and signal transmission. The first region 21 can also be called the silicon-based interposer region. The second region 22 is used for processing the output signals. The second region 22 can also be called the ASIC readout circuit region.

[0041] In some embodiments, the first region 21 and the second region 22 are different functional regions of the substrate. In some embodiments, electronic components (such as pads, conductive lines, etc.) in the first region 21 and the second region 22 are integrated on the substrate using semiconductor processes. For example, a silicon-based interposer and an ASIC readout circuit chip can be bonded together on a single chip 2 via micro-bump bonding, integrating the interposer function and the ASIC readout circuit function onto the same chip using semiconductor processes.

[0042] The transition path 210 is used to transmit the electrical signal (such as a microcurrent) output by the electrode 3 to the second region 22. In some embodiments, multiple electrodes 3 can be electrically connected to the same transition path 210 to achieve the convergence of multiple signals. In other embodiments, when one electrode 3 needs to cover multiple transition paths 210, one electrode can be connected to multiple transition paths 210 to reduce interconnection resistance and provide a redundant path when one path fails. In other embodiments, the transition path 210 can also be electrically connected to the electrodes 3 of the crystal 1 in a one-to-one correspondence, thereby transmitting the electrical signal output by the electrode 3 to the second region 22 respectively. In some embodiments, the transition path 210 is entirely located in the first region 21. In some implementations, a portion of the transition path 210 is located in the first region, and another portion is located in the second region 22.

[0043] The signal processing circuit 220 is used to process the electrical signal output by electrode 3 to realize the photon counting function.

[0044] In some embodiments, each electrode 3 on the crystal 1 is connected to a corresponding transition path 210 in the first region 21 of the chip 2 via a flip chip process. The transition path 210 is electrically connected to the signal processing circuit 220 via wires (such as copper leads).

[0045] In some embodiments, the electrode 3 and the corresponding transition path 210 can be interconnected by filling with conductive paste and by hot pressing.

[0046] In some embodiments, the electrode 3 and the corresponding transition path 210 can also be connected in other feasible ways, which are not limited here.

[0047] In some embodiments, after receiving rays (such as X-rays) or particles, the crystal 1 generates an electrical signal, which is output to the transfer path 210 of the first region 21 of the chip 2 through the electrode 3; the transfer path 210 transmits the electrical signal to the signal processing circuit 220 of the second region 22, processes the electrical signal (such as signal amplification, filtering, etc.), and outputs the processed electrical signal.

[0048] In some embodiments of this specification, by integrating the two functional regions (first region 21 and second region 22) onto the chip, the high-cost, low-yield through-silicon via (TSV) process required by existing top-to-bottom interconnect schemes is avoided, thereby reducing manufacturing difficulty and cost; and the number of multi-layer interconnect interfaces inside the detector package structure is reduced, improving the reliability of the detector. The overall thickness of the package structure is significantly reduced, and the volume is more compact, which is beneficial for the miniaturization design of photon counting detectors and expands their application scenarios in portable devices.

[0049] It should be noted that the above description of the detector packaging structure is for illustrative purposes only and does not limit the scope of this specification. Those skilled in the art can make various modifications and changes to the detector packaging structure under the guidance of this specification. However, these modifications and changes remain within the scope of this specification.

[0050] Figure 3 This is a connection diagram of the adapter path 210 shown according to some embodiments of this specification.

[0051] In some embodiments, such as Figure 2 As shown, the adapter path 210 includes a first pad 211, a second pad 212, and a conductive line 213. The first pad 211 is electrically connected to the second pad 212 via the conductive line 213. The first pad 211 is electrically connected to the electrode 3, and the second pad 212 is electrically connected to the signal processing circuit 220.

[0052] The first pad 211 is used to realize the electrical interconnection between the electrode 3 of the crystal 1 and the chip 2. The crystal 1 and the chip 2 can be fixedly packaged and signal transmitted through the first pad 211. In some embodiments, the first pad 211 can be a metal bump formed by electroplating or dispensing on the surface of the first region 21. The first pad 211 can also be manufactured by photolithography, such as using photolithography to define independent conductive contact areas in the first region 21 and depositing solder balls in the conductive contact areas to form the first pad 211.

[0053] In some embodiments, the distribution of the first pads 211 can be configured as needed. For example, one first pad 211 may correspond to multiple electrodes 3, or multiple first pads 211 may correspond to one electrode. Alternatively, the first pads 211 and electrodes 3 may be in one-to-one correspondence. In some embodiments, the first pads 211 and electrodes 3 can be electrically connected in various ways. For example, the first pads 211 can be aligned with the corresponding electrodes 3 on the crystal 1, and then the first pads 211 and the corresponding electrodes 3 can be connected by eutectic bonding or conductive adhesive bonding. Another example is the use of flip-chip bonding to form metal bumps on the surface of the electrode 3, and reflow soldering to fuse and interconnect the metal bumps with the first pads 211.

[0054] In some embodiments, the connection between the first pad 211 and the electrode 3 can also be achieved in other ways. For example, the first pad 211 and the electrode 3 can be connected by metal leads; but this is not the only possibility.

[0055] The second pad 212 is the soldering point or conductive contact area of ​​the second region 22. The second pad 212 is used to realize the electrical interconnection between the first region 21 and the second region 22. The second pad 212 is formed in a similar manner to the first pad 211.

[0056] In some embodiments, the material of the first pad 211 and the second pad 212 may include at least one of the metals such as aluminum, nickel, and gold. In some embodiments, the first pad 211 and the second pad 212 may employ multi-layer metal stacking (such as at least two of aluminum, nickel, and gold) to ensure low contact resistance.

[0057] Conductive lines 213 are used to connect the first pad 211 and the second pad 212. Conductive lines 213 can be made of metal materials such as aluminum, copper, or gold. In some embodiments, conductive lines 213 can be integrated on the surface or inside of the chip 2 by photolithography, etching, or other methods.

[0058] In some embodiments, the two ends of the conductive line 213 can be connected to the first pad 211 and the second pad 212 in various ways. For example, the two ends of the conductive line 213 can be connected to the first pad 211 and the second pad 212 by ultrasonic welding or thermoforming welding. Another example is using flexible circuit board technology, where printed copper foil is used as the conductive line 213, and conductive adhesive or solder paste is used to electrically interconnect the first pad 211 and the second pad 212 with the two ends of the printed copper foil.

[0059] In some embodiments, the two ends of the conductive line 213 may also be electrically connected to the first pad 211 and the second pad 212 in other feasible ways, which are not limited here.

[0060] In some embodiments, the second pad 212 and the signal processing circuit 220 can be electrically connected in various ways. For example, the second pad 212 can be used as a pin and soldered onto the substrate carrying the signal processing circuit 220 using surface mount technology (SMT). Another example is that the metal pin connected to the second pad 212 can be inserted into a via of the substrate containing the signal processing circuit 220 for soldering using a through-hole soldering process.

[0061] In some embodiments, the connection between the second pad 212 and the signal processing circuit 220 can also be achieved through other feasible methods, such as flexible ribbon cable connection; but it is not limited thereto.

[0062] In some embodiments, when the adapter path 210 is entirely located in the first region 21, the interface between the second pad 212 and the signal processing path 220 can be electrically connected at the boundary between the first and second regions. In some embodiments, when a portion of the adapter path 210 is located in the first region and another portion is located in the second region 22, a portion of the conductive line 213 in the adapter path 210 and the second pad 212 are located in the second region 22.

[0063] In some embodiments, the crystal 1 is provided with multiple electrodes 3, and there are multiple first pads 211 and multiple second pads 212. The multiple first pads 211 and multiple second pads 212 are respectively arranged in an array. The multiple electrodes 3 correspond to the multiple first pads 211 and are electrically connected.

[0064] Multiple first pads 211 or multiple second pads 212 can be arranged in a matrix, circular array, or other shapes. The specific distribution method can be set according to requirements, such as the distribution of transition paths or signal processing circuits. The distribution method of the multiple first pads 211 can be the same as or different from the distribution method of the multiple second pads 212.

[0065] Some embodiments in this specification achieve highly reliable signal transmission between the detector electrodes and external circuits through the correspondence between multiple pads and electrodes and electrical interconnections. The multiple pads and electrodes do not need to correspond one-to-one in physical location, thus improving the design flexibility of the detector package structure.

[0066] In some embodiments of this specification, a transition path 210 is formed by the combination of the first pad 211, the second pad 212, and the conductive line 213, realizing the transition between the electrode 3 and the signal processing circuit 220, improving the stability of the package structure and enhancing the reliability of signal transmission. The distribution of the first pad 211 and the second pad 212 can be flexibly designed according to requirements, improving the applicability of the detector package structure. Structurally, the conductive line 213 between the first pad 211 and the second pad 212 does not need to be directly aligned with the pixel of the crystal 1 or the signal input of the signal processing circuit 220, improving packaging flexibility and reducing the difficulty and cost of the packaging process.

[0067] Figure 4 This is a schematic diagram of a signal processing circuit 220 according to some embodiments of this specification.

[0068] In some embodiments, the signal processing circuit 220 includes one or more signal processing channels 221, which correspond one-to-one with the switching path 210 and are electrically connected.

[0069] Signal processing channel 221 is used to process the electrical signal corresponding to a single electrode 3.

[0070] In some embodiments, the signal processing circuit 220 includes multiple independent parallel front-end circuits (such as analog circuits, digital logic devices, etc.), each front-end circuit serving as an independent signal processing channel 221.

[0071] In some embodiments, the signal processing circuit 220 may be integrated into an application-specific integrated circuit (ASIC), which includes multiple processing paths, each of which constitutes a signal processing channel 221 through internal logic gates or amplifiers.

[0072] In some embodiments, each signal processing channel 221 and its corresponding transition path 210 can be electrically connected in various ways. For example, the second pad 212 of the transition path 210 and the input pin of the signal processing channel 221 can be electrically connected using a gold wire bonding process, enabling unidirectional or bidirectional signal transmission from the transition path 210 to the signal processing channel 221. Alternatively, the second pad 212 of the transition path 210 and the contact point of the signal processing channel 221 can be directly pressed together, achieving electrical connection through flip-chip bonding technology.

[0073] In some embodiments, each signal processing channel 221 and its corresponding transition path 210 may be electrically connected in other feasible ways. No limitation is made here.

[0074] In some embodiments, the signal processing channel 221 includes an amplifier 222, a shaper 223, a comparator 224, and a counter 225 connected in sequence.

[0075] In some embodiments, amplifier 222, shaper 223, comparator 224 and counter 225 are connected in series.

[0076] Amplifier 222 refers to an electronic device or circuit that amplifies the voltage or current gain of the electrical signal received by signal processing channel 221 and converts it into a pulse signal. For example, amplifier 222 can be a charge-sensitive amplifier (CSA). In some embodiments, amplifier 222 is connected to electrode 3 via adapter path 210.

[0077] Shaper 223 refers to a circuit that filters or transforms pulse signals. Shaper 223 can shape the spike pulses output by amplifier 222 into smoother, more symmetrical waveforms (such as Gaussian waveforms).

[0078] Comparator 224 is a circuit that compares an input pulse signal with an energy threshold and outputs a logic level representing the comparison result. The energy threshold can be set empirically. For example, when the pulse is higher than the energy threshold, comparator 224 outputs a high level (e.g., output 1); when the pulse is lower than or equal to the energy threshold, comparator 224 outputs a low level (e.g., output 0).

[0079] Counter 225 is a logic circuit that accumulates the number of input pulses and outputs the accumulated value in digital form. When comparator 224 outputs a high level, counter 225 increments by 1. The value output by each counter 225 represents the number of photons received by each pixel of the crystal.

[0080] In some embodiments of this specification, a chain of processes involving amplification, shaping, comparison, and counting effectively extracts weak signals and filters out background noise. This structure ensures the accuracy of particle detection and improves the energy resolution of the detector at high count rates through precise waveform conversion and threshold discrimination of pulse signals.

[0081] In some embodiments of this specification, the one-to-one correspondence and conductive connection between the signal processing channel 221 and the switching path 210 provides an independent signal processing flow for each electrode 3, which helps to eliminate signal crosstalk and achieve parallel processing, while retaining the independent energy spectrum information of each crystal pixel 1.

[0082] In some embodiments, crystal 1 is disposed on one of two surfaces of chip 2 that are spaced apart along its thickness direction. The thickness direction of chip 2 can be found above. Figures 1-2 And related explanations.

[0083] In some embodiments of this specification, crystal 1 is disposed on one side of chip 2, which enables two-layer stacking of the packaging structure, reduces the number of multiple interconnecting interfaces inside the detector packaging structure, and improves the reliability of the detector. The overall thickness of the packaging structure is significantly reduced, and the volume is more compact, which is beneficial for the miniaturization design of photon counting detectors and expands their application scenarios in portable devices.

[0084] In some embodiments, the number of crystals 1 is multiple.

[0085] refer to Figure 6 The detector module shown has a single detector package structure with multiple crystals 1 on a single chip 2. The number of crystals 1 can be two, three or more.

[0086] In some embodiments, multiple crystals 1 are distributed according to a preset array rule and connected to chip 2. The preset array can be an M×N rectangular array or a ring array. The values ​​of M and N can be set according to requirements. In some embodiments, a preset physical gap is maintained between adjacent crystals 1 to meet the spatial resolution requirements of the detector.

[0087] In some embodiments, the arrangement of the multiple crystals 1 can also be achieved in other ways. For example, a honeycomb arrangement based on detection sensitivity requirements, or a combination of dense and sparse arrangements based on heat dissipation logic. Another example is a composite arrangement based on the mixed assembly of crystals 1 of different materials; however, it is not limited to these. The specific number of crystals 1, the coupling method between each crystal 1, and the physical position parameters can be set according to the actual application scenario.

[0088] The electrodes 3 of multiple crystals 1 correspond one-to-one with the transfer path 210 of the first region 21 of chip 2, and the electrodes 3 of multiple crystals 1 and the transfer path 210 of chip 2 are connected to the signal processing circuit 220.

[0089] In some embodiments of this specification, by setting multiple crystals 1, it is beneficial to reduce the size of crystal 1, improve the yield of crystal 1, and thus improve the reliability of the detector.

[0090] Some embodiments of this specification provide a photon counting detector, including a chip 2 and a plurality of crystals 1. Each crystal 1 forms a photon pixel unit, which is used to receive X-rays and convert them into electrical signals. The crystal 1 is made of cadmium zinc telluride or cadmium telluride. The chip 2 includes an adjacently arranged transition path 210 and a signal processing circuit 220, which are packaged into an integrated structure. The plurality of crystals 1 are soldered to the transition path 210, which is capable of transmitting the electrical signal of any crystal 1 to the signal processing circuit 220.

[0091] A photon pixel unit refers to the smallest sensing area on a photon counting detector.

[0092] In some embodiments, the switching path and processing circuitry can be integrated into the same physical package (such as chip 2) through micro-bump bonding or other packaging technologies.

[0093] In some embodiments, X-ray photons penetrate the object and irradiate each photon pixel unit composed of crystal 1. Crystal 1 absorbs photon energy and instantaneously generates a large number of free charges. Under the action of an external high-voltage electric field, the free charges drift towards electrode 3, forming a weak current pulse (i.e., an electrical signal). The current pulse is input to the corresponding signal processing circuit 220 through the transfer path 210 of chip 2. After processing by the signal processing circuit 220, digitized pixel count information is output, which is then reconstructed into a high-definition energy spectrum image by the back-end system.

[0094] For further details regarding crystal 1, chip 2, transition path 210, and signal processing circuit 220, please refer to [link to documentation]. Figures 1-4 And related content.

[0095] In some embodiments of this specification, the signal transmission distance from the crystal to the processing circuit is shortened by using a cadmium zinc telluride or cadmium telluride crystal in conjunction with an integrated chip structure. This mechanism effectively reduces parasitic capacitance interference during electrical signal transmission, reduces signal attenuation, and facilitates the successful transmission of weak electrical signals, thereby significantly improving the accuracy and response frequency of the detector in identifying photon energy.

[0096] Some embodiments of this specification provide a detector module. Figure 5 This is a schematic diagram of the detector module according to some embodiments shown in this specification. Figure 6 This is a schematic diagram of the detector module according to other embodiments shown in this specification. For example... Figures 5-6 As shown, the detector module includes a substrate 4 and one or more detector packaging structures. The detector packaging structures are disposed on the substrate 4. Each detector packaging structure includes a crystal 1, a chip 2, and one or more electrodes 3.

[0097] The substrate 4 is used to support the detector packaging structure. In some embodiments, the substrate 4 is a plate-like structure. The material of the substrate 4 can be at least one of ceramic, epoxy glass resin, silicon, etc.

[0098] In some embodiments, one or more detector packaging structures may be sequentially arranged on the substrate 4 along a third direction. In some embodiments, the third direction may be the bed-feeding direction of the CT equipment. In some embodiments, the third direction may be... Figure 1 and Figure 3 The X-axis direction or Z-axis direction in the model.

[0099] In some embodiments, one or more detector package structures can be connected to the substrate 4 via surface mount technology (SMT). For example, the solder balls or pins on the lower surface of the chip 2 of the detector package structure are aligned with the pads on the surface of the substrate 4, and the solder is melted by a reflow soldering process to form mechanical connections and / or electrical pathways.

[0100] In some embodiments, the substrate 4 and one or more detector packaging structures can be mechanically connected by bonding with conductive or insulating adhesive, and the substrate 4 and the detector packaging structures are electrically connected by leads 23. Leads 23 are used to connect the substrate 4 and the detector packaging structures. The material of the leads can be gold, copper, aluminum, etc. In some embodiments, the leads 23 are disposed in the second region 22 of the detector packaging structure, and the signal processing circuit 220 is electrically connected to the leads 23.

[0101] In some embodiments, more than one detector packaging structure may be configured in other feasible ways, which are not limited here.

[0102] Taking CT scanners as an example, in some applications, detectors need to have a significant length along the Z-axis to expand the scanning area. Manufacturing a large detector (such as a detector packaging structure) could significantly reduce detector yield or drastically increase manufacturing costs. However, if the detector packaging structure is arranged in multiple rows along the Z-axis, such as 300, 320, 160, or 80 rows, the size of the detector packaging structure does not need to be increased, while simultaneously expanding the scanning area of ​​the CT scanner. This significantly improves the yield of the detector packaging structure, and consequently, the yield of the entire detector module.

[0103] Some embodiments in this specification achieve modularization and miniaturization of the detection unit by integrating the detector packaging structure onto the substrate 4, thereby improving the yield of the detector module.

[0104] In some embodiments, the substrate 4 includes a data acquisition circuit, which has a signal connection with the signal processing circuit 220 in the detector packaging structure.

[0105] The data acquisition circuit is used to introduce the output data of the signal processing circuit 220 (such as the value output by the counter 225) into the subsequent processing equipment.

[0106] In some embodiments, the data acquisition circuit and the signal processing circuit 220 can be connected in various ways. For example, as... Figures 5-6 As shown, the data acquisition circuit and the signal processing circuit 220 are connected via lead 23. Alternatively, the data acquisition circuit and the signal processing circuit 220 can be connected via ball grid array (BGA) packaging technology, using solder balls to connect the circuit nodes on the substrate 4 to the pins of the detector package structure, thereby achieving signal connection.

[0107] In some embodiments, the data acquisition circuit and the signal processing circuit 220 can be connected in other feasible ways, which are not limited here.

[0108] In some embodiments of this specification, the integration of the detector module can be improved by integrating the data acquisition circuit onto the substrate 4.

[0109] Figure 7 This is a schematic diagram of the detector module according to some embodiments of this specification.

[0110] In some embodiments, such as Figure 7 As shown, the data acquisition circuit can be mounted on an external circuit board, with substrate 4 serving only as a signal transmission base. Specifically, substrate 4 can connect the signal from chip 2 to the external data acquisition circuit via a flexible flat cable 41.

[0111] The flexible flat cable 41 can be a flexible flat cable. The flexible flat cable 41 includes a conductor layer and an insulation layer. The conductor layer can be a metal wire (such as copper), and the insulation layer is a flexible film (such as polyimide) covering the conductor layer.

[0112] In other embodiments, the substrate 4 may serve only as a mechanical support base for the detector packaging structure, and the output signal of the chip 2 may be directly connected to an external data acquisition circuit via lead 23 or flexible flat cable 41.

[0113] The basic concepts have been described above. It is clear that the detailed disclosure above is merely illustrative and does not constitute a limitation of the present invention. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to the present invention by those skilled in the art. Such modifications, improvements, and corrections are suggested in this invention and therefore remain within the spirit and scope of the exemplary embodiments of the present invention.

[0114] Furthermore, this invention uses specific terms to describe embodiments of the invention. For example, "one embodiment." "An Example" The terms "and / or some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the present invention. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout the present invention do not necessarily refer to the same embodiment. Furthermore, certain features, structures, or characteristics in one or more embodiments of the present invention can be appropriately combined.

[0115] Similarly, it should be noted that, in order to simplify the description of this invention and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of this invention sometimes combines multiple features into a single embodiment, drawing, or description thereof. In fact, the embodiments have fewer features than all the features of the single embodiment disclosed above.

[0116] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, the numerical parameters used in some embodiments are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit preservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of the invention are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0117] Finally, it should be understood that the embodiments described in this invention are merely illustrative of the principles of the invention. Other modifications may also fall within the scope of this invention. Therefore, alternative configurations of the embodiments of this invention are considered as examples and not limitations, and are regarded as consistent with the teachings of this invention. Accordingly, the embodiments of this invention are not limited to those explicitly described and illustrated herein.

Claims

1. A detector packaging structure, characterized in that, Includes crystals, chips, and one or more electrodes; One or more electrodes are disposed on the crystal; The chip includes a first region and a second region arranged adjacent to each other. The chip has an integrated structure, and the crystal is disposed above the first region. The first region includes at least a portion of a switching path, and the number of switching paths is one or more. The second region includes a signal processing circuit or includes the signal processing circuit and another portion of the switching path. The one or more electrodes are connected to one or more of the aforementioned transition paths, and the one or more electrodes are connected to the signal processing circuit through one or more of the aforementioned transition paths.

2. The detector packaging structure according to claim 1, characterized in that, The adapter path includes a first pad, a second pad, and a conductive line, wherein the first pad is electrically connected to the second pad through the conductive line. The first pad is electrically connected to the electrode, and the second pad is electrically connected to the signal processing circuit.

3. The detector packaging structure according to claim 2, characterized in that, The crystal is provided with multiple electrodes, and there are multiple first pads and multiple second pads, which are arranged in an array.

4. The detector packaging structure according to claim 1, characterized in that, The signal processing circuit includes one or more signal processing channels, and each signal processing channel corresponds to and is electrically connected to the switching path.

5. The detector packaging structure according to claim 4, characterized in that, The signal processing channel includes an amplifier, a shaper, a comparator, and a counter connected in sequence.

6. The detector packaging structure according to claim 1, characterized in that, The crystal is disposed on one of two surfaces of the chip that are spaced apart along the thickness direction.

7. The detector packaging structure according to claim 1, characterized in that, The absolute value of the difference between the thermal expansion coefficient of the chip substrate and the thermal expansion coefficient of the crystal does not exceed 5.

8. A photon counting detector, characterized in that, include: Multiple crystals, each crystal forming a photonic pixel unit, the photonic pixel unit being used to receive X-rays and convert them into electrical signals, the crystals being made of cadmium zinc telluride or cadmium telluride; The chip includes an adjacently arranged switching path and a signal processing circuit, wherein the switching path and the signal processing circuit are packaged into an integrated structure; Multiple crystals are soldered to the adapter path, which is capable of transmitting the electrical signal of any one of the crystals to the signal processing circuit.

9. A detector module, characterized in that, Includes a substrate and one or more detector packaging structures as described in any one of claims 1-7; The one or more detector packaging structures are disposed on the substrate.

10. The detector module according to claim 9, characterized in that, The substrate includes a data acquisition circuit, which is signal-connected to the signal processing circuit in the detector packaging structure.

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