Infrared focal plane mechanical interlocking bump structure and preparation method thereof

Abstract

The application discloses an infrared focal plane mechanical interlocking bump structure and a preparation method thereof. According to the shape of the bump on the silicon readout circuit chip, the mechanical interlocking bump structure is designed and prepared at the photosensitive chip end. In the flip-chip interconnection process, the bump at the silicon readout circuit end is inserted into the mechanical interlocking bump structure at the photosensitive chip end, high-precision mechanical nesting interlocking is formed, random deviation generated in the flip-chip process is limited, and the effective pixel rate of the focal plane is improved. The application is not limited by the scale and pixel size of the focal plane, and is especially suitable for small-pixel focal plane arrays with low tolerance to flip-chip deviation.

Description

Technical Field

[0001] This invention belongs to the field of infrared and optoelectronics, specifically relating to an infrared focal plane mechanically interlocked bump structure and its preparation method, which can suppress random offset during flip bonding, improve flip bonding accuracy, and thus reduce the focal plane blind pixel rate, and is particularly suitable for small pixel focal plane arrays. Background Technology

[0002] With the increasing demands and requirements of infrared focal plane array (FLA) detectors in military, aerospace, and medical fields, they are continuously evolving towards large-scale, high-integration, low-power, and low-cost designs. High-precision coupling and interconnection processes have become a key technology for improving the performance and yield of FLA detectors. The increasing number of focal plane array pixels and the shrinking pixel size to the micrometer level significantly increase the difficulty of hybrid interconnection in infrared FLA detectors. Conventional interconnect bump soldering is prone to causing loose connections or short circuits between adjacent pixels due to random offset during soldering, which no longer meets the requirements for high-precision interconnection. Therefore, it is necessary to invent new interconnect bump structures to limit the offset generated during soldering, effectively increase pixel connectivity, reduce the blind pixel rate of high-density infrared FLA detectors, and simultaneously improve the yield of FLA detectors. Summary of the Invention

[0003] Based on the problems existing in the flip-solder interconnection of large-area high-density focal plane detectors, this invention innovatively proposes an infrared focal plane mechanically interlocked bump structure and its preparation method.

[0004] This method designs and fabricates a mechanically interlocked bump structure on a photosensitive chip; the bump array on the readout circuit chip is fabricated using conventional design and processes; during the focal plane flip-soldering interconnection process, the bumps at the readout circuit end are inserted into the mechanically interlocked bump structure at the photosensitive chip end to form a mechanical nested interlock, which is used to limit the random offset generated during the flip-soldering process.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] The readout circuit chip has a readout circuit bump array, which includes several bumps on the circuit chip; based on the shape of the bumps on the circuit chip, a mechanically interlocked bump structure that is nested and interlocked with all the bumps is designed and fabricated on the photosensitive chip.

[0007] The mechanically interlocked bump structure includes a lower metal recess layer and an upper metal connection layer. The surface of the upper metal connection layer has a bump groove for bump embedding. The bump groove corresponds one-to-one with the bumps on the readout circuit chip in terms of spatial position and is perfectly matched in terms of external dimensions, achieving high-precision nested interlocking.

[0008] If the diameter of the bottom end of the bump on the readout circuit chip with a center distance of C is D0 and the height is H0, then the outer diameter D1 of the bottom end of the lower metal pit layer of the mechanically interlocked bump structure on the photosensitive chip satisfies D0+2μm≤D1≤C-1μm, the inner diameter of the bottom end of the bump groove, i.e. the inner diameter of the bottom end of the upper metal connection layer, D2 satisfies D0≤D2≤D1-2μm, and the height H of the upper metal connection layer is 1~5μm.

[0009] A method for fabricating an infrared focal plane mechanically interlocked bump structure, comprising the following steps: First, fabricating a lower metal layer on a photosensitive chip; second, fabricating a lower metal pit layer; third, fabricating an upper metal interconnect layer on the pit layer; the specific fabrication steps are as follows:

[0010] 1) First photolithography: Spin-coating a thin film onto the cleaned, microscopically inspected, and dried chip sample, baking, exposure, development, and subsequent baking;

[0011] 2) Preparation of under-bump metal: Under-bump metal is prepared by ion beam sputtering. The thickness of the under-bump metal is 0.1~0.5 micrometers and the shape is a circle or square with a diameter of 4~14 micrometers.

[0012] 3) Adhesive stripping: After the chip sample is soaked in acetone, it is washed clean in acetone and alcohol solutions respectively to obtain the metal pattern array under the bumps;

[0013] 4) Growth of the underlying metal layer: The underlying metal layer of the chip's mechanically interlocked bump structure is grown using thermal evaporation or electroplating methods, with a height of 0.5~2 micrometers;

[0014] 5) Second photolithography: The metallized chip sample is spin-coated with thick resist, baked, exposed, developed, and then baked again after development;

[0015] 6) Etching to form the underlying metal pit layer: The outer diameter of the bottom end of the metal pit layer is 4~14 micrometers, and the inner diameter of the bottom end is 3~12 micrometers;

[0016] 7) Surface adhesive removal: After heating the chip sample in an acetone water bath, ultrasonic cleaning is performed to obtain the underlying metal pit layer;

[0017] 8) Growth of the upper metal layer: The upper metal layer of the chip's mechanically interlocked bump structure is grown using thermal evaporation or electroplating methods, with a thickness of 0.5~3 micrometers;

[0018] 9) Third photolithography: The chip sample with the upper metal layer grown is subjected to thick photoresist spin coating, baking, exposure, development, and post-development baking;

[0019] 10) Etching to form the upper metal bonding layer: Etching to obtain the upper metal bonding layer defined by the shape of the lower metal pit layer;

[0020] 11) Floating adhesive removal: After heating the chip sample in an acetone water bath, ultrasonic cleaning is performed to remove excess metal from the chip, obtaining a complete mechanically interlocked bump structure on the photosensitive chip.

[0021] Beneficial effects

[0022] 1. This invention can effectively limit the offset that occurs during the flip-soldering of the infrared focal plane, reduce the number of interconnect blind cells caused by the flip-soldering offset, and improve the effective pixel rate of the infrared focal plane.

[0023] 2. This invention can effectively improve the flip-soldering yield of large-area array small-pixel focal plane detectors;

[0024] 3. The method of the present invention can be applied to focal plane arrays of various specifications, and is especially suitable for small pixel arrays that are sensitive to soldering deviation. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the mechanically interlocked bump structure on the photosensitive chip and the readout circuit bumps after flip-soldering, as shown in the figure.

[0026] Figure 2 yes Figure 1 Sectional view of AA;

[0027] Figure 3 This is a schematic diagram of the fabrication process of the photosensitive chip with mechanically interlocked bump structure in this invention;

[0028] Figure 4 This is a schematic diagram of the photosensitive chip with mechanically interlocked bump structure and the readout circuit before flip-soldering in this invention;

[0029] Figure 5 This is a schematic diagram of the structure of the photosensitive chip with mechanically interlocked bump structure and the readout circuit after flip-soldering.

[0030] In the picture:

[0031] 1. Photosensitive chip;

[0032] 2. Photoresist a (under the metal hole of the photosensitive chip bump);

[0033] 3. Metal under the bump (metal under the bump of the photosensitive chip);

[0034] 4. Lower metal recess layer (lower metal recess layer of mechanical interlocking protrusion structure).

[0035] 5. Photoresist b (etching mask);

[0036] 6. Upper metal connection layer (the upper metal connection layer of the mechanically interlocked protrusion structure).

[0037] 7. Photoresist c (etching mask);

[0038] 8. Read the circuit bumps;

[0039] 9. Read the metal under the circuit bumps;

[0040] 10. Read out the circuit; Detailed Implementation

[0041] The present invention will be further described below with reference to the accompanying drawings and embodiments. The basic idea of ​​the present invention is to limit the offset generated during the flip-soldering interconnection process through a mechanically interlocking bump structure. Figure 1 This diagram illustrates the mechanically interlocked bump structure on a photosensitive chip and the flip-soldering of the readout circuit bumps. For further explanation and detail, the following description uses the flip-soldering process of an InGaAs focal plane detector with a device size of 2560×2048 and a center-to-center distance of 10μm as an example. However, these descriptions should not be construed as limiting the scope of the invention, which is defined by the appended claims.

[0042] Example: 2560×2048 element short-wave infrared InGaAs focal plane array

[0043] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, using a short-wave infrared InGaAs focal plane with a pixel center-to-center distance of 10 micrometers and an array size of 2560×2048:

[0044] The infrared focal plane consists of a photosensitive chip 1 and a readout circuit 10; the readout circuit chip has a readout circuit bump array, which includes several circuit chip bumps 8.

[0045] The basic idea of ​​this invention is to limit the offset during the flip-soldering process and effectively reduce flip-soldering deviation by designing and fabricating a mechanically interlocked bump structure on the photosensitive chip 1 that matches the bump 8 of the readout circuit. During the flip-soldering interconnection process, the center of the mechanically interlocked bump structure on the photosensitive chip end is first aligned with the center of the bump on the readout circuit end, such as... Figure 4 As shown; then the bump at the readout circuit end is inserted into the mechanically interlocked bump structure at the photosensitive chip end, forming a high-precision mechanical nested interlock, as shown. Figure 5 As shown.

[0046] The indium bump (i.e., readout circuit bump 8) on the readout circuit chip has a bottom diameter of 4 micrometers and a height of 5 micrometers, and is fabricated using conventional processes. The mechanically interlocked bump structure on the photosensitive chip is fabricated using the mechanically interlocked bump structure fabrication method described in this invention. First, a lower metal layer 3 is fabricated on the photosensitive chip; then, a lower metal pit layer 4 is fabricated; finally, an upper metal connection layer 6 is fabricated on the lower metal pit layer 4, thus fabricating the mechanically interlocked bump structure.

[0047] The specific process steps for the mechanically interlocked bump structure on the photosensitive chip are as follows: Figure 3 As shown:

[0048] 1) First photolithography: Spin-coat the cleaned, microscopically inspected and dried photosensitive chip sample with AZ4330 at a speed of 3000±500 rpm; expose and develop the spin-coated photoresist gemstone sheet sample; place the developed photosensitive chip 1 into an oven to dry;

[0049] 2) Preparation of under-bump metal: Under-bump cadmium metal was prepared by ion beam sputtering. The thickness of the under-bump metal was 0.2 μm and the shape was a circle with a diameter of 8 μm.

[0050] 3) Adhesive stripping: After the chip sample is soaked in acetone, it is washed clean in acetone and alcohol solutions respectively to obtain the metal pattern array under the bumps;

[0051] 4) Growth of the underlying metal layer: The underlying metal layer of the chip's mechanically interlocked bump structure is grown using thermal evaporation or electroplating, with a height of approximately 2 micrometers;

[0052] 5) Second photolithography: Spin-coating the metallized photosensitive chip with AZ4620 at a speed of 2500±500; exposing and developing the spin-coated photosensitive chip;

[0053] 6) Etching to form the underlying metal pit layer: The outer diameter of the bottom end of the metal pit layer is approximately 8 micrometers, and the inner diameter of the bottom end is approximately 6 micrometers;

[0054] 7) Floating adhesive peeling: After heating the chip sample in an acetone water bath, ultrasonic cleaning is performed to obtain the underlying metal pit layer; several pits are formed in the underlying metal pit layer.

[0055] 8) Growth of the upper metal layer: The upper metal layer of indium with a thickness of about 1 micrometer is grown by thermal evaporation or electroplating for the mechanical interlocking bump structure of the chip.

[0056] 9) Third photolithography: Spin-coat the photosensitive chip with the upper metal layer grown on with AZ4620 at a speed of 2500±500; expose and develop the photosensitive chip with spin-coated photoresist.

[0057] 10) Etching to form the upper metal bonding layer: Etching to obtain the upper metal bonding layer 6 defined by the shape of the lower metal pit layer 4; such as Figure 3 As shown, the upper metal connecting layer 6 replicates the shape and outline of the lower metal pit layer 4, and forms a corresponding pit structure accordingly.

[0058] 11) Floating adhesive peeling: After heating the sample in an acetone water bath for 2-3 hours, peel off the excess indium layer on the photosensitive chip. After ultrasonic cleaning for 2-6 minutes, obtain a mechanically interlocked bump structure with an outer diameter of about 8 micrometers at the bottom, an inner diameter of about 4 micrometers at the bottom, and a height of about 3 micrometers.

[0059] This method designs and fabricates a mechanically interlocked bump structure on the photosensitive chip based on the bump shape of the silicon readout circuit chip.

[0060] like Figure 4 and Figure 5 As shown, the mechanically interlocked bump structure on the photosensitive chip 1 includes a lower metal recess layer 4 and an upper metal connection layer 6. The surface of the upper metal connection layer 6 is formed with bump grooves for the circuit chip bumps 8 to be embedded. The bump grooves in the mechanically interlocked bump structure correspond one-to-one with the readout circuit chip bumps 8 in spatial position. The part of the readout circuit chip bump 8 inserted into the bump groove is perfectly matched with the bump groove in terms of external dimensions, realizing high-precision nested interlocking.

Claims

1. An infrared focal plane mechanically interlocked bump structure, wherein the infrared focal plane is composed of a photosensitive chip (1) and a readout circuit (10); the readout circuit chip has a readout circuit bump array, the readout circuit bump array including a plurality of circuit chip bumps (8); the bump array on the readout circuit chip is fabricated using conventional design and process, characterized in that: A mechanically interlocked bump structure is designed and fabricated on the photosensitive chip (1) and nested and interlocked with the bumps (8) of the circuit chip; The mechanically interlocked bump structure on the photosensitive chip (1) includes a lower metal pit layer (4) and an upper metal connection layer (6). The surface of the upper metal connection layer (6) has a bump groove for the circuit chip bump (8) to be embedded. The bump groove in the mechanically interlocked bump structure corresponds one-to-one with the circuit chip bump (8) in spatial position. During the reverse soldering interconnection process, the circuit chip bump (8) is inserted into the bump groove of the mechanically interlocked bump structure at the end of the photosensitive chip to form a mechanical nested interlock, which is used to limit the random offset generated during the reverse soldering process.

2. The infrared focal plane mechanical interlocking convex point structure according to claim 1, characterized in that: The bump slots in the mechanically interlocked bump structure are perfectly matched with the bumps (8) of the readout circuit chip in terms of external dimensions, achieving high-precision nested interlocking; If the bottom diameter of the readout circuit chip bump (8) with a center distance of C is D0 and the height is H0, then the bottom outer diameter D1 of the lower metal pit layer (4) of the mechanically interlocked bump structure on the photosensitive chip (1) satisfies D0+2μm≤D1≤C-1μm, the bottom inner diameter of the bump groove, i.e. the bottom inner diameter D2 of the upper metal connection layer (6), satisfies D0≤D2≤D1-2μm, and the height H of the upper metal connection layer (6) is 1~5μm.

3. A method for preparing an infrared focal plane mechanically interlocked bump structure based on claim 1 or 2, characterized in that: The preparation method of the mechanically interlocked bump structure on the photosensitive chip is as follows: First step, prepare the lower metal (3) of the bump on the photosensitive chip (1); second step, prepare the lower metal pit layer (4); third step, prepare the upper metal connection layer (6) on the lower metal pit layer (4) to prepare the mechanically interlocked bump structure. The specific fabrication steps for the mechanically interlocked bump structure are as follows: 1) First photolithography: Spin-coating a thin film onto the cleaned, microscopically inspected, and dried chip sample, baking, exposure, development, and subsequent baking; 2) Preparation of under-bump metal: Under-bump metal (3) is prepared by ion beam sputtering, and the shape is circular or square; 3) Adhesive stripping: After the chip sample is soaked in acetone, it is washed clean in acetone and alcohol solutions respectively to obtain the metal pattern array under the bumps; 4) Growth of the underlying metal layer: The underlying metal layer of the chip's mechanically interlocked bump structure is grown using thermal evaporation or electroplating methods; 5) Second photolithography: The metallized chip sample is spin-coated with thick resist, baked, exposed, developed, and then baked again after development; 6) Etching forms the underlying metal pit layer; 7) Floating adhesive peeling: After heating the chip sample in an acetone water bath, ultrasonic cleaning was performed to obtain the underlying metal pit layer (4). 8) Growth of the upper metal layer: The upper metal layer of the chip's mechanically interlocked bump structure is grown using thermal evaporation or electroplating. 9) Third photolithography: The chip sample with the upper metal layer grown is subjected to thick photoresist spin coating, baking, exposure, development, and post-development baking; 10) Etching to form an upper metal bonding layer: Etching to obtain an upper metal bonding layer (6) defined by the shape of the lower metal pit layer (4); 11) Floating adhesive removal: After heating the chip sample in an acetone water bath, ultrasonic cleaning is performed to remove excess metal from the chip, obtaining a complete mechanically interlocked bump structure on the photosensitive chip.

4. The method for preparing an infrared focal plane mechanically interlocked bump structure according to claim 3, characterized in that: In step 2), the thickness of the metal (3) under the bump is 0.1~0.5 micrometers, and the shape is a circle or square with a diameter of 4~14 micrometers; In step 4), the height of the metal layer below the mechanically interlocked bump structure is 0.5~2 micrometers; In step 6), the outer diameter of the bottom end of the lower metal pit layer is 4~14 micrometers, and the inner diameter of the bottom end is 3~12 micrometers; In step 8), the thickness of the metal layer above the chip's mechanically interlocked bump structure is 0.5 to 3 micrometers.

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