Image sensing device

Abstract

Image sensing devices are disclosed. In an embodiment, an image sensing device includes an active pixel region and a peripheral region. The peripheral region is disposed adjacent to at least one side of the active pixel region and includes a light scatter suppression layer, a first base layer spaced apart from the light scatter suppression layer, and a second base layer covering at least a portion of each of the light scatter suppression layer and the first base layer.

Description

Technical Field

[0001] The technology and implementation disclosed in this patent document generally relate to an image sensing device capable of generating image data by sensing light. Background Technology

[0002] Image sensing devices capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With advancements in industries such as automotive, medical, computer, and communications, the demand for high-performance image sensing devices is constantly growing across various fields, including smartphones, digital cameras, gaming consoles, IoT (Internet of Things), robotics, security cameras, and medical miniature cameras.

[0003] Image sensing devices can be broadly categorized into charge-coupled device (CCD) image sensing devices and complementary metal-oxide-semiconductor (CMOS) image sensing devices. Compared to CMOS image sensing devices, CCD image sensing devices offer better image quality, but they tend to consume more power and are larger. CMOS image sensing devices, on the other hand, are smaller and consume less power than CCD image sensing devices. Furthermore, CMOS sensors are manufactured using CMOS fabrication technology, allowing the photosensitive element and other signal processing circuitry to be integrated into a single chip, thus enabling the production of miniaturized image sensing devices at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the Invention

[0004] Various embodiments of the disclosed technology relate to an image sensing device with improved processability or enhanced yield.

[0005] In an embodiment of the disclosed technology, a semiconductor device may include: an active pixel region; and a peripheral region disposed on at least one side of the active pixel region and configured to include a light scattering suppression layer, a first base layer spaced apart from the light scattering suppression layer, and a second base layer covering at least a portion of each of the light scattering suppression layer and the first base layer.

[0006] In some implementations, the second base layer may extend to the active pixel region. The image sensing device also includes a lens layer, wherein the lens layer comprises a plurality of nanostructures spaced apart from each other on the second base layer in the active pixel region.

[0007] In some implementations, the lens layer may also include a dielectric layer disposed between multiple nanostructures.

[0008] In some implementations, the image sensing device may further include: a semiconductor layer disposed below each of the light scattering suppression layer and the first base layer, and including a photoelectric conversion region; and a light blocking layer disposed on the semiconductor layer, and including a first portion and a second portion. The first portion may be disposed below the light scattering suppression layer; the second portion may be disposed below the first base layer.

[0009] In some implementations, the light-blocking layer may include a third portion, through which the first and second portions are integrally connected to each other.

[0010] In some implementations, the third part can be formed as a contact with the second base layer.

[0011] In some implementations, the second base layer may extend between the first base layer and the light scattering suppression layer.

[0012] In some implementations, the peripheral region may further include: a light-blocking region having a light-blocking layer thereon; and a pad region disposed on one side of the light-blocking region and configured to include input / output (I / O) pads, wherein a first base layer is disposed in each of the pad region and the light-blocking region.

[0013] In some implementations, the second base layer may extend from the first base layer onto the light scattering suppression layer; and the second base layer may include a first top surface having a first height and a second top surface having a second height different from the first height. The first top surface may overlap with the light scattering suppression layer in a plane; and the second top surface may overlap with the space between the first base layer and the light scattering suppression layer in a plane.

[0014] In some implementations, the second base layer may include a third top surface in the plane having a third height in the region overlapping with the first base layer, wherein the third height is different from the second height.

[0015] In some implementations, at least one of the first base layer and the second base layer may include at least one of epoxy resin, polyurethane resin, polyester resin, acrylic resin and silicone resin.

[0016] In some implementations, the first base layer may include materials different from those of the second base layer.

[0017] In another embodiment of the disclosed technology, an image sensing device may include: an active pixel region configured to include a semiconductor layer having a photoelectric conversion region; and a peripheral region disposed on at least one side of the active pixel region and configured to include a light scattering suppression layer disposed on the semiconductor layer extending from the active pixel region and a base layer covering at least a portion of the light scattering suppression layer, wherein the base layer includes a recessed groove portion in the direction of the top surface of the semiconductor layer.

[0018] In some implementations, the groove portion may be located outside the end of the light scattering suppression layer in the plane.

[0019] In some implementations, the groove portion can be formed as a line extending along the outer surface of the end of the light scattering suppression layer.

[0020] In some implementations, the base layer may include a first base layer spaced apart from the light scattering suppression layer and a second base layer disposed on the first base layer, wherein the second base layer includes a second base layer formed to cover at least a portion of the first base layer and the light scattering suppression layer.

[0021] In some implementations, the peripheral region may include: a pad region where input / output (I / O) pads exposed from the semiconductor layer are located; and a light-blocking region disposed between the pad region and the active pixel region. A recessed portion may be disposed within the light-blocking region.

[0022] In some implementations, the peripheral region may include: a pad region in which input / output (I / O) pads exposed from the semiconductor layer are located; a light-blocking region disposed between the pad region and the active pixel region; and a margin region located outside the pad region, wherein a recessed portion is disposed in the margin region.

[0023] In another embodiment of the disclosed technology, an image sensing device may include: a semiconductor layer including a photoelectric conversion region; a light scattering suppression layer disposed on the semiconductor layer; a first base layer disposed on the semiconductor layer and spaced apart from the light scattering suppression layer; and a second base layer configured to cover the light scattering suppression layer and the first base layer. The second base layer may include: a first region formed to overlap the light scattering suppression layer in a plane; a second region formed to overlap the first base layer in a plane; and a third region disposed between the first region and the second region, wherein the third region has a top surface recessed into the semiconductor layer.

[0024] In some implementations, the image sensing device may further include a color filter layer disposed on a semiconductor layer, wherein the second base layer includes a region extending from the first region to the top surface of the color filter layer.

[0025] It will be understood that both the above general description and the following detailed description of the disclosed technology are illustrative and explanatory, intended to provide further explanation of the claimed disclosed technology. Attached Figure Description

[0026] The above and other features and advantages of the disclosed technology will become readily apparent when considered in conjunction with the accompanying drawings, with reference to the following detailed description.

[0027] Figure 1 This is a schematic diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0028] Figure 2 This illustrates some implementations based on the disclosed technology. Figure 1 A plan view of a portion of the image sensing device shown.

[0029] Figure 3 This illustrates some implementations based on the disclosed technology. Figure 2 The image sensing device shown is a cross-sectional view of an example captured by line I-I'.

[0030] Figure 4A This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of an example of region (A) shown.

[0031] Figure 4B This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of an example of region (B) shown.

[0032] Figure 5A This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of another example of region (A) shown.

[0033] Figure 5B This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of an example of region (B) shown.

[0034] Figure 6A This illustrates some implementations based on the disclosed technology. Figure 2 A cross-sectional view of another example of an image sensing device captured by line I-I'.

[0035] Figure 6B This illustrates some implementations based on the disclosed technology. Figure 6A An enlarged cross-sectional view of an example of region (C) shown.

[0036] Figures 7A to 7E This is a cross-sectional view illustrating an example of a method for manufacturing an image sensing device based on some embodiments of the disclosed technology. Detailed Implementation

[0037] This patent document provides an implementation and example of an image sensing device capable of generating image data by sensing light, which can be used in a configuration that substantially solves one or more technical or engineering problems and mitigates some limitations or disadvantages encountered in other image sensing devices. Some implementations of the disclosed technology relate to an image sensing device with improved processability or higher yield. Recognizing the above-mentioned problems, some embodiments of the disclosed technology provide an image sensing device comprising a first base layer formed over a peripheral region, thereby achieving improved processability and yield.

[0038] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts. While the disclosed technology is readily adapted to various modifications and alternatives, specific embodiments are shown in the drawings as examples. However, the disclosed technology should not be construed as being limited to the embodiments set forth herein.

[0039] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents, and / or substitutions of the embodiments. Embodiments of the disclosed technology can provide various effects that can be directly or indirectly identified by the disclosed technology.

[0040] Figure 1 This is a schematic diagram illustrating an example of an image sensing device 1 based on some implementations of the disclosed technology.

[0041] Reference Figure 1 The image sensing device 1 according to an example embodiment of the disclosed technology may include a timing control circuit 11, a drive control circuit 12, a pixel array 13, and a readout circuit 14. Figure 1 The components of the image sensing device 1 shown are discussed as examples only, and this patent document covers numerous other changes, substitutions, variations, alterations, and modifications. In this patent document, the term "pixel" may be used to refer to an image sensing pixel configured to detect incident light to generate an electrical signal carrying an image in the incident light.

[0042] The timing control circuit 11 can provide timing signals and control signals to at least one of the drive control circuit 12 and the readout circuit 14. The drive control circuit 12 can enable the pixel array 13 to perform specific operations on the pixels included in the corresponding rows based on the timing signals and control signals provided from the timing control circuit 11.

[0043] The drive control circuit 12 can generate a row selection signal to select at least one row from multiple rows. Pixels of the row selected by the drive control circuit 12 can sequentially send a reference signal and an image signal to the readout circuit 14. Here, the reference signal and the image signal are analog signals. The reference signal can be an electrical signal provided to the readout circuit 14 when the floating diffusion region is reset, and the image signal can be an electrical signal provided to the readout circuit 14 when the photocharge generated by the imaging pixel accumulates in the floating diffusion region.

[0044] Pixel array 13 may include a plurality of pixels (PX) arranged in rows and columns. The plurality of pixels may be connected to a row driver via a plurality of row lines extending in the row direction.

[0045] Each of the plurality of pixels included in pixel array 13 can output a pixel signal in response to incident light received from the outside. Each of the plurality of pixels can be arranged in a two-dimensional (2D) structure. For example, each of the plurality of pixels can be arranged in a matrix structure. The plurality of pixels can be arranged in a first direction and a second direction. For example, the plurality of pixels can be arranged in a row direction and a column direction.

[0046] In the light incident on a pixel, light of a specific wavelength band (e.g., red, green, or blue light) can pass through a filter arranged in the active pixel, and the light that has passed through the filter can be focused onto at least one photoelectric conversion element. The photoelectric conversion element can generate photocharge in response to the incident light. The pixel can generate an electrical signal in response to the amount of photocharge generated.

[0047] When a pixel operates under conditions where the amount of incident light is very small or nonexistent (hereinafter referred to as dark conditions), the pixel can generate a dark signal. The signal generated under dark conditions can be a signal corresponding to the noise component generated inside the image sensing device 1.

[0048] The readout circuit 14 can sample the electrical signals output from the pixel array 13, convert the sampled electrical signals into digital signals, and output the digital signals to the image signal processor. For example, the readout circuit 14 may include a correlated dual sampler (CDS), an analog-to-digital converter (ADC), an output buffer, a column driver, etc.

[0049] Figure 2 This illustrates some implementations based on the disclosed technology. Figure 1 A plan view of a portion of the image sensing device 1 shown.

[0050] Reference Figure 2 The image sensing device 1 may include an active pixel area (APS) and a peripheral area (PR).

[0051] Active pixel area (APS) can include Figure 1The pixel array 13 shown represents a region of active pixels arranged in a two-dimensional (2D) matrix. Each active pixel may include at least one photoelectric conversion element. Each active pixel may use the photoelectric conversion element to generate charge from incident light and may process the charge to output an electrical signal. Each active pixel may include at least one of a transfer transistor, a reset transistor, an amplification transistor, or a selection transistor.

[0052] The peripheral region (PR) may be arranged adjacent to at least one side of the active pixel region (APS). For example, the peripheral region (PR) may be arranged to surround the active pixel region (APS). The peripheral region (PR) may include a light-blocking region (OB) disposed outside the active pixel region (APS) and a pad region (PAD) disposed outside the light-blocking region (OB). The light-blocking region (OB) may be located between the active pixel region (APS) and the pad region (PAD). In an example embodiment, the pad region (PAD) may surround all side surfaces of the light-blocking region (OB). In another embodiment, the pad region (PAD) may not surround some portions of the side surfaces of the light-blocking region (OB).

[0053] The light-blocking region (OB) can be used to prevent or block incident light from passing through the semiconductor layer 100 (see...). Figure 3 The light-blocking region (OB) can include photosensitive pixels (referred to as "black pixels") whose incident light is blocked by the light-blocking region (OB), such that the electrical signal output by the black pixels in the light-blocking region (OB) is generated without incident light, and is therefore an electrical signal representing the level of current or photocharge generated in the absence of incident light. Therefore, the electrical signal from the black pixels can be used to correct the black level or dark level of the active pixels. For example, a black pixel can be configured to output... Figure 1 The pixels of the dark signal.

[0054] The pad area (PAD) may include input / output (I / O) pads 150 for signal communication with external devices of the image sensing device 1 (see [link]). Figure 3 The area of ​​the image sensing device 1. In some implementations, I / O pads refer to pads configured to send and receive electrical signals. The internal circuitry of the image sensing device 1 can be electrically connected to external devices via the pad area (PAD).

[0055] Figure 3 This illustrates some implementations based on the disclosed technology. Figure 2 The image sensing device shown is a cross-sectional view of an example captured by line I-I'.

[0056] exist Figure 3 In this context, for ease of illustration, the size ratio between adjacent nanostructures and components may be exaggerated and may differ from the actual size ratio.

[0057] Reference Figure 3 The image sensing device 1 may include a semiconductor layer 100, an interconnect layer 200, and a light receiving layer 300.

[0058] Semiconductor layer 100 may include a first surface configured to receive incident light and a second surface opposite to or away from the first surface. Light receiving layer 300 may face the first surface, and interconnect layer 200 may face the second surface. Semiconductor layer 100 may be a layer configured to generate charge by converting incident light.

[0059] The semiconductor layer 100 may include a semiconductor substrate 110 and a pixel isolation portion 120.

[0060] The semiconductor substrate 110 may include silicon, germanium, silicon-germanium, group II-VI compound semiconductors, or group III-V compound semiconductors. The semiconductor substrate 110 may include impurities of a first conductivity type.

[0061] Semiconductor substrate 110 may include photoelectric conversion regions (PD1, PD2) that generate charge from incident light (see...) Figure 4A Each of the photoelectric conversion regions (PD1, PD2) can include... Figure 1 and Figure 2 The photoelectric conversion element may include at least one of a photodiode, a phototransistor, a gate, or a pinned photodiode. In an example embodiment, each of the photoelectric conversion regions (PD1, PD2) may be a region within the semiconductor substrate 110 that includes an impurity of a second conductivity type different from the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0062] Pixel isolation portion 120 may be disposed in a trench penetrating to a predetermined depth in semiconductor substrate 110. For example, pixel isolation portion 120 may be formed as a deep trench isolation (DTI) structure. Pixel isolation portion 120 can electrically isolate multiple active pixels from each other. Pixel isolation portion 120 may include an insulating material such as silicon oxide, silicon nitride, or a high dielectric constant (high k) material. However, in some example embodiments, pixel isolation portion 120 may include a pad layer comprising an insulating material and a conductive material layer such as polysilicon.

[0063] In the example implementation, the interconnect layer 200, the semiconductor layer 100, and the light-receiving layer 300 may be stacked sequentially. In this case, Figure 2 In each of the active pixel region (APS), light blocking region (OB), and pad region (PAD), the semiconductor layer 100 may be disposed above the interconnect layer 200 and below the light receiving layer 300.

[0064] In the semiconductor layer 100, the photoelectric conversion regions (PD1, PD2) of the semiconductor substrate 110 (see...) Figure 4A Each of the photoelectric conversion regions (PD1, PD2) can be located within an active pixel region (APS) and a light-blocking region (OB). The photoelectric conversion regions (PD1, PD2) can serve as photoelectric conversion elements for active pixels within the active pixel region (APS) and as photoelectric conversion elements for black pixels within the light-blocking region (OB). In an example embodiment, some photoelectric conversion regions within the light-blocking region (OB) can be dummy regions of dummy pixels. In some implementations, the term "dummy pixel" refers to a pixel constructed like an active pixel but not used for detecting incident light for actual image capture, but rather for serving other purposes (e.g., ensuring process uniformity, enhancing circuit stability, and providing a reference for black level calibration as a dark pixel).

[0065] The pixel isolation portion 120 can be disposed in the active pixel region (APS). Alternatively, the pixel isolation portion 120 can also be disposed in some portions of the light blocking region (OB) (e.g., the region where black pixels are arranged).

[0066] Semiconductor layer 100 may also include input / output (I / O) pads 150 partially exposed to the outside in pad regions (PADs). For example, the input / output (I / O) pads 150 may be configured such that the top surface of the input / output (I / O) pads 150 is exposed to the outside through pad openings (OP_PADs) formed to penetrate the base layer (BL). The input / output (I / O) pads 150 may be electrically connected to circuitry of interconnect layer 200 or semiconductor layer 100. Although for ease of description, the input / output (I / O) pads 150 are shown as embedded in semiconductor substrate 110, the disclosed technology is not limited thereto. It should be noted that the input / output (I / O) pads 150 may be implemented in various forms, as long as at least a portion of the input / output (I / O) pads 150 is exposed to the outside. For example, the input / output (I / O) pads 150 may be disposed on the top surface of semiconductor substrate 110.

[0067] Interconnect layer 200 may include elements and interconnects configured to carry or process electrical signals generated by photoelectric conversion elements and to carry control signals for controlling active pixels. Interconnect layer 200 may include: multiple interconnects 210 comprising at least one layer (see...). Figure 4A ) and the interlayer insulation layer 220 covering the interconnect 210 (see Figure 4A ).

[0068] The interconnect layer 200 may include a gate structure that contacts the bottom surface of the semiconductor substrate 110. The gate structure may be formed together with some regions of the semiconductor substrate 110 (e.g., source / drain regions). Figure 1At least one of the described transfer transistor, reset transistor, amplification transistor, or selection transistor.

[0069] Interconnect layer 200 may cover one surface of semiconductor layer 100 beneath semiconductor layer 100. Interconnect lines 210 of interconnect layer 200 (see...) Figure 4A It can be set in at least one of the active pixel area (APS), light blocking area (OB), and pad area (PAD).

[0070] The light receiving layer 300 may include a color filter layer 310, a grid 315, a light scattering suppression layer 320, a light blocking layer 330, a base layer (BL), and a lens layer 340.

[0071] The color filter layer 310 may include color filters corresponding to the photoelectric conversion regions (PD1, PD2) of the semiconductor substrate 110, respectively. The color filters may include a green filter that transmits green light while blocking other colors, a red filter that transmits red light while blocking other colors, and a blue filter that transmits blue light while blocking other colors. The color filters can selectively transmit incident light of a specific wavelength to determine the type of light received by the photoelectric conversion regions (PD1, PD2) or the type of active pixel. The color filter layer 310 may be a layer in which multiple color filters are arranged in a two-dimensional pattern (e.g., a Bayer pattern). The color filter layer 310 may be disposed on the semiconductor layer 100 in the active pixel region (APS) to capture color information of the image carried in the incident light.

[0072] The grid 315 can be disposed between multiple color filters and can prevent light reflection or guide light so that incident light can smoothly reach the photoelectric conversion regions (PD1, PD2). The bottom surface of the grid 315 can be located at substantially the same height as the bottom surface of the color filters. The grid 315 has a lower height than the color filters, and the color filter layer 310 can cover the grid 315. The grid 315 may include a conductive material. The grid 315 can be disposed above the semiconductor layer 100 in the active pixel region (APS).

[0073] The light scattering suppression layer 320 reduces or suppresses light scattering and can be arranged spaced apart from the color filter layer 310. The light scattering suppression layer 320 can be disposed on the semiconductor layer 100 in the light-blocking region (OB). The light scattering suppression layer 320 prevents light (e.g., light reflected from the semiconductor layer 100 that is not directly incident on it) from being scattered into the photoelectric conversion regions (PD1, PD2) of the active pixel regions (APS). In some implementations, the light scattering suppression layer 320 may comprise the same material as the color filter of the color filter layer 310. At least a portion of the light scattering suppression layer 320 can be formed using the same process as the color filter layer 310.

[0074] In an example embodiment, the light scattering suppression layer 320 may include a plurality of patterns 321 and a cover layer 322 covering the plurality of patterns 321. The plurality of patterns 321 may filter light of different wavelengths from the cover layer 322. For example, the cover layer 322 may include the same material as a blue color filter, and the plurality of patterns 321 may include the same material as a green color filter. In this case, the plurality of patterns 321 may be formed using the same process as the green color filter of the color filter layer 310. However, the configuration and shape of the light scattering suppression layer 320 are not limited thereto and may be modified in various ways.

[0075] A light-blocking layer 330 may be disposed on the semiconductor layer 100 in the light-blocking region (OB). The light-blocking layer 330 may include a portion disposed between the semiconductor layer 100 and the light scattering suppression layer 320. The light scattering suppression layer 320 may cover at least a portion of the top surface of the light-blocking layer 330. The light-blocking layer 330 prevents light from incident on the semiconductor layer 100. The light-blocking layer 330 may include a material that reflects or absorbs incident light. For example, the light-blocking layer may include materials such as chromium (Cr), copper (Cu), tungsten (W), manganese dioxide (MnO2), or graphite.

[0076] The base layer (BL) may cover at least a portion of the color filter layer 310, the light scattering suppression layer 320, and the light blocking layer 330. The base layer (BL) may be disposed within the active pixel region (APS), the light blocking region (OB), and the pad region (PAD). The base layer (BL) may provide a flat upper surface for forming the lens layer 340. The base layer (BL) may include a transparent material. The base layer (BL) may include thermosetting or photocurable materials, such as epoxy resin, polyurethane resin, polyester resin, acrylic resin, silicone resin, etc.

[0077] The base layer (BL) may include a first base layer BL1 and a second base layer BL2 covering at least a portion of the first base layer BL1. The first base layer BL1 may be disposed on at least one of a light blocking region (OB) and a pad region (PAD) serving as a peripheral region (PR). The second base layer BL2 may be disposed on the peripheral region (PR) and an active pixel region (APS). The first base layer BL1 may include a different material than the second base layer BL2. However, in some embodiments, the first base layer BL1 may include the same material as the second base layer BL2, and even if the first and second base layers (BL1, BL2) include the same material, the boundary between the first base layer BL1 and the second base layer BL2 may be distinguished according to process conditions. The first base layer BL1 may be spaced apart from the light scattering suppression layer 320.

[0078] The lens layer 340 may include a support layer 345 on the base layer (BL), a plurality of nanostructures 341, and a dielectric layer 343.

[0079] The support layer 345 may be a padding layer that conformally covers the top surface of the base layer (BL). The support layer 345 may include an insulating material such as silicon oxide or low-temperature oxide (LTO).

[0080] Multiple nanostructures 341 may be arranged on a support layer 345, with spacing between adjacent nanostructures. The multiple nanostructures 341 may be in contact with the top surface of the support layer 345. The multiple nanostructures 341 may be arranged such that the phase of incident light varies according to their positions. Each of the multiple nanostructures 341 may have a size smaller than the wavelength of visible light or the blue wavelength, for example, a width or height in the range of a few nanometers (nm) to several hundred nanometers. The multiple nanostructures 341 may include a dielectric material with a refractive index higher than that of air. For example, the multiple nanostructures 341 may include metal oxides such as titanium dioxide, gallium nitride, silicon nitride, or silicon.

[0081] A dielectric layer 343 may be disposed between multiple nanostructures 341 on the support layer 345. The dielectric layer 343 may comprise a material with a refractive index lower than that of the multiple nanostructures 341, such as silicon oxide, silicon nitride, aluminum oxide, etc. However, in some embodiments, the lens layer 340 may omit the structure of a separate dielectric layer 343, and air may be used as the dielectric material.

[0082] Aberration compensation can be achieved by using nanostructures that provide metasurfaces instead of curved lens structures with significant thickness, providing an image sensing device 1 with relatively small thickness. The shape and arrangement pattern of the multiple nanostructures 341 can be modified in various ways according to the optical function to be achieved by the metalens.

[0083] Figure 4A This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of an example of region (A) shown.

[0084] Reference Figure 4A The photoelectric conversion regions (PD1, PD2) are classified as a first photoelectric conversion region (PD1) and a second photoelectric conversion region (PD2) arranged spaced apart from each other. The first photoelectric conversion region (PD1) and the second photoelectric conversion region (PD2) can form a unit pixel. In this case, the pixel isolation portion 120 may include a main pixel isolation portion 121 that separates the unit pixels from each other and an auxiliary pixel isolation portion 122 disposed between the first photoelectric conversion region (PD1) and the second photoelectric conversion region (PD2). The main pixel isolation portion 121 may be formed in a trench with a depth equal to or greater than the depth of the auxiliary pixel isolation portion 122.

[0085] The color filter layer 310 may include a first color filter 310a and a second color filter 310b. The first color filter 310a and the second color filter 310b may be different types of color filters. For example... Figure 3 As shown, the color filter layer 310 may have green, red, and blue color filters arranged in a Bayer pattern, and each of the first color filter 310a and the second color filter 310b may be one of the green, red, and blue color filters. For example, the first color filter 310a may be a green color filter, and the second color filter 310b may be a red color filter. The first color filter 310a may have a smaller height than the second color filter 310b, but may have substantially the same height depending on some embodiments. Each of the first color filter 310a and the second color filter 310b may correspond to one of the unit pixels. For example, the first color filter 310a may filter the wavelength of light received by the first photoelectric conversion region (PD1) and the second photoelectric conversion region (PD2), and may allow light of a specific wavelength to pass through.

[0086] Mesh 315 may include a bottom surface with the same height as the bottom surface of color filter layer 310. For example, the bottom surface of mesh 315 may be coplanar with the bottom surface of color filter layer 310. Mesh 315 may be arranged to correspond to the main pixel isolation portion 121. Figure 4A In the diagram, grid 315 is shown as being arranged perpendicularly offset from the main pixel isolation portion 121, but is not limited thereto. It should be noted that grid 315 can also be arranged according to the distance from the active pixel region APS (see [reference]). Figure 2 The distance to the center of the image sensing device or the design changes of the image sensing device can be modified in various ways.

[0087] although Figure 4A A semiconductor layer 100 based on a 2PD (double PD) structure is shown (see [reference]). Figure 3 ) and light receiving layer 300 (see Figure 3 However, the disclosed technology is not limited to this. It should be noted that the number of photoelectric conversion regions corresponding to a unit pixel can be changed to 1 or 4, etc.

[0088] Within the base layer (BL), the second base layer BL2 can cover the active pixel area (APS) (see...). Figure 3 At least a portion of the top surface of the color filter layer 310 in the image. The second base layer BL2 provides a flat surface for forming the lens layer 340 of the active pixel region (APS). Since the support layer 345 is formed on the second base layer BL2 with a uniform thickness and the nanostructures 341 are formed on the second base layer BL2 having a flat upper surface, multiple nanostructures 341 can have substantially the same height. Therefore, a highly reliable metalens can be realized.

[0089] In the active pixel region (APS), the thickness of the second base layer BL2 can be greater than the average thickness of the color filter layer 310.

[0090] Figure 4B This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of an example of region (B) shown.

[0091] Reference Figure 4B The first base layer (BL) in the base layer (BL) can be set in the outer region PR (see Figure 2 In, and not set in the active pixel area APS (see Figure 2 In the process, the first base layer BL1 may include a top surface having a height substantially the same as the top surface of the light scattering suppression layer 320. However, depending on the process conditions, the height of the top surface of the first base layer BL1 may differ from the height of the top surface of the light scattering suppression layer 320 by a specific length, or it may be formed at a height higher than the top surface of the light scattering suppression layer 320. The first base layer BL1 may be used to make... Figure 3 The first base layer BL1 is a layer that minimizes the step difference caused by the color filter layer 310 or the light scattering suppression layer 320. In some implementations, the first base layer BL1 may be configured to prevent some components from remaining in the peripheral region (PR) during subsequent processes (e.g., planarization processes) for forming the lens layer 340, thereby allowing the image sensing device 1 to be fabricated with improved yield. For example, when performing deposition and planarization processes to form multiple nanostructures 341 (see... Figure 4A When the first base layer BL1 compensates for the color filter layer 310 (see...), the first base layer BL1 can compensate for the color filter layer 310 (see...). Figure 4A The thickness difference between the light scattering suppression layer 320 and the light scattering suppression layer 320. Therefore, the height of the top surface of the second base layer BL2 can be adjusted to be the same or similar in both the active pixel region (APS) and the light blocking region (OB), thereby preventing the conductive material used for the multiple nanostructures 341 from remaining in the planarization process.

[0092] The light-blocking layer 330 may be formed on the semiconductor substrate 110 with a uniform thickness. The light-blocking layer 330 may include a layer disposed on the semiconductor layer 100 (see [reference]). Figure 3 The semiconductor substrate 110 and the light scattering suppression layer 320 are disposed in a first portion 330_1, a second portion 330_2, and a third portion 330_3. The first to third portions (330_1, 330_2, 330_3) may have a uniform thickness and may be integrally connected to each other.

[0093] The first base layer BL1 may be disposed on the light blocking layer 330 and spaced apart from the light scattering suppression layer 320. The first base layer BL1 may be spaced apart from the light scattering suppression layer 320 in a first direction parallel to the top surface of the semiconductor substrate 110, taking into account process allowances. The light scattering suppression layer 320 may be disposed on a first portion 330_1 of the light blocking layer 330, and the first base layer BL1 may be disposed on a second portion 330_2 of the light blocking layer 330.

[0094] The second base layer BL2 may include settings in the active pixel region APS (see...). Figure 3 and Figure 4A The portion within ) and the settings in the outer area PR (see Figure 3 In the peripheral region (PR), the second base layer BL2 may cover at least a portion of the first base layer BL1 and the light scattering suppression layer 320. The second base layer BL2 may include a portion extending between the light scattering suppression layer 320 and the first base layer BL1 while covering the top surface of the light scattering suppression layer 320 and the first base layer BL1. For example, the second base layer BL2 may extend between the light scattering suppression layer 320 and the first base layer BL1 and may contact a third portion 330_3 of the light blocking layer 330.

[0095] The second base layer BL2 may include a first top surface having a first height (h1) from the top surface of the light blocking layer 330 in a region perpendicularly overlapping with the light scattering suppression layer 320 or in a region above the first portion 330_1. The second base layer BL2 may also include a second top surface having a second height (h2) from the top surface of the light blocking layer 330 in a region perpendicularly overlapping with the first base layer BL1 or in a region above the second portion 330_2. The second base layer BL2 may also include a third top surface having a third height (h3) from the top surface of the light blocking layer 330 in a region disposed between the first base layer BL1 and the light scattering suppression layer 320 or in a region above the third portion 330_3. The third height (h3) may be less than the first height (h1), and the third height (h3) may be less than the second height (h2).

[0096] The second base layer BL2 may include a recessed portion (BLr) on the third portion 330_3, recessed toward the top surface of the semiconductor substrate 110. The top surface of the recessed portion (BLr) may have a third height (h3) smaller than the height of the adjacent region. The recessed portion (BLr) may be a portion formed during the process of forming the second base layer BL2 by filling not only a space relatively larger than the adjacent region, but also the region between the first base layer BL1 and the light scattering suppression layer 320. The recessed portion (BLr) may be located outside the end of the light scattering suppression layer 320. In some embodiments, the recessed portion (BLr) may have a line shape extending in a plane along the outer surface of the end of the light scattering suppression layer 320. In this case, the recessed portion (BLr) may have a line shape extending in a second direction perpendicular to a first direction that spaces the light scattering suppression layer 320 and the first base layer BL1 apart from each other. The recessed portion (BLr) may be located in the light blocking region OB (see Figure 4A )middle.

[0097] In the following description, an image sensing apparatus based on some embodiments of the disclosed technology will be described with reference to the accompanying drawings. For ease of description, the following embodiments will focus on the lens layer and the base layer, but other implementations are also possible. It should be understood that, where necessary, the disclosed technology also includes combinations of these embodiments.

[0098] Figure 5A This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of another example of region (A) shown.

[0099] Figure 5A The image sensing device (1a) according to an example embodiment is shown with Figure 4A The area corresponding to area "A".

[0100] Reference Figure 5A The image sensing device (1a) may have the same characteristics as... Figure 4A The image sensing device 1 has different lens layers 340'. The lens layer 340' may also include a support layer 345, a plurality of nanostructures 341a on the support layer 345, and a conductive pad layer 341b disposed between the support layer 345 and the plurality of nanostructures 341a. The conductive pad layer 341b may be a pad layer with a uniform thickness on the support layer 345.

[0101] The conductive pad layer 341b may comprise the same material as the plurality of nanostructures 341a (e.g., titanium oxide). The conductive pad layer 341b may be integrally attached to the plurality of nanostructures 341a. The conductive pad layer 341b may be attached to the bottom surface of each of the plurality of nanostructures 341a.

[0102] like Figures 3 to 4B As shown, when the base layer (BL) is formed separately in two stages, it can provide PR in the outer region (see...). Figure 3 The base layer (BL) in the active pixel region (APS) and the active pixel region (APS) has no step difference. Therefore, even when the lens layer 340' includes the conductive pad layer 341b, the yield of the image sensing device (1a) can be improved.

[0103] In some embodiments, the lens layer 340' may use air as a dielectric layer and may not include separate material layers between the plurality of nanostructures 341a. In this case, even if the spacing between the plurality of nanostructures 341a is not filled with separate material layers, the conductive pad layer 341b is integrally connected to the plurality of nanostructures 341a while being disposed beneath them, allowing the conductive pad layer 341b to function as a support structure to prevent breakage or damage to the plurality of nanostructures 341a. However, in some embodiments, the lens layer 340' may include separate dielectric layers between the plurality of nanostructures 341a.

[0104] Figure 5B This illustrates some implementations based on the disclosed technology. Figure 3 An enlarged cross-sectional view of an example of region (B) shown.

[0105] Specifically, Figure 5B The image sensing device (1b) according to an example embodiment is shown with Figure 4B The area corresponding to the "B" area.

[0106] Reference Figure 5B In the first base layer (BL1') of the image sensing device (1b), the vertical thickness of the end of the first base layer (BL1') facing the light scattering suppression layer 320 may be less than the thickness of the remaining area outside that end. For example, the thickness of the first base layer (BL1') may gradually increase in the vertical direction as it extends away from the light scattering suppression layer 320. This thickness variation originates from the step difference between the area where the light blocking layer 330 is formed and another area where the light blocking layer 330 is not formed during the material deposition process used to form the first base layer (BL1').

[0107] Each of the second base layer (BL2') and the support layer 345 may be formed to correspond to the shape of the top surface of the first base layer (BL1'), and may have a top surface whose height increases with the distance from the light scattering suppression layer 320.

[0108] The second base layer (BL2') includes a top surface having a first height (h1') measured from the top surface of the light-blocking layer 330 in a region perpendicularly overlapping with the light scattering suppression layer 320 or in a region above the first portion 330_1. The second base layer (BL2') may also include a top surface having a second height (h2') measured from the top surface of the light-blocking layer 330 in a region perpendicularly overlapping with the first base layer (BL1') or in a region above the second portion 330_2. The second height (h2') may correspond to the highest or average height in the region above the first base layer (BL1'). The second base layer (BL2') includes a top surface having a third height (h3') measured from the top surface of the light-blocking layer 330 in a region between the first base layer (BL1') and the light scattering suppression layer 320 or in a region above the third portion 330_3. The third height (h3') may be smaller than the first height (h1') and the third height (h3') may be smaller than the second height (h2'). The second height (h2') can be greater than the first height (h1').

[0109] Figure 6A This illustrates some implementations based on the disclosed technology. Figure 2 A cross-sectional view of another example of an image sensing device captured by line I-I'. Figure 6A The image sensing device (1c) shown in the example embodiment is in conjunction with Figure 3 The cross-sectional view corresponding to the cross-sectional view. Figure 6B This illustrates some implementations based on the disclosed technology. Figure 6A An enlarged cross-sectional view of an example of region (C) shown.

[0110] Reference Figure 6A The peripheral region (PR) of the image sensing device (1c) may include a light-blocking region (OB), a pad region (PAD), and a margin region (MR).

[0111] The allowance region (MR) may be located outside the pad region (PAD). The allowance region (MR) may be an area that takes into account the process allowance in the process of scribing the semiconductor layer 100 or the semiconductor substrate 110 along the scribing (S / L) region.

[0112] The light scattering suppression layer 320 may include a portion extending from the light blocking region (OB) to the pad region (PAD). The light scattering suppression layer 320 may also include a portion extending beyond the input / output (I / O) pads 150 and through the pad opening (OP_PAD). In some embodiments, the margin region (MR) may refer to the entire peripheral region (PR) located outside the light scattering suppression layer 320.

[0113] Reference Figure 6BThe recessed portion (BLr”) of the image sensing device (1c) can be disposed in the margin region (MR). When the light scattering suppression layer 320 extends to the pad region (PAD), the recessed portion (BLr”) can be located outside the light scattering suppression layer 320. The area of ​​the margin region (MR) excluding the recessed portion (BLr”) can be provided with a flat upper surface by the first base layer and the second base layer (BL1, BL2). In this case, with Figure 4B Unlike what is described, the groove portion may not be arranged in the light-blocking region (OB). Image sensing devices based on some embodiments of the disclosed technology can be configured such that multiple nanostructures 341 (see...) Figure 4A The material is formed on the base layer (BL) and mitigates process defects caused by the remaining material layer (e.g., defects in the dicing process), thereby enabling the image sensing device to have improved manufacturability.

[0114] In the plan view, the groove portion (BLr”) can be shaped to extend along the outer surface of the light scattering suppression layer 320 in the allowance region (MR).

[0115] Figures 7A to 7E This is a cross-sectional view illustrating an example of a method for manufacturing an image sensing device based on some embodiments of the disclosed technology.

[0116] Figures 7A to 7E The diagram shows the use of [the two methods] respectively with [other methods]. Figure 4A and Figure 4B An example manufacturing method for an image sensing device that corresponds to the active pixel area (APS) and peripheral area (PR) of the structure.

[0117] Reference Figure 7A A color filter layer (310a, 310b), a light scattering suppression layer 320, and a first base layer BL1 can be formed on the semiconductor substrate 110.

[0118] A first photoelectric conversion region and a second photoelectric conversion region (PD1, PD2) may be formed in the semiconductor substrate 110, and an insulating material may be deposited in trenches formed by etching at least a portion of the semiconductor substrate 110 to form a pixel isolation portion 120. Thereafter, interconnect layers (210, 220) may be formed on the rear surface of the semiconductor substrate 110.

[0119] Subsequently, in the active pixel region (APS), a conductive material layer can be deposited on the top surface of the semiconductor substrate 110, and a patterning process can be performed to form a grid 315. Color filter layers (310a, 310b) can be formed on the semiconductor substrate 110 such that their thickness is greater than the thickness of the grid 315. In some embodiments, when some color filter material of the color filter layers (310a, 310b) is deposited, the pattern 321 can be deposited together in the peripheral region (PR). Before forming the pattern 321 in the peripheral region (PR), a light blocking layer 330 can be deposited on the semiconductor substrate 110 to a specific thickness. Thereafter, a capping layer 322 can be formed to cover the pattern 321 and the light blocking layer 330 by depositing a material that is the same as or similar to the blue material, thereby forming a light scattering suppression layer 320.

[0120] Subsequently, a thermosetting or photocurable material can be deposited in the peripheral region (PR) spaced apart from the light scattering suppression layer 320 using a mask, followed by an annealing process to form the first base layer BL1. The annealing process reduces the height of the material, resulting in the first base layer BL1 having a top surface with a height substantially the same as the top surface of the light scattering suppression layer 320. However, since the heights of the top surfaces of the first base layer BL1 and the light scattering suppression layer 320 are formed through separate processes, manufacturing process errors can range from 0.1% to 10%.

[0121] When the first base layer BL1 is formed, the height difference between the first base layer BL1 and the color filter layers (310a, 310b) can be minimized even in areas where the light scattering suppression layer 320 is not disposed. Therefore, processability in subsequent processes, described later, can be improved.

[0122] Reference Figure 7B This can form the second basic layer BL2.

[0123] A thermosetting material can be deposited on the active pixel region (APS) and peripheral region (PR) to form a second base layer BL2 covering the color filter layer (310a, 310b), the light scattering suppression layer 320, and the first base layer BL1. The thermosetting material can be a different material from the first base layer BL1, but depending on the embodiment, it can also be the same material as the first base layer BL1. Even when the first base layer BL1 and the second base layer BL2 comprise the same material, the boundary between the first base layer BL1 and the deposited thermosetting material can be distinguished by an annealing process or the like. The annealing process can be performed or omitted after the thermosetting material is deposited.

[0124] Since the second base layer BL2 includes a portion with space between the first base layer BL1 and the light scattering suppression layer 320, as shown in the reference... Figures 3 to 4B As described, the second base layer BL2 can therefore have a third height (h3) that is lower than the height of the remaining regions within the corresponding area, as referenced. Figures 3 to 4B As described.

[0125] Since the base layer BL is formed in two steps, forming the first base layer BL1 and the second base layer BL2, the second base layer BL2 can have a second height (h2) on the first base layer BL1 that is the same as or similar to the first height (h1), thereby forming a base layer (BL) that provides a flat surface even in the peripheral region (PR).

[0126] Reference Figure 7C It can form a support layer 345 and a dielectric layer 343.

[0127] A low-temperature oxide (LTO) material can be deposited on the base layer (BL) to form a support layer 345, a dielectric material can be deposited on the support layer 345, and a planarization process can be performed to form a dielectric layer 343.

[0128] Reference Figure 7D Multiple penetration portions penetrating a portion of the dielectric layer 343 can be formed by performing an etching process using a mask (MK). The mask (MK) may be patterned on the active pixel region (APS). Since the dielectric layer 343 exposed to the outside through the mask (MK) can be etched according to the above pattern, multiple penetration portions can be formed, and the top surface of the support layer 345 is exposed to the outside through the multiple penetration portions.

[0129] Reference Figure 7E A deposition process can be performed to fill multiple through-holes and a metamaterial layer 341L can be formed covering the top surface of the dielectric layer 343. The metamaterial layer 341L may include a metal oxide, such as titanium dioxide, gallium nitride, silicon nitride, or silicon. When a planar dielectric layer 343 is formed, the metamaterial layer 341L may have substantially the same top surface on the active pixel region (APS) and the peripheral region (PR).

[0130] Subsequently, a planarization process can be performed to remove the metamaterial layer 341L on the dielectric layer 343, thereby forming multiple nanostructures 341.

[0131] In some implementations, with Figure 7D and Figure 7E Unlike other processes, the planarization process can be performed only after the metamaterial layer 341L is formed, instead of during the process of forming the dielectric layer 343, thereby forming multiple nanostructures 341.

[0132] Because the base layer (BL) with a second height (h2) is disposed in the peripheral region (PR), the metamaterial layer 341L will not remain on the peripheral region (PR) after the planarization process. For example, if the process of forming the first base layer BL1 is omitted, the top surface of the second base layer BL2 can be formed with a lower height in the peripheral region (PR), resulting in the metamaterial layer 341L being located at a relatively low position. In this case, the metamaterial layer 341L may remain in the peripheral region (PR) during the planarization process and may be used for dicing semiconductor dies or forming input / output (I / O) pads 150 (see...). Figure 3 During subsequent scribing processes of the opening, process defects may occur due to the presence of residual metamaterial layer 341L. Alternatively, to provide a flat surface, it may be necessary to deposit excess base material followed by planarization to form a base layer. In some example embodiments of the disclosed technology, the image sensing device can be configured to minimize the amount of metamaterial layer 341L remaining on the peripheral region (PR). As a result, an image sensing device with improved yield or processability can be achieved.

[0133] As is evident from the above description, the disclosed embodiments of the technology provide an image sensing device that forms a first base layer over a peripheral region, thereby enabling the image sensing device to have improved processability or higher yield.

[0134] The implementation of the disclosed technology can provide various effects that can be directly or indirectly recognized through the aforementioned patent documents.

[0135] Although several exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be conceived based on the description and / or illustrations in this patent document.

[0136] Cross-references to related applications

[0137] This patent document claims priority and benefit to Korean Patent Application No. 10-2025-0042774, filed on April 2, 2025, the disclosure of which is incorporated herein by reference in its entirety as part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device comprising: An active pixel region, which includes a photoelectric conversion region; as well as The peripheral region is disposed adjacent to at least one side of the active pixel region and includes a light scattering suppression layer, a first base layer spaced apart from the light scattering suppression layer, and a second base layer covering at least a portion of each of the light scattering suppression layer and the first base layer.

2. The image sensing device according to claim 1, wherein, The second base layer extends to the active pixel region; and The image sensing device further includes a lens layer comprising a plurality of nanostructures spaced apart from each other on the second base layer of the active pixel region.

3. The image sensing device according to claim 2, wherein, The lens layer further includes: A dielectric layer disposed between the plurality of nanostructures.

4. The image sensing device according to claim 1, further comprising: A semiconductor layer is disposed in the peripheral region below the light scattering suppression layer and the first base layer, and includes the photoelectric conversion region in the active pixel region; as well as A light-blocking layer is disposed on at least a portion of the semiconductor layer, and includes a first portion and a second portion. The first portion is disposed below the light scattering suppression layer; and The second part is located below the first base layer.

5. The image sensing device according to claim 4, wherein, The light-blocking layer includes: The third part connects the first part to the second part.

6. The image sensing device according to claim 5, wherein, The third part contacts the second base layer.

7. The image sensing device according to claim 5, wherein, The second base layer extends between the first base layer and the light scattering suppression layer.

8. The image sensing device according to claim 4, wherein, The peripheral area includes: Light-blocking region, wherein the light-blocking layer is located in the light-blocking region; and The pad area is located on one side of the light-blocking area and includes pads for transmitting and receiving electrical signals. The first base layer is disposed in each of the pad area and the light-blocking area.

9. The image sensing device according to claim 1, wherein, The second base layer extends from the first base layer to the light scattering suppression layer; and The second base layer includes a first top surface having a first height and a second top surface having a second height different from the first height. The first top surface is formed to overlap with the light scattering suppression layer in a planar view; and The second top surface is formed to spatially overlap with the first base layer and the light scattering suppression layer in a planar view.

10. The image sensing device according to claim 9, wherein, The second base layer includes a third top surface having a third height in the area overlapping with the first base layer in the plan view. The third height is different from the second height.

11. The image sensing device according to claim 1, wherein, At least one of the first base layer and the second base layer includes at least one of epoxy resin, polyurethane resin, polyester resin, acrylic resin and silicone resin.

12. The image sensing device according to claim 11, wherein, The first base layer comprises a different material than the second base layer.

13. An image sensing device, the image sensing device comprising: An active pixel region, the active pixel region including a first portion of a semiconductor layer having a photoelectric conversion region; as well as The peripheral region, adjacent to the active pixel region, includes a light scattering suppression layer and a base layer. The light scattering suppression layer is disposed on a second portion of the semiconductor layer extending from the first portion of the semiconductor layer, and the base layer covers at least a portion of the light scattering suppression layer. The base layer includes a recessed portion that is recessed toward the top surface of the semiconductor layer.

14. The image sensing device according to claim 13, wherein, In the plan view, the groove portion is located outside the edge portion of the light scattering suppression layer.

15. The image sensing device according to claim 14, wherein, The groove portion is formed as a line shape extending along the outer surface of the edge portion of the light scattering suppression layer.

16. The image sensing device according to claim 13, wherein, The base layer includes a first base layer spaced apart from the light scattering suppression layer and a second base layer disposed on the first base layer. The second base layer covers at least a portion of the first base layer and the light scattering suppression layer.

17. The image sensing device according to claim 13, wherein, The peripheral region includes a pad region exposed from the semiconductor layer and a light-blocking region disposed between the pad region and the active pixel region; and The groove portion is located in the light-blocking area.

18. The image sensing device according to claim 13, wherein, The peripheral area includes: Pad area, in which pads are exposed from the semiconductor layer; A light-blocking region, disposed between the pad region and the active pixel region; and The allowance area is located outside the pad area. The groove portion is located in the allowance area.

19. An image sensing device, the image sensing device comprising: A semiconductor layer, the semiconductor layer including a photoelectric conversion region; A light scattering suppression layer is disposed on the semiconductor layer; A first base layer is disposed on the semiconductor layer and spaced apart from the light scattering suppression layer; as well as A second base layer covers the light scattering suppression layer and the first base layer. The second base layer includes: A first region is formed to overlap with the light scattering suppression layer in a planar view; A second region, which is formed to overlap with the first base layer in a plan view; and A third region is located between the first region and the second region. The third region has a top surface recessed into the semiconductor layer.

20. The image sensing device according to claim 19, further comprising: A color filter layer is disposed on the semiconductor layer. The second base layer includes a region extending from the first region to the top surface of the color filter layer.

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