Image sensing device and imaging system including the same

Abstract

The present application relates to image sensing devices and imaging systems including the same. In one embodiment of the disclosed technology, an image sensing device includes a circuit layer, a photodetector including an active region configured to detect light and disposed on the circuit layer, and a substrate layer on the photodetector, wherein the substrate layer includes a trench recessed in a thickness direction of the substrate layer and surrounding the active region in a plan view.

Description

Technical Field

[0001] The disclosed technology relates to an image sensing device and an imaging system including the same. Background Technology

[0002] Recently, Time-of-Flight (TOF) technology has received significant attention. TOF technology measures the distance between a sensor and a target object by sending pulsed light from a light source located inside or near the sensor towards the target object and receiving the light reflected from the target object. The distance is measured by the time interval between the emission time of the light at the light source and the reception time of the light reflected from the target object. The TOF method uses this TOF measurement to calculate the distance between the sensor and the target object based on a constant speed of light.

[0003] To ensure accurate Time-of-Flight (TOF) measurements, the light-receiving element needs to react immediately when it detects reflected light. Therefore, a highly sensitive photoelectric conversion element is desired. To this end, active research is underway on single-photon avalanche diodes (SPADs) that can be fabricated using CMOS process technology. Summary of the Invention

[0004] The disclosed technology can be implemented in some embodiments as an image sensing device and imaging system designed to increase the absorption rate of light incident on a single-photon avalanche diode (SPAD).

[0005] The disclosed technology can be implemented in some embodiments as an image sensing device and imaging system designed to minimize surface reflections from the SPAD.

[0006] The disclosed technology can be implemented in some embodiments as an image sensing device and imaging system designed to reduce the reflectivity of the upper part of the SPAD, thereby increasing the light transmittance.

[0007] In one embodiment of the disclosed technology, an image sensing device may include: a circuit layer; a photodetector including an active region configured to detect light and disposed on the circuit layer; and a substrate layer located on the photodetector, wherein the substrate layer includes a trench recessed in the thickness direction of the substrate layer and surrounding the active region in a plan view.

[0008] In another embodiment of the disclosed technology, an imaging system may include a light source configured to emit light toward a target object and a pixel array, the pixel array including: a pixel region configured to receive light reflected from the target object and including an active region; and a non-pixel region surrounding the pixel region, wherein the pixel array includes a circuit layer, a photodetector disposed on the circuit layer, and a substrate layer disposed on the photodetector, wherein the substrate layer includes trenches surrounding the active region, deep trenches located in the non-pixel region, and recessed structures located within the trenches or between the deep trenches, the deep trenches having a greater recessed depth than the trenches surrounding the active region, and wherein the trenches, deep trenches, and recessed structures have different recessed depths.

[0009] In some embodiments of the disclosed technology, the absorption rate of the amount of light incident on a single-photon avalanche diode (SPAD) can be increased.

[0010] This minimizes surface reflections on the SPAD.

[0011] In addition, it can reduce the reflectivity of the upper part of the SPAD, thereby increasing the light transmittance.

[0012] However, the advantages and effects associated with some of the embodiments described in this patent document are not limited to those described above, and other advantages, effects and features will become apparent from the following description. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating an imaging system based on one implementation.

[0014] Figure 2 This is a planar diagram of a pixel array based on one implementation method.

[0015] Figure 3 yes Figure 2 A magnified plan view of region Q1 in the image.

[0016] Figure 4 It is along Figure 3 A cross-sectional view of line A-A' in the diagram.

[0017] Figure 5 This is a schematic diagram showing the optical path of incident light incident on a pixel.

[0018] Figure 6 This is a cross-sectional view of a pixel based on another implementation method.

[0019] Figure 7 This is an enlarged view of a pixel array based on another implementation method. Detailed Implementation

[0020] In the following description, embodiments will be described with reference to the accompanying drawings.

[0021] The same reference numerals indicate the same components. Additionally, in the accompanying drawings, the thickness, scale, and dimensions of the components are exaggerated for the purpose of effectively describing the technical content. The term "and / or" includes any one or more combinations that can be defined by the relevant configuration.

[0022] Various components may be described using terms such as "first" and "second," but the components are not limited by these terms. These terms are used to distinguish one component from another. For example, without departing from the scope of the implementation, a "first" component may be referred to as a "second" component, and similarly, a "second" component may be referred to as a "first" component.

[0023] The disclosed technology can be implemented in some embodiments as a pixel structure (e.g., SPAD) designed to maximize light absorption efficiency, particularly for weak signals returning from distant objects. This can be achieved, among other structures and methods, via a trench-type light guide structure that improves internal light propagation and reduces losses.

[0024] Figure 1 This is a block diagram illustrating an imaging system based on one implementation.

[0025] Reference Figure 1 Imaging system 1 can be an imaging device, such as a digital still camera that captures still images or a digital video camera that captures moving images. For example, imaging system 1 can be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a mobile phone (e.g., a smartphone) or other portable or non-portable device or system with imaging capabilities, but is not limited thereto. Imaging system 1 can be a concept comprising means for capturing and generating images of objects by means of including lenses and imaging elements.

[0026] The imaging system 1 may include an image sensing device 100 for capturing still images or video images and an image signal processor 200 for processing the image data captured by the image sensing device 100.

[0027] Image sensing device 100 can use the time-of-flight (TOF) principle to measure distance. Image sensing device 100 may include a focusing pattern or optical device LM (e.g., an optical lens or other focusing or concentrating device) for collecting and guiding light from a target object TO, a pixel array 110 having an array of pixels for receiving and detecting light collected from the target object TO, a pixel driver 120 for driving sensing pixels in pixel array 110, a timing controller 130 coupled to pixel driver 120, a light source LS for emitting light L1 toward the target object TO, a light source driver 140 for controlling the light emission of the light source LS, and a readout circuit 150 coupled to pixel array 110 for reading pixel signals from the pixels of pixel array 110. An imaging system 1 based on one embodiment may also include a light sensor 300. Light sensor 300 can sense the illuminance of the surrounding environment, determine whether the sensed illuminance is greater than or equal to a reference illuminance or less than a reference illuminance, and send the determined result to timing controller 130.

[0028] The light source LS can emit light L1 toward the target object TO in response to a reference pulse signal MLS from the light source driver 140. In some implementations, the light source LS can be or can include a laser diode (LD) or light-emitting diode (LED), near-infrared (NIR) laser, point light source, white lamp, monochromatic light source combined with a monochromator, or a combination of other laser sources (LS) that emits light of a specific wavelength band (e.g., infrared or visible light). For example, the light source LS can emit infrared light with a wavelength of about 800 nm to about 1000 nm. For ease of description, Figure 1 Only one light source LS is shown, but multiple light source LSs may be arranged around the focusing pattern / optical device LM. In one embodiment, the light source LS may include a near-infrared laser source (e.g., a vertical cavity surface-emitting laser (VCSEL)) which includes a point source, but the disclosed technology is not limited thereto.

[0029] The light-gathering pattern / optical device LM can receive and converge or focus light L2 reflected from the target object TO and focus the light L2 onto the pixel SP of the pixel array 110. The light-gathering pattern / optical device LM may include a focusing lens or another cylindrical optical element on a glass or plastic surface. The light-gathering pattern / optical device LM may include a lens group consisting of at least one lens. The light-gathering / focusing pattern / optical device LM may be a microlens, but the disclosed technology is not limited thereto.

[0030] Pixel array 110 may include a plurality of pixels SP arranged continuously in a two-dimensional matrix structure. That is, pixel array 110 may include a plurality of pixels SP arranged continuously in a first direction DR1 and a second direction DR2. Each pixel SP may include a pixel region. Each pixel SP may perform photoelectric conversion on incident light (e.g., reflected light L2 reflected from a target object) received by a light-collecting / focusing pattern / optical device LM and generate and output a pixel signal as an electrical signal corresponding to the incident light. In this case, the pixel signal may be a signal representing information corresponding to the distance from the target object TO, rather than a signal representing the color of the target object TO. Each of the plurality of pixels SP may include a single-photon avalanche diode (SPAD).

[0031] A pixel array 110 with multiple pixels SP can use a direct Time-of-Flight (TOF) method to detect the distance to a target object TO. For reference, the direct TOF method calculates the distance to the target object TO by directly measuring the round-trip time from the time a pulse of light is emitted towards the target object TO to the time the pulse is reflected back from the target object TO, and then calculating the round-trip time and the speed of light. However, the disclosed technology is not limited to this; the pixel array 110 with multiple pixels SP can also use an indirect TOF method to detect the distance to the target object TO.

[0032] Pixel driver 120 can drive pixel array 110 under the control of timing controller 130. For example, pixel driver 120 can generate a quench control signal to control a quench operation that reduces the reverse bias voltage applied to pixel SP to the breakdown voltage or lower. That is, pixel driver 120 can control the opening / closing of pixel SP under the control of timing controller 130.

[0033] The readout circuit 150 can be disposed on one side of the pixel array 110. It can calculate the time delay between the pulse signal (or pixel signal) output from each pixel SP and the reference pulse, and generate and store digital data (or pixel data) corresponding to the time delay. Under the control of the timing controller 130, the readout circuit 150 can send the stored digital data to the image signal processor 200.

[0034] The timing controller 130 controls the overall operation of the image sensing device 100. Specifically, the timing controller 130 generates timing signals to control the operation of the pixel driver 120 and the light source driver 140. Additionally, the timing controller 130 controls the activation or deactivation of the readout circuit 150 and controls the simultaneous or sequential transmission of digital data stored in each readout circuit 150 to the image signal processor 200.

[0035] The light source driver 140 can generate a clock signal that can drive the light source LS under the control of the timing controller 130.

[0036] The image signal processor 200 can process digital data (or pixel data) input from the image sensing device 100 and generate a depth image (in the form of a histogram) representing the distance to the target object TO. Specifically, the image signal processor 200 can calculate the distance to the target object TO for each pixel based on the time delay represented by the digital data received from the readout circuit 150.

[0037] The image signal processor 200 can control the operation of the image sensing device 100. In some implementations, the image signal processor 200 can analyze digital data input from the image sensing device 100 to determine the mode of the image sensing device 100 and control the image sensing device 100 to operate in the determined mode.

[0038] The image signal processor 200 can perform image signal processing on the generated depth image to reduce or remove noise and enhance image quality. The depth image output from the image signal processor 200 can be automatically or in response to a user request stored in the internal or external memory of the imaging system 1 or a device equipped with the imaging system 1. The depth image can be displayed via a display device. In some implementations, the depth image output from the image signal processor 200 can be used to control the operation of the imaging system 1 or a device equipped with the imaging system 1.

[0039] Figure 2 This is a planar diagram of a pixel array based on one implementation method. Figure 3 yes Figure 2 A magnified plan view of region Q1 in the image.

[0040] Reference Figure 2 and Figure 3 The pixel array 110 may include multiple pixels SP, and each pixel SP may include a pixel region PX and a non-pixel region NPX.

[0041] A pixel region PX can be an area that receives external light and converts the received external light into electrical signals. Pixel regions PX can be located within individual pixels SP. Pixel regions PX located within individual pixels SP can be set individually. A photodetector SPAD can be located within a pixel region PX. Pixel regions PX can be substantially the same as, but are not limited to, the area where the photodetector SPAD is located.

[0042] A non-pixel region NPX can be a region that does not receive external light or, even when light is received, does not convert light into an electrical signal. For example, in some implementations, a non-pixel region NPX can be configured to not have operational optical sensing functionality. A non-pixel region NPX can be located around a pixel region PX. A non-pixel region NPX can be located between the pixel regions PX of adjacent pixels SP. A non-pixel region NPX can be positioned around a pixel region PX, but is not limited to these configurations.

[0043] Each pixel SP may include an optically active region AA. The optically active region AA may be arranged within the pixel region PX. In some implementations, the optically active region refers to the region that detects light and converts it into an electrical signal. For example... Figure 4 As shown, in some embodiments, the active region AA may be the first semiconductor region CD1 (see...). Figure 4 The area where ) is located.

[0044] First semiconductor region CD1 (see...) Figure 4 It can be located in the active region AA, and the second semiconductor region CD2 (see Figure 4 It can be located outside the active region AA. The first semiconductor region CD1 (see...) Figure 4 ) and the second semiconductor region CD2 (see Figure 4 It can be located in the pixel region PX.

[0045] In some implementations, the active region AA may be defined by a photodetector SPAD. In some implementations, the photodetector SPAD may include the active region AA.

[0046] In some embodiments, the active region AA may be formed in an island shape in the plan view, but is not limited thereto. The active region AA may be formed such that the region extending in the first direction DR1 in the plan view intersects with the region extending in the second direction DR2, but is not limited thereto. The active region AA may have a "+" shape in the plan view, but is not limited thereto.

[0047] Each pixel SP may include a trench TR, a first recessed structure RC1, and a second recessed structure RC2.

[0048] Each of the first recessed structure RC1 and the second recessed structure RC2 can be formed in a circular shape in a plan view, but is not limited thereto. For example, in a plan view, each of the first recessed structure RC1 and the second recessed structure RC2 can be formed in an elliptical shape or in a polygonal shape, such as a triangle, a quadrilateral, a pentagon, etc.

[0049] In the plan view, the trench TR can be disposed around the active region AA. In the plan view, the trench TR can be configured to surround the active region AA. However, the disclosed technology is not limited thereto; the trench TR can be disposed within the active region AA and along the edge of the active region AA.

[0050] Each of the first recessed structure RC1 and the second recessed structure RC2 may include multiple recessed structures. The multiple first recessed structures RC1 and the multiple second recessed structures RC2 may be disposed within the pixel region PX. The multiple first recessed structures RC1 may be disposed outside the active region AA, and the multiple second recessed structures RC2 may be disposed within the active region AA.

[0051] Multiple first recessed structures RC1 can be disposed outside the groove TR, and multiple second recessed structures RC2 can be surrounded by the groove TR.

[0052] Multiple first recessed structures RC1 may overlap with the second semiconductor region CD2 in the thickness direction (e.g., third direction DR3), and multiple second recessed structures RC2 may overlap with the first semiconductor region CD1 in the thickness direction (e.g., third direction DR3).

[0053] Reference Figure 4 Describe the cross-sectional structure of each pixel SP.

[0054] Figure 4 It is along Figure 3 A cross-sectional view of line A-A' in the diagram. Figure 5 This is a schematic diagram showing the optical path of incident light incident on a pixel.

[0055] Reference Figures 3 to 5 Pixel array 110 according to one embodiment may include a circuit layer CEP and a photodetector on the circuit layer CEP. The photodetector of the pixel SP of pixel array 110 may include a single-photon avalanche diode (SPAD). Pixel array 110 according to one embodiment may include a substrate layer SUB on the photodetector SPAD, a deep trench DTI outside the photodetector SPAD, a trench TR disposed in the pixel region PX, a first recess structure RC1 and a second recess structure RC2, a planarization layer OC on the substrate layer SUB, an insulating layer IL on the planarization layer OC, a filling portion GR disposed in the deep trench DTI, and a focusing pattern / optical device LM on the insulating layer IL.

[0056] The circuit layer CEP can be disposed on the lower surface of the photodetector SPAD, and may include transistors, interconnect layers, and interlayer insulating layers. The transistors may include analog quenching transistors, readout transistors, etc., formed on the lower surface of the photodetector SPAD.

[0057] The photodetector SPAD may include a first semiconductor region CD1, a second semiconductor region CD2, and an intermediate region MA between the first semiconductor region CD1 and the second semiconductor region CD2.

[0058] The first semiconductor region CD1 can be an n-type semiconductor region, and the second semiconductor region CD2 can be a p-type semiconductor region. For example, p-type ions can include boron (B) ions, and n-type ions can include phosphorus (P) and / or arsenic (As) ions. For example, the first semiconductor region CD1 can include a 1-1 semiconductor region CD1a, which is an n+ type semiconductor region, and a 1-2 semiconductor region CD1b, which is an n-type semiconductor region, on the circuit layer CEP. The second semiconductor region CD2 can include a 2-1 semiconductor region CD2a, which is a p+ type semiconductor region, and a 2-2 semiconductor region CD2b, which is a p-type semiconductor region, on the 2-1 semiconductor region CD2a.

[0059] For example, semiconductor region CD1a of 1-1 may have a higher n-type impurity doping concentration than semiconductor region CD1b of 1-2, and semiconductor region CD2a of 2-1 may have a higher p-type impurity doping concentration than semiconductor region CD2b of 2-2. However, the disclosed technology is not limited to this. Semiconductor region CD1 of 1-1 and semiconductor region CD2 of 2-2 may include only one n-type semiconductor region and one p-type semiconductor region.

[0060] In some implementations, the vertical positions of semiconductor region CD1a (1-1) and semiconductor region CD1b (1-2) can be changed, and the vertical positions of semiconductor region CD2a (2-1) and semiconductor region CD2b (2-2) can be changed.

[0061] The intermediate region MA can be disposed between semiconductor region CD1 (1-1) and semiconductor region CD2 (2-2). Alternatively, the intermediate region MA can be disposed on the upper surface of the first semiconductor region CD1. The mechanism of electrons (e-) and holes (h+) in the intermediate region MA will be described below.

[0062] The substrate layer SUB can be disposed on the photodetector SPAD. The substrate layer SUB can be formed of silicon (Si) and / or silicon (Si) compounds, but is not limited thereto.

[0063] The substrate layer SUB may include an n-type semiconductor region or a p-type semiconductor region. However, the impurity doping concentration of the substrate layer SUB may be lower than the impurity doping concentration of each of the first semiconductor region CD1 and the second semiconductor region CD2.

[0064] Deep trenches (DTIs) can be formed in the non-pixel regions (NPX) of the substrate layer (SUB). A deep trench (DTI) can be formed by recessing (or embedding) the substrate layer (SUB) in the thickness direction (third direction DR3). For example, a deep trench (DTI) can completely penetrate the substrate layer (SUB) from the top surface to the bottom surface in the thickness direction (third direction DR3).

[0065] Deep trench TI can expose the circuit layer CEP, but is not limited to this. For example, deep trench TI can be recessed so that a portion of the substrate layer SUB on the circuit layer CEP is retained. Deep trench TI can be formed using deep trench processes.

[0066] The insulating layer IL and the filler GR can be disposed in the deep trench DTI. The insulating layer IL and the filler GR can completely fill the deep trench DTI.

[0067] The refractive index of a deep trench DTI can be, for example, in the range of about 1.4 to about 2.0, but is not limited thereto. A deep trench DTI can be used to totally internally reflect some of the incident light L2 incident on the pixel SP and allow the totally internally reflected light to propagate toward the photodetector SPAD.

[0068] The trench TR, a plurality of first recessed structures RC1, and a plurality of second recessed structures RC2 can be formed in the pixel region PX of the substrate layer SUB. The number of the plurality of first recessed structures RC1 and the plurality of second recessed structures RC2 are not limited to... Figure 3 and Figure 4 The quantities described herein. The number of multiple first recessed structures RC1 and multiple second recessed structures RC2 may vary depending on the design.

[0069] The trench TR, the plurality of first recessed structures RC1, and the plurality of second recessed structures RC2 can be formed by recessing the substrate layer SUB in the thickness direction (third direction DR3). The depth of the trench TR recessed in the thickness direction (third direction DR3) can be greater than the depth of the plurality of first recessed structures RC1 and the plurality of second recessed structures RC2 recessed in the thickness direction (third direction DR3).

[0070] The depths of the plurality of first recessed structures RC1 and the plurality of second recessed structures RC2 recessed in the thickness direction (third direction DR3) may be substantially the same, but are not limited thereto. The depth of the deep trench DTI recessed in the thickness direction (third direction DR3) may be greater than the depth of the trench TR recessed in the thickness direction (third direction DR3).

[0071] The trench TR can be used for total internal reflection of some incident light L2 incident on the pixel SP and allows the total internally reflected light to propagate toward the photodetector SPAD. Specifically, the trench TR can increase the optical path toward the first semiconductor region CD1 through total internal reflection. Therefore, the efficiency of the photodetector SPAD can be further increased.

[0072] Multiple first recessed structures RC1 and multiple second recessed structures RC2 can scatter incident light L2 that is externally incident and passes through the focusing pattern / optical device LM. With the multiple first recessed structures RC1 and multiple second recessed structures RC2 being set, the incident light L2 incident on the pixel SP can be suppressed from being reflected from the surface of the photodetector SPD, thereby increasing the light absorption rate and increasing the light transmittance.

[0073] The depth of the groove TR recessed in the thickness direction (third direction DR3) can be in the range of 2 to 5 times or 2 to 10 times the depth of the plurality of first recessed structures RC1 and the plurality of second recessed structures RC2 recessed in the thickness direction (third direction DR3), but is not limited thereto. When the ratio of the depth of the groove TR recessed in the thickness direction (third direction DR3) to the depth of the plurality of first recessed structures RC1 and the plurality of second recessed structures RC2 recessed in the thickness direction (third direction DR3) is within the above range, the groove TR can more smoothly totally reflect the incident light L2, and the first recessed structures RC1 and the second recessed structures RC2 can more smoothly scatter the incident light L2.

[0074] The deep trench (DTI), trench (TR), multiple first recessed structures (RC1), and multiple second recessed structures (RC2) can increase the optical path by scattering the incident light (L2) or by directing the total internal reflection of the photodetector (SPAD). Therefore, the photoelectric conversion efficiency of the SPAD can be increased.

[0075] The planarization layer OC can fill the trench TR, multiple first recessed structures RC1, and multiple second recessed structures RC2. The planarization layer OC can be disposed on the substrate layer SUB to fill the trench TR, multiple first recessed structures RC1, and multiple second recessed structures RC2. That is, the same material can be disposed (filled) in the trench TR, multiple first recessed structures RC1, and multiple second recessed structures RC2.

[0076] The planarization layer OC may include organic insulating material. Even when trenches TR, multiple first recessed structures RC1, multiple second recessed structures RC2, etc., are disposed on the lower part through the planarization layer OC, the upper part can still be planarized. Therefore, other components can be disposed more smoothly on the planarization layer OC.

[0077] The refractive index of the planarization layer OC can be between, but is not limited to, the refractive index of the substrate layer SUB and the refractive index of the insulating layer IL. For example, the refractive index of the planarization layer OC can be less than the refractive index of the substrate layer SUB and greater than the refractive index of the insulating layer IL.

[0078] An insulating layer IL may be disposed on a planarization layer OC. The insulating layer IL may be disposed not only on the planarization layer OC but also within a deep trench DTI. At least a portion of the insulating layer IL may also be disposed on the sidewalls of the deep trench DTI. The refractive index of the insulating layer IL may have a value between the refractive index of the focusing pattern / optical device LM and the refractive index of the planarization layer OC.

[0079] The deep trench DTI can be filled with a different material than the filling trench TR, the first recessed structure RC1, and the second recessed structure RC2.

[0080] The insulating layer IL may include at least one insulating layer. For example, the insulating layer IL may include a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3. In the disclosed art, an example of the insulating layer IL being formed as three layers is described, but the disclosed art is not limited thereto, and it may be formed by one insulating layer, two insulating layers, or four or more insulating layers.

[0081] The first insulating layer IL1 may include an 11th insulating layer IL11 disposed on the upper surface of the substrate layer SUB and a 12th insulating layer IL12 disposed on the side surface (or deep trench DTI) of the substrate layer SUB. The 11th insulating layer IL11 may be disposed directly on the upper surface of the planarization layer OC, but is not limited thereto.

[0082] The second insulating layer IL2 may include a 21st insulating layer IL21 disposed on the 11th insulating layer IL11 and a 22nd insulating layer IL22 disposed on the 12th insulating layer IL12.

[0083] The third insulating layer IL3 may include a 31st insulating layer IL31 disposed between the 11th insulating layer IL11 and the 21st insulating layer IL21, and a 32nd insulating layer IL32 disposed between the 12th insulating layer IL12 and the 22nd insulating layer IL22.

[0084] The 12th insulating layer IL12, the 32nd insulating layer IL32, and the 22nd insulating layer IL22 can be sequentially disposed on the substrate layer SUB in the deep trench DTI.

[0085] Figure 4 The diagram shows 11th insulating layer IL11 and 12th insulating layer IL12, 21st insulating layer IL21 and 22nd insulating layer IL22, and 31st insulating layer IL31 and 32nd insulating layer IL32, formed as separate layers but in contact with each other. However, the disclosed technology is not limited thereto. For example, according to the process, 11th insulating layer IL11 and 12th insulating layer IL12 may be formed as a single monolithic layer, 21st insulating layer IL21 and 22nd insulating layer IL22 may be formed as a single monolithic layer, and 31st insulating layer IL31 and 32nd insulating layer IL32 may be formed as a single monolithic layer.

[0086] Typically, light exhibits high reflectivity at interfaces between materials with significant differences in refractive index. As mentioned above, when the refractive indices of each component increase sequentially along the path of incident light L2, the reflectivity at the component interfaces is minimized, and the reflection of incident light L2 at each interface is also minimized. Therefore, the absorption rate of incident light L2 in the SPAD photodetector can be increased.

[0087] The first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 can be disposed in each pixel region PX and each non-pixel region NPX. Specifically, the insulating layer IL can be configured to extend to the pixel region PX and the non-pixel region NPX surrounding the pixel region PX of each pixel SP.

[0088] The first insulating layer IL1 to the third insulating layer IL3 may include silicon oxide (SiO2), silicon oxynitride (SiON), and silicon nitride (SiN). x Hafnium oxide (HfO2) and titanium oxide (TiO2) x At least one of the following:

[0089] The filling portion GR can be disposed in a non-pixel region NPX. For example, the filling portion GR can be arranged such that it is sandwiched between insulating layers IL disposed in adjacent pixel regions PX. The filling portion GR can be in direct contact with the insulating layer IL disposed in adjacent pixel SP. For example, the filling portion GR can include tungsten (W), but the disclosed technology is not limited thereto.

[0090] In some embodiments, the insulating layer IL on the upper surface of the substrate layer SUB has low reflectivity relative to the incident light L2, so that the incident light L2, which has passed through the focusing pattern / optical device LM, is not totally reflected, but instead incident on the photodetector SPAD.

[0091] In some implementations, the filler region GR may be omitted, and the polysilicon may be disposed in the area where the filler region GR is disposed (e.g., the non-pixel region NPX).

[0092] The insulating layer IL on the side surface of the substrate layer SUB can be used for total internal reflection of a portion of the incident light L2 that is incident on the photodetector SPAD and propagates toward the non-pixel region NPX. Therefore, the insulating layer IL has a high reflectivity relative to the incident light L2.

[0093] On the upper surface of the substrate layer SUB, a focusing pattern / optical device LM can be disposed on the insulating layer IL. The focusing pattern / optical device LM can be used to receive externally incident light in each pixel region PX. For this purpose, the focusing pattern / optical device LM can have an upwardly convex lens shape and can be formed of a material with a large difference in refractive index compared to the outside air. For example, the refractive index of the focusing pattern / optical device LM can be in the range of about 1.5 to about 1.7, but is not limited thereto.

[0094] like Figure 4 As shown, a focusing pattern / optical device LM can be continuously disposed in the pixel region PX and the non-pixel region NPX, and is formed such that the convex lens-shaped end of the focusing pattern / optical device LM is located in the central portion of the pixel region PX, to provide improved light collection and focus the collected light onto the photodetector SPAD below the focusing pattern / optical device LM. For example, the focusing pattern / optical device LM can be disconnected from the non-pixel region NPX. In this case, multiple focusing patterns / optical devices LM can be located in each pixel region PX to collect light from the target object TO and guide / focus the collected light onto the pixel region.

[0095] A SPAD photodetector can be used as a photoelectric conversion element including a photosensitive PN junction. That is, a SPAD photodetector can detect a target object TO (see [reference]). Figure 1 The system reflects a single photon (e.g., a single photon of the incident light L2) and generates pixel data (or current pulse, pixel signal, or pulse signal) corresponding to the detected single photon.

[0096] In this case, pixel data can be generated through a series of processes triggered by avalanche breakdown by an incident single photon in Geiger mode, with a reverse bias voltage above the breakdown voltage applied between the cathode and anode.

[0097] Here, avalanche breakdown can occur in the intermediate region MA within the photodetector SPAD. Holes (h+) can be located in one region of the intermediate region MA adjacent to the second semiconductor region CD2, and electrons (e-) can be located in another region of the intermediate region MA adjacent to the first semiconductor region CD1.

[0098] A hole (h+) in one region and an electron (e-) in another region can combine to form an electron (e-) and hole (h+) pair. The electron (e-) and hole (h+) pair can be ionized by photons of incident light L2.

[0099] Specifically, when a reverse bias voltage is applied to the photodetector SPAD to increase the electric field, the resulting increase in electric field causes collisional ionization. During this process, electrons (e-) generated from incident photons are accelerated by the strongly applied electric field, thereby generating electron (e-) and hole (h+) pairs. As the electrons (e-) and holes (h+) generated through collisional ionization collide with each other, a large number of charge carriers can be generated.

[0100] Other embodiments of the disclosed technology will be described below. Among the components included in these other embodiments, those referenced are... Figures 1 to 5 The content described is essentially the same, so it is given the same number, and repeated content can be omitted or described briefly.

[0101] Figure 6 This is a cross-sectional view of a pixel based on another implementation method.

[0102] Reference Figure 6 The pixel array 110_1 may include a substrate layer SUB_1 defining a deep trench DTI, a trench TR, a first recessed structure RC1, and a second recessed structure RC2. The substrate layer SUB_1 may include a base layer BL and a pattern layer PL containing different materials.

[0103] The base layer BL can be disposed on the semiconductor regions CD1 and CD2. The base layer BL can be disposed between the pattern layer PL and the semiconductor regions CD1 and CD2. The base layer BL can be formed of silicon (Si) and / or silicon (Si) compounds, but is not limited thereto.

[0104] A pattern layer PL can be disposed on a base layer BL. The pattern layer PL can be disposed between the base layer BL and the planarization layer OC. The pattern layer PL can define multiple first recessed structures RC1 and multiple second recessed structures RC2. The multiple first recessed structures RC1 and multiple second recessed structures RC2 can extend through the pattern layer PL in the thickness direction (third direction DR3). The multiple first recessed structures RC1 and multiple second recessed structures RC2 can expose the base layer BL.

[0105] The trench TR can be defined by a base layer BL and a pattern layer PL. That is, the sidewalls of the trench TR can be formed by the base layer BL and the pattern layer PL.

[0106] The refractive index of the patterned layer PL can be between that of the planarization layer OC and the base layer BL. For example, the refractive index of the patterned layer PL can be greater than that of the planarization layer OC and less than that of the base layer BL. Therefore, the reflectivity of the incident light can be minimized.

[0107] The patterned layer PL can be formed from a material different from the base layer BL. For example, the patterned layer PL can be a region of oxide on the base layer BL. Therefore, when the base layer BL includes silicon (Si), the patterned layer PL can include silicon oxide.

[0108] A deep trench DTI can be defined by a base layer (BL) and a pattern layer (PL). That is, the sidewalls of a deep trench DTI can be formed by the base layer (BL) and the pattern layer (PL).

[0109] Even under these conditions, the deep trench DTI, trench TR, multiple first recessed structures RC1, and multiple second recessed structures RC2 can increase the optical path by scattering the incident light or by directing the light towards the photodetector SPAD for total internal reflection. Therefore, the photoelectric conversion efficiency of the photodetector SPAD can be increased.

[0110] Figure 7 This is an enlarged view of a pixel array based on another implementation method.

[0111] Reference Figure 7 The pixel array 110_2 may include pixels SP1 and SP2 with active regions AA1 and AA2 of different sizes. The first pixel SP1 may include a first active region AA1, and the second pixel SP2 may include a second active region AA2.

[0112] The size (area or width) of the first active region AA1 can be larger than the size of the second active region AA2. The sizes of the active regions AA1 and AA2 are proportional to the signal strength of the photodetector SPAD. That is, the larger the sizes of the active regions AA1 and AA2, the greater the signal strength of the photodetector SPAD.

[0113] When the size of the first active region AA1 is larger than the size of the second active region AA2, the first semiconductor region CD1 of the first pixel SP1 (see...) Figure 4 The size (area) of the second pixel SP2 in the planar diagram can be larger than the first semiconductor region CD1 (see...). Figure 4 The size (area) of the plane figure.

[0114] In this case, the photodetector SPAD of the first pixel SP1 can have a higher sensitivity than the photodetector SPAD of the second pixel SP2. That is, the photodetector SPAD of the first pixel SP1 can be a relatively high-sensitivity photodetector SPAD, and the photodetector SPAD of the second pixel SP2 can be a relatively low-sensitivity photodetector SPAD.

[0115] The first pixel SP1 and the second pixel SP2 can be alternately and repeatedly set in the first direction DR1 and the second direction DR2.

[0116] Under the same illuminance conditions, at a distance TO from the target object (see...) Figure 1 At the same distance, the signal strength of the pixel data generated by the photodetector SPAD of the first pixel SP1 can be greater than the signal strength of the pixel data generated by the photodetector SPAD of the second pixel SP2.

[0117] Optionally, the imaging system including the pixel array 110_2 based on the embodiment can operate a high-sensitivity photodetector SPAD and a low-sensitivity photodetector SPAD (receiving light through the corresponding photodetector SPAD) under different illumination conditions.

[0118] For example, in low-light environments, a relatively large amount of light needs to be detected, so a high-sensitivity photodetector SPAD can be operated. Conversely, in high-light environments, a relatively small amount of light may be sufficient, so a low-sensitivity photodetector SPAD can be used. In some implementations, the choice between a high-sensitivity or low-sensitivity photodetector SPAD may depend on the distance TO from the target object (see [link to implementation]). Figure 1 The distance (which can be detected by the corresponding photodetector SPAD). For example, when the distance is relatively far, a high-sensitivity photodetector SPAD can be operated, and when the distance is relatively close, a low-sensitivity photodetector SPAD can be operated.

[0119] By incorporating SPAD photodetectors with varying sensitivities, distances to target objects can be measured more reliably across a wide range of environments.

[0120] Even under these conditions, the deep trench DTI, trench TR, multiple first recessed structures RC1, and multiple second recessed structures RC2 can increase the optical path by scattering the incident light or by directing the total internal reflection of the light towards the photodetector SPAD. This increases the photoelectric conversion efficiency of the photodetector SPAD.

[0121] Only a few implementations and examples of the disclosed technology have been described. Other implementations, enhancements and variations may be made based on what is described and shown in this patent document.

[0122] Cross-reference to related applications

[0123] This patent document claims priority and benefit to Korean Patent Application No. 10-2025-0045621, filed on April 8, 2025, the entire contents of which are incorporated herein by reference for all purposes.

Claims

1. An image sensing device, the image sensing device comprising: Circuit layer; A photodetector, comprising an active region for detecting light and disposed on the circuit layer; as well as A substrate layer, which is located on the photodetector. The substrate layer includes a trench that is recessed in the thickness direction of the substrate layer and surrounds the active region in a plan view.

2. The image sensing device according to claim 1, further comprising a plurality of first recessed structures and a plurality of second recessed structures recessed into the substrate layer in the thickness direction of the substrate layer. in, The plurality of first recessed structures are arranged outside the groove in the plan view, and The plurality of second recessed structures are surrounded by the groove in the plan view.

3. The image sensing device according to claim 2, wherein, The depth of the groove is greater than the depth of the plurality of first recessed structures and the plurality of second recessed structures.

4. The image sensing device according to claim 2, wherein, The photodetector includes a first semiconductor region and a second semiconductor region disposed around or outside the first semiconductor region, wherein the first semiconductor region is located in the active region of the photodetector.

5. The image sensing device according to claim 4, wherein, The plurality of first recessed structures overlap with the second semiconductor region in the thickness direction, and The plurality of second recessed structures overlap with the first semiconductor region in the thickness direction.

6. The image sensing device according to claim 4, wherein, The first semiconductor region includes an n+ semiconductor region doped with an n-type dopant at a first concentration and an n- semiconductor region doped with the n-type dopant at a second concentration lower than the first concentration and disposed on the n+ semiconductor region. The second semiconductor region includes a p+ semiconductor region doped with a third concentration of p-type dopant and a p- semiconductor region doped with a fourth concentration lower than the third concentration and disposed on the p+ semiconductor region.

7. The image sensing device according to claim 4, wherein, The photodetector also includes an intermediate region disposed between the first semiconductor region and the second semiconductor region.

8. The image sensing device according to claim 1, further comprising a planarization layer disposed on the substrate layer, in, The planarization layer fills the trench.

9. The image sensing device according to claim 8, further comprising: An insulating layer disposed on the planarization layer; A deep trench recessed into the substrate layer in the thickness direction, the recess depth of the deep trench being greater than the recess depth of the trench surrounding the active region; as well as A filling portion is disposed in the deep trench.

10. The image sensing device according to claim 9, wherein, An insulating layer is disposed in the deep trench, and The filling portion is disposed between adjacent insulating layers.

11. The image sensing device according to claim 10, wherein, The image sensing device includes multiple pixels. Each of the plurality of pixels includes a pixel region where the photodetector is disposed, and The deep trench is disposed between the pixel regions of adjacent pixels.

12. The image sensing device according to claim 9, wherein, The depth of the deep trench is greater than the depth of the groove.

13. The image sensing device according to claim 1, wherein, The substrate layer includes a base layer containing one or more materials and a pattern layer disposed on the base layer.

14. The image sensing device according to claim 13, wherein, The refractive index of the patterned layer is less than that of the base layer.

15. The image sensing device according to claim 13, further comprising a plurality of first recessed structures and a plurality of second recessed structures recessed into the substrate layer in the thickness direction of the substrate layer. in, The plurality of first recessed structures and the plurality of second recessed structures are defined by the patterned layer and expose the base layer. The trench is defined by the base layer and the pattern layer.

16. The image sensing device according to claim 15, wherein, The base layer is formed of silicon, and the pattern layer is formed of silicon oxide.

17. The image sensing device according to claim 1, wherein, The substrate layer comprises at least one of silicon (Si) or a silicon-Si compound.

18. A system for imaging a target object, the system comprising: A light source that emits light toward the target object; as well as A pixel array comprising: pixel regions including active regions that receive light reflected from the target object; and non-pixel regions surrounding the pixel regions. The pixel array includes: Circuit layer; A photodetector, comprising an active region for detecting light and disposed on the circuit layer; and A substrate layer is disposed on the photodetector. The substrate layer includes trenches surrounding the active region, deep trenches located in the non-pixel region, and recessed structures located inside the trenches or between the deep trenches and the trenches. The recessed depth of the deep trenches is greater than the recessed depth of the trenches surrounding the active region. The groove, the deep groove, and the recessed structure have different recess depths.

19. The system according to claim 18, wherein, The depth of the recess in the deep trench is greater than the depth of the recess in the trench, and The groove has a greater depth than the recessed structure.

20. The system according to claim 19, wherein, The photodetector includes a single-photon avalanche diode.

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