Heterojunction solar cell, method for manufacturing the same, and electric device

Abstract

The application belongs to the field of solar cells. A heterojunction solar cell and a preparation method thereof and an electric device are provided. The cell comprises a silicon substrate; a first passivation layer located on one side of the silicon substrate; an N-doped layer located on the side of the first passivation layer away from the silicon substrate; a first conductive layer located on the side of the N-doped layer away from the silicon substrate; a first grid electrode located on the side of the first conductive layer away from the first passivation layer; and a first contact layer located between the first conductive layer and the first grid electrode, the first contact layer coincides with the projection of the first grid electrode on the first conductive layer, and the material of the first contact layer is composed of the material of the first conductive layer and the material of the first grid electrode. The solar cell of the application has a low contact resistance between the first grid electrode and the conductive layer, thereby improving the photoelectric performance of the cell.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a heterojunction solar cell, its preparation method, and an electrical device thereof. Background Technology

[0002] A solar cell is a semiconductor device that converts solar energy into electrical energy. Under sunlight, a solar cell generates a photocurrent, which is then output as electrical energy through electrodes. In recent years, solar cell manufacturing technology has continuously improved, production costs have decreased, and conversion efficiency has increased. As a result, solar cell power generation has become increasingly widespread and is a crucial energy source for electricity supply. Heterojunction solar cells are a new type of high-efficiency battery technology that combines the advantages of monocrystalline silicon solar cells and amorphous silicon solar cells. They have the characteristics of low manufacturing temperature, higher conversion efficiency, and good high-temperature performance, and therefore have great market potential.

[0003] Since the lateral conductivity of the doped silicon layer on the surface of the heterojunction is poor, it is necessary to deposit a conductive layer on the doped silicon surface to enhance the lateral transport capability of charge carriers, and then print gate lines on top of the conductive layer. However, the contact resistance between the conductive layer and the gate lines is relatively large.

[0004] Therefore, it is urgent to solve the problem of reducing the contact resistance between the TCO layer and the gate line in order to improve the photoelectric performance of the battery.

[0005] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the Invention

[0006] This application provides a heterojunction solar cell and its fabrication method and power supply device to solve or alleviate the technical problem of high contact resistance between the conductive layer and the grid lines mentioned above.

[0007] A first aspect of this application provides a heterojunction solar cell. The cell includes a silicon substrate; a first passivation layer located on one side of the silicon substrate; an N-plane doped layer located on the side of the first passivation layer away from the silicon substrate; a first conductive layer located on the side of the N-plane doped layer away from the silicon substrate; a first grid electrode located on the side of the first conductive layer away from the first passivation layer; and a first contact layer located between the first conductive layer and the first grid electrode, wherein the projection of the first contact layer onto the first conductive layer coincides with that of the first grid electrode, and the material of the first contact layer is composed of the material of the first conductive layer and the material of the first grid electrode.

[0008] In the solar cell of this application embodiment, the contact resistance between the first grid electrode and the conductive layer is low, thereby improving the photoelectric performance of the cell. This is because a first contact layer is provided between the first grid electrode and the conductive layer, and the width of the first contact layer is the same as that of the grid electrode (i.e., the projections of the first grid electrode and the first contact layer on the first conductive layer coincide). This reduces the contact resistance between the first conductive layer and the first grid electrode, preventing the formation of a large potential barrier at the interface, thereby enhancing the carrier extraction capability, reducing the impedance of the heterojunction solar cell, and improving the photoelectric performance of the heterojunction solar cell.

[0009] According to an embodiment of this application, in a first direction, the content of the first conductive layer material in the first contact layer gradually decreases, and the content of the first gate electrode material gradually increases. The first direction is the direction from the silicon substrate to the first passivation layer in the thickness direction of the silicon substrate.

[0010] According to an embodiment of this application, in the first direction, the content of the first conductive layer material in the first contact layer gradually decreases from 70-80wt% to 10-30wt%; in the first direction, the content of the first gate electrode material in the first contact layer gradually increases from 20-30wt% to 70-90wt%.

[0011] According to an embodiment of this application, the thickness of the first contact layer is 5-15 nm.

[0012] According to embodiments of this application, the first conductive layer material includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO.

[0013] According to an embodiment of this application, the first gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

[0014] According to an embodiment of this application, the heterojunction solar cell further includes: a second passivation layer located on the side of the silicon substrate away from the first passivation layer; a p-side doped layer located on the side of the second passivation layer away from the silicon substrate; a second conductive layer located on the side of the p-side doped layer away from the second passivation layer; a second contact layer located on the side of the second conductive layer away from the p-side passivation layer; and a second grid electrode located on the side of the second contact layer away from the second conductive layer; wherein the material of the second contact layer is composed of the material of the second grid electrode and the material of the second conductive layer, and in a direction opposite to the first direction, the content of the second conductive layer material gradually decreases, and the content of the second grid electrode material gradually increases.

[0015] According to an embodiment of this application, the thickness of the second contact layer is 10-30 nm.

[0016] According to an embodiment of this application, in the direction opposite to the first direction, the content of the second conductive layer material in the second contact layer gradually decreases from 70-80 wt% to 0-10 wt%.

[0017] According to an embodiment of this application, in the direction opposite to the first direction, the content of the second gate electrode material in the second contact layer gradually increases from 20-30 wt% to 90-100 wt%.

[0018] According to embodiments of this application, the second conductive layer material includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO.

[0019] According to an embodiment of this application, the first gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

[0020] A second aspect of this application provides a method for fabricating a heterojunction solar cell. The method includes: providing a silicon substrate; sequentially forming a first passivation layer, an N-side doped layer, and a first conductive layer on one side surface of the silicon substrate; forming a first contact layer on the side of the first conductive layer away from the N-side doped layer according to a first predetermined pattern; and forming a first grid electrode on the side of the first contact layer away from the first conductive layer; wherein the material of the first contact layer is composed of the material of the first conductive layer and the material of the first grid electrode. The method of this application is simple to operate and can yield a heterojunction solar cell with good photoelectric performance.

[0021] According to embodiments of this application, the method of forming a first contact layer on the side of the first conductive layer away from the first passivation layer includes: The first contact layer is formed on the side of the first conductive layer away from the first passivation layer by magnetron sputtering. During the magnetron sputtering process, the first conductive layer material is used as the first target material, the first gate electrode material is used as the second target material, and the radio frequency power of the first target material gradually decreases while the radio frequency power of the second target material gradually increases.

[0022] According to an embodiment of this application, the method further includes: sequentially forming a second passivation layer, a P-side doped layer, and a second conductive layer on the side of the silicon substrate away from the first passivation layer; forming a second contact layer on the side of the second conductive layer away from the P-side doped layer; and forming a second gate electrode on the side of the second contact layer away from the second conductive layer according to a second predetermined pattern, wherein the material of the second contact layer is composed of the material of the second gate electrode and the material of the second conductive layer.

[0023] According to embodiments of this application, the method of forming the second contact layer on the side of the second conductive layer away from the P-plane doped layer includes: The first contact layer is formed on the side of the second conductive layer away from the P-plane doped layer by magnetron sputtering. During the magnetron sputtering process, the second conductive layer material is used as the third target, the second gate electrode material is used as the fourth target, and the radio frequency power of the third target gradually decreases while the radio frequency power of the fourth target gradually increases.

[0024] According to an embodiment of this application, the radio frequency power of the first target is 6-8 W / cm. 2 Gradually decrease to 2-3 W / cm 2 .

[0025] According to embodiments of this application, the radio frequency power of the second target is 1-3 W / cm². 2 Gradually increase to 3-6 W / cm 2 .

[0026] According to an embodiment of this application, the radio frequency power of the third target is 7-8 W / cm². 2 Gradually decrease to 2-3 W / cm 2 .

[0027] According to embodiments of this application, the radio frequency power of the fourth target is 1-3 W / cm². 2 Gradually increase to 3-6 W / cm 2 .

[0028] A third aspect of this application provides an electrical device, including the heterojunction solar cell described in the first aspect or the heterojunction solar cell prepared by the preparation method described in the second aspect. Attached Figure Description

[0029] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0030] Figure 1 This is a schematic diagram of the structure of a heterojunction solar cell provided in an embodiment of this application; Figure 2 This is a schematic diagram of another heterojunction solar cell provided in the embodiments of this application.

[0031] Explanation of reference numerals in the attached figures: 1: Silicon substrate; 2: First passivation layer; 3: N-side doped layer; 4: First conductive layer; 5: First gate electrode; 6: First contact layer; 7: Second passivation layer; 8: P-side doped layer; 9: Second conductive layer; 10: Second contact layer; 11: Second gate electrode. Detailed Implementation

[0032] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0034] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0037] A first aspect of this application provides a heterojunction solar cell. (See reference...) Figure 1 The battery includes a silicon substrate 1; a first passivation layer 2 located on one side of the silicon substrate 1; an N-side doped layer 3 located on the side of the first passivation layer 2 away from the silicon substrate 1; a first conductive layer 4 located on the side of the N-side doped layer away from the silicon substrate 1; a first gate electrode 5 located on the side of the first conductive layer 4 away from the N-side doped layer 3; and a first contact layer 6 located between the first conductive layer 4 and the first gate electrode 5, wherein the projection of the first contact layer 6 onto the first conductive layer 4 coincides with that of the first gate electrode 5, and the material of the first contact layer 6 is composed of the material of the first conductive layer and the material of the first gate electrode.

[0038] In the solar cell of this application embodiment, the contact resistance between the first grid electrode and the conductive layer is low, thereby improving the photoelectric performance of the cell. This is because a first contact layer is provided between the first grid electrode and the conductive layer, and the width of the first contact layer is the same as that of the grid electrode (i.e., the projections of the first grid electrode and the first contact layer on the first conductive layer coincide). This reduces the contact resistance between the first conductive layer and the first grid electrode, preventing the formation of a large potential barrier at the interface, thereby enhancing the carrier extraction capability, reducing the impedance of the heterojunction solar cell, and improving the photoelectric performance of the heterojunction solar cell.

[0039] Specifically, the first contact layer is composed of a first conductive layer material and a first grid electrode material. This solves problems such as band and work function mismatch and the formation of a carrier transport barrier between the metal grid electrode and the first conductive layer material. The presence of the first contact layer also reduces the presence of voids between the metal grid electrode and the first conductive layer (in some pyramid-shaped light-trapping structures, the silver paste at the base of the grid lines may not be completely filled). In summary, the first contact layer, composed of the first conductive layer material and the first grid electrode material, allows for a gradual transition of the transport barrier, thereby reducing the contact resistance between the first conductive layer and the first grid electrode, and thus improving the photoelectric performance of the solar cell.

[0040] In some embodiments, in a first direction, the content of the first conductive layer material in the first contact layer gradually decreases, while the content of the first gate electrode material gradually increases. The first direction is the thickness direction of the silicon substrate pointing from the silicon substrate to the first passivation layer. This facilitates a gradual transition in material properties, thereby optimizing bandgap mismatch and improving battery efficiency.

[0041] In some embodiments, in the first direction, the content of the first conductive layer material in the first contact layer gradually decreases from 70-80 wt% to 10-30 wt%. This range of variation in the content of the first conductive layer material facilitates a slow transition in composition from the contact position with the TCO (Temporal Coefficient of Conductivity) to the contact position with the metal gate line. The energy band and work function of this mixture are between these two positions, allowing for a gradual transition in material properties.

[0042] Understandably, the content of the first conductive layer material gradually decreases from 70-80 wt% to 10-30 wt%. This gradual decrease occurs uniformly in increments of 10 wt%, 15 wt%, or 20 wt% as the film grows; for example, the content of the first conductive layer material gradually and uniformly decreases from 70-80 wt% to 10 wt%. Alternatively, the content of the first conductive layer material can be randomly and gradually decreased from 70-80 wt% to 10-30 wt%.

[0043] In some embodiments, in the first direction, the content of the first gate electrode material in the first contact layer gradually increases from 20-30 wt% to 70-90 wt%. This variation in the content of the first gate electrode is beneficial because as one moves closer to the first gate electrode, the metal composition in the first contact layer gradually increases, and may even slowly transition to pure metal, thus forming a metal contact with the fine gate line, thereby creating a complete ohmic contact and enhancing carrier transport.

[0044] Understandably, the content of the first gate electrode material gradually increases from 20-30 wt% to 70-90 wt%. This gradual increase occurs when the content increases uniformly by 10 wt%, 15 wt%, 20 wt%, or any other arbitrary percentage as the thin film grows. Alternatively, the content of the first gate electrode can be gradually increased from 20-30 wt% to 70-90 wt% using a random variable.

[0045] In some embodiments, the thickness of the first contact layer is 5-15 nm. If the thickness of the first contact layer is too thick, it will prolong the process time and is not conducive to mass production; if the thickness of the first contact layer is too thin, it will fail to reduce the work function and bandgap between the first conductive layer and the first gate electrode.

[0046] In some embodiments, the silicon substrate comprises an N-type silicon wafer. The N-row silicon wafer has a pyramidal textured surface.

[0047] In some embodiments, the first passivation layer comprises intrinsic hydrogenated amorphous silicon, hydrogenated oxygen-doped amorphous silicon, or hydrogenated carbon-doped amorphous silicon. Thus, the first passivation layer can passivate dangling bonds formed after the silicon substrate has been diced.

[0048] Optionally, the thickness of the first passivation layer is 5-15 nm.

[0049] In some embodiments, the N-side doped layer includes phosphorus-doped amorphous silicon, phosphorus-doped microcrystalline silicon, phosphorus-doped microcrystalline silicon oxide, or phosphorus-doped microcrystalline silicon carbide.

[0050] Optionally, the thickness of the N-side doped layer is 5-30 nm.

[0051] The first conductive layer can enhance lateral conductivity to transport charge carriers, and also serves as an anti-reflection layer material to reduce the surface reflectivity of the solar cell.

[0052] Optionally, the first conductive layer material includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO.

[0053] Optionally, the thickness of the first conductive layer is 80-90 nm.

[0054] In some embodiments, the first gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

[0055] In some embodiments, reference Figure 2 The heterojunction solar cell further includes: a second passivation layer 7, located on the side of the silicon substrate 1 away from the first passivation layer 2; a P-side doped layer 8, located on the side of the second passivation layer 7 away from the silicon substrate; a second conductive layer 9, located on the side of the P-side doped layer 8 away from the second passivation layer 7; a second contact layer 10, located on the side of the second conductive layer 9 away from the P-side passivation layer; and a second grid electrode 11, located on the side of the second contact layer 10 away from the second conductive layer 9. The second contact layer material is composed of the second grid electrode material and the second conductive layer material. In the direction opposite to the first direction, the content of the second conductive layer material gradually decreases, and the content of the second grid electrode material gradually increases. Thus, by covering the second conductive layer with the second contact layer, due to the strong conductivity of the second contact layer, a fine grid electrode does not need to be designed on the P-side; that is, the second contact layer can function as a fine grid electrode, and the second grid electrode can function as the main grid electrode.

[0056] In some embodiments, the thickness of the second contact layer is 10-30 nm.

[0057] In some embodiments, in the direction opposite to the first direction, the thickness and content of the second conductive layer material in the second contact layer gradually decrease from 70-80 wt% to 0-10 wt%. Thus, in addition to the function of the first contact layer, the second contact layer, when in contact with the second main grid electrode, has a material composition close to pure metal, which is beneficial for enhancing the internal reflection of long-wavelength incident light and improving the current density of the solar cell.

[0058] Understandably, in the second contact layer, the content of the second conductive layer material gradually decreases from 70-80 wt% to 0-10 wt%. This gradual decrease is carried out uniformly in increments of 10 wt%, 15 wt%, or 20 wt% as the film grows; for example, the content of the second conductive layer material decreases uniformly from an initial 80 wt% to 0. Alternatively, the content of the second conductive layer material can be gradually decreased from 70-80 wt% to 0-10 wt% using a random variable.

[0059] In some embodiments, in the direction opposite to the first direction, the content of the second grid electrode material in the second contact layer gradually increases from 20-30 wt% to 90-100 wt%. In this way, in addition to having the function of the first contact layer, the material composition of the second contact layer is close to pure metal when it comes into contact with the second grid electrode, which is beneficial to enhance the internal reflection of long-wavelength incident light and improve the current density of the solar cell.

[0060] Understandably, in the second contact layer, the content of the second gate electrode material gradually increases from 20-30 wt% to 90-100 wt%. This gradual increase is carried out by uniformly increasing the content by any number of 10 wt%, 15 wt%, or 20 wt% as the thin film grows.

[0061] In some embodiments, the second gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

[0062] In some embodiments, the second passivation layer comprises intrinsic hydrogenated amorphous silicon, hydrogenated oxygen-doped amorphous silicon, or hydrogenated carbon-doped amorphous silicon. Thus, the second passivation layer can passivate dangling bonds formed after the silicon wafer has been cut.

[0063] Optionally, the thickness of the second passivation layer is 5-15 nm.

[0064] In some embodiments, the P-side doped layer includes boron-doped amorphous silicon, boron-doped microcrystalline silicon, boron-doped microcrystalline silicon oxide, or boron-doped microcrystalline silicon carbide.

[0065] Optionally, the thickness of the P-side doped layer is 5-40 nm.

[0066] The second conductive layer can enhance lateral conductivity to transport charge carriers, and also serve as an anti-reflection layer material to reduce the surface reflectivity of the solar cell.

[0067] Optionally, the material of the second conductive layer includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO.

[0068] Optionally, the thickness of the second conductive layer is 100-140 nm. A thickness greater than that of the first conductive layer is beneficial for enhancing the lateral transport of charge carriers on the back side (P-side).

[0069] In some embodiments, the first gate electrode includes a first main gate electrode and a first fine gate electrode, wherein the first main gate electrode is located on the side of the first fine gate electrode away from the first contact layer and intersects the first fine gate electrode and the first main gate electrode perpendicularly.

[0070] Optionally, the first main gate electrode and the first fine gate electrode are made of the same material.

[0071] A second aspect of this application provides a method for fabricating a heterojunction solar cell. The method includes the following steps: (1) A silicon substrate is provided; (2) A first passivation layer, an N-side doped layer, and a first conductive layer are sequentially formed on one side surface of the silicon substrate; (3) A first contact layer is formed on the side of the first conductive layer away from the N-side doped layer according to a first predetermined pattern; (4) A first gate electrode is formed on the side of the first contact layer away from the first conductive layer; wherein the material of the first contact layer is composed of the material of the first conductive layer and the material of the first gate electrode. The method of this application is simple to operate and can obtain a heterojunction solar cell with good photoelectric performance.

[0072] According to an embodiment of this application, step (1) provides a silicon substrate.

[0073] In some embodiments, the silicon substrate is cleaned and texturized. The purpose of the cleaning process is to remove surface organic matter and metal ions, facilitating the formation of the functional layer of the solar cell on the silicon substrate surface. This application does not limit the cleaning method; it can be an RCA industry standard wet cleaning process, i.e., using SPM (H2SO4 / H2O2), HF (DHF), APM (NH4OH / H2O2 / H2O), or HPM (HCl / H2O2 / H2O). The purpose of texturizing is to form a uniformly sized, uneven structure on the silicon wafer surface. This uneven structure exhibits a pyramid-like microstructure, with millions of tetrahedral pyramids forming per square centimeter of silicon surface. This treatment allows the pyramidal structure on the silicon wafer surface to increase light absorption when incident light enters from different angles, thereby improving the short-circuit current and conversion efficiency of the cell. The texturing process for monocrystalline silicon utilizes the anisotropic etching of silicon. This application does not limit the specific method used for texturing; hot alkaline solutions such as sodium hydroxide, potassium hydroxide, lithium hydroxide, and ethylenediamine solutions can be used to achieve this process. Alternatively, after obtaining a silicon substrate with several tetrahedral pyramids on its surface through texturing with a hot alkaline solution, a suitable method, such as mechanical polishing, can be used to polish the tetrahedral pyramids constituting the pyramidal textured surface of the silicon substrate, transforming the sharp pyramidal structures on the surface of the tetrahedral pyramidal structure into a smooth, pyramidal-like structure. Furthermore, an acidic solution, such as HF, can be used to remove the oxide layer from the pyramidal textured surface. Optionally, the cleaning and texturing process of the silicon wafer can be performed multiple times as needed. For example, after texturing with a hot alkaline solution, a cleaning process can be performed again as required by the design and process.

[0074] According to an embodiment of this application, step (2) involves sequentially forming a first passivation layer, an N-side doped layer, and a first conductive layer on one side surface of a silicon substrate.

[0075] In some embodiments, a first passivation layer, an N-side doped layer, and a first conductive layer are sequentially formed on one side surface of a silicon substrate using a PEVCD device.

[0076] Optionally, the first passivation layer comprises intrinsic hydrogenated amorphous silicon, hydrogenated oxygen-doped amorphous silicon, or hydrogenated carbon-doped amorphous silicon. Thus, the first passivation layer can passivate dangling bonds formed after the silicon substrate has been cut.

[0077] Optionally, the thickness of the first passivation layer is 5-15 nm.

[0078] In some embodiments, the N-side doped layer includes phosphorus-doped amorphous silicon, phosphorus-doped microcrystalline silicon, phosphorus-doped microcrystalline silicon oxide, or phosphorus-doped microcrystalline silicon carbide.

[0079] Optionally, the thickness of the N-side doped layer is 5-30 nm.

[0080] Generally, the first conductive layer can enhance lateral conductivity to transport charge carriers, and also serve as an anti-reflection layer material to reduce the surface reflectivity of the solar cell.

[0081] Optionally, the first conductive layer material includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO.

[0082] Optionally, the thickness of the first conductive layer is 80-90 nm.

[0083] According to an embodiment of this application, step (3) involves forming a first contact layer on the side of the first conductive layer away from the N-plane doped layer according to a first predetermined pattern, wherein the material of the first contact layer is composed of the first conductive layer material and the first gate electrode material.

[0084] In some embodiments, the first predetermined pattern refers to the pattern forming the first gate electrode.

[0085] In some embodiments, forming the first contact layer on the side of the first conductive layer away from the first passivation layer includes: forming the first contact layer on the side of the first conductive layer away from the first passivation layer by magnetron sputtering; during magnetron sputtering, the first conductive layer material is used as the first target, the first gate electrode material is used as the second target, the RF power of the first target gradually decreases, and the RF power of the second target gradually increases. This is beneficial for adjusting the composition of each component in the first contact layer, reducing the proportion of the first conductive layer material in the first contact layer, and increasing the proportion of the first gate electrode material.

[0086] Optionally, the RF power of the first target is 6-8 W / cm 2 Gradually decrease to 2-3 W / cm 2 This causes the content of the first conductive layer material to gradually decrease in the first direction.

[0087] Optionally, the RF power of the second target is 1-3 W / cm 2 Gradually increase to 3-6 W / cm2 This causes the content of the first grid electrode material to gradually increase in the first direction.

[0088] As an example, in magnetron sputtering, the first conductive layer material is used as the first target, and the first gate electrode material is used as the second target. The RF power of the first target is 7W / cm². 2 Gradually decrease to 2W / cm 2 The second target's RF power is 2W / cm 2 W gradually increased to 5 W / cm 2 .

[0089] In some embodiments, after step (3) and before step (4), the method further includes: sequentially forming a second passivation layer, a P-side doped layer, and a second conductive layer on the side of the silicon substrate away from the first passivation layer; forming a second contact layer on the side of the second conductive layer away from the P-side doped layer; and forming a second gate electrode on the side of the second contact layer away from the second conductive layer according to a second predetermined pattern, wherein the material of the second contact layer is composed of the material of the second gate electrode and the material of the second conductive layer.

[0090] The second predetermined pattern refers to the pattern of the second gate electrode.

[0091] In some embodiments, forming the second contact layer on the side of the second conductive layer away from the P-side doped layer includes: forming the first contact layer on the side of the second conductive layer away from the P-side doped layer using magnetron sputtering; during magnetron sputtering, the material of the second conductive layer is used as the third target, and the material of the second gate electrode is used as the fourth target, with the RF power of the third target gradually decreasing and the RF power of the fourth target gradually increasing. In this way, the second contact layer can act as a fine gate electrode, which is beneficial for further enhancing the lateral transport of charge carriers on the back side. The fine bandgap gate also helps reduce metal electrode consumption. Furthermore, in addition to the function of the first contact layer, the material composition of the second contact layer is close to pure metal when in contact with the second gate electrode, which is beneficial for enhancing the internal reflection of long-wavelength incident light and improving the current density of the solar cell.

[0092] In some embodiments, the RF power of the third target is 7-8 W / cm 2 Gradually decrease to 2-3 W / cm 2 .

[0093] In some embodiments, the RF power of the fourth target is 1-3 W / cm 2 Gradually increase to 3-6 W / cm 2 This causes the content of the second grid electrode material to gradually increase in the direction opposite to the first direction.

[0094] Optionally, the formation of a second passivation layer, a P-side doped layer, and a second conductive layer sequentially on the side of the silicon substrate away from the first passivation layer is performed in a PECVD apparatus.

[0095] In some embodiments, the second passivation layer comprises intrinsic hydrogenated amorphous silicon, hydrogenated oxygen-doped amorphous silicon, or hydrogenated carbon-doped amorphous silicon. Thus, the second passivation layer can passivate dangling bonds formed after the silicon wafer has been cut.

[0096] Optionally, the thickness of the second passivation layer is 5-15 nm.

[0097] In some embodiments, the P-side doped layer includes boron-doped amorphous silicon, boron-doped microcrystalline silicon, boron-doped microcrystalline silicon oxide, or boron-doped microcrystalline silicon carbide.

[0098] Optionally, the thickness of the P-side doped layer is 5-30 nm.

[0099] The second conductive layer can enhance lateral conductivity to transport charge carriers, and also serves as an anti-reflection layer material to reduce the surface reflectivity of the solar cell.

[0100] Optionally, the material of the second conductive layer includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO.

[0101] Optionally, the thickness of the second conductive layer is 100-140 nm.

[0102] In the above terminology, the basis for the gradual increase in target RF power is that with increased power, more argon plasma can bombard the target surface per unit time, sputtering out more target material. This results in more molecules of the first gate electrode material (or second gate electrode material) target within the chamber at that time, thus sputtering more first gate electrode material (or second gate electrode material) onto the surface of the material (first conductive layer or second conductive layer). The gradual increase in target RF power is achieved by increasing the sputtering power by 0.5 W / cm² at fixed time intervals as the thin film grows. 2 This is done in a certain way.

[0103] The rationale for gradually decreasing the target RF power is that with reduced power, argon plasma can bombard the target surface per unit time, sputtering less target material. This leads to a gradual decrease in the number of molecules of the first or second conductive layer material within the chamber during that time period, resulting in a gradual reduction in the amount of TCO (first or second conductive layer material) sputtered onto the material surface. The gradual decrease in target RF power is achieved by increasing the sputtering power by 0.5 W / cm² at fixed time intervals as the thin film grows. 2 This is done in a certain way.

[0104] According to an embodiment of this application, step (4) involves forming a first gate electrode on the side of the first contact layer away from the first conductive layer.

[0105] Optionally, the first gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

[0106] Optionally, the method of forming the first gate electrode includes screen printing.

[0107] In some embodiments, the first gate electrode includes a first main gate electrode and a first fine gate electrode, wherein the first main gate electrode is located on the side of the first fine gate electrode away from the first contact layer, and the first main gate electrode intersects the first fine gate electrode perpendicularly.

[0108] In some embodiments, a second gate electrode is formed on the side of the second contact layer away from the second conductive layer.

[0109] In some embodiments, the second gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

[0110] In some embodiments, the second contact layer can function as a fine gate electrode, in which case the second gate line electrode serves as the second main gate electrode, and the number of gate lines in the second main gate electrode is greater than the number of gate lines in the first main gate electrode. This has the advantage of enhancing lateral transport and collection of charge carriers and reducing the series resistance of the solar cell.

[0111] In some embodiments, the method further includes baking and curing the solar cell forming the first main grid electrode and the second main grid electrode at 150-200°C.

[0112] A third aspect of this application provides an electrical device, including the heterojunction solar cell described in the first aspect or the heterojunction solar cell prepared by the preparation method described in the second aspect.

[0113] Optionally, the electrical equipment can be electric transportation equipment (such as ships, spacecraft, electric vehicles, and battery-powered vehicles), lighting equipment (lamp fixtures and auxiliary lighting elements), photovoltaic power generation equipment, and other equipment that requires electrical energy. The electrical equipment provided in this application has a high utilization rate of solar energy, which is beneficial for reducing costs and improving battery life.

[0114] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. It should be understood that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0115] Example 1 S1: Provides an N-type silicon substrate; the silicon substrate has a front side and a back side disposed opposite to each other; S2: The front and back sides of the silicon substrate are cleaned and textured to form a uniform pyramid textured structure on the front and back surfaces. Then, RCA cleaning is used to remove organic matter and metal ions from the surface. Next, the surface pyramid is smoothed by the Rounding process. Finally, the oxide layer is removed by HF solution. S3: A first passivation layer with a thickness of 10 nm is prepared on one side (equivalent to the front side) of a silicon substrate using a PECVD device; S4: A second passivation layer with a thickness of 11 nm is prepared on another surface (equivalent to the back side) using a PECVD device.

[0116] S5: An N-side doped layer (phosphorus-doped amorphous silicon layer) with a thickness of 25 nm and a first conductive layer (ITO) with a thickness of 85 nm are sequentially formed on the surface of the first passivation layer away from the silicon substrate using a PECVD device.

[0117] S6: According to the predetermined pattern, a first contact layer is formed on the side of the first conductive layer away from the N-plane doped layer using magnetron sputtering; during magnetron sputtering, the first conductive layer material ITO is used as the first target, and the first gate electrode material silver is used as the second target. The RF power of the first target is gradually reduced (from 7W / cm²). 2 Gradually decrease to 2W / cm 2 The RF power of the second target gradually increases (from 2W / cm). 2 Gradually increase to 5 W / cm 2 The thickness of the first contact layer is controlled to be 10nm. Initially, the material content of the first conductive layer is 80wt% and the material content of the first gate electrode is 20wt%. When sputtering ends, the material content of the first conductive layer is 10wt% and the material content of the first gate electrode is 90wt%.

[0118] S7: Using a PEVCD device, a 25nm thick P-side doped layer (boron-doped amorphous silicon layer) and an 85nm thick first conductive layer (ITO) are sequentially formed on the surface of the second passivation layer away from the silicon substrate.

[0119] S8: A first contact layer is formed on the side of the second conductive layer away from the P-plane doped layer using magnetron sputtering; during magnetron sputtering, ITO (the material of the third conductive layer) is used as the first target, and silver (the material of the second gate electrode) is used as the fourth target. The RF power of the third target gradually decreases (from 7W / cm²). 2 Gradually decrease to 3W / cm 2 The RF power of the fourth target gradually increases (from 2W / cm). 2 Gradually increase to 5 W / cm 2A second contact layer with a thickness of 20 nm was obtained. Initially, the material content of the second conductive layer was 80 wt% and the material content of the second gate electrode was 20 wt%. At the end of sputtering, the material content of the second conductive layer was 0 wt% and the material content of the second gate electrode was 100 wt%.

[0120] S9: A first fine gate electrode is formed on the side of the first contact layer away from the first conductive layer, and a first main gate electrode is formed on the side of the first fine gate electrode away from the first contact layer. The first main gate electrode is perpendicular to the first fine gate electrode.

[0121] A second gate electrode is formed on the side of the second contact layer away from the second conductive layer (the second contact layer acts as a fine gate electrode and a second main gate electrode). The first fine gate electrode, the first main gate electrode, and the second gate electrode are all metallic silver electrodes.

[0122] S10: Dry the product obtained in step S9 at 200°C to obtain a heterojunction solar cell.

[0123] Examples 2 and 3 Heterojunction solar cells were prepared according to the method of Example 1, except that in S6, the thicknesses of the first contact layers were 5 nm and 15 nm, respectively.

[0124] Examples 4 and 5 Heterojunction solar cells were prepared according to Example 1, except that in S8, the thicknesses of the first contact layers were 10 nm and 30 nm, respectively.

[0125] Example 6 A heterojunction solar cell was fabricated according to the method described in Example 1, except that in S6: a first contact layer was formed on the side of the first conductive layer away from the N-plane doped layer by magnetron sputtering according to a predetermined pattern; during magnetron sputtering, the first conductive layer material ITO was used as the first target material, and the first grid electrode material silver was used as the second target material, and the radio frequency power of the first target material was gradually reduced (from 7W / cm). 2 Uneven reduction to 2W / cm 2 The RF power of the second target gradually increases (from 2W / cm). 2 Uneven up to 5W / cm 2 The thickness of the first contact layer is controlled to be 10nm. Initially, the material content of the first conductive layer is 80wt% and the material content of the first gate electrode is 20wt%. When sputtering ends, the material content of the first conductive layer is 10wt% and the material content of the first gate electrode is 90wt%.

[0126] S8: A first contact layer is formed on the side of the second conductive layer away from the P-plane doped layer using magnetron sputtering; during magnetron sputtering, ITO (the material of the third conductive layer) is used as the first target, and silver (the material of the first gate electrode) is used as the fourth target. The RF power of the third target is gradually reduced (from 7W / cm²). 2 Uneven reduction to 3W / cm 2 The RF power of the fourth target gradually increases (from 2W / cm). 2 Uneven increase to 5W / cm 2 A second contact layer with a thickness of 20 nm was obtained. Initially, the material content of the second conductive layer was 80 wt% and the material content of the first gate electrode was 20 wt%. When sputtering was completed, the material content of the second conductive layer was 0 wt% and the material content of the first gate electrode was 100 wt%.

[0127] Comparative Example 1 The heterojunction solar cell was fabricated in accordance with the method of Example 1, except that steps S6 and S8 were not performed.

[0128] Comparative Example 2 The heterojunction solar cell was fabricated according to the method of Example 1, except that, in step S6: a first contact layer was formed on the side of the first conductive layer away from the N-side doped layer by magnetron sputtering according to a predetermined pattern; during magnetron sputtering, the first conductive layer material ITO was used as the first target material, and the RF power of the first target material was 6 W / cm. 2 Furthermore, the thickness of the first contact layer is controlled to be 10nm.

[0129] Comparative Example 3 The heterojunction solar cell was fabricated according to the method of Example 1, except that, in step S6: a first contact layer was formed on the side of the first conductive layer away from the N-side doped layer by magnetron sputtering according to a predetermined pattern; during magnetron sputtering, silver, a fine grid electrode material, was used as the second target, and the radio frequency power of the second target was 5 W / cm. 2 Furthermore, the thickness of the first contact layer is controlled to be 10nm.

[0130] The batteries of the above embodiments and comparative examples were tested as follows, and the results are shown in Table 1.

[0131] Photovoltaic performance test: The battery was placed under standard sunlight (100mW / cm²) on a solar simulator AM1.5G. 2 Under these conditions, a Keithley 2400 source meter was used to perform voltage-current curve scanning; the scanning range was -0.5-2V, the scanning step size was 20mV, and the scanning time was 30s.

[0132] Table 1

[0133] As shown in Table 1 above, the heterojunction solar cells of Examples 1-6 exhibit superior photoelectric performance compared to the solar cells of Comparative Examples 1-3. This is because the addition of a special contact layer (first contact layer or second base layer) reduces the work function mismatch and bandgap between the first conductive layer and the first grid electrode (between the second conductive layer and the second main grid), and lowers the carrier transport barrier. This helps to reduce the Rs of the heterojunction solar cell, thereby improving the FF and efficiency of the heterojunction solar cell.

[0134] Comparing Example 1 and Example 6, the heterojunction solar cell obtained by uniformly varying the materials of the first conductive layer and the first grid electrode in the first contact layer and the materials of the second conductive layer and the first grid electrode in the second contact layer in Example 1 has better performance than the heterojunction solar cell in Example 6. This shows that uniform variation of materials in the first contact layer and / or the second contact layer is beneficial to reducing band bending caused by work function mismatch.

[0135] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0136] It should also be noted that the terms "some embodiments," "other embodiments," and "embodiments" used in this application refer to specific features, structures, or characteristics described in connection with those embodiments, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0137] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0138] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A heterojunction solar cell, characterized in that, include: Silicon substrate; A first passivation layer is located on one side of the silicon substrate; An N-side doped layer is located on the side of the first passivation layer away from the silicon substrate; A first conductive layer is located on the side of the N-plane doped layer away from the silicon substrate; The first gate electrode is located on the side of the first conductive layer away from the first passivation layer; A first contact layer is located between the first conductive layer and the first gate electrode. The projection of the first contact layer and the first gate electrode onto the first conductive layer coincides. The material of the first contact layer is composed of the material of the first conductive layer and the material of the first gate electrode.

2. The heterojunction solar cell according to claim 1, characterized in that, In a first direction, the content of the first conductive layer material in the first contact layer gradually decreases, and the content of the first gate electrode material gradually increases. The first direction is the direction from the silicon substrate to the first passivation layer in the thickness direction of the silicon substrate.

3. The heterojunction solar cell according to claim 1 or 2, characterized in that, In the first direction, the content of the first conductive layer material in the first contact layer gradually decreases from 70-80 wt% to 10-30 wt%. In the first direction, the content of the first gate electrode material in the first contact layer gradually increases from 20-30wt% to 70-90wt%.

4. The heterojunction solar cell according to claim 1 or 2, characterized in that, The thickness of the first contact layer is 5-15 nm; And / or, the first conductive layer material includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO; And / or, the first gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

5. The heterojunction solar cell according to claim 1, characterized in that, Also includes: A second passivation layer is located on the side of the silicon substrate away from the first passivation layer; A P-side doped layer is located on the side of the second passivation layer away from the silicon substrate; The second conductive layer is located on the side of the P-plane doped layer away from the second passivation layer; The second contact layer is located on the side of the second conductive layer away from the P-surface passivation layer; The second gate electrode is located on the side of the second contact layer away from the second conductive layer; The second contact layer material is composed of the second gate electrode material and the second conductive layer material. In the direction opposite to the first direction, the content of the second conductive layer material gradually decreases, and the content of the second gate electrode material gradually increases.

6. The heterojunction solar cell according to claim 5, characterized in that, The thickness of the second contact layer is 10-30 nm; And / or, in the direction opposite to the first direction, the content of the second conductive layer material in the second contact layer gradually decreases from 70-80 wt% to 0-10 wt%; And / or, in the direction opposite to the first direction, the content of the second gate electrode material in the second contact layer gradually increases from 20-30 wt% to 90-100 wt%; And / or, the second conductive layer material includes at least one of ITO, IWO, IZO, AZO, ICO, and GZO; And / or, the first gate electrode material includes at least one of Ag, Cu, Al, Ni, and Au.

7. A method for fabricating a heterojunction solar cell, characterized in that, include: Provide silicon substrate; A first passivation layer, an N-plane doped layer, and a first conductive layer are sequentially formed on one side surface of the silicon substrate; A first contact layer is formed on the side of the first conductive layer away from the N-plane doped layer according to a first predetermined pattern; A first gate electrode is formed on the side of the first contact layer away from the first conductive layer; The material of the first contact layer is composed of the material of the first conductive layer and the material of the first gate electrode.

8. The preparation method according to claim 7, characterized in that, The method of forming a first contact layer on the side of the first conductive layer away from the first passivation layer includes: The first contact layer is formed on the side of the first conductive layer away from the first passivation layer by magnetron sputtering. During the magnetron sputtering process, the first conductive layer material is used as the first target material, the first gate electrode material is used as the second target material, and the radio frequency power of the first target material gradually decreases while the radio frequency power of the second target material gradually increases.

9. The preparation method according to claim 8, characterized in that, Also includes: A second passivation layer, a P-side doped layer, and a second conductive layer are sequentially formed on the side of the silicon substrate away from the first passivation layer. A second contact layer is formed on the side of the second conductive layer away from the P-plane doped layer; A second gate electrode is formed on the side of the second contact layer away from the second conductive layer according to a second predetermined pattern. The second contact layer material is composed of the second gate electrode and the second conductive layer material.

10. The preparation method according to claim 9, characterized in that, The method of forming the second contact layer on the side of the second conductive layer away from the P-plane doped layer includes: The first contact layer is formed on the side of the second conductive layer away from the P-plane doped layer by magnetron sputtering. During the magnetron sputtering process, the second conductive layer material is used as the third target, the second gate electrode material is used as the fourth target, and the radio frequency power of the third target gradually decreases while the radio frequency power of the fourth target gradually increases.

11. The preparation method according to claim 10, characterized in that, The first target material has a radio frequency power of 6-8 W / cm 2 Gradually decrease to 2-3 W / cm 2 ; And / or, the RF power of the second target is 1-3 W / cm 2 Gradually increase to 3-6 W / cm 2 ; And / or, the RF power of the third target is 7-8 W / cm 2 Gradually decrease to 2-3 W / cm 2 ; And / or, the RF power of the fourth target is 1-3 W / cm 2 Gradually increase to 3-6 W / cm 2 .

12. An electrical appliance, characterized in that, This includes heterojunction solar cells according to any one of claims 1-6, or heterojunction solar cells prepared using the method according to any one of claims 7-11.

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