Copper-indium-gallium-selenium solar cell with interface dipole layer and method of manufacturing the same

Abstract

The application provides a preparation method of a copper-indium-gallium-selenium solar cell with an interface dipole layer, comprising the following steps: firstly, preparing a back electrode layer and a copper-indium-gallium-selenium absorbing layer on a substrate in sequence; then introducing a silver source and a cesium source on the surface of the copper-indium-gallium-selenium absorbing layer in sequence, so that the silver source fills defect sites on the surface of the copper-indium-gallium-selenium absorbing layer, and the cesium source grows in combination with the silver source to obtain a precursor layer; then performing annealing treatment on the precursor layer, so that the silver source and the cesium source diffuse and rearrange to obtain the interface dipole layer; and finally preparing a buffer layer, a window layer and a grid line on the interface dipole layer in sequence. In another aspect of the application, a copper-indium-gallium-selenium solar cell obtained by using the above preparation method is also provided.

Description

Technical Field

[0001] This application belongs to the field of thin-film solar cells, specifically relating to a copper indium gallium selenide solar cell with an interface dipole layer and its preparation method. Background Technology

[0002] Copper indium gallium selenide (CIGS or CIGSe) thin-film solar cells, as a new generation of photovoltaic devices, still have actual open-circuit voltages significantly lower than the theoretical limit, and voltage loss restricts further performance improvements. Research indicates that bulk defects in the absorber layer and recombination centers at the absorber / buffer layer interface are the main reasons for enhanced non-radiative recombination of charge carriers. Among numerous optimization techniques, alkali metal (Na, K, Rb, Cs) post-treatment techniques are widely used in CIGS device systems due to their effectiveness in passivating grain boundary defects, modulating surface band structures, and optimizing charge carrier distribution. Heavy alkali metal treatments, represented by cesium, have shown some effectiveness in improving open-circuit voltage.

[0003] However, cesium post-processing methods in related technologies still have significant limitations in practical applications. Cesium tends to form a non-uniform distribution on the surface of the absorber layer and at grain boundaries, leading to localized enrichment. This non-uniform distribution easily forms potential barriers or high-resistivity regions at the interface, affecting carrier transport processes and potentially causing an increase in series resistance and a decrease in fill factor, thus limiting further improvements in device performance. Although related technologies have improved these problems to some extent by adjusting the doping dosage or process conditions, it is still difficult to effectively control the spatial distribution of cesium and its localized effects.

[0004] Therefore, there is an urgent need to develop a new interface modulation method to achieve precise control over the distribution and behavior of alkali metals on the absorber surface, thereby reducing interfacial recombination while improving carrier transport performance and achieving a synergistic improvement in open-circuit voltage and fill factor. This technological breakthrough has significant implications for the interface modulation of high-efficiency thin-film solar cells. Summary of the Invention

[0005] In view of this, in order to solve at least one technical problem in related technologies and other aspects, this application proposes a method for fabricating a copper indium gallium selenide solar cell with an interface dipole layer, comprising:

[0006] A back electrode layer and a copper indium gallium selenide (CIGS) absorber layer are sequentially fabricated on a substrate.

[0007] Silver and cesium sources are sequentially introduced onto the surface of the copper indium gallium selenide (CIGS) absorber layer. The silver source fills the defect sites on the surface of the CIGS absorber layer, and the cesium source grows by attaching to the silver source to obtain a precursor layer. The precursor layer is then annealed to allow the silver and cesium sources to diffuse and rearrange, resulting in an interfacial dipole layer.

[0008] A buffer layer, a window layer, and a gate line are sequentially fabricated in the interface dipole layer.

[0009] According to embodiments of this application, the method for introducing a silver source includes at least one of evaporation, sputtering, co-evaporation, and solution methods;

[0010] The methods for introducing cesium sources include at least one of the following: evaporation, solution method, and solid-state diffusion method;

[0011] Based on the total number of atoms in the silver and cesium sources, the proportion of atoms in the silver source is 0.01 to 0.3.

[0012] According to embodiments of this application, the silver source is selected from at least one of metallic silver, silver fluoride, and silver sulfide; the cesium source is selected from at least one of cesium fluoride, cesium carbonate, cesium nitrate, cesium hydroxide, cesium sulfide, and cesium iodide.

[0013] According to embodiments of this application, in the annealing process, the annealing environment is a vacuum or inert atmosphere, with a vacuum degree of 10. -3 ~10 -5 Pa, annealing temperature is 100~500℃, annealing time is 1-30min.

[0014] According to embodiments of this application, the preparation of the back electrode layer includes:

[0015] Molybdenum is deposited on the surface of a substrate by magnetron sputtering to form a back electrode. The substrate is soda-lime glass and the thickness of the back electrode layer is 500~1500 nm. In the magnetron sputtering, the sputtering power is 100~400 W and the sputtering pressure is 0.1~0.5 Pa.

[0016] According to an embodiment of this application, the preparation of a copper indium gallium selenide (CIGS) absorber layer includes: depositing CIGS on the surface of a back electrode layer using a three-step co-evaporation method to obtain a CIGS absorber layer with a thickness of 1.5~3.5 μm; wherein the temperature gradient of the three-step co-evaporation method is 420℃, 450℃, and 450℃ respectively, and the band gap of CIGS is 1.02~1.34 eV.

[0017] According to an embodiment of this application, the preparation of the buffer layer includes: depositing cadmium sulfide on the surface of the interfacial dipole layer by chemical bath deposition to obtain a buffer layer with a thickness of 30~60nm; wherein, in the chemical bath deposition method, the deposition temperature is 50~95℃ and the deposition time is 5~20min.

[0018] According to an embodiment of this application, the preparation of the window layer includes:

[0019] Intrinsic zinc oxide and aluminum-doped zinc oxide are sequentially deposited on the surface of the buffer layer by magnetron sputtering to obtain a window layer. The thickness of the intrinsic zinc oxide is 50~120nm and the thickness of the aluminum-doped zinc oxide is 200~600nm. In the magnetron sputtering, the sputtering power is 50~300W and the sputtering pressure is 0.2~1.0Pa.

[0020] According to an embodiment of this application, the preparation of the gate line includes: sequentially depositing nickel and aluminum on the surface of the window layer by electron beam evaporation to obtain the gate line, wherein the thickness of nickel is 20~50nm and the thickness of aluminum is 50~150nm; wherein the evaporation beam current of the electron beam evaporation method is 0.03~0.3A.

[0021] In another aspect of this application, a copper indium gallium selenide (CIGS) solar cell prepared according to the aforementioned method is also proposed, comprising a substrate, a back electrode layer, a CIGS absorber layer, an interface dipole layer, a buffer layer, a window layer, and grid lines; wherein the interface dipole layer is a silver-cesium composite material, and the proportion of silver atoms is 0.01 to 0.3% based on the total number of atoms in the silver-cesium composite material.

[0022] According to embodiments of this application, a back electrode layer and a copper indium gallium selenide (CIGS) absorber layer are first sequentially fabricated on a substrate to provide a basis for subsequent interface modulation. A silver source and a cesium source are sequentially introduced onto the surface of the CIGS absorber layer. The silver source preferentially fills surface defect sites, eliminating high-energy defects on the CIGS absorber layer surface and providing uniform nucleation sites for the subsequent cesium source. The cesium source grows by attaching to the silver source, avoiding local enrichment of cesium at CIGS grain boundaries or defects, forming a precursor layer with uniform compositional distribution. The precursor layer is annealed, causing diffusion and rearrangement of the silver and cesium sources, promoting further reaction to form a stable compound layer. This layer generates a directional charge separation effect in the vertical direction, i.e., an interface dipole layer. This interface dipole layer can adjust the band bending on the surface of the CIGS absorber layer, reducing carrier recombination losses at the interface. Simultaneously, due to the uniform cesium distribution, no local high-resistivity region or reverse barrier is formed at the interface, thereby increasing the open-circuit voltage while avoiding a decrease in the fill factor. Finally, a buffer layer, a window layer, and grid lines are sequentially fabricated on the interface dipole layer to complete the solar cell structure. Through the above steps, the interface passivation structure was optimized without significantly altering the original process route. Attached Figure Description

[0023] Figure 1 These are comparative images of the microstructure of the copper indium gallium selenide (CIGS) absorber layer in the test examples of this application. (a) is a scanning electron microscope image of the CIGS absorber layer in Example 1, and (b) is a scanning electron microscope image of the CIGS absorber layer in Comparative Example 1.

[0024] Figure 2 This is a depth profile comparison of the Cs element distribution in the copper indium gallium selenide absorber layer in the test example of this application;

[0025] Figure 3 The above are comparison diagrams of the energy level structure of the copper indium gallium selenide absorber layer in the test examples of this application, where (a) is the valence band spectrum and (b) is the secondary electron cutoff edge spectrum.

[0026] Figure 4 This is a comparison chart of the external quantum efficiency (EQE) and integral current of the copper indium gallium selenide solar cell in the test examples of this application;

[0027] Figure 5 This is a comparison chart of the characteristic curves (JV curves) showing the relationship between current density and voltage of the copper indium gallium selenide solar cell in the test examples of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0029] The endpoints and any values ​​of the ranges disclosed in this application are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this application.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0032] It should be noted that, unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person with ordinary skill in the art to which this application pertains. Where the terms "first," "second," etc., are used throughout, they are used only to distinguish similar objects and should not be construed as indicating or implying their relative importance, order of precedence, or implicitly specifying the number of technical features indicated. It should be understood that the data in the descriptions of "first," "second," etc., can be interchanged where appropriate.

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application.

[0034] Similarly, to simplify this application and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0035] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0036] In the process of realizing this application, it was discovered that although simple cesium (Cs) post-treatment can passivate defects and increase open-circuit voltage, cesium tends to accumulate locally on the surface and at grain boundaries of the copper indium gallium selenide (CIGS) absorber layer, forming discontinuous regions with high resistance, which actually impairs the fill factor. Silver has homology and good chemical affinity with the CIGS absorber layer, and can preferentially fill surface defect sites to form a uniform distribution.

[0037] Therefore, this application proposes to introduce silver onto the surface of the copper indium gallium selenide (CIGS) absorber layer before introducing cesium, so that the silver uniformly covers and occupies the surface defect sites. The subsequently introduced cesium will attach to the uniform nucleation sites provided by the silver and grow together, thereby avoiding the spontaneous aggregation of cesium. After annealing, the silver and cesium diffuse and rearrange, eventually forming a continuous and uniform interfacial dipole layer.

[0038] This application proposes a method for fabricating a copper indium gallium selenide (CIGS) solar cell with an interface dipole layer, comprising:

[0039] A back electrode layer and a copper indium gallium selenide (CIGS) absorber layer are sequentially fabricated on a substrate.

[0040] Silver and cesium sources are sequentially introduced onto the surface of the copper indium gallium selenide (CIGS) absorber layer. The silver source fills the defect sites on the surface of the CIGS absorber layer, and the cesium source grows by attaching to the silver source to obtain a precursor layer. The precursor layer is then annealed to allow the silver and cesium sources to diffuse and rearrange, resulting in an interfacial dipole layer.

[0041] A buffer layer, a window layer, and a gate line are sequentially fabricated in the interface dipole layer.

[0042] According to embodiments of this application, a back electrode layer and a copper indium gallium selenide (CIGS) absorber layer are first sequentially fabricated on a substrate to provide a basis for subsequent interface modulation. A silver source and a cesium source are sequentially introduced onto the surface of the CIGS absorber layer. The silver source preferentially fills surface defect sites, eliminating high-energy defects on the CIGS absorber layer surface and providing uniform nucleation sites for the subsequent cesium source. The cesium source grows by attaching to the silver source, avoiding local enrichment of cesium at CIGS grain boundaries or defects, forming a precursor layer with uniform compositional distribution. The precursor layer is annealed, causing diffusion and rearrangement of the silver and cesium sources, promoting further reaction to form a stable compound layer. This layer generates a directional charge separation effect in the vertical direction, i.e., an interface dipole layer. This interface dipole layer can adjust the band bending on the surface of the CIGS absorber layer, reducing carrier recombination losses at the interface. Simultaneously, due to the uniform cesium distribution, no local high-resistivity region or reverse barrier is formed at the interface, thereby increasing the open-circuit voltage while avoiding a decrease in the fill factor. Finally, a buffer layer, a window layer, and grid lines are sequentially fabricated on the interface dipole layer to complete the solar cell structure. Through the above steps, the interface passivation structure was optimized without significantly altering the original process route.

[0043] According to embodiments of this application, the method for introducing a silver source includes at least one of evaporation, sputtering, co-evaporation, and solution methods;

[0044] The methods for introducing cesium sources include at least one of the following: evaporation, solution method, and solid-state diffusion method;

[0045] Based on the total number of atoms in the silver and cesium sources, the proportion of atoms in the silver source is 0.01 to 0.3.

[0046] According to the embodiments of this application, the methods for introducing silver and cesium sources are universal and can be flexibly selected according to different process conditions and equipment. Specifically, among the methods for introducing silver sources, evaporation and sputtering methods can precisely control the deposition thickness and uniformity of the silver source and are easily integrated with existing vacuum processes; co-evaporation simplifies the process flow; and solution methods do not require vacuum equipment, have lower costs, and are suitable for large-area preparation. Among the methods for introducing silver sources, evaporation offers good controllability, solution methods can achieve uniform coating of the surface and grain boundary regions, and solid-state diffusion methods are simple. The combination of multiple introduction methods gives the precursor layer good process compatibility and adjustability.

[0047] In some specific embodiments, controlling the atomic percentage of the silver source in the precursor layer is beneficial for appropriately leveraging the regulatory effect of silver on cesium. If the atomic percentage of the silver source is less than 0.01, the coverage density of the silver source on the surface of the absorption layer is insufficient, failing to provide a sufficient number of uniformly distributed nucleation sites and making it difficult to fill defects on the surface of the copper indium gallium selenide (CIGS) absorption layer. Cesium sources still tend to accumulate at local defects, making it difficult to achieve a continuous and uniform distribution, thus failing to effectively improve the problem of uneven cesium distribution. If the atomic percentage of the silver source is greater than 0.3, excessive silver source may form a thick silver-rich layer on the surface of the absorption layer. On the one hand, this hinders the effective contact between the cesium source and the absorption layer; on the other hand, it may generate an excessively thick silver-cesium compound layer after annealing. If this layer is too thick, it may also become an additional barrier to carrier transport, increasing the interfacial series resistance and causing a decrease in the fill factor.

[0048] According to embodiments of this application, the silver source is selected from at least one of metallic silver, silver fluoride, and silver sulfide; the cesium source is selected from at least one of cesium fluoride, cesium carbonate, cesium nitrate, cesium hydroxide, cesium sulfide, and cesium iodide.

[0049] According to embodiments of this application, the silver source can take various forms, and the cesium source is selected from common cesium salts such as cesium fluoride and cesium carbonate, or cesium hydroxides, with a wide range of material sources. Different cesium sources have different decomposition temperatures and reactivity, which can be selected according to actual process requirements, facilitating the formation of a uniform interfacial dipole layer in synergy with the silver source.

[0050] According to embodiments of this application, in the annealing process, the annealing environment is a vacuum or inert atmosphere, with a vacuum degree of 10. -3 ~10 -5 Pa, for example, can be 10. -3 Pa, 10 -4 Pa, 10 -5 The annealing temperature is 100~500℃, for example, 100℃, 200℃, 300℃, 400℃, 500℃, etc., or any two of them. The annealing time is 1-30min, for example, 1min, 5min, 10min, 15min, 20min, 25min, 30min, etc., or any two of them.

[0051] According to embodiments of this application, a vacuum or inert atmosphere is beneficial to prevent the oxidation of silver and cesium sources; a higher vacuum level is beneficial to the removal of impurities; and suitable annealing temperature and annealing time are beneficial to promoting the full diffusion and reaction of silver and cesium to form a uniform and stable interfacial dipole layer.

[0052] In some specific embodiments, if the annealing temperature is below 100°C or the time is too short, diffusion will be insufficient; if the annealing temperature is above 500°C or the time is too long, it will easily lead to an excessively thick interfacial dipole layer or compositional segregation, increasing interfacial recombination and series resistance.

[0053] In some specific embodiments, the annealing process is either in-situ annealing or off-situ annealing; the heating equipment is one of a tube furnace, a rapid annealing furnace, or a heating system integrated into the deposition equipment;

[0054] According to embodiments of this application, the preparation of the back electrode layer includes:

[0055] Molybdenum is deposited on the surface of a substrate by magnetron sputtering to form a back electrode. The substrate is soda-lime glass, and the thickness of the back electrode layer is 500~1500nm, for example, 500nm, 1000nm, 1500nm, or any combination thereof. In the magnetron sputtering, the sputtering power is 100~400W, for example, 100W, 200W, 300W, 400W, or any combination thereof, and the sputtering pressure is 0.1~0.5Pa, for example, 0.1Pa, 0.2Pa, 0.3Pa, 0.4Pa, 0.5Pa, or any combination thereof.

[0056] According to embodiments of this application, using molybdenum as a metal source, a back electrode with lower resistance and higher adhesion can be obtained by magnetron sputtering. Specifically, suitable sputtering power and sputtering gas pressure are beneficial for controlling the density and stress of the thin film; suitable back electrode thickness is beneficial for providing good conductivity and back reflection.

[0057] In some specific embodiments, if the back electrode layer is too thin, the resulting resistance will be large; if the back electrode layer is too thick, the stress will increase and the cost will rise. If the deposition power is too low, the deposition rate will be slow and the film will be loose; if the deposition power is too high, internal stress will be generated. If the deposition gas pressure is too low, the film will be dense but the adhesion will be poor; if the deposition gas pressure is too high, the structure will be loose and the resistance will increase.

[0058] According to embodiments of this application, the preparation of a copper indium gallium selenide (CIGS) absorber layer includes:

[0059] A copper indium gallium selenide (CIGS) absorber layer is obtained by depositing CIGS on the surface of the back electrode layer using a three-step co-evaporation method. Specifically, the first step involves co-evaporating an indium source, a gallium source, and a selenium source to form an CIGS precursor layer on the back electrode layer surface. The second step introduces a copper source while continuing to supply a selenium source, transforming the precursor layer into a CIGS crystalline phase and promoting grain growth. The third step stops the copper source supply while continuing to introduce indium, gallium, and selenium sources to adjust the surface composition of the absorber layer, making the absorber layer copper-poor overall and creating a compositional environment favorable for the subsequent introduction of silver and cesium sources. The thickness of the CIGS absorber layer is 1.5–3.5 μm, for example, it can be 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or any combination thereof; where…

[0060] The temperature gradients of the three-step co-evaporation method are 420℃, 450℃, and 450℃ respectively, and the band gap of copper indium gallium selenide is 1.02~1.34eV.

[0061] According to the embodiments of this application, the above-described three-step co-evaporation method and temperature gradient are beneficial for obtaining a copper indium gallium selenide (CIGS) absorber layer with good crystal quality and controllable surface composition. The lower temperature in the first step facilitates the formation of a continuous CIGS precursor layer; the temperature settings in the second and third steps promote the formation of the CIGS crystal phase and avoid excessively high temperatures that could lead to elemental volatilization or surface composition segregation. By supplementing the indium, gallium, and selenium sources in the third step, the absorber layer surface can maintain a moderately copper-poor state, thereby reducing high-energy surface defects and providing a basis for subsequent silver source occupancy of surface defect sites, control of cesium source distribution, and formation of an interfacial dipole layer.

[0062] In some specific embodiments, if the temperature of the three-step co-evaporation method is too low, the copper indium gallium selenide (CIGS) crystal phase will not form sufficiently, resulting in a smaller absorber layer grain size and an increase in bulk and surface defects, which is detrimental to the uniform distribution of the silver and cesium sources on the surface. If the temperature is too high, it can easily lead to the volatilization of elements such as selenium and indium or abnormal distribution of gallium elements, causing surface composition segregation and making it difficult for the subsequent silver / cesium synergistic modulation process to proceed stably. If the band gap of the CIGS absorber layer is lower than 1.02 eV, the open-circuit voltage loss of the device will be large; if the band gap is higher than 1.34 eV, the short-circuit current will decrease, and it may exacerbate the band mismatch at the absorber / buffer layer interface, weakening the improvement effect of the interface dipole layer on carrier transport and interface recombination.

[0063] According to an embodiment of this application, the preparation of the buffer layer includes:

[0064] Cadmium sulfide is deposited on the surface of the interfacial dipole layer using a chemical bath deposition method to obtain a buffer layer. The thickness of the buffer layer is 30-60 nm, for example, it can be 30 nm, 40 nm, 50 nm, 60 nm, or any combination thereof.

[0065] In the chemical bath deposition method, the deposition temperature is 50~95℃, for example, it can be 50℃, 55℃, 60℃, 65℃, 70℃, 75℃, 80℃, 85℃, 90℃, 95℃, etc. or any two of them, and the deposition time is 5~20min, for example, it can be 5min, 10min, 15min, 20min, etc. or any two of them.

[0066] According to embodiments of this application, cadmium sulfide can be uniformly coated onto the surface of the interface dipole layer by chemical bath deposition to form a dense buffer layer; controlling the deposition temperature and deposition time helps to control the reaction rate and obtain a uniform thin layer with controllable thickness, thereby achieving bandgap matching with the copper indium gallium selenide absorber layer.

[0067] In some specific embodiments, if the thickness of the buffer layer is too thin, the coverage will be incomplete; if it is too thick, the light absorption loss will increase. If the deposition temperature is too low or the deposition time is too short, the deposition will be insufficient. If the deposition temperature is too high or the deposition time is too long, agglomeration or impurities will easily occur, affecting the interface quality.

[0068] According to embodiments of this application, the preparation of the window layer includes: sequentially depositing intrinsic zinc oxide (i-ZnO) and aluminum-doped zinc oxide (AZO) on the surface of a buffer layer by magnetron sputtering to obtain the window layer. The thickness of the intrinsic zinc oxide is 50-120 nm, for example, it can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc., or any combination thereof. The thickness of the aluminum-doped zinc oxide is 200-600 nm, for example, it can be... The sputtering wavelength is 200nm, 300nm, 400nm, 500nm, 600nm, or any combination thereof; in magnetron sputtering, the sputtering power is 50~300W, for example, 50W, 100W, 150W, 200W, 250W, 300W, or any combination thereof, and the sputtering pressure is 0.2~1.0Pa, for example, 0.2Pa, 0.4Pa, 0.6Pa, 0.8Pa, 1.0Pa, or any combination thereof.

[0069] According to the embodiments of this application, a uniform and dense thin film can be obtained by preparing a window layer by magnetron sputtering; wherein, intrinsic zinc oxide can serve as a high-resistivity layer to prevent leakage, and aluminum-doped zinc oxide provides good lateral conductivity; suitable sputtering power and sputtering gas pressure are beneficial for controlling film quality and transmittance.

[0070] In some specific embodiments, if the intrinsic zinc oxide is too thin, leakage current will increase, and if it is too thick, the series resistance will increase; if the aluminum-doped zinc oxide is too thin, the conductivity will be insufficient, and if it is too thick, the light transmittance will be reduced; if the power or gas pressure deviates from the range, the film will be loose, the internal stress will be large, or the resistance will increase.

[0071] According to embodiments of this application, fabricating the gate line includes:

[0072] Nickel and aluminum are sequentially deposited on the surface of the window layer by electron beam evaporation to obtain the gate line. The thickness of nickel is 20~50nm, for example, 20nm, 30nm, 40nm, 50nm, or any combination thereof, and the thickness of aluminum is 50~150nm, for example, 50nm, 100nm, 150nm, or any combination thereof. The evaporation beam current of the electron beam evaporation method is 0.03~0.3A, for example, 0.03A, 0.05A, 0.1A, 0.2A, 0.3A, or any combination thereof.

[0073] According to embodiments of this application, nickel and aluminum are deposited sequentially using electron beam evaporation. Nickel is beneficial for enhancing the adhesion between the gate line and the window layer, while aluminum is beneficial for providing higher conductivity. Controlling an appropriate evaporation beam current is beneficial for controlling the deposition rate and film quality.

[0074] In some specific embodiments, if the nickel layer is too thin, the adhesion will be insufficient, and if it is too thick, the light-shielding and stress will be increased; if the aluminum layer is too thin, the conductivity will be poor, and if it is too thick, the light-shielding loss will be increased; if the beam current is too low, the film layer will be loose, and if the beam current is too high, it will easily cause sputtering or damage to the window layer.

[0075] In another aspect of this application, a copper indium gallium selenide (CIGS) solar cell prepared according to the aforementioned method is also proposed, comprising a substrate, a back electrode layer, a CIGS absorber layer, an interface dipole layer, a buffer layer, a window layer, and grid lines; wherein the interface dipole layer is a silver-cesium composite material, and the proportion of silver atoms is 0.01 to 0.3 based on the total number of atoms in the silver-cesium composite material, for example, it can be 0.01, 0.05, 0.1, 0.2, 0.3, or any combination thereof.

[0076] According to embodiments of this application, using a silver-cesium composite material with a specific silver atomic ratio as the interfacial dipole layer is beneficial for controlling the uniform distribution of cesium by silver, while avoiding the additional potential barrier formed by excessive silver, effectively reducing interfacial recombination and improving carrier transport performance. The interfacial dipole layer can adjust the bandgap of the absorber surface, reducing interfacial recombination losses. Furthermore, due to the uniform distribution of silver and cesium, there are no local high-resistivity regions at the interface, thereby improving the open-circuit voltage while maintaining the fill factor, achieving an overall improvement in battery performance. The open-circuit voltage can be increased by up to 50mV, and the device efficiency is significantly improved.

[0077] In some specific embodiments, the substrate is made of soda-lime glass, the back electrode layer is made of molybdenum (Mo), the interface dipole layer is made of silver-cesium composite material (Ag-Cs), the buffer layer is made of cadmium sulfide (CdS), the window layer is made of intrinsic zinc oxide (i-ZnO) and aluminum-doped zinc oxide (AZO or Al:ZnO), and the gate line is made of nickel and aluminum (Ni:Al).

[0078] It should be noted that the described embodiments are merely some, not all, of the embodiments described in this application. Other embodiments obtained by those skilled in the art based on the embodiments described in this application without inventive effort are all within the scope of protection of this application.

[0079] Example 1

[0080] In this embodiment 1, a copper indium gallium selenide (CIGSe) battery is provided, with the following specific structure: a Mo back electrode, a CIGSe absorber layer, an interface dipole layer, a CdS buffer layer, i-ZnO and Al:ZnO window layers, and a Ni:Al gate. The interface dipole layer is formed by sequentially introducing Ag and Cs and then performing a post-processing.

[0081] The specific steps are as follows:

[0082] Step 1: Cleaning and pretreatment of the soda-lime glass substrate

[0083] The soda-lime glass substrate was sequentially immersed in detergent, deionized water, methanol, acetone, and isopropanol, and ultrasonically cleaned for 10 minutes in each solution to thoroughly remove organic contaminants and particulate impurities from the surface. After cleaning, the substrate was transferred to a vacuum drying oven and dried at 80°C for 30 minutes to ensure a clean and contamination-free surface before use.

[0084] Step 2: Deposit Mo back electrode

[0085] A bilayer Mo back electrode was deposited on a pretreated soda-lime glass substrate using DC magnetron sputtering. The first Mo layer deposition conditions were: sputtering pressure 0.2 Pa, sputtering power 200 W, and deposition thickness 600 nm; the second Mo layer deposition conditions were: sputtering pressure 0.4 Pa, sputtering power 320 W, and deposition thickness 700 nm.

[0086] Step 3: Preparation of CIGSe absorber layer

[0087] A CIGSe absorber layer was deposited on the Mo back electrode using a three-step co-evaporation method. The specific process parameters were as follows: the substrate temperature was set to 420℃, 450℃, and 450℃ sequentially; the film thickness was controlled at 2.0 μm; and the Eg was 1.15 eV.

[0088] Step 4: Fabrication of the interfacial dipole layer

[0089] 1) Introduction of Ag

[0090] Ag was introduced onto the surface of the CIGSe absorber layer using electron beam evaporation, and a thin Ag layer of about 15 nm thickness was deposited to achieve uniform distribution of Ag on the surface of the absorber layer.

[0091] 2) Cs post-processing

[0092] After Ag introduction, Cs post-treatment was performed on the sample surface. The Cs source was introduced by evaporation, and a Cs layer with a thickness of 10 nm was deposited on the surface of the absorption layer.

[0093] 3) Annealing treatment

[0094] The processed sample was placed in a tube furnace and evacuated to 10 °C. -4 Pa, then heated to 300℃ at a heating rate of 10℃ / min, and annealed at a constant temperature for 5 min. The heat treatment process promotes the diffusion and rearrangement of Cs under the regulation of Ag, forming a stable interfacial dipole layer on the surface of the CIGSe absorber layer.

[0095] Step 5: Prepare the CdS buffer layer

[0096] A CdS buffer layer was prepared by chemical bath deposition. 0.05 M Cd source, 2.0 M thiourea, and 3.5 M ammonia were added to 500 mL of deionized water. The deposition temperature was controlled at 85 °C, the deposition time at 7 min, and the stirring speed at 500 r / min, resulting in a CdS buffer layer with a thickness of approximately 50 nm.

[0097] Step 6: Preparation of i-ZnO and Al:ZnO window layers

[0098] i-ZnO and Al:ZnO window layers were deposited sequentially using magnetron sputtering. The i-ZnO deposition conditions were: sputtering pressure 0.90 Pa, sputtering power 100 W, and deposition thickness 70 nm; the Al:ZnO deposition conditions were: sputtering pressure 0.5 Pa, sputtering power 300 W, and deposition thickness 450 nm.

[0099] Step 7: Fabrication of Ni:Al gate electrode

[0100] Ni:Al gate electrodes were deposited using electron beam evaporation. First, a 50 nm thick Ni layer was deposited under an evaporation beam current of 0.04 A; subsequently, an 80 nm thick Al layer was deposited under an evaporation beam current of 0.2 A.

[0101] Comparative Example 1

[0102] Comparative Example 1 provides a CIGSe battery with the following structure: a Mo back electrode, a CIGSe absorber layer, an interface passivation layer, a CdS buffer layer, i-ZnO and Al:ZnO window layers, and a Ni:Al gate. The specific fabrication steps of the CIGSe battery in Comparative Example 1 are the same as or similar to those in Example 1, except that the interface passivation layer in Comparative Example 1 contains only cesium.

[0103] Test case

[0104] In this test example, the specific morphology and application performance of the CIGSe batteries prepared in Example 1 and Comparative Example 1 are compared.

[0105] First, the microstructure and elemental composition of the copper indium gallium selenide (CIGS) absorber layers in Example 1 and Comparative Example 1 were tested.

[0106] Figure 1 These are comparative images of the microstructure of the copper indium gallium selenide (CIGS) absorber layer in the test examples of this application. (a) is a scanning electron microscope image of the CIGS absorber layer in Example 1, and (b) is a scanning electron microscope image of the CIGS absorber layer in Comparative Example 1.

[0107] like Figure 1As shown in (a) and (b), after the interface dipole layer treatment, a continuous surface structure layer is formed on the surface of the copper indium gallium selenide (CIGS) absorber layer. Its morphology is significantly different from that of the untreated CIGS absorber layer, indicating a change in surface characteristics. That is, the introduction of Ag and the subsequent treatment with Cs resulted in a stable surface layer structure on the CIGSe surface.

[0108] Figure 2 This is a depth profile comparison of the Cs element distribution in the copper indium gallium selenide absorber layer in the test example of this application.

[0109] like Figure 2 As shown, in Comparative Example 1, Cs exhibits a certain degree of localized enrichment on the surface and near-surface region. However, in Example 1, after Ag was introduced and regulated, the distribution of Cs on the absorber layer surface became more uniform, and the localized enrichment phenomenon was significantly suppressed. These results demonstrate that the introduction of Ag can effectively regulate the diffusion and distribution behavior of Cs on the absorber layer surface, transforming it from localized aggregation to a relatively uniform distribution, thereby structurally improving the interface state and... Figure 1 The formation of the surface structure of the copper indium gallium selenide absorber layer shown corresponds to this.

[0110] Figure 3 The above are comparison diagrams of the energy level structure of the copper indium gallium selenide absorber layer in the test examples of this application. (a) is the valence band spectrum and (b) is the secondary electron cutoff edge spectrum.

[0111] like Figure 3 As shown in (a) and (b), the surface energy level structure of the sample changes after the interface dipole layer treatment, manifested as a shift in the valence band position and work function, indicating that the surface potential distribution is adjusted. This change helps optimize the band matching relationship at the interface, reduces the recombination probability of charge carriers at the interface, and thus improves the electrical characteristics of the device. Combined with... Figure 2 The changes in Cs distribution suggest that the energy level adjustment originates from changes in surface composition and distribution.

[0112] Next, the CIGSe batteries prepared in Example 1 and Comparative Example 1 were subjected to practical performance tests.

[0113] Figure 4 This is a comparison chart of the external quantum efficiency (EQE) and integrated current of the CIGSe solar cell in the test examples of this application.

[0114] like Figure 4As shown, the CIGSe solar cell prepared in Example 1 exhibits a slight overall improvement in light response across the entire wavelength range, indicating that interfacial recombination is suppressed to a certain extent, thereby improving the collection efficiency of photogenerated carriers. Meanwhile, the integrated current curves show that the difference in short-circuit current density (JSC) between the two is small, consistent with the JV test results. The difference appearing around approximately 500 nm may be related to the influence of changes in the surface state of the absorber layer after surface modulation on the subsequent growth of the buffer layer.

[0115] Furthermore, the parameters of the CIGSe solar cells obtained in Example 1 and Comparative Example 1 are compared in Table 1 below.

[0116] Table 1

[0117]

[0118] Figure 5 This is a comparison chart of the current density versus voltage characteristic curves (JV curves) of the CIGSe solar cells in the test examples of this application.

[0119] like Figure 5 As shown, the overall photoelectric performance of the CIGSe solar cell prepared in Example 1 was significantly improved, with both open-circuit voltage (VOC) and fill factor (FF) showing an improvement trend, while the JSC showed little change. Further analysis using Table 1 shows that the VOC of the device in Example 1 increased from 633mV to 683mV, an increase of approximately 50mV; the FF remained basically stable without a significant decrease; and the JSC increased from 35.17mA / cm². 2 Slightly increased to 35.22 mA / cm 2 The final photoelectric conversion efficiency of the device increased from 16.71% to 17.99%. These results demonstrate that the modulation of the interface dipole layer can effectively avoid the decrease in fill factor that may be caused by traditional alkali metal post-processing while increasing the open-circuit voltage, thereby improving device performance.

[0120] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a copper indium gallium selenide (CIGS) solar cell with an interfacial dipole layer, comprising: A back electrode layer and a copper indium gallium selenide (CIGS) absorber layer are sequentially fabricated on a substrate. A silver source and a cesium source are sequentially introduced onto the surface of the copper indium gallium selenide (CIGS) absorber layer, so that the silver source fills the defect sites on the surface of the CIGS absorber layer, and the cesium source grows by attaching to the silver source to obtain a precursor layer. The precursor layer is then annealed to allow the silver source and the cesium source to diffuse and rearrange, thereby obtaining an interfacial dipole layer. A buffer layer, a window layer, and a gate line are sequentially fabricated in the interface dipole layer.

2. The preparation method according to claim 1, wherein, The method for introducing the silver source includes at least one of the following: evaporation, sputtering, co-evaporation, and solution method. The method for introducing the cesium source includes at least one of the following: evaporation method, solution method, and solid-state diffusion method; Based on the total number of atoms in the silver source and the cesium source, the atomic percentage of the silver source is 0.01 to 0.

3.

3. The preparation method according to claim 1, wherein, The silver source is selected from at least one of metallic silver, silver fluoride, and silver sulfide; The cesium source is selected from at least one of cesium fluoride, cesium carbonate, cesium nitrate, cesium hydroxide, cesium sulfide, and cesium iodide.

4. The preparation method according to claim 1, wherein, In the annealing process, The annealing environment is a vacuum or inert atmosphere with a vacuum degree of 10. -3 ~10 -5 Pa, annealing temperature is 100~500℃, annealing time is 1-30min.

5. The preparation method according to claim 1, wherein, The preparation of the back electrode layer includes: Molybdenum is deposited on the surface of a substrate, which is made of soda-lime glass, to form a back electrode. The thickness of the back electrode layer is 500-1500 nm. In the magnetron sputtering, the sputtering power is 100~400W and the sputtering pressure is 0.1~0.5Pa.

6. The preparation method according to claim 5, wherein, The preparation of the copper indium gallium selenide absorber layer includes: The copper indium gallium selenide (CIGS) absorber layer is obtained by depositing CIGS on the surface of the back electrode layer using a three-step co-evaporation method. The thickness of the CIGS absorber layer is 1.5~3.5 μm. The temperature gradients of the three-step co-evaporation method are 420℃, 450℃, and 450℃ respectively, and the band gap of the copper indium gallium selenide is 1.02~1.34eV.

7. The preparation method according to claim 6, wherein, Preparing the buffer layer includes: The buffer layer is obtained by depositing cadmium sulfide on the surface of the interfacial dipole layer using a chemical bath deposition method, and the thickness of the buffer layer is 30-60 nm. In the chemical bath deposition method, the deposition temperature is 50~95℃ and the deposition time is 5~20min.

8. The preparation method according to claim 7, wherein, Preparing the window layer includes: The window layer is obtained by sequentially depositing intrinsic zinc oxide and aluminum-doped zinc oxide on the surface of the buffer layer via magnetron sputtering. The thickness of the intrinsic zinc oxide is 50-120 nm, and the thickness of the aluminum-doped zinc oxide is 200-600 nm. In the magnetron sputtering, the sputtering power is 50~300W and the sputtering pressure is 0.2~1.0Pa.

9. The preparation method according to claim 8, wherein, Fabricating the gate line includes: The gate line is obtained by sequentially depositing nickel and aluminum on the surface of the window layer using electron beam evaporation. The thickness of the nickel is 20-50 nm, and the thickness of the aluminum is 50-150 nm. The evaporation beam current of the electron beam evaporation method is 0.03~0.3A.

10. A copper indium gallium selenide (CIGS) solar cell prepared by any one of claims 1 to 9, comprising a substrate, a back electrode layer, a CIGS absorber layer, an interface dipole layer, a buffer layer, a window layer, and grid lines; wherein, The interface dipole layer is a silver-cesium composite material, and the proportion of silver atoms is 0.01~0.3% based on the total number of atoms in the silver-cesium composite material.

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