Conductive multilayer stack for silicon solar cells and methods of manufacture and use thereof including laser-based methods

Abstract

Conductive multilayer stacks or conductive multilayer lines for use as metallization layers in photovoltaic devices and other devices; solar cells having conductive multilayer stacks or lines; solar modules having such cells; and methods of forming conductive multilayer stacks or lines. The conductive multilayer stacks or lines have a metal layer comprising copper (Cu) or coated aluminum; a silver contact layer; and a solderable layer between and contacting the metal layer and the silver contact layer.

Description

Related applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 594,199, filed October 30, 2023, and U.S. Provisional Application No. 63 / 711,821, filed October 25, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to solar cells and modules, and methods of manufacturing and using them. Background Technology

[0003] A solar cell has at least three distinct metallization layers: fine mesh lines, busbars, and pads, each of which transfers charge from the silicon in the solar cell to other components of the module. Broadly speaking, there are two types of solar cells: symmetrical solar cells and asymmetrical solar cells. A symmetrical solar cell has metallization layers on both the front and back sides of the solar cell and is connected from the top of one cell to the bottom of another (e.g., by soldering busbars). An asymmetrical solar cell has a metallization layer on one side of the solar cell (e.g., on the back side) and is connected from the metallized side of one cell to the metallized side of another (e.g., by soldering busbars).

[0004] In 2021, approximately 95% of all manufactured solar cells were symmetrical and used the Passivated Emitter and Back Contact (PERC) solar cell architecture. PERC cells are constructed using silicon nitride, aluminum oxide, and silicon oxide (SiO2). x Passivating the front and back surfaces of solar cells reduces the area where silicon-aluminum eutectic forms (better called the back surface field) to reduce surface recombination on the back side and achieve good cell efficiency.

[0005] The "Tunneling Oxide Passivated Contact" (TOPCon) architecture improves surface passivation in solar cells by eliminating back surface field formation and by using an additional passivation layer on the back side of the solar cell. The TOPCon architecture is typically used with n-type wafers, not only because n-type wafers have a higher volumetric minority carrier lifetime, but also because passivating p-type silicon (Si) surfaces with transparent materials is challenging. Using n-type wafers allows cell manufacturers to use alumina and silicon nitride / silicon oxynitride passivated stacks of PERC cells on the illuminated (e.g., front) side, along with silicon oxide (tunneling oxide) and n-type passivated contacts. + The combination of polycrystalline silicon minimizes recombination at the n-Si surface. TOPCon and other next-generation battery designs typically use between 70% and 150% more silver per cell than current PERC designs.

[0006] The heterojunction (HJT) architecture uses a combination of intrinsic and doped hydrogenated amorphous silicon passivation layers to minimize surface recombination on n-type silicon wafers, thereby maximizing solar cell efficiency. Specialized silver paste is often used, which crystallizes amorphous silicon at relatively low temperatures and cures at temperatures between 150°C and 200°C. The conductivity of these metallization layers is lower than that of the high-temperature silver paste used in TOPCon cells. Therefore, the silver consumption of HJT cells can be much higher than that of TOPCon / PERC cells. Efforts have been made to reduce silver consumption using silver-coated copper particles, but the required silver coating is relatively thick, resulting in minimal silver savings.

[0007] Asymmetric solar cells exhibit higher photocurrent densities due to increased light absorption. The most common type of asymmetric silicon solar cell is called an "interdigitated back contact" (IBC) cell, and they can be manufactured using both p-type and n-type wafers. One of the biggest challenges in commercializing IBC cells is reducing Ag usage (significantly greater than in PERC cells) and cell interconnection. When using ribbon solder only on the back side, stress can cause the wafer to bend and crack during module assembly. Various passivation structures can be used on asymmetric cells, similar to those used in symmetric TOPCon and HJT cells.

[0008] Silver (Ag) is crucial in the solar energy supply chain and may constrain future solar cell production and the large-scale commercialization of more efficient cell designs. In 2023, silver used in silicon cells currently accounted for 16% of the world's annual silver consumption and 15% of module costs. Silver is expensive, its price is volatile, and it is primarily a byproduct of base metal mining, limiting production increases. While solar cell production has increased tenfold since 2010, similar growth cannot be sustained without a significant reduction in silver consumption. The high cost of silver makes the transition to more efficient cell architectures (e.g., TOPCon, HJT, and p-type IBC) less economically viable, as these architectures consume significantly more silver per cell.

[0009] There has been a long-standing need for using base metals to form the metallization layer in silicon solar cells. Base metal foils (e.g., aluminum and copper foils) have high bulk conductivity and are relatively inexpensive. One metallization method involves bonding the metal foil to a metal layer (e.g., silver or aluminum pads) attached to the silicon wafer. The most common strategy is to use uncoated aluminum foil, which is laser-welded to the metal layer (e.g., silver pads) on the solar cell. Laser-welding uncoated aluminum foil presents at least two challenges that have prevented the commercialization of this process: 1) poor adhesion between the metal foil and the underlying silver pads, and 2) increased contact resistance between aluminum and silver under humid and hot conditions caused by electroplating corrosion.

[0010] Therefore, there is a need to develop processes that allow inexpensive base metals to replace the metallization layers in solar cells, as well as the majority of silver in integrated circuits and light-emitting diodes. These coatings and processes enable lower-temperature bonding methods, such as soldering. It is also desirable for the coatings to reduce corrosion between the silver and the metal foil for operation under humid and hot conditions. Summary of the Invention

[0011] The disclosure herein relates to conductive multilayer stacks (CMS), which, in some embodiments, are formed using metal foils soldered to silver pads and laser-cut into desired shapes. Conductive multilayer stacks have numerous applications, including in integrated circuits, light-emitting diodes, and solar cell applications. These conductive multilayer stacks are particularly useful as metallization layers on solar cells. Conductive multilayer stacks can reduce silver consumption on solar cells while maintaining excellent electrical properties and strong damp-heat reliability.

[0012] In this embodiment, a conductive multilayer stack is described, comprising a metal layer; a silver contact layer comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and a solderable layer between and contacting the metal layer and the silver contact layer; wherein the glass paste sublayer of the conductive multilayer stack contacts at least a portion of a silicon substrate, at least a portion of at least one passivation layer on the silicon substrate, or a combination thereof. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut.

[0013] In this embodiment, a conductive multilayer line is described, comprising at least two conductive multilayer stacks on a silicon substrate having at least one passivation layer. Each of the at least two conductive multilayer stacks comprises a metal layer; silver contact pads comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and a solderable layer between the metal layer and the silver contact pads and contacting both the metal layer and the silver contact pads; wherein the glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, at least a portion of the at least one passivation layer, or a combination thereof. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut.

[0014] In this embodiment, a conductive multilayer stack on a solar cell is described, the conductive multilayer stack comprising a metal layer; a silver contact layer comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and a solderable layer between and contacting the metal layer and the silver contact layer; wherein the solar cell has a doped silicon substrate having a front surface and a rear surface, wherein the front surface of the doped silicon substrate is a light-facing surface, and wherein the rear surface of the doped silicon substrate is opposite to the light-facing surface of the doped silicon substrate; wherein at least one passivation layer is provided on the front surface, the rear surface, or both of the front and rear surfaces of the doped silicon substrate; and wherein the glass paste sublayer of the conductive multilayer stack contacts at least a portion of the front surface and / or the rear surface of the doped silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination of both. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The at least one passivation layer may include a tunneling oxide layer, a doped layer on at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on at least a portion of the doped layer. The at least one passivation layer may comprise SiOx, AlOx, or SiOxNy. The back surface of the doped silicon substrate may further include at least one doped layer, wherein the at least one doped layer comprises at least one doped region and at least one oppositely doped region.

[0015] In this embodiment, a conductive multilayer stack on a solar cell is described, the conductive multilayer stack comprising a metal layer; a silver contact layer, wherein the silver contact layer does not contain glass paste; and a solderable layer between and contacting the metal layer and the silver contact layer; wherein the solar cell has a doped silicon substrate having a front surface and a rear surface, wherein the front surface of the doped silicon substrate is a light-facing surface, and wherein the rear surface of the doped silicon substrate is opposite to the light-facing surface of the doped silicon substrate; wherein the front surface, the rear surface, or both of the front and rear surfaces of the doped silicon substrate have at least one passivation layer, wherein the at least one passivation layer comprises an intrinsic amorphous layer on at least a portion of the doped silicon substrate and a doped layer on at least a portion of the intrinsic amorphous layer; wherein the solar cell has a transparent conductive oxide layer on at least a portion of the doped layer; and wherein the silver contact layer of the conductive multilayer stack contacts at least a portion of the transparent conductive oxide layer. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The at least one passivation layer may be on the back surface of the doped silicon substrate, wherein the doped layer of the at least one passivation layer includes at least one doped region and at least one oppositely doped region.

[0016] In this embodiment, a symmetrical solar cell is described, comprising a doped silicon substrate having a front surface and a rear surface; at least one passivation layer on at least a portion of the front surface and / or the rear surface of the doped silicon substrate, wherein the front surface of the doped silicon substrate is a light-facing surface and the rear surface is opposite to the light-facing surface; and at least one fine grid line on the front surface, the rear surface, or a portion of both the front and rear surfaces of the doped silicon substrate. The at least one fine grid line is a conductive multilayer line comprising at least two conductive multilayer stacks, each of the at least two conductive multilayer stacks comprising a metal layer; silver contact pads comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and a solderable layer between the metal layer and the silver contact pads and contacting the metal layer and the silver contact pads; wherein the glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof. The metal layer of the conductive multilayer stack is a continuous layer connecting at least two conductive multilayer stacks in the conductive multilayer line. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The at least one passivation layer may include a tunneling oxide layer, a doped layer on at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on at least a portion of the doped layer. The at least one passivation layer may comprise SiOx, AlOx, or SiOxNy. The symmetrical solar cell may further include at least one pad on a portion of the front, back, or both front and back surfaces of the doped silicon substrate, wherein the at least one fine grid line contacts the at least one pad. The symmetrical solar cell may further include at least one bus on a portion of the front, back, or both front and back surfaces of the doped silicon substrate, wherein the at least one fine grid line contacts the at least one bus. The symmetrical solar cell may further include a bus ribbon that contacts the metal layer of the at least one fine grid line, wherein the bus ribbon includes a metal core and a solder coating.

[0017] In an embodiment, this document describes a symmetrical solar cell comprising a doped silicon substrate having a front surface and a rear surface, wherein the front surface of the doped silicon substrate is a light-facing surface and the rear surface is opposite to the light-facing surface; at least one passivation layer on at least a portion of the front surface, rear surface, or both of the front and rear surfaces of the silicon substrate, wherein the at least one passivation layer comprises an intrinsic amorphous layer on at least a portion of the doped silicon substrate and a doped layer on at least a portion of the intrinsic amorphous layer; a transparent conductive oxide layer on at least a portion of the at least one passivation layer; and at least one fine grid line on at least a portion of the front surface, rear surface, or both of the front and rear surfaces of the doped silicon substrate. The at least one fine mesh line is a conductive multilayer line comprising at least two conductive multilayer stacks, each of the at least two conductive multilayer stacks comprising a metal layer; silver contact pads, wherein the silver contact pads do not contain glass paste; and a solderable layer between and contacting the metal layer and the silver contact pads; wherein the silver contact pads of the conductive multilayer stacks contact at least a portion of the transparent conductive oxide layer. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks in the conductive multilayer line. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The symmetrical solar cell may further include at least one bus bar on at least a portion of the front, back, or both front and back surfaces of the doped silicon substrate, wherein the at least one fine mesh line contacts the at least one bus bar. The symmetrical solar cell may further include a busbar that contacts the metal layer of the at least one fine grid line, wherein the busbar includes a metal core and a solder coating, and wherein the metal layer of the at least one fine grid line comprises, is composed of, or is substantially composed of Cu.

[0018] In this embodiment, an asymmetric solar cell is described, comprising a silicon substrate having a front surface and a rear surface, the front surface being an light-facing surface, wherein the rear surface is opposite to the light-facing surface; at least one passivation layer directly on at least a portion of the rear surface of the silicon substrate; at least one first fine mesh line on at least a portion of the rear surface of the silicon substrate; and at least one second fine mesh line on at least a portion of the rear surface of the silicon substrate. The at least one first fine mesh line or the at least one second fine mesh line is a first conductive multilayer line comprising at least two conductive multilayer stacks; wherein the conductive multilayer stack comprises: a metal layer; a silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and a solderable layer between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; wherein the glass paste sublayer of the conductive multilayer stack contacts the rear surface of the silicon substrate, contacts the at least one passivation layer, or contacts a combination thereof. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks of the first conductive multilayer line. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The asymmetric solar cell may further include at least one first interconnect pad contacting the at least one first fine grid line; and at least one second interconnect pad contacting the at least one second fine grid line; wherein the at least one first interconnect pad is a third conductive multilayer line comprising at least two conductive multilayer stacks; and wherein the at least one second interconnect pad is a fourth conductive multilayer line comprising at least two conductive multilayer stacks. The back surface of the doped silicon substrate may further include at least one doped layer, wherein the at least one doped layer includes at least one doped region and at least one oppositely doped region. The at least one passivation layer may include a tunneling oxide layer, a doped layer on at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on at least a portion of the doped layer. The at least one passivation layer may comprise SiOx, AlOx, or SiOxNy.

[0019] In this embodiment, an asymmetric solar cell is described, comprising a silicon substrate having a front surface and a rear surface, the front surface being a light-facing surface, wherein the rear surface is opposite to the light-facing surface; at least one passivation layer on at least a portion of the rear surface of the silicon substrate, wherein the at least one passivation layer comprises an intrinsic amorphous layer on at least a portion of the substrate and a doped layer on at least a portion of the intrinsic amorphous layer, wherein the doped layer comprises at least one doped region and at least one oppositely doped region; a transparent conductive oxide layer on at least a portion of the at least one passivation layer; at least one first fine mesh line on at least a portion of the transparent conductive oxide layer; and at least one second fine mesh line on at least a portion of the transparent conductive oxide layer. At least one of the first fine mesh line or the at least one second fine mesh line is a first conductive multilayer line comprising at least two conductive multilayer stacks; wherein the conductive multilayer stack comprises a metal layer; a silver contact pad comprising a silver sublayer and free of glass paste; and a solderable layer between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; wherein the silver contact pad of the conductive multilayer stack contacts at least a portion of the transparent conductive oxide layer. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks of the first conductive multilayer line. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The asymmetric solar cell may further include at least one first interconnect pad contacting the at least one first fine mesh line; and at least one second interconnect pad contacting the at least one second fine mesh line; wherein the at least one first interconnect pad is a third conductive multilayer line comprising at least two conductive multilayer stacks; and wherein the at least one second interconnect pad is a fourth conductive multilayer line comprising at least two conductive multilayer stacks. The asymmetric solar cell may further include at least one first pad on at least a first portion of the front, back, or front and back surfaces of the silicon substrate and at least one second pad on at least a second portion of the front, back, or front and back surfaces of the silicon substrate, wherein the at least one first fine mesh line contacts the at least one first pad, and wherein the at least one second fine mesh line contacts the at least one second pad.

[0020] In this embodiment, a solar cell module is described, the solar cell module including a first solar cell and a second solar cell; and an interconnect connecting the first solar cell and the second solar cell. The first solar cell and the second solar cell include a doped silicon substrate having a front surface and a rear surface, wherein the front surface is a light-facing surface and the rear surface is opposite to the light-facing surface; at least one passivation layer directly on the front surface, rear surface, or at least a portion of both the front and rear surfaces of the doped silicon substrate; and at least one fine grid line on the front surface, rear surface, or a portion of both the front and rear surfaces of the doped silicon substrate. The at least one fine grid line is a conductive multilayer line comprising at least two conductive multilayer stacks, each of the at least two conductive multilayer stacks comprising a metal layer; silver contact pads comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and a solderable layer between the metal layer and the silver contact pads and contacting both the metal layer and the silver contact pads; and wherein the glass paste sublayer of the conductive multilayer stack contacts at least a portion of a silicon substrate, contacts at least one passivation layer, or contacts a combination thereof. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks of the conductive multilayer line. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The first solar cell and the second solar cell may further include at least one pad on the front surface, rear surface, or a portion of both the front and rear surfaces of the doped silicon substrate; and at least one bus bar on the front surface, rear surface, or a portion of both the front and rear surfaces of the doped silicon substrate, wherein the at least one bus bar contacts the at least one pad, wherein the interconnect includes a first bus strip contacting the at least one pad on the first solar cell and the at least one pad on the second solar cell, and a bus strip contacting the first bus strip. The interconnect may include a first interconnect pad on the first solar cell and a second interconnect pad on the second solar cell, wherein the first interconnect pad contacts the second interconnect pad to form a contact area. The interconnect may include at least one first bus strip contacting the at least one fine grid line on the first solar cell or the at least one fine grid line on the second solar cell, wherein the at least one first bus strip includes a metal core and a solder coating, and wherein the interconnect further includes a bus strip contacting the at least one first bus strip. The at least one passivation layer may include a tunneling oxide layer, a doped layer on at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on at least a portion of the doped layer.The at least one passivation layer may contain SiOx, AlOx, or SiOxNy.

[0021] In this embodiment, a solar cell module is described, comprising a first solar cell and a second solar cell; and an interconnect connecting the first solar cell and the second solar cell. The first solar cell and the second solar cell include a doped silicon substrate having a front surface and a rear surface, wherein the front surface is a light-facing surface and the rear surface is opposite to the light-facing surface; at least one passivation layer directly on at least a portion of the front surface, rear surface, or both of the front and rear surfaces of the silicon substrate, wherein the at least one passivation layer comprises an intrinsic amorphous layer on at least a portion of the doped silicon substrate and a doped layer on at least a portion of the intrinsic amorphous layer; a transparent conductive oxide layer on at least a portion of the at least one passivation layer; and at least one fine grid line on at least a portion of the front surface, rear surface, or both of the front and rear surfaces of the doped silicon substrate. The at least one fine grid line is a conductive multilayer line comprising at least two conductive multilayer stacks, each of the at least two conductive multilayer stacks comprising a metal layer; silver contact pads comprising a silver sublayer and free of glass paste; and a solderable layer between and contacting the metal layer and the silver contact pads; wherein the silver contact pads of the conductive multilayer stack contact at least a portion of the transparent conductive oxide layer. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks of the conductive multilayer line. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The first solar cell and the second solar cell may further include at least one pad on at least a portion of the front, back, or front and back surfaces of the doped silicon substrate; and at least one bus bar on at least a portion of the front, back, or front and back surfaces of the doped silicon substrate, wherein the at least one bus bar contacts the at least one pad, wherein the interconnect includes a first bus strip contacting the at least one pad on the first solar cell and the at least one pad on the second solar cell, and a bus strip contacting the first bus strip. The interconnect may include a first interconnect pad on the first solar cell and a second interconnect pad on the second solar cell, wherein the first interconnect pad contacts the second interconnect pad to form a contact area. The interconnect may include at least one first bus strip contacting the at least one fine grid line on the first solar cell or the second solar cell, wherein the at least one first bus strip includes a metal core and a solder coating, and wherein the interconnect further includes a bus strip contacting the at least one first bus strip.

[0022] In this embodiment, a solar cell module is described, comprising a first solar cell and a second solar cell; and an interconnect connecting the first solar cell and the second solar cell. The first solar cell and the second solar cell comprise a silicon substrate having a front surface and a rear surface, the front surface being a light-facing surface, wherein the rear surface is opposite to the light-facing surface; at least one passivation layer directly on at least a portion of the rear surface of the silicon substrate; at least one first fine mesh line on at least a portion of the rear surface of the silicon substrate; and at least one second fine mesh line on at least a portion of the rear surface of the silicon substrate. The at least one first fine mesh line, the at least one second fine mesh line, or both are first conductive multilayer lines comprising at least two conductive multilayer stacks; and wherein the conductive multilayer stack in the at least two conductive multilayer stacks comprises a metal layer; a silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and a solderable layer between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; wherein the glass paste sublayer of the conductive multilayer stack is on the silicon substrate, on the at least one passivation layer, or on a combination thereof. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The interconnect may include at least one first interconnect pad on the first solar cell, the at least one first interconnect pad contacting the at least one first fine grid line; and at least one second interconnect pad on the second solar cell, the at least one second interconnect pad contacting the at least one second fine grid line; wherein the at least one first interconnect pad is connected to the at least one second interconnect pad. The solar cell module may further include at least one first pad on a portion of the front, back, or both front and back surfaces of the silicon substrate on the first solar cell, and at least one second pad on a portion of the front, back, or both front and back surfaces of the silicon substrate on the second solar cell, wherein the at least one first fine grid line on the first solar cell contacts the at least one first pad; and wherein the at least one second fine grid line on the second solar cell contacts the at least one second pad; wherein the interconnect includes a bus ribbon contacting the at least one first pad on the first solar cell and the at least one second pad on the second solar cell, and wherein the bus ribbon contacts the bus ribbon. The back surface of the doped silicon substrate may further include at least one doped layer, wherein the at least one doped layer includes at least one doped region and at least one oppositely doped region.The at least one passivation layer may include a tunneling oxide layer, a doped layer on at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on at least a portion of the doped layer. The at least one passivation layer may contain SiOx, AlOx, or SiOxNy.

[0023] In this embodiment, a solar cell module is described, comprising a first solar cell and a second solar cell; and an interconnect connecting the first solar cell and the second solar cell. The first solar cell and the second solar cell comprise a silicon substrate having a front surface and a rear surface, the front surface being a light-facing surface, wherein the rear surface is opposite to the light-facing surface; at least one passivation layer directly on at least a portion of the rear surface of the silicon substrate, wherein the at least one passivation layer comprises an intrinsic amorphous layer on at least a portion of the substrate and a doped layer on at least a portion of the intrinsic amorphous layer, wherein the doped layer comprises at least one doped region and at least one oppositely doped region; a transparent conductive oxide layer on at least a portion of the at least one passivation layer; at least one first fine mesh line on at least a portion of the transparent conductive oxide layer; and at least one second fine mesh line on at least a portion of the transparent conductive oxide layer. At least one of the at least one first fine mesh line or the at least one second fine mesh line is a first conductive multilayer line comprising at least two conductive multilayer stacks, wherein the conductive multilayer stack comprises a metal layer; silver contact pads comprising a silver sublayer and free of glass paste; and a solderable layer between and contacting the metal layer and the silver contact pads; wherein the silver contact pads of the conductive multilayer stack contact at least a portion of the transparent conductive oxide layer. The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks. The metal layer comprises copper (Cu) or coated aluminum. The metal layer may be laser-cut. The interconnect may include at least one first interconnect pad on the first solar cell, the at least one first interconnect pad contacting the at least one first fine mesh line; and at least one second interconnect pad on the second solar cell, the at least one second interconnect pad contacting the at least one second fine mesh line; wherein the at least one first interconnect pad is connected to the at least one second interconnect pad.The solar cell module may further include at least one first pad on at least a portion of the front, back, or front and back surfaces of the silicon substrate on the first solar cell, and at least one second pad on at least a portion of the front, back, or front and back surfaces of the silicon substrate on the second solar cell, wherein at least one first fine mesh line on the first solar cell contacts the at least one first pad, wherein at least one second fine mesh line on the second solar cell contacts the at least one second pad, and wherein the interconnect includes a bus ribbon contacting the at least one first pad on the first solar cell and the at least one second pad on the second solar cell, and wherein a bus strip contacts the bus ribbon.

[0024] In an embodiment, this document describes a method for forming a conductive multilayer stack, the method comprising: providing a silicon substrate having at least one passivation layer on a front surface and / or a rear surface of the silicon substrate; forming silver contact pads comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; forming a solderable layer by applying solderable paste to the silver contact pads; applying a metal layer comprising copper (Cu) or coated aluminum to the solderable layer; and heating the metal layer to mechanically bond the metal layer to the solderable layer and to mechanically bond the solderable layer to the silver contact pads; wherein the glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof.

[0025] In an embodiment, this document describes a method for forming conductive multilayer lines, the method comprising providing a silicon substrate having at least one passivation layer; forming a discontinuity line of silver contact pads, wherein the silver contact pads in the discontinuity line of silver contact pads comprise a silver sublayer and a glass paste sublayer, wherein the silver sublayer is on the glass paste sublayer; forming a discontinuity line of solderable pads by applying a discontinuity line of solderable paste aligned with the discontinuity line of the silver contact pads; applying a metal layer comprising copper (Cu) or coated aluminum to the discontinuity line of the solderable pads; and heating the metal layer to mechanically bond the metal layer to the discontinuity line of the solderable pads and mechanically bond the discontinuity line of the solderable pads to the discontinuity line of the silver contact pads; wherein the glass paste sublayer of the discontinuity line of the silver contact pads contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof. The method may further include mechanically bonding a bus solder strip to the metal layer of the conductive multilayer stack or the conductive multilayer line, wherein the bus solder strip includes a metal core and a solder coating, and wherein the metal layer of the conductive multilayer stack or the conductive multilayer line comprises, is composed of, or is substantially composed of Cu.

[0026] In an embodiment, this document describes a method for forming a conductive multilayer stack, the method comprising providing a silicon substrate having at least one passivation layer and a transparent conductive oxide layer on a front surface and / or a rear surface of the silicon substrate; forming silver contact pads, wherein the silver contact pads do not contain glass paste; forming a solderable layer by applying solderable paste to the silver contact pads; applying a metal layer to the solderable layer, the metal layer comprising copper (Cu) or coated aluminum; and heating the metal layer to mechanically bond the metal layer to the solderable layer and to mechanically bond the solderable layer to the silver contact pads; wherein the silver contact pads are on at least a portion of the transparent conductive oxide layer.

[0027] In an embodiment, this document describes a method for forming conductive multilayer lines, the method comprising: providing a silicon substrate having at least one passivation layer and a transparent conductive oxide layer on the at least one passivation layer; forming discontinuous lines of silver contact pads, wherein the silver contact pads in the discontinuous lines of the silver contact pads do not contain glass paste; forming discontinuous lines of solderable pads by applying discontinuous lines of solderable paste aligned with the discontinuous lines of the silver contact pads; applying a metal layer comprising copper (Cu) or coated aluminum to the discontinuous lines of the solderable pads; and heating the metal layer to mechanically bond the metal layer to the discontinuous lines of the solderable pads and mechanically bond the discontinuous lines of the solderable pads to the discontinuous lines of the silver contact pads; wherein the silver contact pads are on at least a portion of the transparent conductive oxide layer. The method may further include laser-cutting the metal layer into a pattern prior to applying the metal layer. The method may further include mechanically bonding a busbar to a metal layer of the conductive multilayer stack or the conductive multilayer line, wherein the busbar includes a metal core and a solder coating, wherein the metal layer comprises Cu, and wherein the busbar includes a metal core and a solder coating.

[0028] These and other features, aspects, and advantages of this disclosure will be apparent from the following detailed description and accompanying drawings, which are briefly described below. Unless the context clearly specifies otherwise, this disclosure is intended to be understood throughout such that any separable feature or element of this disclosure, in any aspect and embodiment thereof, should be considered as intended to be composable. Attached Figure Description

[0029] When read in conjunction with the accompanying drawings, those skilled in the art will readily understand the foregoing and other aspects from the following description of illustrative embodiments. The drawings are merely illustrative and are not intended to be exhaustive or to limit the disclosure herein.

[0030] Figure 1 This is a schematic diagram of an exemplary silicon solar cell.

[0031] Figure 2 This is a schematic cross-sectional view of an exemplary conductive multilayer stack (CMS) disposed on a silicon substrate, conforming to some embodiments of the present disclosure.

[0032] Figure 3 This is a schematic diagram of an exemplary silicon solar cell including silver contact pads, busbars, and pads, which conforms to some embodiments of this disclosure.

[0033] Figure 4This is a schematic diagram of an exemplary silicon solar cell including silver contact pads and pads, which conforms to some embodiments of this disclosure.

[0034] Figure 5 This is a schematic diagram of an exemplary asymmetric solar cell using continuous silver fine grid lines and pads.

[0035] Figure 6 This is a schematic diagram of an exemplary asymmetric solar cell including silver contact pads, which conforms to some embodiments of this disclosure.

[0036] Figures 7A to 7C These are top-view images of different stages of fabricating an exemplary CMS on a silicon substrate, conforming to some embodiments of this disclosure.

[0037] Figure 7D This is a height map of an exemplary CMS on a silicon substrate that conforms to some embodiments of this disclosure.

[0038] Figure 8 This is a schematic cross-sectional view of an exemplary conductive multilayer line disposed on a silicon substrate, conforming to some embodiments of the present disclosure.

[0039] Figure 9A This is a top view image of a metal layer of an exemplary CMS that utilizes horizontal laser cutting, conforming to some embodiments of this disclosure.

[0040] Figure 9B This is a top view image of a metal layer of an exemplary CMS that utilizes laser cutting, conforming to some embodiments of this disclosure.

[0041] Figure 9C This is a height diagram of the metal layer of an exemplary CMS using laser cutting, conforming to some embodiments of this disclosure.

[0042] Figure 10A This is a schematic cross-sectional view of the metal layer of an exemplary CMS that is laser-cut according to some embodiments of this disclosure.

[0043] Figure 10B These are some embodiments conforming to this disclosure. Figure 10A A top view of the metal layer.

[0044] Figure 11 This is a schematic diagram of an exemplary silicon solar cell conforming to some embodiments of the present disclosure, the exemplary silicon solar cell including conductive multilayer lines, busbars and pads located on a silicon wafer.

[0045] Figure 12 This is a schematic diagram of an exemplary silicon solar cell conforming to some embodiments of the present disclosure, the exemplary silicon solar cell including conductive multilayer lines and pads located on a silicon wafer.

[0046] Figure 13 This is a schematic diagram of an exemplary solar cell module conforming to some embodiments of the present disclosure, the exemplary solar cell module including a silicon solar cell and a busbar electrically connected to the pads of the solar cell.

[0047] Figure 14 This is a schematic diagram of an exemplary silicon solar cell including silver contact pads, which conforms to some embodiments of this disclosure.

[0048] Figure 15 This is a schematic diagram of an exemplary silicon solar cell including conductive multilayer lines, which conforms to some embodiments of this disclosure.

[0049] Figure 16A is a schematic diagram of an exemplary silicon solar cell including conductive multilayer lines, which conforms to some embodiments of the present disclosure.

[0050] Figure 16B This is a schematic diagram of two exemplary solar cells of FIG16A connected in series, which conform to some embodiments of the present disclosure.

[0051] Figure 17 This is a schematic diagram of an exemplary solar cell module conforming to some embodiments of the present disclosure, the exemplary solar cell module including a silicon solar cell having conductive multilayer lines connected in series via interconnecting pads and electrically connected via a bus.

[0052] Figure 18A is a schematic diagram of an exemplary asymmetric solar cell including conductive multilayer lines, which conforms to some embodiments of the present disclosure.

[0053] Figure 18B This is a schematic diagram of two exemplary asymmetric solar cells of FIG18A connected in series, which conform to some embodiments of the present disclosure.

[0054] Figure 19 This is a schematic diagram of an exemplary asymmetric solar cell interconnect scheme conforming to some embodiments of this disclosure.

[0055] Figure 20 This is a schematic cross-sectional view of an exemplary conductive multilayer line with busbars disposed on a silicon substrate, conforming to some embodiments of the present disclosure.

[0056] Figure 21A This is a top view image of a solar cell including multiple silver contact pads, which conforms to some embodiments of this disclosure.

[0057] Figure 21B Some embodiments conforming to this disclosure are as follows: Figure 21A The image shown is a top view of a solar cell, which comprises multiple conductive layers.

[0058] Figure 21CSome embodiments conforming to this disclosure are as follows: Figure 21A The image shown is a top view of a solar cell, which includes busbars and conductive multilayer wires. Detailed Implementation

[0059] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following disclosure relates to the drawings, wherein, unless otherwise indicated, the same reference numerals in different drawings denote the same or similar elements. The embodiments set forth in the following description of exemplary embodiments do not represent all embodiments. Rather, they are merely examples of apparatus and methods conforming to aspects relevant to the disclosed embodiments. This disclosure includes any combination of two, three, four, or more features or elements set forth in the exemplary embodiments, whether or not such features or elements are explicitly combined in the specific embodiments described herein. Other aspects and advantages of this disclosure will become apparent hereinafter.

[0060] For clarity, the relative dimensions of components in the accompanying drawings may be exaggerated. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and only differences with respect to the various embodiments are described. As used herein, unless expressly stated otherwise, the terms "or" and "and / or" cover all possible combinations unless impractical. For example, if it is stated that a component may include A or B, unless expressly stated otherwise or impractical, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, and / or C, unless expressly stated otherwise or impractical, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0061] As used herein, the term “about” means approximately, within a certain range, almost, or around. When the term “about” is used in conjunction with a range of numbers, it modifies the range by extending the upper and lower boundaries of the value. Generally, the term “about” is used herein to modify values ​​that are higher than and lower than the value within a 5% variance. All numerical values ​​are modified by the term “about”, whether or not explicitly indicated. Numerical values ​​modified by the term “about” include specifically identified values. For example, “about 100” means a number in the range of 95 to 105, including 95, 100, and 105. Unless otherwise indicated herein, the ranges of values ​​described herein are intended only as a simplified way of individually representing each individual value within this range, and each individual value is incorporated into this specification as if it were individually described herein.

[0062] When describing relationships between components, the preposition "on" is used herein to mean that the components may or may not be in direct contact with each other (e.g., physical contact). For example, if a particular component (e.g., a layer) is stated to be on a substrate, one or more additional components (e.g., one or more additional layers) may be present between the particular component and the substrate, unless otherwise expressly stated or impractical. As used herein, the expression "directly on" should be understood to mean that the components are in at least partial direct contact with each other. For example, if a particular component (e.g., a layer) is stated to be directly on a substrate, at least a portion of the particular component is directly positioned on and in contact with the substrate, unless otherwise expressly stated or impractical.

[0063] When describing the "doped" components of a solar cell, the term "doped" can be understood to mean any concentration of dopant. For example, the doped layer of a solar cell can be understood as containing any concentration of n-type or p-type dopant. When describing the dopant concentration of a solar cell component, the term "highly doped" can be understood to mean a dopant concentration greater than or equal to 10⁻⁶. 18 cm -3 For example, a highly doped layer can have 10 18 cm -3 Up to 10 20 cm -3 The dopant concentration. If a component is stated to be "medium doped," the dopant concentration of the component is from 10 unless otherwise explicitly stated or impractical. 16 cm -3 to less than 10 18 cm -3 If a component is stated to be "lightly doped," the doping concentration of the component is less than 10 unless otherwise explicitly stated or impractical. 16 cm -3 For example, lightly doped layers can have a doping level of 10. 14 cm -3 to less than 10 16 cm -3 The doping concentration.

[0064] As used herein, the term "part" may be understood to mean the entire component or any sub-range or fraction thereof. For example, a part of the front surface of the substrate may be understood to mean the entire front surface of the substrate, 1 / 2, 1 / 3, 1 / 4, or any other area fraction of the front surface of the substrate. As another example, if a component is stated to be "at least a portion" of the rear surface of the substrate, unless otherwise expressly stated or impractical, the component may be on the entire rear surface of the substrate or may be on a small portion of the total area of ​​the rear surface of the substrate.

[0065] The substrate can be a solid, planar, rigid inorganic material. In some embodiments, the substrate comprises at least one material selected from silicon, silicon carbide, alumina, sapphire, germanium, gallium arsenide, gallium nitride, diamond, and indium phosphide, and combinations thereof. Such substrates are commonly used for depositing films to fabricate transistors, light-emitting diodes, integrated circuits, and photovoltaic cells. The substrate can be a single crystal (monocrystalline) or a polycrystalline (polycrystalline). The substrate can be p-type or n-type doped by adding small amounts of dopants (e.g., for p-type silicon, adding boron, aluminum, or gallium, and for n-type silicon, adding phosphorus, arsenic, or antimony). In some embodiments, the substrate is doped with at least one material selected from boron, aluminum, gallium, indium, thallium, phosphorus, arsenic, antimony, bismuth, alloys thereof, composites thereof, and combinations thereof. Doping semiconductor substrates is a well-known technique in the art. Silicon is the most commonly used light-absorbing substrate for photovoltaic cells, and these substrates are commonly referred to as silicon wafers. It should be understood that the terms "silicon substrate" and "silicon wafer" are used interchangeably in this disclosure.

[0066] Solar cells (also known as photovoltaic cells) convert light energy into electrical energy through the photovoltaic effect. Solar cells use a PN junction (e.g., a p-type silicon substrate with a heavily doped n-type layer at the surface) to separate electron and hole carriers in the solar cell, thereby generating a voltage that does useful work. The power conversion efficiency of a solar cell can be optimized by maximizing light absorption in silicon and by minimizing minority carrier recombination and resistive losses. The silicon substrate of a solar cell is typically 120 µm to 180 µm thick and is lightly doped with p-type or n-type (10⁻¹⁰) silicon. 15 Up to 10 17 cm -3 In some embodiments, the substrate of a solar cell may have a p-type doped region and another n-type doped region, thereby forming a PN junction within the substrate. In some embodiments, the substrate of a solar cell may be an n-type doped substrate, and the p-type region may be formed on the surface of the n-type doped substrate (e.g., the p-type emitter layer of a TOPCon solar cell). Reducing the silicon substrate thickness to below 90 µm is desirable to lower manufacturing costs, improve efficiency, and enhance solar cell flexibility; however, such thin silicon substrates currently increase the likelihood of wafer cracking during manufacturing. passivation layer on silicon solar cells

[0067] Silicon has a high refractive index, resulting in strong reflection of light in the visible spectrum, and the bare silicon surface exhibits a high surface recombination rate. Passivation layers are used to reduce the surface recombination rate and improve light absorption by altering the refractive index. In some embodiments, the passivation layer on the substrate surface comprises at least one material selected from silicon (Si), nitrogen (N), aluminum (Al), oxygen (O), germanium (Ge), hafnium (Hf), gallium (Ga), their composites, and combinations thereof. Silicon dioxide and low-oxide silicon (SiO₂) are also included.x Alumina and low-alumina (AlO) are passivation layers that can be controllably grown on silicon wafers at high temperatures in the presence of oxygen, ranging from 1 nm to 5 nm. x AlO₂ can be used as a passivation layer in p-type silicon and can be grown via, for example, atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). It may be desirable to use AlO₂. x The thickness is minimized to approximately 4 nm to 5 nm, which allows for more controlled deposition via ALD. In some embodiments, at least one passivation layer comprises aluminum oxide with a thickness ranging from 1 nm to 5 nm. In some examples, SiO2... x AlO can be deposited on p-type silicon surfaces x Previously grown in an ALD system. Polycrystalline silicon (poly-Si) combined with SiO x It can also be used in the passivation layer of solar cells. Poly-Si can be deposited using various methods, including but not limited to low-pressure chemical vapor deposition (LPCVD), which allows the use of phosphorus (n... + In-situ n-type doping of poly-Si is performed. This passivation strategy can be useful when applied to the n-type side of certain battery architectures, such as TOPCon. Poly-Si thicknesses can range from 50 nm to 200 nm, and the doping density can be optimized to minimize recombination and contact resistance. Silicon nitride (SiN) with different silicon, nitrogen, and oxygen compositions is also available. x Silicon oxynitride (SiON) and silicon oxynitride (SiN) can also be used to tune the refractive index to reduce light reflection at the silicon surface. Multiple gradient SiN films with total film thicknesses ranging from 50 nm to 100 nm or from 70 nm to 80 nm are available. x Layers and SiON capping layers can be used to minimize reflection. SiN x It can also be combined with SiO xCombined use can further reduce the surface recombination rate on n-type silicon. The hydrogenated form of the passivation layer can also be combined to improve chemical surface passivation or reliability under irradiation, heat, and / or humidity conditions. In some embodiments, the at least one passivation layer may comprise an intrinsic amorphous layer and a doped layer, such as an amorphous doped layer. This passivation strategy can be useful when applied to the front or back of certain cell architectures, such as HJTs. For HJT solar cells, the at least one passivation layer on the front and / or back surface of the silicon substrate may include, but is not limited to, a 2 nm to 5 nm layer of hydrogenated intrinsic amorphous silicon (a-Si:H(i)) and a 10 nm to 50 nm layer of doped hydrogenated amorphous silicon (a-Si:H). The HJT solar cell may further include a transparent conductive oxide (TCO) layer on the at least one passivation layer. It should be understood that the above passivation layers should not be construed as limiting. The refractive indices of the above passivation layers are well known, and the thicknesses of individual passivation layers and passivation layer stacks can be measured using, for example, elliptic polarization techniques. See Shah and Arvind, eds., "Solar Cells and Modules," Springer International Publishing, 2020, which is incorporated herein by reference in its entirety. SiO x N y SiO x and AlO x The material can be found in "Solar Cells and Modules" edited by Shah and Arvind. Solar cell architecture

[0068] In some embodiments, a PERC solar cell can be fabricated as a doped substrate having a thin (30 nm to 200 nm) opposite doping layer in the front surface. In some embodiments, the thin opposite doping layer can be a doped region in the front surface of the substrate. In some embodiments, the substrate can be p-type, and the thin opposite doping layer is n-type. + Type. In some embodiments, the thin, oppositely doped layer comprises phosphorus. SiO x (1 nm to 5 nm) and SiN x / SiON (50 nm to 100 nm) can be used before passivation (n + (Type) surface, and SiO x (1 nm to 5 nm), AlO x (2 nm to 7 nm) and / or SiN x / SiON (50 nm to 100 nm) can be used on the passivated (p-type) surface. In some embodiments, the PERC solar cell further includes AlO₂ between the SiO₂ and SiN₂ / SiON passivation layers on the front surface. x (1 nm to 5 nm) layers. In some embodiments, AlO x (1 nm to 5 nm) and SiN x / SiON (50 nm to 100 nm) layers can be used on passivated (p-type) surfaces.

[0069] In some embodiments, a TOPCon solar cell can be fabricated as a doped substrate having a thin (30 nm to 200 nm) opposite doping layer on its front surface. In some embodiments, the thin opposite doping layer can be a doped region in the front surface of the substrate. In some embodiments, the substrate can be n-type, and the thin opposite doping layer is p-type. + Type. In some embodiments, the thin, oppositely doped layer comprises phosphorus. In some embodiments, at least one passivation layer may be used to passivate the front and / or back surfaces of the TOPCon solar cell. In some embodiments, SiO x (1 nm to 5 nm), AlO x (2 nm to 7 nm) and SiN x / SiON (50 nm to 100 nm) layers can be used before passivation (p + (Type) surface, and SiO x (1 nm to 5 nm), n + poly-Si (50 nm to 200 nm), AlO x (2 nm to 7 nm) and SiN x A SiON (50 nm to 100 nm) layer can be used on the passivated (n-type) surface. In some embodiments, SiO x (1 nm to 5 nm), n + poly-Si (50-200 nm) and / or SiN x A layer of / SiON (50-100 nm) can be used to passivate the back side.

[0070] It should be understood that the above embodiments should not be construed as limiting. Those skilled in the art are aware of other cell architectures and deposition techniques for reducing silicon cell recombination. In this document, "p" + "or "n + The "+" in the figure is used to indicate a highly doped layer (e.g., ≥ 10). 18 cm -3It should be noted that the solar cells described in this disclosure can be used in bifacial modules that absorb light from both sides of the solar cell. Bifacial cells can be designed to minimize the metallization area on the back side of the solar cell, increase the available surface area to improve light absorption, and reduce the thickness of the passivation layer to improve light absorption.

[0071] In some embodiments, the HJT solar cell can be fabricated having a doped substrate having 2 nm to 5 nm of intrinsic hydrogenated amorphous silicon (a-Si:H(i)), a 10 nm to 50 nm doped hydrogenated amorphous silicon layer (a-Si:H), and a transparent conductive oxide (TCO) layer on its front surface, and a-Si:H(i), a 10 nm to 50 nm doped hydrogenated amorphous silicon layer (a-Si:H), and a TCO layer on its rear surface. In some embodiments, the substrate is n-type. In some embodiments, the doped hydrogenated amorphous silicon on the front surface is p-type, while the doped hydrogenated amorphous silicon layer on the rear surface is n-type. + Type. In some embodiments, the doped hydrogenated amorphous silicon layer on the front surface is n + The TCO layer is p-type, and the doped hydrogenated amorphous silicon layer on the surface is p-type. In some embodiments, the TCO layer is typically 50 nm to 100 nm thick and is made of indium tin oxide.

[0072] It should be noted that similar passivation schemes can be used for asymmetric solar cells, such as, but not limited to, interdigitated back contact (IBC) cells. In some embodiments, IBC solar cells can be fabricated with a doped substrate, wherein SiO2... x (1 nm to 5 nm), n + poly-Si (50 nm to 200 nm), AlO x (2 nm to 7 nm) and / or SiN x / SiON (50 nm to 100 nm) is used to passivate a portion of the solar cell, including the back surface. In some embodiments, the IBC solar cell is p-type. In some embodiments, a portion of the back surface of the IBC solar cell is n-type, and a portion of the back surface of the IBC solar cell is p-type. Metallization layer on silicon solar cells

[0073] Silicon solar cells include multiple metallization layers, which are components used to transfer charge from the silicon wafer to the solar cell module. Figure 1This is a schematic diagram of a conventional silicon solar cell 100, which includes a silicon substrate 110 and three metallization layers: fine mesh lines 120, busbars 130, and pads 140. The fine mesh lines 120 provide ohmic contact with the silicon substrate 110 and transfer charge to the busbars 130 connected to the pads 140. As used herein, a “fine mesh line” (often referred to as a “finger”) can be understood to mean a metallization line directly on the solar cell that collects current from the silicon wafer. As used herein, a “busbar” can be understood to mean a metallization line on the solar cell that connects to the “fine mesh line,” typically extends perpendicular to the “fine mesh line,” and transfers the collected current from the “fine mesh line” to another component of the solar cell or solar module. As used herein, a “pad” can be understood to mean a metallized surface of the solar cell that allows electrical interconnection between solar cells. It should be understood that in some embodiments, the “fine mesh line” or “busbar” is a conductive multilayer wire, as described herein, or made of standard materials known in the art. Conventional solar cells are interconnected via soldered wires from one solar cell's pad to the pads of adjacent solar cells. Solar cells (such as PERC and TOPCon) contain fine mesh lines, busbars, and pads on both the front (i.e., the light-facing surface) and back surfaces of the cell. Solar cells (such as IBC cells) contain fine mesh lines, busbars, and / or pads only on the back surface of the cell. The metallization layer can be made of different metals, including silver, aluminum, and copper. Silver is commonly used to manufacture the silver fine mesh lines, silver busbars, and silver pads on solar cells.

[0074] Silver paste can be screen-printed, then dried and co-fired to form a silver metallization layer on a solar cell. For screen printing, the silver paste typically consists of silver particles, glass paste, organic binders, and additives well known in the art. During co-firing, the silver metallization layer is annealed in air using a peak firing profile with a peak temperature range from 650°C to 820°C and a heating and cooling rate greater than 10°C / sec. The term "co-firing" describes a time period of annealing a silicon substrate at temperatures greater than 400°C, greater than 600°C, or greater than 700°C for 1 second to 60 minutes, or any range thereof.

[0075] During co-firing, the glass paste melts and silver particles sinter, creating a silver contact layer structure in which a thin glass paste sublayer contacts a portion of the silicon substrate (or a portion of the passivation layer on the silicon substrate) and a silver sublayer formed on the thin glass paste sublayer. The glass paste in the silver paste (e.g., bismuth oxide and lead oxide) can be designed to etch through the passivation layer (e.g., SiNx, AlOx) to directly contact the silicon, which can be useful for fine mesh lines. Etching the glass paste through the passivation layer to the silicon surface can reduce ohmic contact between the silver sublayer and the silicon substrate and can increase the surface recombination rate in the etched area, which can reduce the open-circuit voltage. Glass pastes are known to be modified to significantly reduce the etching of the passivation layer and maintain a low surface recombination rate. These paste formulations can be used for pads and buses where charge does not need to be extracted from the silicon wafer. For pads and buses, the silver contact layer is disposed on the silicon substrate and can directly contact the passivation layer or the silicon substrate, depending on the metallization layer function and the glass paste formulation. The glass slurry sublayer comprises at least one material selected from bismuth (Bi), lead (Pb), tin (Sn), tellurium (Te), antimony (Sb), lead (Pb), oxygen (O), thallium (Tl), vanadium (V), silver (Ag), phosphorus (P), silicon (Si), their alloys, their oxides, their composites, and combinations thereof.

[0076] The glass paste sublayer can be thin, ranging from 1 nm to 3 µm, from 1 nm to 1 µm, or from 1 nm to 200 nm. The conductivity of the glass paste sublayer is lower than that of the silver sublayer, so minimizing the glass paste sublayer thickness may be desirable. Thin glass paste sublayers can be discontinuous, and when using cross-sectional scanning electron microscopy with energy-dispersive X-ray spectroscopy (SEM / EDX), the silver may appear to be in direct contact with the silicon wafer. The glass paste is typically designed to have a certain silver solubility at elevated temperatures, resulting in the formation of silver deposits within the glass paste sublayer and at the silicon / glass paste sublayer interface. These silver deposits can be measured by performing transmission electron microscopy (TEM) on a cross-section of the conductive multilayer stack. It is believed that the silver deposits reduce the ohmic contact between the silver contact layer and the silicon substrate and improve the conductivity of the glass paste sublayer.

[0077] The thickness of the silver layer can range from 3 µm to 30 µm, from 5 µm to 25 µm, from 5 µm to 20 µm, or from 5 µm to 15 µm, depending on the metallization layer. The thickness of the silver layer can also depend on the silver loading in the paste and the thickness of the printed film. For pads, the silver layer thickness can be designed to be as thin as possible while maintaining good solderability and adhesion, for example, when bridging wires with solder coating. When using tin-lead based solder wire, the silver layer for pads can have a thickness of 4 µm to 8 µm. For fine grid lines, the silver layer thickness can be optimized to minimize silver consumption (e.g., on the front side) while maintaining low series resistance. The silver layer for fine grid lines can have a thickness of 4 µm to 20 µm. Silver paste typically contains a multi-peaked distribution of silver grain size to increase film density and minimize porosity during co-firing. The resulting silver layer structure may contain small voids and have a porosity of less than 15%, less than 10%, less than 5%, or less than 2% by volume. It should be noted that the electroplated metal layer is a solid with a porosity of less than 0.25% by volume, and the pores are generally not visible under cross-sectional SEM / EDX. The porosity of various layers can be measured in the range of 0.01 kPa to 2 MPa using a mercury porosimeter (such as the CE instrument Pascal 140 (low pressure) or Pascal 440 (high pressure)). Porosity can also be observed using cross-sectional SEM to identify the presence of any pores in the membrane, and image processing (such as ImageJ) can be used to calculate the porosity fraction.

[0078] Aluminum paste can also be screen-printed, then dried and co-fired to form an aluminum metallization layer on the solar cell. Compared to silver-based systems, aluminum-based metallization layers have several disadvantages. For example, co-fired aluminum layers have significantly higher bulk resistivity compared to silver layers. The aluminum paste is made from Al particles, which do not fully sinter during firing, resulting in lower conductivity. Al particles are typically larger than Ag particles, leading to wider fine grid lines, larger solar cell shadows, and lower short-circuit current density trapped from the solar cell. Furthermore, aluminum forms a eutectic with silicon at 577°C, creating a highly p-type back surface field (BSF) that can penetrate several micrometers into the silicon substrate. The PN junction is typically smaller than 200 nm and can be shunt by the BSF. The BSF has a high defect density, leading to high minority carrier recombination, which may be undesirable.

[0079] Meier et al. described how to use four-point probe electrical measurements to determine the resistivity of each metallization layer and its contribution to the total series resistance on a complete solar cell. See Meier et al., “Determining components of series resistance from measurements on a finished cell,” IEEE (2006), pp. 1315–1318, which is incorporated herein by reference in its entirety. The bulk resistivity of the metallization layer is directly related to the bulk resistivity of the material used to fabricate the metallization layer. Pure Ag has a resistivity of 1.5 × 10⁻⁶. -8 The bulk resistance is Ω-m, while the pure Ag metallization layer used in conventional solar cells has a bulk resistance 1.2 to 5 times higher. Bulk resistance can be important for fine mesh lines that must carry current over relatively long (e.g., greater than 1 cm) lengths. When the cell is finished with solder ribbons in the module, the bulk resistance of the front busbar and the rear solder ribbon layer may be less important.

[0080] Embodiments of this disclosure provide a conductive multilayer stack that can replace the silver mesh lines and busbars in conventional solar cells and can significantly reduce the amount of silver consumed in solar cell metallization. Reference is now made to... Figure 2 This is a schematic cross-section of a conductive multilayer stack conforming to some embodiments of the present disclosure. Figure 2 A conductive multilayer stack 200 is shown, comprising a metal layer 230, a solderable layer 241, and a silver contact layer 220. In some embodiments, the silver contact layer 220 comprises a glass paste sublayer 221 and a silver sublayer 222 on the glass paste sublayer 221. In some embodiments, the silver contact layer 220 may include the silver sublayer 222 but not the glass paste sublayer 221. In some embodiments, the glass paste sublayer 221 penetrates at least one passivation layer 211. In some embodiments, the glass paste sublayer 221 penetrates at least one passivation layer 211 and contacts a substrate 210. In some embodiments, the silver contact layer 220 may be a continuous thin silver mesh (e.g., 5 micrometers thick). In some embodiments, the silver contact layer 220 may be discrete silver contact pads. Therefore, it should be understood that the silver contact layer 220 may be continuous or discontinuous. In some embodiments, the conductive multilayer stack 200 may be disposed on the surface of the substrate 210 and / or on the surface of at least one passivation layer 211 disposed on the surface of the substrate 210 (e.g., the front surface or the rear surface), wherein the surface of the substrate 210 contains at least one passivation layer 211 on the surface of the substrate 210 (e.g., the front surface or the rear surface).

[0081] In some embodiments, Figure 2The metal layer 230 comprises an aluminum layer and at least one corrosion-resistant joint (CRJ) layer. In some embodiments, the aluminum layer comprises a 30 µm thick aluminum alloy having a low porosity (e.g., less than 0.25%). In some embodiments, the at least one CRJ layer comprises a 50 nm thick titanium layer, wherein the aluminum layer is on the at least one CRJ layer. In some embodiments, the aluminum layer comprises an exposed surface containing natural oxides and is non-weldable. In some embodiments, the metal layer 230 comprises a copper layer without any CRJ layer. In some embodiments, the metal layer 230 has a thickness of 4 µm to 100 µm, 4 µm to 50 µm, 4 µm to 40 µm, 4 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 10 µm, or 4 µm to 6 µm. In some embodiments, the metal layer 230 has a thickness of 4 µm to 100 µm, 4 µm to 50 µm, 4 µm to 25 µm, 4 µm to 10 µm, or 4 µm to 6 µm. In some embodiments, the metal layer 230 has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. In some embodiments, the silver layer 222 has a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. In some embodiments, the solderable layer 241 has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. In some embodiments, the solderable layer 241 has a thickness of 3 µm to 50 µm, 4 µm to 40 µm, 4 µm to 30 µm, 4 µm to 20 µm, or 4 µm to 10 µm. In some embodiments, the solderable layer 241 is a 15 µm thick Sn-containing layer adhered to the silver layer 222. 97 Cu 2.75 Ag 0.25 The SAC305 solder has a higher melting point than SnPb-based solders, enabling the cells to be soldered together using busbars and conventional module manufacturing tools. In some embodiments, the solderable layer 241 is a 15 µm thick layer containing Bi2Pb adhered to the silver layer 222. 58 Sn 42A layer of (BiSn). The low melting point of tin-bismuth solder may result in less thermal stress on the system. Tin-bismuth solder is commonly used on busbars to bond HJT cells. BiSn solder may be effective for low-temperature applications and for eliminating traditional silver pads from solar cells.

[0082] In some embodiments, the substrate 210 is a silicon substrate for a solar cell, and at least one passivation layer 211 is at least one passivation layer for a solar cell. In some embodiments, the at least one passivation layer 211 may include a tunneling oxide layer, a doped layer comprising n-type doped polycrystalline silicon (poly-Si) on at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on at least a portion of the doped layer. In some embodiments, a glass paste sublayer 221 may penetrate the at least one SiOxNy passivation layer and contact the doped layer. In some embodiments, the tunneling oxide layer comprises SiOx. The at least one SiOxNy passivation layer may comprise SiOx, SiNy, SiON, or a combination thereof. In some embodiments, the tunneling oxide layer is 1 nm to 5 nm thick, the doped layer is 50 nm to 200 nm thick, and / or the at least one SiOxNy passivation layer is 50 nm to 100 nm thick.

[0083] In some embodiments, at least one passivation layer 211 comprises SiOx, AlOx, and / or SiOxNy. In some embodiments, at least one passivation layer 211 comprises a first passivation layer comprising SiOx and at least one second passivation layer comprising SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. In some embodiments, at least one passivation layer 211 comprises a first passivation layer comprising AlOx and at least one second passivation layer comprising SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. The at least one second passivation layer comprising SiOxNy may comprise SiOx, SiNy, SiON, or a combination thereof. The first passivation layer may be 1 nm to 5 nm thick, and / or the at least one second passivation layer may be 50 nm to 100 nm thick. In some embodiments, the at least one second passivation layer is directly on the first passivation layer. In some embodiments, an intermediate passivation layer may be located between the first passivation layer and the at least one second passivation layer, wherein the intermediate passivation layer comprises AlOx. The intermediate passivation layer may have a thickness ranging from 1 nm to 5 nm. In some embodiments, the glass paste sublayer 221 may penetrate at least one passivation layer comprising SiOx, AlOx, and / or SiOxNy.

[0084] In some embodiments, the surface of the silicon substrate 210 (e.g., the front surface and / or the back surface) may further include a doped layer (not shown), and at least one passivation layer 211 is on the doped layer. The silicon substrate 210 may be doped with a dopant, and the doped layer may have a different dopant, a different dopant type, and / or a different dopant concentration than the silicon substrate 210. In some embodiments, at least one passivation layer 211 may comprise SiOx, AlOx, or SiOxNy. In some embodiments, at least one passivation layer 211 comprises a first passivation layer comprising SiOx and at least one second passivation layer comprising SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. In some embodiments, the first passivation layer has a thickness ranging from 1 nm to 5 nm. In some embodiments, the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. In some embodiments, the at least one second passivation layer is directly on the first passivation layer. In some embodiments, an intermediate passivation layer may be between the first passivation layer and the at least one second passivation layer, wherein the intermediate passivation layer comprises AlOx. The intermediate passivation layer can have a thickness ranging from 1 nm to 5 nm. In some embodiments, the glass paste sublayer 221 can penetrate at least one passivation layer 211 and contact the doped layer. In some embodiments, the doped layer can be 30 nm to 200 nm thick. In some embodiments, the doped layer contains an n-type dopant or a p-type dopant.

[0085] In some embodiments, at least one passivation layer 211 and a conductive multilayer stack 200 are located on the back surface of a silicon substrate 210. In some embodiments, the back surface of the silicon substrate 210 may further include at least one doped layer (not shown), and the at least one passivation layer 211 is on the at least one doped layer. In some embodiments, the at least one doped layer includes at least one doped region and at least one opposite doped region. The at least one doped region may contain a p-type dopant, and the at least one opposite doped region may contain an n-type dopant, or vice versa. In some embodiments, a glass paste sublayer 221 may penetrate at least one passivation layer 211 and contact the at least one opposite doped region. In some embodiments, the at least one doped region or the at least one opposite doped region may have a thickness ranging from 30 nm to 200 nm.

[0086] In some embodiments, the silicon substrate 210 is a silicon substrate for an HJT solar cell, and the conductive multilayer stack 200 does not include a glass paste sublayer 221. In some embodiments, at least one passivation layer 211 includes an intrinsic amorphous layer on at least a portion of the silicon substrate 210 and a doped layer on at least a portion of the intrinsic amorphous layer. A transparent conductive oxide layer (not shown) may be present on at least a portion of the doped layer of the at least one passivation layer 211. A silver contact layer 220 may contact at least a portion of the transparent conductive oxide layer. In some embodiments, the silicon substrate 210 may be doped, and the doped layer may contain different dopants, different dopant types, and / or different dopant concentrations than those of the silicon substrate 210. In some embodiments, the doped layer includes p-type doped hydrogenated amorphous silicon (a-Si:H(p)) or n-type doped hydrogenated amorphous silicon (a-Si:H(n)). In some embodiments, the transparent conductive oxide layer includes indium tin oxide. In some embodiments, the intrinsic amorphous layer contacts at least a portion of the silicon substrate 210, the doped layer contacts at least a portion of the intrinsic amorphous layer, and the transparent conductive oxide layer contacts at least a portion of the doped layer. In some embodiments, a transparent conductive oxide layer is located between and contacts at least a portion of the at least one doped region and at least a portion of the silver contact layer 220. In some embodiments, a transparent conductive oxide layer is located between and contacts at least a portion of the at least one oppositely doped region and at least a portion of the silver contact layer 220. In some embodiments, at least one passivation layer 211 is located on the front and / or back surface of the silicon substrate of the HJT solar cell. In some embodiments, the doped layer comprises at least one doped region and at least one oppositely doped region. The at least one doped region may contain a p-type dopant, and the at least one oppositely doped region may contain an n-type dopant, or vice versa. In some embodiments, the at least one doped region may be separate from the at least one oppositely doped region. In some embodiments, the thickness of the intrinsic amorphous layer ranges from 2 nm to 5 nm, the thickness of the doped layer ranges from 10 nm to 50 nm, or the thickness of the transparent conductive oxide layer ranges from 50 nm to 100 nm.

[0087] This can be achieved by first fabricating a silver contact layer (e.g., Figure 2 The silver contact layer 220 in this disclosure is used to fabricate a conductive multilayer stack on a solar cell. Reference is now made to... Figure 3 This is a schematic diagram of a silicon solar cell including silver contact pads, busbars, and pads, which conforms to some embodiments of this disclosure. Figure 3A solar cell 300 is shown, comprising a silicon substrate 310, a busbar 340, and pads 330; however, the continuous fine grid lines conventionally used in solar cells (e.g., Figure 1 The fine grid lines 120 in the image are replaced by discontinuous lines of the silver contact pads 320. It should be understood that the solar cell 300 may include at least one passivation layer on the silicon substrate 310 as described above. In some embodiments, the discontinuous lines of the silver contact pads 320 are straight lines extending parallel to the edge of the silicon substrate 310. Although in Figure 3 Not shown, but the discontinuity line of the silver contact pad 320 can be zigzag, curved, or any other line shape. In some embodiments, the first silver contact pad in the silver contact pad 320 can be separated from the second silver contact pad in the silver contact pad 320 by, for example, greater than 200 µm, greater than 500 µm, greater than 1 mm, greater than 2 mm, or greater than 3 mm. In some embodiments, the first silver contact pad in the silver contact pad 320 can be separated from the second silver contact pad in the silver contact pad 320 by a distance of 200 µm to 2 mm, 200 µm to 1 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. The first silver contact pad and the second silver contact pad in the silver contact pad 320 are continuous silver contact pads in a discontinuity line.

[0088] It should be understood that the description herein regarding silver contact pad 320 can be applied to one or more silver contact pads in silver contact pad 320. In some embodiments, each silver contact pad in silver contact pad 320 may have a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. In some embodiments, each silver contact pad in the silver contact pad 320 may have a length ranging from 30 µm to 250 µm, from 30 µm to 225 µm, from 30 µm to 200 µm, from 30 µm to 175 µm, from 30 µm to 150 µm, from 30 µm to 125 µm, from 30 µm to 100 µm, from 30 µm to 75 µm, from 30 µm to 60 µm, from 30 µm to 50 µm, or from 30 µm to 40 µm. In some embodiments, each silver contact pad in the silver contact pad 320 may be square and have a length greater than 20 µm, 30 µm, 40 µm, 50 µm, 60 µm, 75 µm, 100 µm, 125 µm, 150 µm, or 200 µm. The silver contact pads 320 can have any shape (e.g., circular, rectangular, elliptical, or a combination thereof). In some embodiments, each silver contact pad in the silver contact pads 320 can have a thickness of 4 µm to 10 µm, or the first silver contact pad of the silver contact pads 320 can have a thickness of 4 µm to 10 µm, and the second silver contact pad of the silver contact pads 320 can have a thickness of 4 µm to 15 µm.

[0089] Silver contact pads 320 can be manufactured by altering the fine mesh pattern on the screen printing lines to form a desired size, quantity, and / or shape. In some embodiments, silver contact pads 320 may include a glass paste sublayer (e.g., Figure 2 The glass slurry sublayer 221) and the silver layer on the glass slurry sublayer (e.g., Figure 2(Silver layer 222 in the middle). In some embodiments, the silver contact pad 320 may include a silver layer without glass paste. It may be desirable to minimize the surface area and / or thickness of the silver contact pad 320 to reduce silver consumption. Existing silver metallization pastes may be used in conjunction with drying and co-firing to form the silver contact pad 320. It may also be desirable to modify existing silver pastes to improve adhesion, passivation layer etching, and / or contact resistance. For example, to change the thickness, the silver loading in the paste can be varied (e.g., from 90 wt.% Ag particles to 85 wt.% Ag particles). As another example, adhesion can be varied by changing the glass paste loading in the paste (e.g., from 1 wt.% to 2 wt.%) or by changing the type of glass paste. In some embodiments, contact resistance can be improved by reducing the glass paste concentration in the paste and / or changing the type of glass paste. Conventional symmetrical solar cells may contain 80 to 200 fine silver grid lines per side and have the highest silver usage. In contrast, some embodiments of this disclosure provide silver contact pads (e.g., Figure 3 The discontinuous lines of the silver contact pads 320 in the solar cell, wherein the silver used in the discontinuous lines can be finer than the continuous grid lines in conventional solar cells (e.g., ...). Figure 1 The finer grid lines in the 120 grid are reduced by 25%, 50%, 60%, 75%, 90%, or 95%.

[0090] Now for reference Figure 4 This is a schematic diagram of a silicon solar cell 400 conforming to some embodiments of the present disclosure, the silicon solar cell including a silicon substrate 410, a first plurality of silver contact pads 420, a second plurality of silver contact pads 440 and pads 430. Figure 4 This demonstrates that the continuous silver busbars used in conventional solar cells can be replaced with a second plurality of silver contact pads 440 (e.g., Figure 1 Busbar 130 in the middle is used to further reduce silver consumption. In some embodiments, the second plurality of silver contact pads 440 are discontinuities of the silver contact pads. It should be understood that the solar cell 400 may include at least one passivation layer on the silicon substrate 410 as described above. In some embodiments, the discontinuities of the second plurality of silver contact pads 440 are straight lines extending parallel to the edge of the silicon substrate 410. Although in Figure 4Not shown, but the discontinuities of the second plurality of silver contact pads 440 can be zigzag, curved, or any other line shape. It should be understood that the description herein regarding the second plurality of silver contact pads 440 can be applied to one or more silver contact pads in the second plurality of silver contact pads 440. It should be further understood that in some embodiments, the first plurality of silver contact pads 420 are discontinuities of silver contact pads perpendicular to the discontinuities of the second plurality of silver contact pads 440. In some embodiments, the silver contact pads in the second plurality of silver contact pads 440 can be separated by a distance greater than 200 µm, greater than 500 µm, greater than 1 mm, greater than 2 mm, or greater than 3 mm. In some embodiments, the silver contact pads in the second plurality of silver contact pads 440 can be separated by a distance of 200 µm to 2 mm, 200 µm to 1 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. In some embodiments, the silver contact pads in the second plurality of silver contact pads 440 may have a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. In some embodiments, the silver contact pads in the second plurality of silver contact pads 440 may have a length ranging from 30 µm to 250 µm, from 30 µm to 225 µm, from 30 µm to 200 µm, from 30 µm to 175 µm, from 30 µm to 150 µm, from 30 µm to 125 µm, from 30 µm to 100 µm, from 30 µm to 75 µm, from 30 µm to 60 µm, from 30 µm to 50 µm, or from 30 µm to 40 µm. In some embodiments, the silver contact pads in the second plurality of silver contact pads 440 may be square, with a length greater than 10 µm, 15 µm, 20 µm, 30 µm, 40 µm, 50 µm, 60 µm, 75 µm, 100 µm, 125 µm, 150 µm, or 200 µm. The second plurality of silver contact pads 440 may have any shape (e.g., circular, rectangular, elliptical, etc., or combinations thereof) to reduce silver consumption. In some embodiments, the second plurality of silver contact pads 440 may be manufactured by changing the busbar screen pattern on the screen printing line to form the desired size, number, and / or shape. Existing silver metallizing pastes may be used in conjunction with drying and co-firing to form the second plurality of silver contact pads 440. In some embodiments, it may be advantageous to use a “floating busbar” paste containing a non-burnt glass paste. The first plurality of silver contact pads 420 are as described above (e.g., Figure 3 (Silver contact pad 320 in the middle).

[0091] As described above, asymmetric solar cells (e.g., interdigitated back contact (IBC) cells) can be designed to maximize light absorption on the front side of the solar cell and metallize the back side. Now refer to... Figure 5 This is a schematic diagram of a conventional asymmetric solar cell 500 design, which includes aluminum fine mesh lines 560 contacting the p-type region on the rear surface 510 of the asymmetric solar cell 500 and silver fine mesh lines 530 contacting the n-type region. The aluminum fine mesh lines 560 are not solderable; therefore, they are connected to silver pads 550, which can be soldered to contact silver pads 540 at one end of the asymmetric solar cell 500. The silver fine mesh lines 530 are connected to pads 520 at the opposite end of the asymmetric solar cell 500. It should be understood that... Figure 5 The design of an asymmetric solar cell for a p-type cell is demonstrated. For an n-type asymmetric solar cell, a fine silver grid line can replace the fine aluminum grid line 560, the silver pad 550 can be removed, and the replacement fine silver grid line can be soldered to the silver pad 540.

[0092] Now for reference Figure 6 This is a schematic diagram of an exemplary asymmetric solar cell including silver contact pads that conforms to some embodiments of the present disclosure. Figure 6 An exemplary p-type asymmetric solar cell 600 is shown, the asymmetric solar cell having a first plurality of silver contact pads 630 contacting an n-type region on a rear surface 610 of the p-type asymmetric solar cell 600, and aluminum fine mesh lines 660 contacting the p-type region on the rear surface 610 of the p-type asymmetric solar cell 600. It should be understood that the asymmetric solar cell 600 may include at least one passivation layer on the rear surface 610 as described above. Additionally, the p-type asymmetric solar cell 600 may include components that can replace the silver pads 520 and 540, respectively. Figure 5 The first plurality of silver contact pads 620 and the third plurality of silver contact pads 640 are provided. After metallization (described further below), the first plurality of silver contact pads 620 can be connected to the third plurality of silver contact pads 640, and the aluminum fine mesh line 660 can be connected to the second plurality of silver contact pads 620. It should be understood that for n-type asymmetric cells, the aluminum fine mesh line 660 can be replaced by a fourth plurality of silver contact pads (not shown), and the silver pads 650 can be removed.

[0093] therefore, Figures 2 to 4 and Figure 6 This demonstrates that conductive multilayer stacks can be applied to conventional solar cell designs with minimal processing adjustments, significantly reducing silver consumption.

[0094] The silver contact pads provided by the embodiments of this disclosure can make ohmic contacts with a silicon substrate (e.g., for solar cells), but require an additional metal layer (e.g., Figure 2 The metal layer 230 in the middle is used to transfer charge away from the silicon substrate. For example, Figures 2 to 4 and Figure 6 The schematic diagrams of solar cells shown all include silver contact pads to extract charge from the silicon substrate, but continuous electrical connections between silver contact pads may be needed to transfer charge from the wafer to other components of the solar cell module.

[0095] The conductive multilayer stack disclosed herein can be electrically connected to a busbar electrically connected to at least one pad or interconnect pad. In some embodiments, a method for manufacturing a metallization layer for a solar cell is provided, the method comprising the steps of: providing a silicon substrate, applying a silver metallization paste to a surface of the silicon substrate in a discontinuous pad design, drying the silver layer, and co-firing a silicon wafer to form silver contact pads. A solderable paste with a melting point below 450°C can be printed on top of the silver contact pads and can subsequently be dried or cured to form a solderable layer. In some embodiments, a metal layer can be placed on the solderable layer, followed by heating to mechanically bond the metal layer to the silver contact pads, and then laser-cut to form a narrow line shape. In some embodiments, the metal layer can be laser-cut first, then placed on top of the solderable layer, and then soldered to the silver contact pads. In some embodiments, the metal layer comprises copper. In some embodiments, the metal layer is pure copper or a copper alloy foil. In some embodiments, the metal layer is copper foil. In some embodiments, a flux (e.g., Alpha NR205) can be added to the coated aluminum foil or directly to the silver contact pads to aid soldering. In some embodiments, the solderable layer contains flux that can clean the surface of the metal layer and the surface of the silver contact pads during soldering. Conductive multilayer stacking process and the resulting metal wire structure on silicon solar cells

[0096] Now for reference Figures 7A to 7C It is a top-view image of a metallized solar cell at different stages of manufacturing a conductive multilayer stack. Figure 7A This is a top-view microscopic image of silver contact pads printed on a silicon wafer coated with at least one passivation layer. On the silicon wafer coated with at least one passivation layer, the silver contact pads in a row are spaced 500 µm apart from their nearest neighbor. The silver contact pads are... Figure 7A The larger pads are located between the larger pads in the middle. Larger pads on the left and right sides of each horizontal row of silver contact pads are used to support the structure for measurement. Figure 7C The characteristics of conductive multilayer lines. The silver contact pads in a row are separated by 1400 µm from the silver contact pads in the adjacent column (e.g., directly above or directly below). Figure 7AThe silver contact pads in the [structure] have an average diameter of 79.7 µm and an average thickness of 7 µm. Solder paste (SAC305) was then screen-printed onto [the surface]. Figure 7B The silver contact pads and larger contact pads are shown. The SAC35 solder layer is approximately 25 µm thick (before soldering) and completely covers the silver contact pads. Finally, copper foil is placed on top of the solder-coated silver contact pads (and larger contact pads) and soldered for less than five seconds at a temperature below 300°C. The copper foil is kept taut and then laser-cut to form the desired line shape using a 70 W fiber laser (1064 nm wavelength, 30 µm focal spot size) in pulse mode with a pulse duration of 200 ns, a repetition rate of 250 kHz, and a scan speed of 1 m / s. Figure 7C Six conductive multilayer lines with twelve conductive multilayer stacks are shown. The conductive multilayer stacks include a metal layer (e.g., copper), a solderable layer, and silver contact pads on a passivated silicon wafer. Figure 7C Each conductive multilayer line shown has a metal layer that is a continuous layer, in which case the metal layer connects the conductive multilayer stack and constitutes each conductive multilayer stack 200 of the conductive multilayer line (see [reference]). Figure 2 The corresponding metal layer 230. The conductive multilayer line may include multiple conductive multilayer stacks. The metal (e.g., copper) layer may have a line width of less than 250 µm. For fine grid lines, it may be desirable to reduce the conductive multilayer line width to less than 500 µm, 450 µm, 400 µm, 350 µm, 300 µm, 250 µm, 200 µm, 150 µm, 125 µm, 100 µm, 75 µm, 60 µm, 50 µm, 40 µm, or 30 µm. When measured using confocal microscopy, the laser-cut edge may have an in-plane edge roughness of less than 10 µm Ra. The average burr height may be less than 6 µm. The conductive multilayer line may be flat and, in some embodiments, raised above the silicon substrate. Figure 7D This is a 3D image produced using a confocal microscope (20x magnification). Part 701 of the image is a silicon wafer, and part 702 is a copper foil, which is relatively flat and 25 µm above the silicon wafer. The conductive multilayer line has a height determined by the solderable layer thickness, soldering conditions, foil tension, and / or foil thickness. In some embodiments, the conductive multilayer line height may be less than 60 µm above the silicon substrate, less than 50 µm above the silicon substrate, less than 40 µm above the silicon substrate, less than 30 µm above the silicon substrate, less than 25 µm above the silicon substrate, less than 20 µm above the silicon substrate, less than 15 µm above the silicon substrate, or less than 10 µm above the silicon substrate. Laser cutting of conductive multilayer wires enables novel battery geometries and significant silver savings.

[0097] Embodiments of this disclosure can reduce the total metallization area on a solar cell and thus reduce silver consumption by more than 90 wt.%, more than 80 wt.%, more than 70 wt.%, or more than 50 wt.%, by converting continuous metal lines (e.g., fine mesh lines and / or busbars) into discrete silver contact pads. The amount of metallization on a solar cell can be quantified, for example, by determining the mass (mg / cell) of silver paste applied per cell before and after screen-spraying the metallization paste, determining the percentage of metallized area (e.g., 7%), or determining the metallization volume on the solar cell. The percentage of metallized area can be determined using a flatbed scanner, imaging software, or other equipment for determining the percentage of surface area. The metallization volume can be determined using a confocal microscope. In some embodiments, the size of the silver contact pads and the spacing between the silver contact pads can determine the total silver savings. In some embodiments, the total silver paste consumption on a solar cell including a conductive multilayer stack ranges from 5 mg / cell to 120 mg / cell, from 5 mg / cell to 90 mg / cell, from 5 mg / cell to 75 mg / cell, from 5 mg / cell to 60 mg / cell, from 10 mg / cell to 50 mg / cell, from 10 mg / cell to 40 mg / cell, or from 20 mg / cell to 50 mg / cell. In some embodiments, the total metallization area on a solar cell including a conductive multilayer stack (e.g., including silver contact pads) can range from 0.5% to 7%, from 0.5% to 6%, from 0.5% to 5%, from 0.5% to 4%, from 0.5% to 3%, from 0.5% to 2%, from 0.5% to 1%, or from 0.5% to 0.75%. In contrast, conventional solar cells can use 140 mg / cell of silver and exhibit a total metallization area of ​​8% to 9%.

[0098] Now for reference Figure 8 This is a schematic cross-section of a conductive multilayer line 800 on a substrate 810, conforming to some embodiments of the present disclosure. The conductive multilayer line includes a metal layer 830, a solderable layer 840, and silver contact pads 820. The silver contact pads include a glass paste sublayer 821 and a silver sublayer 822. The substrate 810 contains at least one passivation layer 811 on its surface. It should be understood that the metal layer 830, solderable layer 840, substrate 810, and at least one passivation layer 811 are as described above, for example... Figure 2 As described above, and the silver contact pad 820 is as described in the text. Figure 3 , Figure 4 and Figure 6 As described in [the text]. Figure 8As shown, the illustrated conductive multilayer line 800 includes three conductive multilayer stacks identified by three silver contact pads 820, wherein the solderable layer 840 includes three regions formed on the three silver contact pads 820, and the conductive multilayer stacks have each conductive multilayer stack 200 constituting the conductive multilayer line (see [reference]). Figure 2 The corresponding metal layer 230 of the conductive multilayer line 800 is a continuous common metal layer 830. In this way, the conductive multilayer line 800 connects a series of silver contact pads 820. In some embodiments, the silver contact pads 820 are separated from their nearest neighboring silver contact pads (i.e., the nearest silver contact pads) by more than 200 µm, more than 300 µm, more than 400 µm, more than 500 µm, more than 700 µm, more than 800 µm, more than 1 mm, and more than 2 mm. In some embodiments, the silver contact pads 820 may be separated by 200 µm to 2 mm, 300 µm to 1 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm.

[0099] In some embodiments, the metal layer of a conductive multilayer stack or conductive multilayer wire can be formed by laser cutting coated aluminum foil. The aluminum surface may have natural oxides that are difficult to directly solder to silver. Laser welding can be used to directly weld silver to aluminum, but laser welding can cause thermal shock and the weld area is quite small. This can result in weak, discontinuous welds and make consistently passing thermal cycling tests challenging. Furthermore, aluminum and silver are electrochemically different materials and can corrode under humid conditions. Solar modules typically require >1000 hours of humid heat (85°C / 85% relative humidity). Coating aluminum foil allows for the fabrication of metal wires on silicon solar cells via laser cutting. The coated aluminum layer may include an aluminum layer and at least one corrosion-resistant joint (CRJ) layer on at least one side.

[0100] In some embodiments, the aluminum layer has a thickness of 3 µm to 200 µm, 10 µm to 100 µm, 10 µm to 75 µm, or 10 µm to 30 µm. A 30 µm thick rolled aluminum alloy foil can serve as the aluminum layer. The rolled aluminum foil is not porous and has high bulk conductivity. The composition and thickness of the aluminum alloy layer can be optimized to be robust, relatively conductive, and sufficiently flexible to be wound and positioned over the solar cell. The aluminum layer may include aluminum and combinations of copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), or more, such as alloys, to strengthen the foil and improve laser cutting characteristics. The conductivity of the aluminum foil can be significantly higher than that of films produced by printing and firing metal particles. Bulk resistivity can be a useful characteristic, which can be measured using a four-point probe system to determine the sheet resistance and divide by the film thickness. The bulk resistivity of pure aluminum is 2.6E-6 Ohm-cm. The bulk resistivity of aluminum particle films can be 10 to 100 times higher than that of pure aluminum. In some embodiments, the aluminum layer is a solid metal with no porosity or with less than 0.25% porosity. Pure aluminum has the highest electrical conductivity, but its ultimate tensile strength is relatively low (<200 MPa), thus requiring special treatment. Alloyed aluminum typically increases bulk resistivity but reduces flexibility. In some embodiments, the metal layer has a bulk resistivity of 2.6E-6 Ohm-cm to 13E-6 Ohm-cm, 2.6E-6 Ohm-cm to 6.2E-6 Ohm-cm, or 2.6E-6 Ohm-cm to 3.9E-6 Ohm-cm. Higher strength aluminum alloys, such as the 1100, 0303, 0304, 5083, 7075, and 8079 series, also exhibit good corrosion resistance and reasonable electrical conductivity. Metals can be selected based on the metal alloy and thickness, resulting in negligible series resistance after manufacturing and continued good performance after damp heat testing (85°C, 85% relative humidity, for 1000 to 4000 hours).

[0101] Surface roughness of metal foil can be an important consideration for conformally coating thin layers onto the foil. Surface roughness can be measured using a Keyence laser profilometer. A laser profilometer can measure average roughness (Ra), RMS roughness (Rq), and peak height (Rz). A smooth foil allows for minimizing coating thickness. Common “converter” aluminum foils have significantly higher roughness (i.e., Ra ≥ 400 nm) and finer structural tears; physical vapor deposition coatings below 200 nm may not conformally coat these foils sufficiently, resulting in pinholes in the coating. Aluminum foil exposed at these pinholes may react with silver or solder materials and increase contact resistance when exposed to humid heat. Therefore, minimizing surface roughness and coating thickness is desirable for conformally coating the aluminum layer. Smoothing rolls can be used during cold rolling of the foil to minimize surface roughness. When the average surface roughness > 400 nm, it may be desirable to smooth the surface by depositing aluminum or to planarize the surface by chemical and mechanical means (e.g., chemical mechanical polishing). In some embodiments, the average surface roughness is less than 450 nm, less than 400 nm, less than 350 nm, less than 300 nm, less than 250 nm, and / or less than 20 nm. In some embodiments, the aluminum foil has a roughness of less than 10 nm. Hereinafter, a solderable layer is a layer containing solder material. A solderable layer is a layer that can be soldered. For example, an electronic ink layer can be soldered and is therefore a solderable layer. A solderable layer may include a solder material layer and a layer that can be soldered but does not contain solder material.

[0102] In some embodiments, the metal layer may be selected from a foil with a smooth side having a low surface roughness. In some embodiments, the metal layer may be a 30 µm thick aluminum alloy (8079 series) foil. Table 1 shows Keyence surface images of the glossy side of the metal foil, which have Ra = 175 nm, Rq = 214 nm, and Rz = 1,196 nm. Table 1 shows Keyence surface images of the matte side of the metal foil, which have Ra = 458 nm, Rq = 573 nm, and Rz = 3,270 nm. It may be desirable to coat the metal foil with an average surface roughness of less than 500 nm, less than 400 nm, or less than 300 nm to prevent pinholes. It should be understood that only one side of the aluminum metal layer may be coated with a corrosion-resistant bonding layer to allow bonding to the silver contact pads. The exposed surface of the aluminum metal layer (e.g., the surface facing away from the silver contact layer / silver contact pads) may contain a natural oxide, or a laser power-absorbing layer (e.g., carbon black, titanium, or nickel), or a corrosion-resistant layer (e.g., titanium nitride). It should be understood that it may not be necessary to use a corrosion-resistant bonding layer on the exposed surface of the aluminum layer. Table 1: Foil Roughness Indicators of Solar Grade Aluminum Foil

[0103] In some embodiments, the coated aluminum layer includes at least one corrosion-resistant joint (CRJ) layer. The CRJ layer may contain a material different from that of the aluminum layer. In some embodiments, the first CRJ layer in contact with the aluminum layer (or the coated aluminum layer) may contain chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), alloys thereof, nitrides thereof, borides thereof, composites thereof, or combinations thereof. In some embodiments, the first CRJ layer has a thickness of 1 nm to 2 µm, or 5 nm to 1 µm, 10 nm to 200 nm, or 20 nm to 150 nm. The at least one CRJ may be deposited by evaporation deposition, sputtering deposition, ALD, electroplating, or electroless deposition. In some embodiments, a 30 µm thick aluminum alloy (8079 series) foil is first plasma etched in a vacuum to remove the natural oxide (Al2O3) before directly sputtering a 75 nm thick titanium layer onto the bare aluminum surface.

[0104] In some embodiments, a solderable material (such as silver and copper) may also be used as the at least one CRJ layer. In some embodiments, a first CRJ layer is applied to prevent corrosion and interdiffusion of additional coatings. In some embodiments, the aluminum metal layer is a 30 μm thick 8079 aluminum alloy, the first CRJ layer is a 20 nm to 100 nm thick titanium layer, and the second (outer) coating is a 100 nm thick solderable material containing copper. The second (outer) CRJ layer may be in contact with the first CRJ layer. The second CRJ layer may contain silver (Ag), copper (Cu), alloys thereof, composites thereof, or a combination thereof. In some embodiments, the second (outer) CRJ layer has a thickness from 2 nm to 2 µm, from 5 nm to 1 µm, from 20 nm to 250 nm, or from 40 nm to 250 nm. The at least one CRJ layer may be deposited via evaporation deposition, sputtering deposition, ALD, electroplating, or electroless deposition. In some embodiments, the second (outer) coating contains 200 nm of copper. In some embodiments, the coated aluminum layer comprises a 30 μm aluminum foil coated with a first CRJ layer of 50 nm titanium and a second (outward-facing) coating of 200 nm copper. In some embodiments, a third CRJ layer may be applied to prevent copper diffusion. In some embodiments, the first CRJ layer is 50 nm titanium, the second CRJ layer is 200 nm copper, and the third CRJ layer is 10 nm silver. It may be desirable to minimize the thickness of at least one CRJ layer to below 500 nm, below 400 nm, below 350 nm, below 300 nm, below 250 nm, or below 200 nm. Glass / glass encapsulation (i.e., the solar cell sandwiched between two pieces of glass) can be used to significantly reduce moisture ingress into the module. For glass / glass modules, an aluminum foil with a thin (50 nm to 500 nm) copper coating can be used as the sole CRJ layer.

[0105] In some embodiments, the metal layer of the conductive multilayer stack or conductive multilayer line can be a copper metal layer, such as a copper metal layer formed by laser cutting copper foil. The copper foil can be formed on a titanium drum by electrodeposition, having a thickness of 4 µm to 100 µm. In some embodiments, the copper metal layer has a thickness of 4 µm to 100 µm, 4 µm to 50 µm, 4 µm to 25 µm, 4 µm to 10 µm, or 4 µm to 6 µm. The copper foil can achieve an ultimate tensile strength greater than 400 MPa and exhibits good temperature stability. For battery foil and printed circuit board applications, the copper foil is typically treated with a thin metal oxide layer. These coatings are well known in the copper foil industry, and some coatings are intended to improve the solderability of the copper foil. Electrodeposited copper foil typically has at least one smooth (also known as bright) side and may have a matte (also known as dark) side. Keyence surface imaging of the bright side of the copper foil measured Ra = 260 nm, Rq = 320 nm, and Rz = 2120 nm. Keyence surface imaging of the matte side of the copper foil measured Ra = 1370 nm, Rq = 1760 nm, and Rz = 14290 nm. A smooth copper foil is likely desirable to improve solderability, resulting in strong adhesion, exhibiting low contact resistance, and demonstrating excellent damp-heat reliability. Copper is solderable and chemically compatible with silver. For the same thickness, the copper foil is priced per unit area ($ / m²). 2 It could be ten times that of aluminum. The thickness of silver metallization lines has steadily decreased to 5 µm to 12 µm over the past decade, and these silver lines can be replaced with 4 µm to 10 µm copper foil while maintaining equivalent (or higher) conductivity. In some embodiments, thin copper foil can be used economically to replace the metallization layer on silicon cells.

[0106] In some embodiments, the solder paste comprises solder particles, organic binders, fluxes or activators, and additives well known in the field of soldering technology. Different metals can be joined by soldering, a process distinct from fusion welding. The silver contact layer and silver contact pads can be firmly bonded to the silicon wafer after co-firing; however, the coefficient of thermal expansion of silicon differs from that of the silver sublayer and the glass paste sublayer, making the silver contact layer susceptible to thermal shock. In some embodiments, the copper foil and silver contact pads are bonded at temperatures below 500°C, below 450°C, below 400°C, below 350°C, below 300°C, below 250°C, or below 150°C. In some embodiments, Sn coated with 20 µm to 40 µm is used. 60 Pb 40Solar cells are soldered using busbars with (SnPb) layers having a liquidus point close to 190°C. Solar cells are typically soldered together on a hot plate using infrared heating; soldering conditions can exceed the liquidus point by 10 to 50 degrees. Therefore, the solder material may have a liquidus point above 200°C after initial soldering. Solderable materials can have liquidus points that allow bonding at temperatures ranging from 130°C to 500°C, 130°C to 400°C, or 190°C to 350°C.

[0107] Solder particles may contain compositions as described in Table 2, for example. The diameter of the solder particles may vary from 1 μm to 25 µm, from 5 μm to 20 µm, or from 5 μm to 10 μm. In some embodiments, the solder particle size may be minimized and printed as a thin layer with minimal material usage. The flux included in the solder paste may be designed to clean silver and copper surfaces. Table 2. Welding Compounds

[0108] Alternative solder pastes (commonly referred to as conductive inks) that do not contain solder particles and can be used for soldering at low temperatures (e.g., below 300°C) can also be used. Examples of such solder pastes are described in U.S. Patent No. 10,301,497, U.S. Patent Application Publication No. 2015 / 0298248 A1, and U.S. Patent Application Publication No. 2023 / 0242783, each of which is incorporated herein by reference in its entirety. These conductive inks can be deposited by screen printing and dried below 150°C, or UV cured and subsequently heated to below 300°C to solder to copper or coated aluminum foil. These conductive inks can also form solderable layers in conductive multilayer stacks and conductive multilayer lines as described herein. Methods for forming CMS and cutting narrow metal wires on solar cells

[0109] In some embodiments, fabricating a conductive multilayer stack or a conductive multilayer line with a narrow linewidth on a solar cell may include: 1) precisely positioning the solar cell under a foil for a metal layer, 2) welding, and 3) laser cutting. In some embodiments, the conductive multilayer stack or conductive multilayer line may be formed by first welding the metal foil and then laser cutting it, or by first laser cutting the metal foil to form a narrow line and then welding the narrow line. Laser cutting first may be advantageous because the foil can be cut under a wide variety of processing conditions without damaging the surface passivation layer on the silicon wafer.

[0110] Reference marks can be added to the solar cell during screen printing. These reference marks can be used to orient the wafer under the foil and identify the position of the silver contact layer of the silver contact pads on the silicon wafer. An opening is laser-cut from the foil prior to positioning the soldering and laser dicing tools to achieve visual registration with the reference marks on the wafer. Wafer alignment is well-known in the solar cell industry and can achieve accuracy below 20 micrometers when the solder paste is screen-printed on top of the silver contact layer or silver contact pads.

[0111] Soldering can be used to join metal layers, solderable layers, and silver contact layers (or silver contact pads) to form conductive multilayer stacks or conductive multilayer lines. The silicon wafer can be preheated using a heated chuck during cell positioning. The preheating temperature should not exceed the flux activation temperature. In some embodiments, the wafer is heated to temperatures greater than 100°C, greater than 130°C, greater than 150°C, greater than 175°C, greater than 200°C, or greater than 250°C for soldering. Once the wafer has been moved into contact with the metal layer, the foil can be heated to temperatures greater than 150°C, greater than 200°C, greater than 250°C, greater than 300°C, greater than 350°C, or greater than 400°C for a duration of less than 1 second, less than 2 seconds, less than 3 seconds, or less than 180 seconds. The foil can be heated via infrared heating, hot air, or a heating block. The foil can be kept taut but may not always be perfectly horizontal when in contact with the silicon wafer. The heating block can be made by placing a resistance heater within a solid block of metal (e.g., copper) or ceramic, and can be used to gently press the foil onto the silicon substrate, resulting in more uniform soldering. In some embodiments, the heating block is opaque and does not move away from the battery after soldering to allow for laser cutting from above. Hot air can also be used to heat the foil and apply gentle pressure to it to improve large-area bonding.

[0112] Laser cutting can be used to form metallized lines on conductive multilayer stacks or conductive multilayer lines. In some embodiments, continuous and pulsed laser beams are focused to spot sizes of less than 100 µm, less than 80 µm, less than 60 µm, less than 40 µm, or less than 30 µm and used to cut metal foil. The laser beam can be redirected at a constant scanning speed of 0.5 m / s to 100 m / s using a galvanometer scanning mirror, which produces the desired line shape. A wide variety of cutting conditions can be used (e.g., when cutting metal foil prior to soldering and when the foil is far from the silicon wafer surface).

[0113] In some embodiments, a laser is used to cut a foil for a metal layer into narrow, fine grid lines in free space. In some embodiments, a 100 W fiber laser can be used in pulse mode, with a repetition rate set to 250 kHz and a pulse duration set to 200 ns. The laser beam can be redirected at the front surface of the metal foil at a speed of ≥ 1 m / s using a galvanometer scanning mirror. In some embodiments, fine lines 100 µm wide can be formed by splitting the laser-cut lines by 150 µm. The laser cutting process may result in material being ejected in a solid, liquid, or plasma phase, or a combination thereof. Laser cutting may result in material accumulation in both the upward (away from the substrate) and downward (towards the substrate) directions. This results in out-of-plane material accumulation along the cut lines, which can depend on laser processing settings such as laser power, repetition rate, pulse duration, scanning speed, wavelength, spot size, foil thickness, or foil material. Burrs are defined as material that remains and accumulates above the metal foil during the cutting process. When cutting in free space, without underlying substrate material, material from the coated base metal also accumulates at the rear surface of the metal layer. This accumulation on the back surface is called slag. The average burr height is the average height of the burr from the plane of the coated metal front surface. The average slag height is the average height of the slag from the plane of the back surface of the metal layer. Burrs are also characterized by their roughness, which is quantified by the average burr roughness (burr Ra). Burr Ra is the arithmetic mean of the absolute values ​​of the burr profile deviations from the average burr height. Slag is also characterized by its roughness, which is quantified by the average slag roughness (slag Ra). Laser cutting can also produce in-plane edge roughness along the cutting line path in a plane parallel to the substrate plane. In-plane edge roughness is quantified by the average in-plane roughness (in-plane Ra).

[0114] Confocal microscopy (e.g., 3D surface profilometers, Keyence's VK-X3000 series) can be used to measure properties of laser-cut lines, including in-plane edge roughness, average burr height, burr roughness, average slag height, and slag roughness. A confocal microscope can be positioned in a confocal configuration around a region of interest (ROI), where a laser beam scans the surface of the object within the ROI, thereby rendering a quantitative 3D representation of the cut with nanometer-level height accuracy in the vertical direction and micrometer-level resolution in the horizontal plane. Average burr height and roughness can be calculated from height profile data obtained on the incident side of the metal layer using confocal microscopy. In-plane edge roughness can be calculated from an in-plane frontal image of the cut line using image processing and edge detection. Burr Ra can be calculated from the edge line profile extracted from image processing.

[0115] Burrs, slag, and edge roughness can be controlled by reducing the laser pulse duration (e.g., from nanosecond to picosecond or femtosecond lasers), reducing the laser spot size, and other laser processing parameters (e.g., repetition rate, pulse mode, galvanometer scanning speed), as well as by changing the thickness and material of the metal foil. Now refer to... Figure 9A The images shown are top-view confocal microscopy images (20x objectives, all at the same magnification) of a metal layer conforming to some embodiments of this disclosure, where two horizontal laser cuts were performed using nanosecond (900, top of metal layer, 910, bottom of metal layer), picosecond (920, top of metal layer, 930, bottom of metal layer), and femtosecond (940, top of metal layer, 950, bottom of metal layer) laser pulses with a duration interval of 75 µm. The top of the metal layer refers to the surface of the metal layer facing the laser beam. Burrs 960 and slag 970 are visible at the edges of the cut lines. The in-plane edge roughness of the nanosecond laser cut obtained from 900 is approximately 40 µm. The picosecond laser cut 920 has approximately 30 µm, while the femtosecond laser cut 920 has approximately 20 µm. The average burr height is approximately 20 µm for the nanosecond laser, approximately 15 µm for the picosecond laser, and approximately 15 µm for the femtosecond laser. The burr roughness of nanosecond lasers is approximately 6 µm Ra, picosecond lasers are approximately 4 µm Ra, and femtosecond lasers are approximately 3 µm Ra. The average height of scum is approximately 7 µm for nanosecond lasers, approximately 5 µm for picosecond lasers, and approximately 5 µm for femtosecond lasers. The scum roughness is approximately 4 µm Ra for nanosecond lasers, approximately 3 µm Ra for picosecond lasers, and approximately 2.5 µm Ra for femtosecond lasers. It should be noted that the average height and roughness of burrs and scum can be further reduced by changing laser parameters (pulse duration, repetition rate, wavelength, scanning speed) and optical configuration (focal size, beam shape).

[0116] Now for reference Figure 9B This is a top-view confocal microscope image (50x magnification) of a 6 μm copper foil cut with a pulsed nanosecond laser according to some embodiments of this disclosure. Burrs 970 are clearly visible at the edge of the copper foil, with a maximum height of approximately 5.5 µm, and... Figure 9C The color z-scale plot further illustrates this. Nanosecond lasers cut through partially molten material, which is... Figure 9BAs can be seen in the image. In-plane edge roughness can be measured in any Keyence software and calculated by binarizing the image so that pixels containing copper are one color and pixels not containing copper are another. This binarization can be performed in software such as ImageJ. The profile of the cut edge can then be found using a traveling block algorithm, which is implemented in many packages, including the scikit-image Python package. This profile can be fitted to a line, and the displacement of this profile relative to the line can be used to calculate roughness values, such as Ra and Rz. Using this method, the Ra of the cut line is calculated to be 1 µm. It should be noted that the foil is relatively flat (< 2 µm curved). This appears fundamentally different from screen-printed silver wire, solder wire, and electroplated copper wire, which can have trapezoidal and / or circular height profiles.

[0117] Now for reference Figure 10A This is a schematic cross-section of a laser-cut metal foil 1000 for a metal layer conforming to some embodiments of the present disclosure; burrs 1001, dross 1002, a front surface 1003 of the metal foil; and a rear surface 1004 of the metal foil. In some embodiments, the burrs have an average height 1005 and a roughness 1006, and the dross has an average height 1007 and a roughness 1008. Reference now is made to... Figure 10B This is a schematic top view of the in-plane edges of a laser-cut metal foil 1010 and cutting lines 1011 for a metal layer, conforming to some embodiments of this disclosure. In some embodiments, the metal layer has an in-plane edge roughness greater than 1 µm, greater than 2 µm, greater than 5 µm, greater than 10 µm, greater than 20 µm, or greater than 30 µm. In some embodiments, the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. In some embodiments, the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. In some embodiments, the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. In some embodiments, the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. In some embodiments, the metal layer has a scum roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. Laser cutting after foil welding and subsequent metal wire morphology

[0118] In some embodiments, the metal foil can be brought into contact with the solar cell after the metal layers of the metal foil have been soldered to form a conductive multilayer stack or conductive multilayer lines. Laser power of a few milliwatts can damage the passivation layer on the solar cell. The foil should be carefully cut to form the desired metallization pattern. Galvanometer scanners are relatively inexpensive and can move at speeds >50 m / s. The laser beam parameters can be tuned to thin areas on the foil, rather than cutting through completely. This can be done in one pass or by multiple consecutive laser passes. If the laser-irradiated area is thin enough and sufficiently damaged, it can be removed with very little force; this is called a “kissing cut.” The solder joint is relatively robust, and the kissing cut can be aided by holding the metal lines in place as the foil is lifted above the wafer after the kissing cut. Kissing cuts can be used to prevent damage to the passivation layer after the conductive multilayer stack or conductive multilayer lines have been formed.

[0119] If laser cutting is performed before bonding the metal layer to the silver contact layer (or silver contact pads), a dross height exceeding the thickness of the silver sublayer can hinder good contact between the metal layer and the silver contact layer (or silver contact pads) and negatively impact the bonding. The average dross height and average roughness can be measured using the same measurements used to calculate the burr morphology characteristics on the back side (e.g., the side facing away from the incident laser) of a metal foil coated after laser cutting. Minimizing the average dross height and roughness may be desirable to improve bonding. In some embodiments, picosecond and nanosecond lasers can be used to reduce the average dross height and roughness. It should also be noted that laser-cut CMS layers have a unique morphology different from screen-printed and electroplated metallized layers, which typically appear trapezoidal when viewed in cross-section. Screen-printed and electroplated metallized layers do not have burrs on their edges. Screen-printed and electroplated metallization layers also exhibit relatively low in-plane line roughness, considered to be less than 10 µm, less than 5 µm, or less than 2 µm, depending on the paste rheology and printing / electroplating techniques. Laser-cut metallization layers of conductive multilayer stacks and conductive multilayer lines can have edges containing both out-of-plane material buildup (e.g., burrs) and in-plane roughness, distinguishing laser-cut lines from screen-printed and electroplated lines. Silicon solar cell manufacturing

[0120] Methods for manufacturing PN junction silicon solar cells are known in the art. “Solar Cells and Modules,” edited by Shah and Arvind, Springer International Publishing, 2020, which is incorporated herein by reference in its entirety, provides process flows for manufacturing different types of solar cells, including PERC, TOPCon, HJT, and IBC. In some embodiments, the method for manufacturing a solar cell includes the steps of: providing a silicon wafer substrate, texturing, dopant diffusion, etching, polishing, and depositing passivation layers on the front and back surfaces. In some embodiments, the silicon wafer substrate is monocrystalline and is n-type or p-type doped. In some embodiments, the substrate is a monocrystalline n-type silicon wafer with a p-type emitter.

[0121] A metallization layer can be formed by depositing silver metallization (and optionally aluminum) paste onto at least one surface of a solar cell, followed by drying and co-firing. Different metallization pastes are used to form fine mesh lines, connecting busbars, and pads. Methods such as screen printing, gravure printing, spray deposition, seam coating, transfer printing, 3D printing, and / or inkjet printing can be used to apply various layers. As a non-limiting example, Maxwell and AMAT screen printers can be used to deposit silver paste to form silver contact pads and busbars. In some embodiments, the solar cell has at least one passivation layer covering at least a portion of the back surface of the silicon wafer. Drying the various layers of the solar cell can be performed in a belt furnace at temperatures ranging from 150°C to 300°C for 30 seconds to 15 minutes. In some embodiments, a Despatch CDF 7210 belt furnace can be used to co-fire silicon solar cells comprising conductive multilayer stacks or conductive multilayer lines as described herein. In some embodiments, co-firing can be performed using rapid heating techniques, involving heating to temperatures greater than 760°C in air for 0.5 to 3 seconds, a common temperature profile for aluminum-backed surface-field silicon solar cells. The wafer's temperature profile is typically calibrated using a DataPaq® system with thermocouples attached to the bare wafer. For symmetric solar cells, such as PERC and TOPCon, metallization layers are applied to both the front and back sides. For asymmetric solar cells, such as IBC, metallization is applied only to the back side.

[0122] In some embodiments, a solar cell can be manufactured to form Figure 3 The silver contact pad 320 shown. After co-firing, it can be... Figure 3The solar cell shown is placed in a screen printing tool, and solder paste can be printed on top of the silver contact pads 320, and optionally dried or cured. A metal foil (e.g., copper foil) can then be placed on the silicon cell, where hot pressing at 280°C for one second is applied to solder the foil to the silver contact pads of the solar cell, followed by cutting the desired continuous fine grid line shape using a nanosecond pulsed laser. Now refer to... Figure 11 This is a schematic diagram of a silicon solar cell 1100 (e.g., a symmetrical solar cell) conforming to some embodiments of the present disclosure. The silicon solar cell includes fine grid lines 1120, busbars 1140, and pads 1130 on a silicon substrate 1110. The fine grid lines are conductive multilayer lines comprising a conductive multilayer stack as described above. It should be understood that the silicon solar cell 1100 may include at least one passivation layer on the silicon substrate 1110 as described above. In some embodiments, the metal layer of the fine grid lines 1120 may have a width of less than 500 µm, 450 µm, 400 µm, 350 µm, 300 µm, 250 µm, 200 µm, 150 µm, 125 µm, 100 µm, 75 µm, 60 µm, 50 µm, 40 µm, or 30 µm. In some embodiments, the metal layer of the fine grid lines 1120 may have a width ranging from 30 µm to 500 µm, from 30 µm to 450 µm, from 30 µm to 400 µm, from 30 µm to 350 µm, from 30 µm to 300 µm, from 30 µm to 250 µm, from 30 µm to 200 µm, from 30 µm to 150 µm, from 40 µm to 125 µm, from 40 µm to 100 µm, from 50 µm to 100 µm, or from 50 µm to 75 µm. In some embodiments, the metal layer of the fine grid lines 1120 may have a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. In some embodiments, the silver used for the fine grid lines 1120 may be more than that used for continuous fine grid lines (e.g., Figure 1 The finer grid lines (120) are reduced by 25%, 50%, 60%, 75%, 90%, or 95%. It should be understood that... Figure 11 The schematic diagram shown can also be applied to a silicon solar cell 1110 including fine grid lines 1120, which are conductive multilayer lines including a conductive multilayer stack as described above, the conductive multilayer stack not including a glass paste sublayer.

[0123] Some embodiments of this disclosure provide fine grid lines that include at least one conductive multilayer stack (e.g., a conductive multilayer line) to reduce silver consumption in a solar cell. In some embodiments, the fine grid line including at least one conductive multilayer stack is a back surface fine grid line on a TOPCon cell, wherein the back surface fine grid line has a width ranging from 30 µm to 500 µm, from 30 µm to 450 µm, from 30 µm to 400 µm, from 30 µm to 350 µm, from 30 µm to 300 µm, from 30 µm to 250 µm, from 30 µm to 200 µm, from 30 µm to 150 µm, from 40 µm to 125 µm, from 40 µm to 100 µm, from 50 µm to 100 µm, or from 50 µm to 75 µm. In some embodiments, at least one conductive multilayer stack of fine mesh lines on the back surface comprises a 6 µm thick copper foil, a solderable layer comprising a 20 µm thick SAC305 layer, and silver contact pads comprising a 5 µm silver sublayer and a glass paste sublayer of less than 100 nm. In some embodiments, the solar cell may comprise a silicon wafer substrate having at least one passivation layer thereon, wherein the at least one passivation layer comprises a doped poly-Si layer. Fine mesh lines can be applied to multiple cells multiple times using a single metal foil. This can significantly reduce the cost of using coated aluminum or copper foil and the amount of metal foil required per production line per day.

[0124] It should be noted that conventional front-surface fine grid lines are typically less than 50 µm wide. Back-surface fine grid lines wider than 50 µm, including at least one conductive multilayer stack, do not impede the front efficiency of the solar cell, as the solar cell efficiency can be measured by measuring the light impact on the front surface. Front-surface fine grid lines can have a width of 50 µm or greater. If the front-surface fine grid lines have a width greater than 50 µm, the number of grid lines can be reduced to compensate for any front-surface shading issues.

[0125] In some embodiments, the solar cell is manufactured such that at least one fine grid line is formed by a first plurality of silver contact pads 420 and is composed of... Figure 4 The second plurality of silver contact pads 440 shown form at least one busbar. After co-firing, it can be... Figure 4 The solar cell shown is placed in a screen printing tool, and solder paste can be printed on top of a first plurality of silver contact pads 420 and a second plurality of silver contact pads 440, and optionally dried or cured. A metal foil can then be placed on the silicon cell, wherein hot pressing is applied at 350°C for one second to solder the foil to the solar cell, followed by the use of a nanosecond pulsed laser to cut at least one desired continuous fine grid line and a desired continuous busbar. Now refer to Figure 12 This is a schematic diagram of a silicon solar cell 1200 (e.g., a symmetrical solar cell) conforming to some embodiments of the present disclosure. The silicon solar cell includes fine grid lines 1220, busbars 1240, and pads 1230 on a silicon substrate 1210. The fine grid lines are conductive multilayer lines comprising at least one conductive multilayer stack, as described above. The busbars are conductive multilayer lines comprising at least one conductive multilayer stack, as described above. It should be understood that the silicon solar cell 1200 may include at least one passivation layer on the silicon substrate 1210 as described above. In some embodiments, the metal layer of the fine grid lines 1220 may have a width ranging from 30 µm to 500 µm, from 30 µm to 450 µm, from 30 µm to 400 µm, from 30 µm to 350 µm, from 30 µm to 300 µm, from 30 µm to 250 µm, from 30 µm to 200 µm, from 30 µm to 150 µm, from 40 µm to 125 µm, from 40 µm to 100 µm, from 50 µm to 100 µm, or from 50 µm to 75 µm. In some embodiments, the metal layer of the fine grid lines 1220 may have a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. In some embodiments, the silver contained in the fine grid line 1220 may be greater than that contained in continuous fine grid lines (e.g., Figure 1 The fine grid lines 120 in the busbar 1240 are less than 25%, less than 50%, less than 60%, less than 75%, less than 90%, or less than 95%. In some embodiments, the metal layer of the busbar 1240 may have a width of less than 500 µm, less than 450 µm, less than 400 µm, less than 350 µm, less than 300 µm, less than 250 µm, less than 200 µm, less than 150 µm, or less than 100 µm. In some embodiments, the metal layer of the busbar 1240 may have a width of 4 µm to 500 µm, 4 µm to 450 µm, 4 µm to 400 µm, 4 µm to 350 µm, 4 µm to 300 µm, 4 µm to 250 µm, 4 µm to 200 µm, 4 µm to 150 µm, 4 µm to 100 µm, 4 µm to 500 µm, 4 µm to 50 µm, 4 µm to 25 µm, 4 µm to 10 µm, or 4 µm to 6 µm. In some embodiments, the metal layer of the busbar 1240 may have a thickness of 4 µm to 100 µm, 4 µm to 50 µm, 4 µm to 25 µm, 4 µm to 10 µm, or 4 µm to 6 µm. In some embodiments, the silver contained in the busbar 1240 may be greater than that in a continuous busbar (e.g., Figure 1The busbar 1240 may be 25%, 50%, 60%, 75%, 90%, or 95% less than the fine grid line 1220. In some embodiments, the busbar 1240 may be perpendicular to the fine grid line 1220, and if the fine grid line 1220 and the busbar 1240 are cut from the same foil simultaneously, the foil may not be reusable multiple times. In some embodiments, it is preferable to separate the fine grid line and busbar formation and cutting steps into separate processes (e.g., after the fine grid line 1220 is formed, the wafer is rotated 90 degrees, solder paste is applied, soldering is performed, and then laser cutting is performed in the same direction as the fine grid line 1220) to improve foil utilization. Conventional solar modules and interconnected cells via CMS layer

[0126] A solar module may include a front panel, a front encapsulant layer, silicon solar cells, cell interconnects, a rear encapsulant layer, and a backsheet. As is known to those skilled in the art of solar modules, many possible module designs exist in which such solar cells can be used. A first solar cell in the solar module can be connected to a second solar cell in the solar module using interconnects. In some embodiments, the interconnects may include busbars connected to pads on the first solar cell and pads on the second solar cell. Reference now... Figure 13 This is a schematic diagram of a solar cell module 1300 conforming to some embodiments of the present disclosure. The solar cell module includes symmetrical silicon solar cells 1310 and interconnects, the interconnects including bus strips 1320 electrically connected to pads of the solar cells 1310 and bus strips 1330 electrically in contact with the bus strips 1320. Typically, 60 or 72 solar cells are combined in a commercial module, but more or fewer solar cells may be combined, depending on the application (e.g., consumer electronics, residential, commercial, utility, etc.). The number of solar cells 1310 in the solar cell module 1300 is not intended to be limited. The length of the solar cells can vary from 125 mm to 500 mm, or any range contained therein, and can also be cut in half, third, quarter, or other fractions to reduce current density and increase operating voltage when connected in series. It should be understood that the symmetrical solar cells 1310 may include fine grid lines as conductive multilayer lines (e.g., Figure 12 The fine mesh lines 1220 in the middle) and / or as busbars for conductive multilayer lines (e.g., Figure 12 (Busbar 1240 in the middle). It should be understood that the symmetrical solar cell 1310 may include at least one passivation layer thereon as described above.

[0127] With a diameter of 280 micrometers and Sn 60 Pb 40Coated copper busbars are typically bonded to pads on conventional PERC and TOPCon solar cells to extract charge. Further reductions in the diameter of these busbars are being investigated to allow for wider use across cells. "Microfilament" techniques for soldering to pads may be promising, but they present challenges associated with soldering busbars to pads compared to embodiments of this disclosure (e.g., foil interconnects). When using embodiments of this disclosure as interconnects (e.g., foil interconnects), numerous segmented lines can be attached across the solar cell while applying uniform tension, as these lines can be supported on more than just both sides. For conventional busbar interconnect schemes, segmenting the busbars along their direction is challenging. A perpendicular line pattern is typically required to efficiently extract charge from the cell. When placed perpendicular to other busbars, unsegmentable busbars require overlapping points. This can lead to increased stress points for cell breakage. It should be noted that busbars have bends that can apply pressure to the solar cell, which can increase cracking and are generally more difficult to solder than flat surfaces. In contrast, for example, by using metal foil interconnects, it has been found that constructing interconnect schemes at various angles on the same plane is fairly simple. The foil is flat, which minimizes stress on the solar cell, and its surface is easier to solder compared to curved lines. Finally, it is also easier to align a single foil with an accuracy of less than 20 micrometers compared to more than 100 individual bus ribbons. Due to reduced process complexity and better wafer yield, foil-based strategies may outperform conventional bus ribbon interconnect schemes.

[0128] CMS-containing solar cells with pads (e.g., Figure 11 and Figure 12Busbars can be used as interconnects, and conventional module cascading / bridging devices can be used to interconnect solar cells. In some embodiments of this disclosure, solar cells comprising fine grid lines and / or busbars can be incorporated into a solar module, the fine grid lines being conductive multilayer lines comprising conductive multilayer stacks, and the busbars being conductive multilayer lines comprising conductive multilayer stacks. Interconnects can be used to electrically connect solar cells to other components of the module, such as bypass diodes (not shown) and junction boxes (not shown). In some embodiments, interconnects may include busbars 1320 and one or more bus strips 1330. Solar cells in a solar module can be electrically interconnected using busbars 1320 as interconnects. In some embodiments of the disclosure herein, the busbar is a metal core with a solder coating. The metal core may comprise copper, aluminum, carbon, tin, iron, alloys thereof, composites thereof, or combinations thereof. In some embodiments, the busbar may have a diameter of 80 µm to 1000 µm, 100 µm to 300 µm, 120 µm to 200 µm, or any range thereof. The solder coating can have a thickness of 0.5 µm to 100 µm, 10 µm to 50 µm, or any range thereof. The solder coating can contain tin, lead, silver, bismuth, copper, zinc, antimony, manganese, indium, their alloys, their compounds, or combinations thereof. In some embodiments, the busbar is a copper strip with a diameter of 150 µm and coated with a 20 µm thick tin:lead (60:40 wt%) solder coating. The length of the busbar can be determined by application, design, and substrate dimensions. The module typically includes bypass diodes, junction boxes, and support frames that do not directly contact the solar cells. The bypass diodes and junction boxes can also be considered part of the interconnects.

[0129] The front panel provides mechanical support for the solar module and has the desired optical transmission characteristics for a portion of the solar spectrum that the solar cell is designed to absorb. The solar module is positioned such that the front panel faces the light source, such as sunlight. The front panel is typically made of soda-lime glass with a low iron content. The front and rear encapsulant layers protect the solar cell from electrical, chemical, physical, and environmental stressors during operation. The encapsulant is typically in the form of a polymer sheet. Examples of materials that can be used as encapsulants include, but are not limited to, ethylene vinyl acetate (EVA), polyethylene-co-methacrylic acid (ionomer), polyvinyl butyral (PVB), thermoplastic urethane (TPU), poly-α-olefin, polydimethylsiloxane (PDMS), other polysiloxanes (i.e., silicones), and combinations thereof. The back panel provides protection for the solar cell from the back and may or may not be optically transparent. The solar module is positioned such that the back panel faces away from the light source. The back panel can be a multilayer structure made of three polymer films. DuPont™ Tedlar® polyvinyl fluoride (PVF) film is typically used in the back panel. Fluoropolymers and polyethylene terephthalate (PET) can also be used in backsheets. Bifacial modules typically use transparent backsheets to increase light collection on the back of the module. Glass sheets can also be used as backsheets, which can help provide structural support for the solar module. Transparent Tedlar can also be used as a polymer transparent backsheet. Support frames (not shown) can also be used to improve structural support; support frames are typically made of aluminum.

[0130] In some embodiments of this disclosure, a method for forming a solar cell module is provided. Busbars can be soldered to pads on the front and / or rear surfaces of a first solar cell. Subsequent solar cells can be placed adjacent to the first solar cell, and busbars contacting the front and / or rear surfaces of the first solar cell can be soldered to pads on the rear and / or front surfaces of adjacent solar cells. The resulting structure of busbars, the first solar cell, and the second solar cell can be referred to as a "cell string". Busbars can be soldered manually with a soldering iron or using an automatic wiring machine or threading machine (which typically heats the bottom and top of the substrate with near-infrared heating). Multiple cell strings can be arranged on a front encapsulation layer already applied to a front panel. These multiple cell strings can be connected to each other by soldering busbars to bus strips to create circuitry. The bus strips can be wider than the busbars used in the cell strings. After the circuitry between all cell strings is completed, a back encapsulation material can be applied to the back of the connected cell strings, and a backplate can be placed on the back encapsulation material. The assembly is then sealed using a vacuum lamination process and heated (typically below 200°C) to polymerize the encapsulation material. A frame is typically attached around the front panel to provide structural support. Finally, the junction box connects to the battery interconnects and is attached to the solar module. Bypass diodes may be located in the junction box or attached inside the module during battery interconnect fabrication.

[0131] Figure 3 and Figure 4 Both show silver pads (e.g., silver pad 330 and silver pad 430). Therefore, Figure 3 and Figure 4 The solar cells shown can be placed in conventional busbar bonding equipment during solar module manufacturing. For conventional solar cells, high adhesion between the pads and the silicon substrate is likely desired after the busbars are soldered to the pads. Poor adhesion at any interface of the busbar / pad joint can cause the busbars to detach from the cell (e.g., during thermal cycling) and reduce the power conversion efficiency of the solar module. Soldering the busbars to the pads on the solar cells is a challenging process that can lead to poor attachment (e.g., cold joint failure) or cell cracking, both of which can be observed on the solar module using electroluminescence measurements before completion. Poorly soldered busbars or damaged solar cells are typically removed and replaced by hand, which reduces solar cell production yield and increases maintenance costs. Therefore, it may be desirable to develop alternative solar cell interconnects or interconnect processes that do not require heating the entire wafer and high-precision busbar placement, and use more robust techniques than soldering the busbars to the pads.

[0132] Now for reference Figure 14This is a schematic diagram of a silicon solar cell 1400 conforming to some embodiments of the present disclosure, the silicon solar cell including a silicon substrate 1410, a first plurality of silver contact pads 1440, and a second plurality of silver contact pads 1450. It should be understood that the silicon solar cell 1400 may include at least one passivation layer on the silicon substrate 1410 as described above. The first plurality of silver contacts 1440 may be as described above (e.g., Figure 3 Silver contact pads 320 or Figure 4 The first plurality of silver contact pads 420 in the middle). The second plurality of silver contact pads 1450 can be as described above (e.g., Figure 4 (The second plurality of silver contact pads 440 in the cell). In this cell schematic, the pads have been completely removed, and the silicon solar cell 1400 can be interconnected with other solar cells in the module using different methods that do not require busbars, as described below.

[0133] In some embodiments, a solar cell can be manufactured to include, for example, Figure 14 The silver contact pad 1440 is shown. The solar cell 1400 does not have pads and can be connected to a second solar cell without the use of conventional interconnect devices. After co-firing, it can be... Figure 14 The solar cell 1400 shown is placed in a screen printing tool, and solder paste can be printed onto the first plurality of silver contact pads 1440 and the second plurality of silver contact pads 1450. A metal foil can then be placed on the solar cell 1400, wherein a thermo-pressurization is applied at 350°C for one second to solder the foil to the solar cell 1400, followed by cutting using a nanosecond pulsed laser. Figure 15 The desired foil shape is shown. Figure 15 This is a schematic diagram of a silicon solar cell 1500 conforming to some embodiments of the present disclosure. The silicon solar cell includes busbars 1540 and fine grid lines 1520 on a silicon substrate 1510. The busbars are conductive multilayer lines comprising at least one conductive multilayer stack, as described above, and the fine grid lines are conductive multilayer lines comprising at least one conductive multilayer stack. It should be understood that the silicon solar cell 1500 may include at least one passivation layer on the silicon substrate 1510 as described above. Figure 15 In this configuration, there are no pads, and interconnect pads 1530 can be used to electrically connect busbars 1540. In some embodiments, to connect one silicon solar cell to another, interconnect pads 1530 can be placed on one end of the solar cell, and another interconnect pad can be present on the opposite end of the solar cell. Figure 15 (Not shown in the image).

[0134] In some embodiments, the metal layer of the fine grid lines 1520 may have a width of less than 500 µm, 450 µm, 400 µm, 350 µm, 300 µm, 250 µm, 200 µm, 150 µm, 125 µm, 100 µm, 75 µm, 60 µm, 50 µm, 40 µm, or 30 µm. In some embodiments, the metal layer of the fine grid lines 1520 may have a width ranging from 30 µm to 500 µm, from 30 µm to 450 µm, from 30 µm to 400 µm, from 30 µm to 350 µm, from 30 µm to 300 µm, from 30 µm to 250 µm, from 30 µm to 200 µm, from 30 µm to 150 µm, from 40 µm to 125 µm, from 40 µm to 100 µm, from 50 µm to 100 µm, or from 50 µm to 75 µm. In some embodiments, the metal layer of the fine grid lines 1520 may have a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. In some embodiments, the fine grid line 1520 includes silver ratio continuous fine grid lines (e.g., Figure 1 The fine grid lines 120 in the busbar 1540 are less than 25%, less than 50%, less than 60%, less than 75%, less than 90%, or less than 95%. In some embodiments, the metal layer of the busbar 1540 may have a width of less than 500 µm, less than 450 µm, less than 400 µm, less than 350 µm, less than 300 µm, less than 250 µm, less than 200 µm, less than 150 µm, or less than 100 µm. In some embodiments, the metal layer of the busbar 1540 may have a width of 4 µm to 500 µm, 4 µm to 450 µm, 4 µm to 400 µm, 4 µm to 350 µm, 4 µm to 300 µm, 4 µm to 250 µm, 4 µm to 200 µm, 4 µm to 150 µm, 4 µm to 100 µm, 4 µm to 500 µm, 4 µm to 50 µm, 4 µm to 25 µm, 4 µm to 10 µm, or 4 µm to 6 µm. In some embodiments, the metal layer of the busbar 1540 may have a thickness of 4 µm to 100 µm, 4 µm to 50 µm, 4 µm to 25 µm, 4 µm to 10 µm, or 4 µm to 6 µm. In some embodiments, the silver contained in the busbar 1540 may be greater than that in conventional busbars (e.g., Figure 1 The busbar 140 is 25% less, 50% less, 60% less, 75% less, 90% less, or 95% less.

[0135] Interconnect pads 1530 may be connected to busbars 1540 and / or fine mesh lines 1520 at multiple points. In some embodiments, interconnect pads 1530 may be copper foil or aluminum foil. In some embodiments, interconnect pads 1530 may be soldered to the metal layers of busbars 1540 and / or fine mesh lines 1520. In some embodiments, interconnect pads 1530 may be conductive multilayer lines comprising at least two conductive multilayer stacks, as described above. Figure 15 This demonstrates that silver consumption can be significantly reduced. Compared to solar cells using conventional fine grid lines and / or conventional busbars and pads, low foil utilization can be supported by reducing silver consumption by at least 30 wt.%, at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 80 wt.%, or at least 90 wt.%.

[0136] Copper and aluminum foils can be ultrasonically welded or laser-welded to the same metal (e.g., copper / copper and aluminum / aluminum joints). These techniques enable weldless interconnects where the metal foil can extend beyond the edge of the solar cell. This paper describes methods for manufacturing and using copper or coated aluminum foil that can be ultrasonically welded to metal layers in conductive multilayer stacks or conductive multilayer lines to achieve novel solar cell interconnect schemes for symmetrical and asymmetrical solar cell modules.

[0137] In some embodiments, the interconnects in the solar module include interconnect pads on a first solar cell that are connected to interconnect pads on a second solar cell. Symmetrical solar cells (e.g., including fine grid lines as conductive multilayer lines as described above and busbars as conductive multilayer lines as described above, but without pads) are also included. Figure 15 The solar cell may further include interconnect pads 1530 made of a base metal that extend beyond the edge of the solar cell. Referring now to FIG16A, which is a schematic diagram of a silicon solar cell 1600 conforming to some embodiments of the present disclosure, the silicon solar cell includes fine grid lines 1620 and busbars 1640 on a silicon substrate 1610, the fine grid lines being conductive multilayer lines including at least one conductive multilayer stack as described above, and the busbars being conductive multilayer lines including at least one conductive multilayer stack as described above. It should be understood that the silicon solar cell 1600 may include at least one passivation layer on the silicon substrate 1610 as described above. As shown in FIG16A, the interconnect pads 1630 extend beyond the edge of the silicon substrate 1610. In some embodiments, symmetrical solar cells may be connected together using interconnect pads, such as… Figure 16B As shown. In some embodiments, the first silicon solar cell of FIG16A can be connected to the second silicon solar cell of FIG16A via interconnect pad 1630. Figure 16BAn interconnect pad 1630 on one end of the rear surface of a solar cell conforming to some embodiments of the present disclosure is shown, the interconnect pad contacting another interconnect pad 1630 on the front surface of a second solar cell. In some embodiments, the interconnect pads 1630 may be ultrasonically soldered together. In some embodiments, the interconnect pads 1630 may be laser soldered together. In some embodiments, no solder material is required to connect the interconnect pads 1630. Therefore, some embodiments of the present disclosure (e.g., as shown in the example) Figure 16B The embodiments shown in the figure can eliminate lead (Pb) from the solar cell module because busbars are conventionally made using tin (Sn) and (Pb) solder.

[0138] Now for reference Figure 17 This is a schematic diagram of a solar cell module 1700 including symmetrical solar cells with interconnecting pads, which conforms to some embodiments of the present disclosure. Figure 17 This demonstrates the ability to stack solar cells in series without the need for busbars. Figure 17 A bus strip 1720 is also shown, which electrically connects two interconnect pads from adjacent tandemly stacked solar cell stacks. A weld joint 1710 is formed by welding the interconnect pads. The weld joint 1710 can bond the front of one solar cell to the rear of another (adjacent) solar cell. It should be understood that the solar cells in the solar cell module 1700 may include at least one passivation layer thereon as described above. It should be understood that the solar cells in the solar cell module 1700 may include fine grid lines, which are conductive multilayer lines including at least one conductive multilayer stack as described above (e.g., fine grid line 1620 in FIG. 16A). It should be understood that the solar cells in the solar cell module 1700 may include busbars, which are conductive multilayer lines including at least one conductive multilayer stack as described above (e.g., busbar 1640 in FIG. 16A).

[0139] As shown in Figure 16A, Figure 16B and Figure 17Similar techniques described herein can be used for asymmetric cells. Referring now to FIG18A, which is a schematic diagram of an asymmetric silicon solar cell 1800 conforming to some embodiments of the present disclosure, the asymmetric silicon solar cell includes fine grid lines 1830 and interconnect pads 1820 and 1840 on a silicon substrate 1810, the fine grid lines being conductive multilayer lines comprising at least two conductive multilayer stacks as described above. It should be understood that the asymmetric silicon solar cell 1800 may include at least one passivation layer on the silicon substrate 1810 as described above. FIG18A also shows aluminum fine grid lines 1860 connected to silver pads 1850, which are connected to interconnect pads 1840. The aluminum fine grid lines 1860 may be on at least one first portion of the silicon wafer 1820, and the fine grid lines 1830 may be on at least one second portion of the silicon wafer 1820. In some embodiments, the at least one first portion of the silicon wafer 1820 is a doped region, and the at least one second portion of the silicon wafer 1820 is an oppositely doped region. It should be understood that FIG18A is not intended to limit the design of asymmetric solar cells. As a non-restrictive example, and as stated above in Figure 5 and Figure 6 As described herein, the aluminum fine mesh line 1860 and silver pad 1850 can be replaced by a fine mesh line, which is a conductive multilayer line comprising at least two conductive multilayer stacks as described above.

[0140] like Figure 18A and Figure 18B As shown, interconnect pads 1820 and 1840 may extend beyond the edge of silicon substrate 1810. In some embodiments, interconnect pads 1820 and 1840 may be metal foils fused to fine mesh lines 1830 and silver pads 1850, respectively. In some embodiments, interconnect pads 1820 and 1840 may be conductive multilayer lines comprising at least two conductive multilayer stacks as described above. For example, interconnect pad 1820 may include pads soldered to multiple silver contact pads (e.g., ...). Figure 6 The metal foil of the solderable layer on the second plurality of silver contact pads 620. In some embodiments, the asymmetric solar cell illustrated in FIG18A can be bonded together using interconnecting pads 1820 and 1840, as Figure 18B As shown. Figure 18B Interconnect pads 1820 on the rear surface of a first solar cell conforming to some embodiments of the present disclosure are shown, the interconnect pads being solderable to interconnect pads 1840 on the rear surface of a second solar cell.

[0141] Now for reference Figure 19 This is a schematic diagram of a solar cell module 1900 including asymmetric solar cells with interconnecting pads, which conforms to some embodiments of the present disclosure. Figure 19This demonstrates the ability to stack solar cells in series without the need for busbars. Figure 19 Busbar 1920 is also shown, which electrically connects two interconnect pads from adjacent series-stacked solar cell stacks. Welded joint 1910 can be formed by welding interconnect pads. Welded joint 1910 can join the front of one solar cell to the rear of another (adjacent) solar cell. In some embodiments, using welded joint 1910 to series-stack asymmetric solar cells may be advantageous because the asymmetric cells may not experience any excessive heat generated by applying conventional busbars and may remain flat after interconnection (e.g., may not experience significant bending). It should be understood that the asymmetric solar cells in solar cell module 1900 may include at least one passivation layer thereon as described above. It should be understood that the asymmetric solar cells in solar cell module 1900 may include fine grid lines, which are conductive multilayer lines (e.g., fine grid line 1830 in FIG. 18A) that include at least one conductive multilayer stack as described above.

[0142] In addition to the above, it has been found that bus ribbons can be easily soldered to the surface of solar cells excluding pads, which simplifies bus ribbon soldering using conventional module manufacturing equipment. As mentioned above, a common yield problem with conventional bus ribbon interconnect schemes using pads is the potential for cold joints when the bus ribbon and pad are misaligned or not fully soldered. It has been found that, in some embodiments, bus ribbons can be soldered to the metal layers (such as copper foil) of conductive multilayer stacks or conductive multilayer lines without using pads. Reference now... Figure 20 This is a cross-sectional schematic diagram of a conductive multilayer line 2000 that further includes a busbar 2050, in accordance with some embodiments of this disclosure. Figure 20 A copper metal layer 2030 is shown, having a solderable exposed surface 2033, and a bus ribbon 2050 comprising a metal core 2051 and a solder coating 2052, wherein the bus ribbon 2050 is soldered to the copper metal layer 2030. The conductive multilayer line 2000 can be fabricated as described above, the silicon substrate 2010 can be as described above, the bus ribbon 2050 can be as described above, and at least one passivation layer 2011 can be as described above. The bus ribbon 2050 can be placed on the conductive multilayer line 2000 by applying flux between the bus ribbon 2050 and the metal surface 2033, and then heat is applied to solder the bus ribbon 2050 to the copper metal layer 2030. It may be desirable for the solder coating 2052 to have a lower liquidus point than the solderable layer 2040 to prevent alteration of the underlying conductive multilayer line 2000 during soldering.

[0143] In some embodiments, the interconnects of a solar cell module (e.g., a solar cell module including symmetrical solar cells as described above) may include bus solder ribbons that contact a first fine grid line on a first solar cell and a second fine grid line on a second solar cell, wherein the first fine grid line is a conductive multilayer line as described above, the second fine grid line is a conductive multilayer line as described above, and wherein the interconnects further include bus strips that contact the bus solder ribbons.

[0144] Now for reference Figures 21A to 21C This is a top view image of a metallized solar cell conforming to some embodiments of the present disclosure. Figure 21A This is a top view image of a solar cell conforming to some embodiments of the present disclosure, showing a plurality of silver contact pads 2110 printed on the entire surface of the solar cell. In some embodiments, Figure 21A This can be the front surface of a solar cell. In some embodiments, Figure 21A This can be the back surface of a solar cell. Multiple silver contact pads 2110 can be as described above. Figure 21A In this embodiment, the silver contact pads among the plurality of silver contact pads 2110 have a diameter of approximately 150 micrometers. In some embodiments, a first silver contact pad among the plurality of silver contact pads 2110 may be separated from a second silver contact pad among the plurality of silver contact pads 2110 by a distance of 400 micrometers. Figure 21A In the process, the edge of the first silver contact pad among the multiple silver contact pads 2110 can be separated from the edge of the second silver contact pad among the multiple silver contact pads 2110 by a distance of approximately 400 micrometers. Figure 21A The busbar 2120 is further shown. The busbar may be a conductive multilayer wire as described above, or it may be made of standard materials known in the art.

[0145] Figure 21B Some embodiments conforming to this disclosure are as follows: Figure 21A The image shown is a top view of a solar cell, which comprises multiple conductive layers. Figure 21B Showing included Figure 21A A conductive multilayer line 2130 is formed by multiple silver contact pads 2110. Specifically, a solderable layer is applied to the multiple silver contact pads 2110 as described above, and a metal layer is applied to the solderable layer as described above. In some embodiments, the conductive multilayer line 2130 includes a copper metal layer. In some embodiments, the conductive multilayer line 2130 includes a copper foil metal layer. In some embodiments, the conductive multilayer line 2130 includes a metal layer having a width of 200 micrometers. Figure 21B In this case, the metal layer is a copper foil with a width of approximately 200 micrometers. For example... Figure 21BAs can be seen, the metal layer of each conductive multilayer line 2130 spans a row of silver contact pads (e.g., Figure 21A A row of multiple silver contact pads 2110 extends. Conductive multilayer lines 2130 can be connected to busbar 2120.

[0146] Figure 21C Is it like this? Figure 21B The image shows a top view of a solar cell. Figure 21C Busbars conforming to some embodiments of this disclosure are shown. Busbar 2140 is shown as contact conductive multilayer line 2130, as described above. Figure 21C This illustrates the bonding of bus solder ribbon 2140 to the copper metal layer of a conductive multilayer line 2130. In some embodiments, the bus solder ribbon 2140 is bonded to the copper metal layer of each conductive multilayer line 2130. Figure 21C In the middle, the busbar 2140 is a SnPb strip about 0.9 mm wide.

[0147] In some embodiments, the busbar 2140 may also be Figure 21C The interconnects of the solar cells and their extensions (e.g., Figure 21C (Top and bottom views of the image) to the adjacent solar cells in the solar module. In some embodiments, Figure 21C The rear surface of the solar cell is shown, and the busbar 2140 can extend to an adjacent solar cell, wherein the busbar 2140 contacts a pad on the front surface of the adjacent solar cell. In some embodiments, Figure 21C The rear surface of a solar cell having at least one passivation layer thereon as described above is shown, and adjacent solar cells may have at least one passivation layer thereon as described above. In some embodiments, busbar 2120 is for example... Figure 21C The solar cell shown may not be necessary because the busbar 2140 can contact each of the conductive multilayer wires in the conductive multilayer wires 2130. Therefore, the busbar 2120 may be optional for the solar cell, as... Figure 21C As shown. In some embodiments, the silver contact pads used to manufacture the conductive multilayer busbar (e.g., Figure 14 The second set of multiple silver contact pads (1450) can be optional because Figure 21C This suggests that busbars (made of standard materials or conductive multilayer wires) may not be needed to electrically connect the fine grid lines on solar cells.

[0148] In some embodiments, applying busbars to multiple conductive multilayer lines eliminates the need for pads and connects multiple solar cells in a solar module, eliminating busbars, increasing the yield of busbar contact with solar cells, and further reducing silver consumption in the solar cells. Busbars are typically bonded to pads, which may require 15 mg to 20 mg of silver per cell. Pads are typically > 2 mm wide to ensure the busbars can always be soldered to the solar cells. In conventional solar cells, pads are not directly connected to all fine mesh lines, and busbars are required to complete the connection. In some embodiments, if one or more busbars are connected to one or more conductive multilayer lines, busbars may not be necessary. Measuring the characteristics of the CMS layer on a solar cell

[0149] In some embodiments, the characteristics of conductive multilayer stacks on solar cells and structures including conductive multilayer stacks can be measured and evaluated.

[0150] Corrosion Resistance: Contact resistance between layers on a solar cell can affect series resistance and power conversion efficiency. For fine grid lines, busbars, and solder ribbon layers (with or without one or more conductive multilayer stacks), their contact resistance can be measured using transmission line measurements (TLMs), as described by Meier et al., “Cu Backside Busbar Tape: Eliminating Ag and Enabling Full Al Coverage in Crystalline Silicon SolarCells,” IEEE Photovoltaic Experts Meeting, June 15-19, 2015, New Orleans, Louisiana, which is incorporated herein by reference. Transmission line graphs exhibit linear behavior, where the slope represents the bulk resistivity of the underlying substrate or metal layer, and the y-intercept is twice the contact resistance between the contact layer and the underlying substrate (e.g., a silver contact layer / silicon wafer stack). The y-intercept depends on the contact area, adhesion, and individual layers. During damp heat testing (e.g., 85% relative humidity, 85°C, for 1000 to 2000 hours), layers may corrode, increasing contact resistance. Corrosion can be particularly problematic for metal / metal contacts, and increased contact resistance increases series resistance and reduces the module's fill factor. Those skilled in the art of solar cells can measure changes in contact resistance due to damp heat testing by performing a TLM on the conductive multilayer stack before and after damp heat testing. Increased contact resistance can be directly correlated with corrosion in the conductive multilayer stack. In some embodiments, the conductive multilayer stack is considered corrosion-stable if the contact resistance of the damp heat-treated sample increases by less than 5%, less than 10%, less than 15%, less than 20%, less than 25%, less than 50%, less than 100%, less than 200%, less than 400%, less than 500%, or less than 800% compared to the pretreated sample.

[0151] Layer thickness: Scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDX) (collectively, SEM / EDX) can be used to identify individual layers, measure average layer thickness, and thickness variations in structures with and without one or more conductive multilayer stacks. SEM / EDX as used herein was performed using a Zeiss Gemini Ultra-55 analytical field emission scanning electron microscope equipped with a Bruker XFlash® 6∣ 60 detector. Cross-sectional SEM images of the conductive multilayer stacks were prepared by ion milling. A thin epoxy layer was applied to the top of the co-fired multilayer stack and dried for at least 30 minutes. The sample was then transferred to a JEOL IB-03010CP ion mill and operated at 5 kV and 120 µA for 8 hours to remove 80 micrometers from the sample edges. The milled sample was stored in a nitrogen glove box prior to SEM / EDX. In addition to cross-sectional SEM, the Olympus LEXT OLS4000 3D laser measurement microscope and / or profilometer (such as Veeco Dektak150) can be used to accurately measure the film thickness and variations over the described area.

[0152] It will be apparent to those skilled in the art that suitable modifications and adaptations can be made to the structures, methods, and applications described herein without departing from the scope of any of its embodiments or aspects. The structures and methods provided are exemplary and not intended to limit the scope of the claimed embodiments. All the various embodiments, aspects, and options disclosed herein can be combined in all variations. The scope of the structures, methods, and applications described herein includes all actual or potential combinations of the embodiments, aspects, options, examples, and preferences herein. Unless otherwise expressly provided, all patents and publications referenced herein are incorporated herein by reference for their specific teachings as indicated.

[0153] Before describing exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following examples, and that other embodiments are possible and can be practiced or performed in various ways. The embodiments may be further described using the following terms: 1. A conductive multilayer stack, comprising: A metal layer comprising copper (Cu) or coated aluminum; A silver contact layer, the silver contact layer comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between and in contact with the metal layer and the silver contact layer; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of at least one passivation layer on the silicon substrate, or contacts a combination thereof. 2. The conductive multilayer stack as described in Clause 1, wherein the metal layer has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 3. The conductive multilayer stack as described in Clause 1 or 2, wherein the metal layer has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 4. The conductive multilayer stack as described in any one of clauses 1 to 3, wherein the substrate has a thickness ranging from 120 µm to 180 µm. 5. The conductive multilayer stack as described in any one of clauses 1 to 4, wherein the metal layer comprises, is composed of, or is substantially composed of Cu. 6. The conductive multilayer stack as described in any one of clauses 1 to 5, wherein the metal layer comprises, is composed of, or is substantially composed of coated aluminum. 7. The conductive multilayer stack as described in Clause 6, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the solderable layer. 8. The conductive multilayer stack as described in Clause 7, wherein the coated aluminum does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 9. The conductive multilayer stack as described in clause 7 or 8, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal: Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 10. The conductive multilayer stack as described in any one of clauses 7 to 9, further comprising a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 11. The conductive multilayer stack as described in Clause 10, wherein the second metal layer comprises copper. 12. The conductive multilayer stack as described in any one of Clauses 7 to 11, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 13. The conductive multilayer stack as described in any one of clauses 1 to 12, wherein the glass paste sublayer penetrates the at least one passivation layer. 14. The conductive multilayer stack as described in any one of clauses 1 to 13, wherein the metal layer has a surface roughness Ra ranging from 100 nm to 500 nm, from 200 nm to 500 nm, or from 300 nm to 500 nm. 15. The conductive multilayer stack as described in any one of clauses 1 to 14, wherein the metal layer is laser-cut. 16. The conductive multilayer stack as described in Clause 15, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 17. The conductive multilayer stack as described in Clause 15 or 16, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 18. The conductive multilayer stack as described in any one of clauses 15 to 17, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 19. The conductive multilayer stack as described in any one of clauses 15 to 18, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 20. The conductive multilayer stack as described in any one of clauses 15 to 19, wherein the metal layer has a slag roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 21. The conductive multilayer stack as described in any one of clauses 1 to 20, wherein the solderable layer has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. 22. The conductive multilayer stack as described in any one of clauses 1 to 21, wherein the silver layer has a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 23. The conductive multilayer stack as described in any one of clauses 1 to 22, wherein the glass paste sublayer has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 24. The conductive multilayer stack as described in any one of clauses 1 to 23, wherein the solderable layer is a solder layer comprising solder material. 25. The conductive multilayer stack as described in Clause 24, wherein the solder material is silver-aluminum-copper (SAC) solder material. 26. The conductive multilayer stack as described in any one of clauses 1 to 25, wherein the silver contact layer is a silver contact pad. 27. The conductive multilayer stack as described in any one of clauses 1 to 26, wherein the silicon substrate and at least one passivation layer are the silicon substrate and at least one passivation layer of a solar cell. 28. A solar cell comprising at least two grid lines having two or more conductive multilayer stacks as described in any one of clauses 1 to 27. 29. The solar cell as described in Clause 28, wherein the at least two grid lines are fine grid lines, busbars, or a combination thereof. 30. The solar cell as described in Clause 29, wherein the silver contact pads of the first conductive multilayer stack in the two or more conductive multilayer stacks are separated from the silver contact pads of the second conductive multilayer stack in the two or more conductive multilayer stacks by a distance of 200 µm to 2 mm, 300 µm to 1 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 31. A conductive multilayer wire, comprising: At least two conductive multilayer stacks on a silicon substrate having at least one passivation layer, wherein the conductive multilayer stacks comprise: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks. 32. The conductive multilayer line as described in Clause 31, wherein the silver contact pads of the first conductive multilayer stack in the at least two conductive multilayer stacks are separated from the silver contact pads of the second conductive multilayer stack by a distance of 200 µm to 2 mm, 300 µm to 1 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 33. The conductive multilayer wire as described in clause 31 or 32, wherein the metal layer has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 34. The conductive multilayer line as described in any one of clauses 31 to 33, wherein the metal layer has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 35. The conductive multilayer line as described in any one of clauses 31 to 34, wherein the silicon substrate has a thickness ranging from 120 µm to 180 µm. 36. The conductive multilayer wire as described in any one of clauses 31 to 35, wherein the metal layer comprises, is composed of, or is substantially composed of Cu. 37. The conductive multilayer wire as described in any one of clauses 31 to 35, wherein the metal layer comprises, is composed of, or is substantially composed of coated aluminum. 38. The conductive multilayer wire as described in Clause 37, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the solderable layer. 39. The conductive multilayer wire as described in Clause 38, wherein the coated aluminum layer does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 40. The conductive multilayer wire as described in clause 38 or 39, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal: Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 41. The conductive multilayer wire as described in any one of clauses 38 to 40, further comprising a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 42. The conductive multilayer wire as described in Clause 41, wherein the second metal layer comprises copper. 43. The conductive multilayer wire as described in any one of clauses 38 to 42, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 44. The conductive multilayer wire as described in any one of clauses 31 to 43, wherein the glass paste sublayer penetrates the at least one passivation layer. 45. A conductive multilayer line as described in any one of clauses 31 to 44, wherein the metal layer has a surface roughness Ra ranging from 100 nm to 500 nm, from 200 nm to 500 nm, or from 300 nm to 500 nm. 46. ​​The conductive multilayer wire as described in any one of clauses 31 to 45, wherein the metal layer is laser-cut. 47. The conductive multilayer line as described in Clause 46, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 48. The conductive multilayer line as described in clause 46 or 47, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 49. The conductive multilayer line as described in any one of clauses 46 to 48, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 50. The conductive multilayer wire as described in any one of clauses 46 to 49, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 51. The conductive multilayer wire as described in any one of clauses 46 to 50, wherein the metal layer has a scum roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 52. The conductive multilayer wire as described in any one of clauses 46 to 51, wherein the solderable layer has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. 53. The conductive multilayer line as described in any one of clauses 31 to 52, wherein the silver contact pads have a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 54. The conductive multilayer line as described in any one of clauses 31 to 53, wherein the glass paste sublayer has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 55. The conductive multilayer wire as described in any one of clauses 31 to 54, wherein the solderable layer is a solder layer comprising solder material. 56. The conductive multilayer wire as described in Clause 55, wherein the solder material is silver-aluminum-copper (SAC) solder material. 57. The conductive multilayer wire as described in any one of clauses 31 to 56, wherein the metal layer is planar. 58. The conductive multilayer line as described in any one of clauses 31 to 57, wherein the silicon substrate and at least one passivation layer are the silicon substrate and at least one passivation layer of a solar cell. 59. The conductive multilayer line as described in any one of clauses 31 to 58, wherein the conductive multilayer line is a fine grid line, a busbar, or a combination thereof in a solar cell. 60. The conductive multilayer line of any one of clauses 31 to 59, wherein the conductive multilayer line comprises at least three conductive multilayer stacks, wherein the metal layer of the conductive multilayer stack is a continuous layer connecting the at least three conductive multilayer stacks. 61. A conductive multilayer stack on a solar cell, the conductive multilayer stack comprising: A metal layer comprising copper (Cu) or coated aluminum; A silver contact layer, the silver contact layer comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between and in contact with the metal layer and the silver contact layer; and The solar cell has a doped silicon substrate, the doped silicon substrate having a front surface and a rear surface, wherein the front surface of the doped silicon substrate is the light-facing surface, and wherein the rear surface of the doped silicon substrate is opposite to the light-facing surface of the doped silicon substrate; The doped silicon substrate has at least one passivation layer on its front and / or rear surfaces; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the front and / or back surfaces of the doped silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination of both. 62. The conductive multilayer stack as described in Clause 61, wherein the at least one passivation layer comprises a tunneling oxide layer, a doped layer on at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on at least a portion of the doped layer, wherein the doped layer comprises n-type doped polysilicon (poly-Si). 63. The conductive multilayer stack as described in Clause 62, wherein the glass paste sublayer penetrates the at least one SiOxNy passivation layer and contacts the doped layer. 64. The conductive multilayer stack as described in clause 62 or 63, wherein the tunneling oxide layer comprises SiOx. 65. The conductive multilayer stack as described in any one of clauses 62 to 64, wherein the at least one SiOxNy passivation layer comprises SiOx, SiNy, SiON, or a combination thereof. 66. The conductive multilayer stack as described in any one of clauses 62 to 65, wherein the tunneling oxide layer has a thickness ranging from 1 nm to 5 nm. 67. A conductive multilayer stack as described in any one of clauses 62 to 66, wherein the doped layer has a thickness ranging from 50 nm to 200 nm. 68. The conductive multilayer stack as described in any one of clauses 62 to 67, wherein the at least one SiOxNy passivation layer has a thickness ranging from 50 nm to 100 nm. 69. The conductive multilayer stack as described in Clause 61, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 70. The conductive multilayer stack as described in Clause 69, wherein the at least one passivation layer comprises a first passivation layer comprising SiOx and at least one second passivation layer comprising SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 71. The conductive multilayer stack as described in Clause 69, wherein the at least one passivation layer comprises a first passivation layer containing AlOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 72. The conductive multilayer stack as described in clause 70 or 71, wherein the at least one second passivation layer comprising SiOxNy comprises SiOx, SiNy, SiON, or a combination thereof. 73. The conductive multilayer stack as described in any one of clauses 70 to 72, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 74. The conductive multilayer stack as described in any one of clauses 70 to 73, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 75. The conductive multilayer stack as described in any one of clauses 70 or 72 to 74, further comprising an intermediate passivation layer between the first passivation layer and the at least one second passivation layer, wherein the intermediate passivation layer comprises AlOx. 76. The conductive multilayer stack as described in Clause 75, wherein the intermediate passivation layer has a thickness ranging from 1 nm to 5 nm. 77. The conductive multilayer stack as described in any one of clauses 69 to 76, wherein the glass paste sublayer penetrates the at least one passivation layer. 78. The conductive multilayer stack as described in Clause 61, wherein the front and / or rear surfaces of the doped silicon substrate further comprise a doped layer, and wherein the doped layer has a different dopant, a different dopant type, and / or a different dopant concentration than the doped silicon substrate. 79. The conductive multilayer stack as described in Clause 78, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 80. The conductive multilayer stack as described in Clause 79, wherein the at least one passivation layer comprises a first passivation layer comprising SiOx and at least one second passivation layer comprising SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 81. The conductive multilayer stack as described in Clause 80, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 82. The conductive multilayer stack as described in clause 80 or 81, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 83. The conductive multilayer stack as described in any one of clauses 80 to 82, further comprising an intermediate passivation layer between the first passivation layer and the at least one second passivation layer, wherein the intermediate passivation layer comprises AlOx. 84. The conductive multilayer stack as described in Clause 83, wherein the intermediate passivation layer has a thickness of 1 nm to 5 nm. 85. A conductive multilayer stack as described in any one of clauses 78 to 84, wherein the glass paste sublayer penetrates the at least one passivation layer and contacts the doped layer. 86. The conductive multilayer stack as described in any one of clauses 78 to 85, wherein the thickness of the doped layer is from 30 nm to 200 nm. 87. The conductive multilayer stack as described in any one of clauses 78 to 86, wherein the doped layer comprises an n-type dopant. 88. The conductive multilayer stack as described in any one of clauses 78 to 86, wherein the doped layer comprises a p-type dopant. 89. The conductive multilayer stack as described in any one of clauses 61 to 89, wherein the at least one passivation layer is on the front surface of the doped silicon substrate. 90. A conductive multilayer stack as described in any one of clauses 61 to 89, wherein the at least one passivation layer is on the back surface of the doped silicon substrate. 91. A conductive multilayer stack as described in any one of clauses 61 or 69 to 90, wherein the at least one passivation layer is on the back surface of the doped silicon substrate, wherein the back surface of the doped silicon substrate further comprises at least one doped layer, and wherein the at least one doped layer comprises at least one doped region and at least one oppositely doped region. 92. The conductive multilayer stack as described in Clause 91, wherein the at least one doped region comprises a p-type dopant, and the at least one oppositely doped region comprises an n-type dopant. 93. The conductive multilayer stack as described in clause 91 or 92, wherein the glass paste sublayer penetrates the at least one passivation layer to contact the at least one doped region. 94. A conductive multilayer stack as described in clause 91 or 92, wherein the glass paste sublayer penetrates the at least one passivation layer to contact the at least one oppositely doped region. 95. A conductive multilayer stack as described in any one of clauses 91 to 94, wherein the at least one doped region has a thickness ranging from 30 nm to 200 nm. 96. A conductive multilayer stack as described in any one of clauses 91 to 95, wherein the at least one oppositely doped region has a thickness ranging from 30 nm to 200 nm. 97. The conductive multilayer stack as described in any one of clauses 61 to 96, wherein the doped silicon substrate comprises an n-type dopant. 98. The conductive multilayer stack as described in any one of clauses 61 to 96, wherein the doped silicon substrate comprises a p-type dopant. 99. The conductive multilayer stack as described in any one of clauses 61 to 98, wherein the metal layer has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 100. A conductive multilayer stack as described in any one of clauses 61 to 99, wherein the metal layer has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 101. A conductive multilayer stack as described in any one of clauses 61 to 100, wherein the substrate has a thickness ranging from 120 µm to 180 µm. 102. The conductive multilayer stack as described in any one of clauses 61 to 101, wherein the metal layer comprises, is composed of, or is substantially composed of Cu. 103. The conductive multilayer stack as described in any one of clauses 61 to 101, wherein the metal layer comprises, is composed of, or is substantially composed of coated aluminum. 104. The conductive multilayer stack as described in Clause 103, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the solderable layer. 105. The conductive multilayer stack as described in Clause 104, wherein the coated aluminum does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 106. The conductive multilayer stack as described in clauses 104 or 105, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal: Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; or Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 107. The conductive multilayer stack as described in any one of clauses 104 to 106, further comprising a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 108. The conductive multilayer stack as described in Clause 107, wherein the second metal layer comprises copper. 109. The conductive multilayer stack as described in any one of clauses 104 to 108, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 110. A conductive multilayer stack as described in any one of clauses 61 to 109, wherein the glass paste sublayer penetrates the at least one passivation layer and contacts the front and / or back surfaces of the doped silicon substrate. 111. A conductive multilayer stack as described in any one of clauses 61 to 110, wherein the metal layer has a surface roughness Ra ranging from 100 nm to 500 nm, from 200 nm to 500 nm, or from 300 nm to 500 nm. 112. The conductive multilayer stack as described in any one of clauses 61 to 111, wherein the metal layer is laser-cut. 113. The conductive multilayer stack as described in Clause 112, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 114. The conductive multilayer stack as described in clause 112 or 113, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 115. A conductive multilayer stack as described in any one of clauses 112 to 114, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 116. The conductive multilayer stack as described in any one of clauses 112 to 115, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 117. A conductive multilayer stack as described in any one of clauses 112 to 116, wherein the metal layer has a scum roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 118. The conductive multilayer stack as described in any one of clauses 61 to 117, wherein the solderable layer has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. 119. The conductive multilayer stack as described in any one of clauses 61 to 118, wherein the silver contact layer has a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 120. A conductive multilayer stack as described in any one of clauses 61 to 119, wherein the glass paste sublayer has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 121. The conductive multilayer stack as described in any one of clauses 61 to 120, wherein the solderable layer is a solder layer comprising solder material. 122. The conductive multilayer stack as described in Clause 121, wherein the solder material is silver-aluminum-copper (SAC) solder material. 123. The conductive multilayer stack as described in any one of clauses 61 to 122, wherein the silver contact layer is a silver contact pad. 124. The conductive multilayer stack as described in any one of clauses 61 to 123, wherein the silicon substrate and the at least one passivation layer are the silicon substrate and at least one passivation layer of a solar cell. 125. A solar cell comprising at least two grid lines having two or more conductive multilayer stacks as described in any one of clauses 61 to 124. 126. The solar cell as described in Clause 125, wherein the at least two grid lines are fine grid lines, busbars, or a combination thereof. 127. The solar cell as described in Clause 125 or 126, wherein the silver contact pads of the first conductive multilayer stack in the two or more conductive multilayer stacks are separated from the silver contact pads of the second conductive multilayer stack in the two or more conductive multilayer stacks by a distance of 200 µm to 2 mm, 200 µm to 1 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 128. A symmetrical solar cell, comprising: A doped silicon substrate having a front surface and a rear surface; At least one passivation layer on at least a portion of the front and / or rear surfaces of the doped silicon substrate, wherein the front surface of the doped silicon substrate is a light-facing surface, and the rear surface is opposite to the light-facing surface; and At least one fine grid line on a portion of the front and / or rear surface of the doped silicon substrate; Wherein, the at least one fine grid line is a conductive multilayer line comprising at least two conductive multilayer stacks, wherein the conductive multilayer stacks in the at least two conductive multilayer stacks include: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting both the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer connecting at least two conductive multilayer stacks in the conductive multilayer line. 129. The symmetrical solar cell as described in Clause 128, wherein the at least one passivation layer comprises a tunneling oxide layer, a doped layer on top of at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on top of at least a portion of the doped layer, wherein the doped layer comprises n-type doped polycrystalline silicon (poly-Si). 130. The symmetrical solar cell as described in Clause 129, wherein the glass slurry sublayer penetrates the at least one SiOxNy passivation layer and contacts the doped layer. 131. A symmetrical solar cell as described in clauses 129 or 130, wherein the tunneling oxide layer comprises SiOx. 132. The symmetrical solar cell of any one of clauses 129 to 131, wherein the at least one SiOxNy passivation layer comprises SiOx, SiNy, SiON, or a combination thereof. 133. A symmetrical solar cell as described in any one of clauses 129 to 132, wherein the tunneling oxide layer has a thickness ranging from 1 nm to 5 nm. 134. A symmetrical solar cell as described in any one of clauses 129 to 133, wherein the doped layer has a thickness ranging from 50 nm to 200 nm. 135. A symmetrical solar cell as described in any one of clauses 129 to 134, wherein the at least one SiOxNy passivation layer has a thickness ranging from 50 nm to 100 nm. 136. The symmetrical solar cell as described in Clause 128, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 137. The symmetrical solar cell as described in Clause 136, wherein the at least one passivation layer comprises a first passivation layer containing SiOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 138. The symmetrical solar cell as described in Clause 136, wherein the at least one passivation layer comprises a first passivation layer containing AlOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 139. The symmetrical solar cell as described in Clause 137 or 138, wherein the at least one second passivation layer comprising SiOxNy comprises SiOx, SiNy, SiON, or any combination thereof. 140. A symmetrical solar cell as described in any one of clauses 137 to 139, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 141. A symmetrical solar cell as described in any one of clauses 137 to 140, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 142. The symmetrical solar cell of any one of clauses 137 or 139 to 141, further comprising an intermediate passivation layer between the first passivation layer and the second passivation layer, wherein the intermediate passivation layer comprises AlOx. 143. The symmetrical solar cell as described in Clause 142, wherein the intermediate passivation layer has a thickness ranging from 1 nm to 5 nm. 144. A symmetrical solar cell as described in any one of clauses 136 to 143, wherein the glass slurry sublayer penetrates the at least one passivation layer. 145. The symmetrical solar cell as described in Clause 128, wherein the front and / or rear surfaces of the doped silicon substrate further comprise a doped layer, and wherein the doped layer has a different dopant, a different dopant type, and / or a different dopant concentration than the doped silicon substrate. 146. The symmetrical solar cell as described in Clause 145, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 147. The symmetrical solar cell as described in Clause 146, wherein the at least one passivation layer comprises a first passivation layer containing SiOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 148. The symmetrical solar cell as described in Clause 147, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 149. A symmetrical solar cell as described in clauses 147 or 148, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 150. A symmetrical solar cell as described in any one of clauses 147 to 149, further comprising an intermediate passivation layer between the first passivation layer and the at least one second passivation layer, wherein the intermediate passivation layer comprises AlOx. 151. The symmetrical solar cell as described in Clause 150, wherein the intermediate passivation layer has a thickness of 1 nm to 5 nm. 152. A symmetrical solar cell as described in any one of clauses 145 to 151, wherein the glass slurry sublayer penetrates the at least one passivation layer to contact the doped layer. 153. The symmetrical solar cell of any one of clauses 145 to 152, wherein the thickness of the doped layer is from 30 nm to 200 nm. 154. A symmetrical solar cell as described in any one of clauses 145 to 153, wherein the doped layer comprises an n-type dopant. 155. A symmetrical solar cell as described in any one of clauses 145 to 153, wherein the doped layer comprises a p-type dopant. 156. A symmetrical solar cell as described in any one of clauses 128 to 155, wherein the at least one passivation layer is on the front surface of the doped silicon surface. 157. A symmetrical solar cell as described in any one of clauses 128 to 155, wherein the at least one passivation layer is on the back surface of the doped silicon substrate. 158. The symmetrical solar cell of any one of clauses 128 to 157, wherein the doped silicon substrate is n-type doped. 159. The symmetrical solar cell of any one of clauses 128 to 157, wherein the doped silicon substrate is p-type doped. 160. A symmetrical solar cell as described in any one of clauses 128 to 159, further comprising at least one pad on a portion of the front and / or rear surface of the doped silicon substrate, wherein the at least one fine grid line contacts the at least one pad. 161. The symmetrical solar cell of any one of clauses 128 to 160, further comprising at least one busbar on a portion of the front and / or rear surface of the doped silicon substrate, wherein the at least one fine mesh line contacts the at least one busbar. 162. The symmetrical solar cell as described in Clause 161, wherein the at least one busbar comprises at least two conductive multilayer stacks, and the conductive multilayer stacks of the at least two conductive multilayer stacks include: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the at least one busbar. 163. The symmetrical solar cell of any one of clauses 128 to 162, wherein the silver contact pads of the first conductive multilayer stack of the at least two conductive multilayer stacks of the at least one fine grid line are separated from the silver contact pads of the second conductive multilayer stack of the at least two conductive multilayer stacks by a distance of 200 µm to 2 mm, 300 µm to 2 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 164. The symmetrical solar cell of any one of clauses 128 to 163, wherein the metal layer of the at least one fine grid line and the at least one busbar (when present) has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 165. A symmetrical solar cell as described in any one of clauses 128 to 164, wherein the metal layer of the at least one fine grid line and the at least one busbar (when present) has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 166. A symmetrical solar cell as described in any one of clauses 128 to 165, wherein the substrate has a thickness ranging from 120 µm to 180 µm. 167. A symmetrical solar cell as described in any one of clauses 128 to 166, wherein the metal layer of the at least one fine grid line and the at least one busbar (if present) comprises, is composed of, or is substantially composed of Cu. 168. The symmetrical solar cell as described in Clause 167, further comprising a busbar that contacts a metal layer of the at least one fine grid line, wherein the busbar comprises a metal core and a solder coating. 169. The symmetrical solar cell as described in Clause 168, wherein the busbar is welded to the metal layer of the at least one fine grid line. 170. A symmetrical solar cell as described in Clause 168 or 169, wherein the metal core comprises copper, aluminum, carbon, tin, iron, alloys thereof, composites thereof, or combinations thereof. 171. The symmetrical solar cell of any one of clauses 168 to 170, wherein the metal core comprises copper. 172. The symmetrical solar cell as described in any one of clauses 168 to 171, wherein the busbar has a diameter of 80 µm to 1000 µm, 100 µm to 300 µm, or 120 µm to 200 µm. 173. The symmetrical solar cell of any one of clauses 168 to 172, wherein the solder coating has a thickness of 0.5 µm to 100 µm or 10 µm to 50 µm. 174. The symmetrical solar cell of any one of clauses 168 to 173, wherein the solder coating comprises tin, lead, bismuth, copper, zinc, antimony, manganese, indium, alloys thereof, compounds thereof, or any combination thereof. 175. A symmetrical solar cell as described in any one of clauses 128 to 166, wherein the metal layer of the at least one fine grid line and the at least one busbar (if present) comprises, is composed of, or is substantially composed of coated aluminum. 176. The symmetrical solar cell as described in Clause 175, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the solderable layer. 177. The symmetrical solar cell as described in Clause 176, wherein the coated aluminum does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 178. A symmetrical solar cell as described in clauses 176 or 177, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal: Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; or Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 179. The symmetrical solar cell of any one of clauses 176 to 178 further includes a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 180. The symmetrical solar cell as described in Clause 179, wherein the second metal layer comprises copper. 181. A symmetrical solar cell as described in any one of clauses 176 to 180, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 182. A symmetrical solar cell as described in any one of Clauses 128 to 181, wherein the metal layer of the at least one fine grid line and the at least one busbar (when present) has a surface roughness Ra ranging from 100 nm to 500 nm, from 200 nm to 500 nm, or from 300 nm to 500 nm. 183. The symmetrical solar cell of any one of clauses 128 to 182, wherein the metal layer of the at least one fine grid line and the at least one busbar (if present) is laser-cut. 184. The symmetrical solar cell as described in Clause 183, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 185. A symmetrical solar cell as described in clauses 183 or 184, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 186. A symmetrical solar cell as described in any one of clauses 183 to 185, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 187. A conductive multilayer stack as described in any one of clauses 183 to 186, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 188. A conductive multilayer stack as described in any one of clauses 183 to 187, wherein the metal layer has a scum roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 189. The symmetrical solar cell of any one of clauses 128 to 188, wherein the weldable layer of the at least one fine grid line and the at least one busbar (when present) has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. 190. A symmetrical solar cell as described in any one of clauses 128 to 189, wherein the silver contact pads of the at least one fine grid line and the at least one busbar (when present) have a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 191. A symmetrical solar cell as described in any one of Clauses 128 to 190, wherein the glass slurry sublayer of the at least one fine grid line and the at least one busbar (when present) has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 192. The symmetrical solar cell of any one of clauses 128 to 191, wherein the solderable layer of the at least one fine grid line and the at least one busbar (when present) is a solder layer comprising solder material. 193. The symmetrical solar cell as described in Clause 192, wherein the solder material is silver-aluminum-copper (SAC) solder material. 194. A symmetrical solar cell as described in any one of clauses 128 to 193, wherein the front and / or rear surfaces of the doped silicon substrate have a total surface area, wherein the silver contact pads of the at least one fine grid line and the at least one busbar (if present) have a combined surface area, and wherein the combined surface area ranges from 0.5% to 7%, 0.5% to 6%, 0.5% to 5%, 0.5% to 4%, 0.5% to 3%, 0.5% to 2%, 0.5% to 1%, or 0.5% to 0.75% of the total surface area. 195. An asymmetric solar cell, comprising: A silicon substrate having a front surface and a rear surface, the front surface being a light-facing surface, wherein the rear surface is opposite to the light-facing surface; At least one passivation layer directly on at least a portion of the rear surface of the silicon substrate; At least one first fine grid line on at least a portion of the rear surface of the silicon substrate; At least one second fine grid line on at least a portion of the rear surface of the silicon substrate; Wherein, the at least one first fine grid line or the at least one second fine grid line is a first conductive multilayer line comprising at least two conductive multilayer stacks; Wherein, the conductive multilayer stack in the at least two conductive multilayer stacks includes: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts the back surface of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and Wherein, the metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the first conductive multilayer line. 196. The asymmetric solar cell as described in Clause 195, wherein the at least one first fine grid line or the at least one second fine grid line is the first conductive multilayer line, and the other comprises sintered aluminum. 197. The asymmetric solar cell as described in Clause 195, wherein the at least one first fine grid line is a first conductive multilayer line comprising at least two conductive multilayer stacks, and wherein the at least one second fine grid line is a second conductive multilayer line comprising at least two conductive multilayer stacks. 198. The asymmetric solar cell as described in any one of clauses 195 to 197, further comprising: At least one first interconnect pad contacting the at least one first fine grid line; and At least one second interconnect pad that contacts at least one second fine grid line; Wherein, the at least one first interconnect pad is a third conductive multilayer line comprising at least two conductive multilayer stacks; and Wherein, the at least one second interconnect pad is a fourth conductive multilayer line comprising at least two conductive multilayer stacks, and the conductive multilayer stacks in the at least two conductive multilayer stacks of the third and / or fourth conductive multilayer lines include: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between the metal layer and the silver contact pads, and contacts both the metal layer and the silver contact pads; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and Wherein, the metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the at least one first and / or second interconnect pad. 199. The asymmetric solar cell as described in Clause 198, wherein the metal layers of the at least two conductive multilayer stacks of the first conductive multilayer line are continuous layers connected to the at least two conductive multilayer stacks of the third conductive multilayer line. 200. The asymmetric solar cell as described in clauses 198 or 199, wherein the metal layers of the at least two conductive multilayer stacks of the second conductive multilayer line are continuous layers connected to the at least two conductive multilayer stacks of the fourth conductive multilayer line. 201. The asymmetric solar cell of any one of clauses 195 to 197, further comprising at least one first pad on a first portion of the front and / or rear surface of the silicon substrate and at least one second pad on a second portion of the front and / or rear surface of the silicon substrate, wherein the at least one first fine mesh line contacts the at least one first pad, and wherein the at least one second fine mesh line contacts the at least one second pad. 202. The asymmetric solar cell of any one of clauses 195 to 201, wherein the back surface of the doped silicon substrate further comprises at least one doped layer, wherein the at least one doped layer comprises at least one doped region and at least one oppositely doped region. 203. The asymmetric solar cell as described in Clause 202, wherein the at least one doped region comprises a p-type dopant, and the at least one opposite doped region comprises an n-type dopant. 204. The asymmetric solar cell as described in clauses 202 or 203, wherein the glass slurry sublayer penetrates the at least one passivation layer and contacts the at least one doped region. 205. The asymmetric solar cell as described in clauses 202 or 203, wherein the glass paste sublayer penetrates the at least one passivation layer and contacts the at least one oppositely doped region and the glass paste sublayer. 206. The asymmetric solar cell as described in any one of clauses 202 to 205, wherein the at least one doped region has a thickness ranging from 30 nm to 200 nm. 207. The asymmetric solar cell as described in any one of clauses 203 to 207, wherein the at least one oppositely doped region has a thickness ranging from 30 nm to 200 nm. 208. The asymmetric solar cell as described in any one of clauses 195 to 201, wherein the at least one passivation layer comprises: Tunneling through the oxide layer; A doped layer on top of at least a first portion of the tunneling oxide layer and an opposite doped layer on top of at least a second portion of the tunneling oxide layer, wherein the doped layer comprises n-type doped polysilicon (poly-Si), and wherein the opposite doped layer comprises p-type doped polysilicon (poly-Si); and At least one SiOxNy passivation layer on top of at least a portion of the doped layer and on at least a portion of the opposite doped layer. 209. The asymmetric solar cell as described in Clause 208, wherein the glass slurry sublayer of the at least one first fine and / or second fine grid line penetrates the at least one SiOxNy passivation layer and contacts a doped layer comprising n-type doped poly-Si. 210. The asymmetric solar cell as described in Clause 208, wherein the glass slurry sublayer of the at least one first fine and / or second fine grid line penetrates the at least one SiOxNy passivation layer and contacts an oppositely doped layer comprising p-type doped poly-Si. 211. The asymmetric solar cell of any one of clauses 208 to 210, wherein the tunneling oxide layer comprises SiOx. 212. The asymmetric solar cell as described in any one of clauses 208 to 211, wherein the at least one SiOxNy passivation layer comprises SiOx, SiNy, SiON, or a combination thereof. 213. The asymmetric solar cell as described in any one of clauses 208 to 212, wherein the tunneling oxide layer has a thickness ranging from 1 nm to 5 nm. 214. The asymmetric solar cell as described in any one of clauses 208 to 213, wherein the doped layer and / or the opposite doped layer has a thickness ranging from 50 nm to 200 nm. 215. The asymmetric solar cell as described in any one of clauses 208 to 214, wherein the at least one SiOxNy passivation layer has a thickness ranging from 50 nm to 100 nm. 216. The asymmetric solar cell as described in any one of clauses 195 to 207, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 217. The asymmetric solar cell as described in Clause 216, wherein the at least one passivation layer comprises a first passivation layer containing SiOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 218. The asymmetric solar cell as described in Clause 216, wherein the at least one passivation layer comprises a first passivation layer containing AlOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 219. The asymmetric solar cell as described in clauses 217 or 218, wherein the at least one second passivation layer comprising SiOxNy comprises SiOx, SiNy, SiON, or a combination thereof. 220. The asymmetric solar cell as described in any one of clauses 217 to 219, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 221. The asymmetric solar cell as described in any one of clauses 217 to 220, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 222. The asymmetric solar cell as described in any one of clauses 217 or 219 to 221, further comprising an intermediate passivation layer between the first passivation layer and the second passivation layer, wherein the intermediate passivation layer comprises AlOx. 223. The asymmetric solar cell as described in Clause 222, wherein the intermediate passivation layer has a thickness ranging from 1 nm to 5 nm. 224. The asymmetric solar cell as described in any one of clauses 216 to 223, wherein the glass slurry sublayer penetrates the at least one passivation layer. 225. The asymmetric solar cell of any one of clauses 195 to 224, wherein the silicon substrate is p-type doped. 226. The asymmetric solar cell as described in any one of clauses 195 to 224, wherein the silicon substrate is n-type doped. 227. The asymmetric solar cell as described in any one of clauses 195 to 226, wherein the silver contact pads of the first conductive multilayer stack of the at least two conductive multilayer stacks of the conductive multilayer line are separated from the silver contact pads of the second conductive multilayer stack by a distance of 200 µm to 2 mm, 300 µm to 2 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 228. The asymmetric solar cell as described in any one of clauses 195 to 227, wherein the metal layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 229. The asymmetric solar cell as described in any one of clauses 195 to 228, wherein the metal layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 230. The asymmetric solar cell as described in any one of clauses 195 to 229, wherein the substrate has a thickness ranging from 120 µm to 180 µm. 231. The asymmetric solar cell as described in any one of clauses 195 to 230, wherein the metal layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) comprises, is composed of, or is substantially composed of Cu. 232. The asymmetric solar cell as described in any one of clauses 195 to 230, wherein the metal layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) comprises, is composed of, or is substantially composed of aluminum. 233. The asymmetric solar cell as described in Clause 232, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the weldable layer. 234. The asymmetric solar cell as described in Clause 233, wherein the coated aluminum does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 235. The asymmetric solar cell as described in clause 233 or 234, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal: Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; or Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 236. The asymmetric solar cell of any one of clauses 233 to 235, further comprising a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 237. The asymmetric solar cell as described in Clause 236, wherein the second metal layer comprises copper. 238. The asymmetric solar cell as described in any one of clauses 233 to 237, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 239. The asymmetric solar cell as described in any one of clauses 195 to 238, wherein the metal layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) has a surface roughness Ra ranging from 100 nm to 500 nm; from 200 nm to 500 nm; or from 300 nm to 500 nm. 240. The asymmetric solar cell as described in any one of clauses 195 to 239, wherein the metal layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (if present) is laser-cut. 241. The asymmetric solar cell as described in Clause 240, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 242. The asymmetric solar cell as described in clause 240 or 241, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 243. The asymmetric solar cell as described in any one of clauses 240 to 242, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 244. The asymmetric solar cell as described in any one of clauses 240 to 243, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 245. The asymmetric solar cell as described in any one of clauses 240 to 244, wherein the metal layer has a slag roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 246. The asymmetric solar cell as described in any one of clauses 195 to 245, wherein the solderable layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. 247. The asymmetric solar cell as described in any one of clauses 195 to 246, wherein the silver contact pads of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) have a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 248. The asymmetric solar cell as described in any one of clauses 195 to 247, wherein the glass paste sublayer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 249. The asymmetric solar cell as described in any one of clauses 195 to 248, wherein the solderable layer of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (when present) is a solder layer comprising solder material. 250. The asymmetric solar cell as described in Clause 249, wherein the solder material is silver-aluminum-copper (SAC) solder material. 251. The asymmetric solar cell as described in any one of clauses 195 to 250, wherein the back surface of the silicon substrate has a total surface area, wherein the silver contact pads of the at least one first and / or second fine grid line and the at least one first and / or second interconnect pad (if present) have a combined surface area, and wherein the combined surface area ranges from 0.5% to 7%, 0.5% to 6%, 0.5% to 5%, 0.5% to 4%, 0.5% to 3%, 0.5% to 2%, 0.5% to 1%, or 0.5% to 0.75% of the total surface area. 252. A solar cell module, comprising: First solar cell and second solar cell; Interconnectors that connect the first solar cell and the second solar cell. Wherein, the first solar cell and the second solar cell include: A doped silicon substrate having a front surface and a rear surface, wherein the front surface is a light-facing surface and the rear surface is opposite to the light-facing surface; At least one passivation layer directly on at least a portion of the front and / or rear surfaces of the doped silicon substrate; and At least one fine grid line on a portion of the front and / or rear surface of the doped silicon substrate; Wherein, the at least one fine grid line is a conductive multilayer line comprising at least two conductive multilayer stacks, wherein the conductive multilayer stacks in the at least two conductive multilayer stacks include: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between the metal layer and the silver contact pads, and contacts both the metal layer and the silver contact pads; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and Wherein, the metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the conductive multilayer lines. 253. The solar cell module as described in Clause 252, wherein the first solar cell and the second solar cell further comprise: At least one pad on a portion of the front and / or rear surface of the doped silicon substrate; and At least one busbar on a portion of the front and / or rear surface of the doped silicon substrate, wherein the at least one busbar contacts the at least one pad. The interconnect includes a first bus strip that contacts at least one pad on the first solar cell and at least one pad on the second solar cell, and a bus strip that contacts the first bus strip. 254. The solar cell module as described in Clause 253, wherein the at least one fine grid line on the first solar cell contacts the at least one busbar on the first solar cell, and the at least one fine grid line on the second solar cell contacts the at least one busbar on the second solar cell. 255. A solar cell module as described in clauses 253 or 254, wherein at least one corresponding busbar on the first solar cell and the second solar cell is a conductive multilayer line comprising at least two conductive multilayer stacks, wherein the conductive multilayer stacks in the at least two conductive multilayer stacks include: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the at least one busbar. 256. The solar cell module as described in Clause 252, wherein the interconnect includes a first interconnect pad on the first solar cell and a second interconnect pad on the second solar cell, wherein the first interconnect pad contacts the second interconnect pad to form a contact area. 257. The solar cell module as described in Clause 256, wherein the first solar cell and the second solar cell further include at least one busbar on a portion of the front and / or rear surface of the doped silicon substrate, wherein a corresponding fine mesh line contacts a corresponding at least one busbar. 258. The solar cell module as described in Clause 257, wherein the corresponding at least one busbar on the first solar cell and the second solar cell comprises at least two conductive multilayer stacks, wherein the conductive multilayer stacks of the at least two conductive multilayer stacks include: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between the metal layer and the silver contact pads, and contacts both the metal layer and the silver contact pads; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the at least one busbar. 259. A solar cell module as described in any one of clauses 256 to 258, wherein the first interconnect pad contacts the at least two conductive multilayer stacks of the at least one fine grid line of the corresponding first solar cell and the at least two conductive multilayer stacks of the at least one bus bar, as well as the second fine grid line on the first solar cell, and wherein the second interconnect pad contacts the at least two conductive multilayer stacks of the at least one fine grid line of the second solar cell and the at least two conductive multilayer stacks of the at least one bus bar. 260. The solar cell module of any one of clauses 256 to 259, wherein the first interconnect pad, the second interconnect pad, or both are metals comprising copper (Cu) or coated aluminum. 261. The solar cell module as described in any one of clauses 256 to 260, wherein the contact area between the first interconnect pad and the second interconnect pad is a weld. 262. The solar cell module of any one of clauses 259 to 261, wherein the first interconnect pad contacts the metal layers of the at least two conductive multilayer stacks of the at least one fine grid line on the first solar cell and / or the metal layers of the at least two conductive multilayer stacks of the at least one busbar. 263. The solar cell module of any one of clauses 259 to 262, wherein the second interconnect pad contacts the metal layers of the at least two conductive multilayer stacks of the at least one fine grid line on the second solar cell and / or the metal layers of the at least two conductive multilayer stacks of the at least one busbar. 264. The solar cell module of any one of clauses 257 to 263, wherein the first interconnect pad contacts the at least one busbar on the first solar cell. 265. The solar cell module of any one of clauses 257 to 264, wherein the second interconnect pad contacts the at least one busbar on the second solar cell. 266. The solar cell module as described in any one of clauses 257 to 265, wherein the first interconnect pad and / or the second interconnect pad are conductive multilayer lines comprising at least two conductive multilayer stacks, wherein the conductive multilayer stacks in the at least two conductive multilayer stacks comprise: A metal layer comprising copper (Cu) or coated aluminum; The silver contact pad includes a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the conductive multilayer lines. 267. The solar cell module as described in Clause 252, wherein the interconnect includes at least one first bus solder strip contacting the at least one fine grid line on the first solar cell or the at least one fine grid line on the second solar cell, wherein the at least one first bus solder strip includes a metal core and a solder coating, and wherein the interconnect further includes a bus strip contacting the at least one first bus solder strip. 268. The solar cell module as described in Clause 267, wherein the at least one first busbar contacts the at least one fine grid line on the first solar cell and the at least one fine grid line on the second solar cell. 269. The solar cell module as described in Clause 268, wherein the at least one first busbar is welded to a corresponding metal layer of at least one fine grid line of the first solar cell and the second solar cell. 270. The solar cell module as described in Clause 269, wherein, with respect to both the first solar cell and the second solar cell, the metal layer of the at least two conductive multilayer stacks with at least one fine grid line comprises copper (Cu). 271. The solar cell module of any one of clauses 267 to 270, wherein the metal core comprises copper, aluminum, carbon, tin, iron, alloys thereof, composites thereof, or combinations thereof. 272. The solar cell module of any one of clauses 267 to 271, wherein the metal core comprises copper. 273. The solar cell module as described in any one of clauses 267 to 272, wherein the at least one first busbar has a diameter of 80 µm to 1000 µm, 100 µm to 300 µm, or 120 µm to 200 µm. 274. The solar cell module of any one of clauses 267 to 273, wherein the solder coating has a thickness of 0.5 µm to 100 µm or 10 µm to 50 µm. 275. The solar cell module of any one of clauses 267 to 274, wherein the solder coating comprises tin, lead, silver, bismuth, copper, zinc, antimony, manganese, indium, alloys thereof, compounds thereof, or combinations thereof. 276. The solar cell module of any one of clauses 267 to 275, wherein the first solar cell and the second solar cell further include at least one pad on the respective front and / or rear surfaces of the first solar cell and the second solar cell. 277. The solar cell module as described in Clause 276, wherein the first solar cell and the second solar cell further include at least one second busbar that contacts at least one corresponding pad on the front and / or rear surfaces of the first solar cell and the second solar cell. 278. The solar cell module of any one of clauses 268 to 277, wherein the at least one first bus solder strip contacts the corresponding at least one fine grid line on the rear surface of the first solar cell and the second solar cell. 279. The solar cell module of any one of clauses 252 to 278, wherein the at least one passivation layer comprises a tunneling oxide layer, a doped layer on top of at least a portion of the tunneling oxide layer, and at least one SiOxNy passivation layer on top of at least a portion of the doped layer, wherein the doped layer comprises n-type doped polycrystalline silicon (poly-Si). 280. The solar cell module as described in Clause 279, wherein the glass slurry sublayer penetrates the at least one SiOxNy passivation layer and contacts the doped layer comprising the n-type doped poly-Si. 281. The solar cell module as described in clauses 279 or 280, wherein the tunneling oxide layer comprises SiOx. 282. The solar cell module of any one of clauses 279 to 281, wherein the at least one SiOxNy passivation layer comprises SiOx, SiNy, SiON, or a combination thereof. 283. The solar cell module of any one of clauses 279 to 282, wherein the tunneling oxide layer has a thickness ranging from 1 nm to 5 nm. 284. The solar cell module of any one of clauses 279 to 283, wherein the doped layer has a thickness ranging from 50 nm to 200 nm. 285. The solar cell module of any one of clauses 279 to 284, wherein the at least one SiOxNy passivation layer has a thickness ranging from 50 nm to 100 nm. 286. The solar cell module of any one of clauses 252 to 278, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 287. The solar cell module as described in Clause 286, wherein the at least one passivation layer comprises a first passivation layer comprising SiOx and at least one second passivation layer comprising SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 288. The solar cell module as described in Clause 287, wherein the at least one passivation layer comprises a first passivation layer containing AlOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 289. The solar cell module as described in Clause 287 or 288, wherein the at least one second passivation layer comprising SiOxNy comprises SiOx, SiNy, SiON, or any combination thereof. 290. The solar cell module as described in any one of clauses 287 to 289, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 291. The solar cell module of any one of clauses 287 to 290, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 292. The solar cell module as described in any one of clauses 287 or 289 to 291, further comprising an intermediate passivation layer between the first passivation layer and the at least one second passivation layer, wherein the intermediate passivation layer comprises AlOx. 293. The solar cell module as described in Clause 292, wherein the intermediate passivation layer has a thickness ranging from 1 nm to 5 nm. 294. The solar cell module as described in any one of clauses 286 to 293, wherein the glass slurry sublayer penetrates the at least one passivation layer. 295. The solar cell module of any one of clauses 252 to 278, wherein the front and / or rear surfaces of the doped silicon substrate further comprise a doped layer, and wherein the doped layer has a different dopant, a different dopant type, and / or a different dopant concentration than the doped silicon substrate. 296. The solar cell module as described in Clause 295, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 297. The solar cell module as described in Clause 296, wherein the at least one passivation layer comprises a first passivation layer containing SiOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 298. The solar cell module as described in Clause 297, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 299. A solar cell module as described in clauses 297 or 298, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 300. The solar cell module as described in any one of clauses 297 to 299, further comprising an intermediate passivation layer between the first passivation layer and the at least one second passivation layer, wherein the intermediate passivation layer comprises AlOx. 301. The solar cell module as described in Clause 300, wherein the intermediate passivation layer has a thickness of 1 nm to 5 nm. 302. The solar cell module of any one of clauses 295 to 301, wherein the glass slurry sublayer penetrates the at least one passivation layer and contacts the doped layer. 303. The solar cell module as described in any one of clauses 295 to 302, wherein the thickness of the doped layer is from 30 nm to 200 nm. 304. The solar cell module of any one of clauses 295 to 303, wherein the doped layer comprises an n-type dopant. 305. The solar cell module of any one of clauses 295 to 303, wherein the doped layer comprises a p-type dopant. 306. The solar cell module of any one of clauses 252 to 305, wherein the at least one passivation layer is on the front surface of the doped silicon substrate. 307. The solar cell module of any one of clauses 252 to 305, wherein the at least one passivation layer is on the back surface of the doped silicon substrate. 308. The solar cell module of any one of clauses 252 to 307, wherein the doped silicon substrate is n-type doped. 309. The solar cell module of any one of clauses 252 to 307, wherein the doped silicon substrate is p-type doped. 310. The solar cell module of any one of clauses 252 to 309, wherein the silver contact pads of the first conductive multilayer stack of the at least two conductive multilayer stacks of the at least one fine grid line are separated from the silver contact pads of the second conductive multilayer stack of the at least two conductive multilayer stacks by a distance of 200 µm to 2 mm, 300 µm to 2 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 311. The solar cell module of any one of clauses 252 to 310, wherein the metal layers of the at least one fine grid line and the at least one busbar (if present) and the first and / or second interconnect pads (if present) have a thickness ranging from 4 µm to 100 µm, 4 µm to 50 µm, 4 µm to 25 µm, 4 µm to 10 µm, or 4 µm to 6 µm. 312. The solar cell module of any one of clauses 252 to 311, wherein the metal layer of the at least one fine grid line and the at least one busbar (if present) and the first and / or second interconnect pad (if present) has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 313. The solar cell module of any one of clauses 252 to 312, wherein the substrate has a thickness ranging from 120 µm to 180 µm. 314. The solar cell module of any one of clauses 252 to 313, wherein the metal layer of the at least one fine grid line and the at least one busbar (if present) and the first and / or second interconnect pad (if present) comprises, is composed of, or is substantially composed of Cu. 315. The solar cell module of any one of clauses 252 to 313, wherein the metal layer of the at least one fine grid line and the at least one busbar (if present) and the first and / or second interconnect pad (if present) comprises, is composed of, or is substantially composed of aluminum. 316. The solar cell module as described in clause 315, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the solderable layer. 317. The solar cell module as described in Clause 316, wherein the coated aluminum does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 318. The solar cell module as described in clauses 316 or 317, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; or Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 319. The solar cell module of any one of clauses 316 to 318 further includes a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 320. The solar cell module as described in Clause 318, wherein the second metal layer comprises copper. 321. The solar cell module of any one of clauses 317 to 320, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 322. The solar cell module of any one of clauses 252 to 321, wherein the metal layer of the at least one fine grid line and the at least one busbar (when present) and the first and / or second interconnect pad (when present) has a surface roughness Ra ranging from 100 nm to 500 nm; from 200 nm to 500 nm; or from 300 nm to 500 nm. 323. The solar cell module as described in any one of clauses 252 to 322, wherein the metal layers of the at least one fine grid line and the at least one busbar (if present) and the first and / or second interconnect pads (if present) are laser-cut. 324. The solar cell module as described in Clause 323, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 325. The solar cell module as described in clause 323 or 324, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 326. The solar cell module of any one of clauses 322 to 325, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 327. The conductive multilayer stack as described in any one of clauses 323 to 326, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 328. The conductive multilayer stack as described in any one of clauses 323 to 327, wherein the metal layer has a scum roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 329. The solar cell module of any one of clauses 252 to 328, wherein the solderable layer of the at least one fine grid line and the at least one busbar (when present) and the first and / or second interconnect pad (when present) has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. 330. The solar cell module of any one of clauses 252 to 329, wherein the silver contact pads of the at least one fine grid line and the at least one busbar (if present) and the first and / or second interconnect pads (if present) have a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 331. The solar cell module of any one of clauses 252 to 330, wherein the glass paste sublayer of the at least one fine grid line and the at least one busbar (if present) and the first and / or second interconnect pad (if present) has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 332. The solar cell module as described in any one of clauses 252 to 331, wherein the solderable layer of the at least one fine grid line and the at least one busbar (when present) and the first and / or second interconnect pad (when present) is a solder layer comprising solder material. 333. The solar cell module as described in Clause 332, wherein the solder material is silver-aluminum-copper (SAC) solder material. 334. A solar cell module, comprising: First solar cell and second solar cell; An interconnect connecting the first solar cell and the second solar cell; Wherein, the first solar cell and the second solar cell include: A silicon substrate having a front surface and a rear surface, the front surface being a light-facing surface, wherein the rear surface is opposite to the light-facing surface; At least one passivation layer directly on at least a portion of the rear surface of the silicon substrate; At least one first fine grid line on at least a portion of the rear surface of the silicon substrate; and At least one second fine grid line on at least a portion of the rear surface of the silicon substrate; Wherein, at least one of the at least one first fine mesh line or the at least one second fine mesh line is a first conductive multilayer line comprising at least two conductive multilayer stacks; and Wherein, the conductive multilayer stack in the at least two conductive multilayer stacks includes: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting the metal layer and the silver contact pad; Wherein, the glass paste sublayer of the conductive multilayer stack is on the silicon substrate, on the at least one passivation layer, or on a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks. 335. The solar cell module as described in Clause 334, wherein the at least one first fine mesh line or the at least one second fine mesh line is the first conductive multilayer line, and the other comprises sintered aluminum. 336. The solar cell module as described in Clause 334, wherein the at least one first fine grid line is a first conductive multilayer line comprising at least two conductive multilayer stacks, and wherein the at least one second fine grid line is a second conductive multilayer line comprising at least two conductive multilayer stacks. 337. The solar cell module as described in any one of clauses 334 to 336, wherein the interconnecting element comprises: At least one first interconnect pad on the first solar cell, the at least one first interconnect pad contacting the at least one first fine grid line; At least one second interconnect pad on the second solar cell, the at least one second interconnect pad contacting the at least one second fine grid line; Wherein, the at least one first interconnect pad is connected to the at least one second interconnect pad. 338. The solar cell module as described in Clause 337, wherein the at least one first interconnect pad is a third conductive multilayer line comprising at least two conductive multilayer stacks, and wherein the at least one second interconnect pad is a fourth conductive multilayer line comprising at least two conductive multilayer stacks, wherein the conductive multilayer stacks in the at least two conductive multilayer stacks of the third and / or fourth conductive multilayer lines comprise: A metal layer comprising copper (Cu) or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between the metal layer and the silver contact pads, and contacts both the metal layer and the silver contact pads; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and Wherein, the metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the at least one first and / or second interconnect pad. 339. The solar cell module as described in Clause 338, wherein the metal layers of the at least two conductive multilayer stacks of the first conductive multilayer line are continuous layers connected to the at least two conductive multilayer stacks of the third conductive multilayer line. 340. The solar cell module as described in clauses 338 or 339, wherein the metal layers of the at least two conductive multilayer stacks of the second conductive multilayer are continuous layers of the at least two conductive multilayer stacks connected to the fourth conductive multilayer line. 341. The solar cell module of any one of clauses 338 to 340, wherein the metal layer of the at least one first interconnect pad on the first solar cell is connected to the metal layer of the at least one second interconnect pad on the second solar cell. 342. The solar cell module as described in Clause 341, wherein the metal layer of the at least one first interconnect pad on the first solar cell is soldered to the metal layer of the at least one second interconnect pad on the second solar cell. 343. The solar cell module as described in any one of clauses 334 to 336, further comprising: At least one first pad on a portion of the front and / or rear surface of the silicon substrate on the first solar cell, and at least one second pad on a portion of the front and / or rear surface of the silicon substrate on the second solar cell. Wherein, at least one first fine grid line on the first solar cell contacts at least one first pad; and Wherein, at least one second fine grid line on the second solar cell contacts the at least one second pad; The interconnect includes a bus strip that contacts at least one first pad on the first solar cell and at least one second pad on the second solar cell, and wherein the bus strip contacts the bus strip. 344. The solar cell module of any one of clauses 334 to 343, wherein the back surface of the doped silicon substrate further comprises at least one doped layer, wherein the at least one doped layer has at least one doped region and at least one oppositely doped region. 345. The solar cell module as described in Clause 344, wherein the at least one doped region comprises a p-type dopant, and the at least one oppositely doped region comprises an n-type dopant. 346. The solar cell module as described in clauses 344 or 345, wherein the glass slurry sublayer penetrates the at least one passivation layer and contacts the at least one doped region. 347. A solar cell module as described in clause 344 or 345, wherein the glass slurry sublayer penetrates the at least one passivation layer and contacts the at least one oppositely doped region. 348. The solar cell module of any one of clauses 344 to 347, wherein the at least one doped region has a thickness ranging from 30 nm to 200 nm. 349. The solar cell module of any one of clauses 344 to 348, wherein the at least one oppositely doped region has a thickness ranging from 30 nm to 200 nm. 350. The solar cell module as described in any one of clauses 333 to 342, wherein the at least one passivation layer comprises Tunneling through the oxide layer; A doped layer on top of at least a first portion of the tunneling oxide layer and an opposite doped layer on top of at least a second portion of the tunneling oxide layer, wherein the doped layer comprises n-type doped polysilicon (poly-Si), and wherein the opposite doped layer comprises p-type doped polysilicon (poly-Si); and At least one SiOxNy passivation layer on top of at least a portion of the doped layer and on at least a portion of the opposite doped layer. 351. The solar cell module as described in Clause 350, wherein the glass slurry sublayer of the at least one first fine grid line or the at least one second fine grid line penetrates the at least one SiOxNy passivation layer and contacts a doped layer comprising n-type doped poly-Si. 352. The solar cell module as described in Clause 350, wherein the glass slurry sublayer of the at least one first fine grid line or the at least one second fine grid line penetrates the at least one SiOxNy passivation layer and contacts an oppositely doped layer comprising p-type doped poly-Si. 353. The solar cell module of any one of clauses 350 to 352, wherein the tunneling oxide layer comprises SiOx. 354. The solar cell module as described in any one of clauses 350 to 353, wherein the at least one SiOxNy passivation layer comprises SiOx, SiNy, SiON, or a combination thereof. 355. The solar cell module as described in any one of clauses 350 to 354, wherein the tunneling oxide layer has a thickness ranging from 1 nm to 5 nm. 356. The solar cell module as described in any one of clauses 350 to 355, wherein the doped layer and / or the opposite doped layer has a thickness ranging from 50 nm to 200 nm. 357. The solar cell module as described in any one of clauses 350 to 356, wherein the at least one SiOxNy passivation layer has a thickness ranging from 50 nm to 100 nm. 358. The solar cell module of any one of clauses 334 to 349, wherein the at least one passivation layer comprises SiOx, AlOx, or SiOxNy. 359. The solar cell module as described in Clause 358, wherein the at least one passivation layer comprises a first passivation layer containing SiOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 360. The solar cell module as described in Clause 358, wherein the at least one passivation layer comprises a first passivation layer containing AlOx and at least one second passivation layer containing SiOxNy, wherein the at least one second passivation layer is on at least a portion of the first passivation layer. 361. The solar cell module as described in clauses 359 or 360, wherein the at least one second passivation layer comprising SiOxNy comprises SiOx, SiNy, SiON, or any combination thereof. 362. The solar cell module as described in any one of clauses 359 to 361, wherein the first passivation layer has a thickness ranging from 1 nm to 5 nm. 363. The solar cell module as described in any one of clauses 359 to 362, wherein the at least one second passivation layer has a thickness ranging from 50 nm to 100 nm. 364. The solar cell module as described in any one of clauses 359 or 361 to 363, further comprising an intermediate passivation layer between the first passivation layer and the second passivation layer, wherein the intermediate passivation layer comprises AlOx. 365. The solar cell module as described in Clause 364, wherein the intermediate passivation layer has a thickness ranging from 1 nm to 5 nm. 366. The solar cell module as described in any one of clauses 358 to 365, wherein the glass slurry sublayer penetrates the at least one passivation layer. 367. The solar cell module of any one of clauses 334 to 366, wherein the silicon substrate is p-type doped. 368. The solar cell module of any one of clauses 334 to 366, wherein the silicon substrate is n-type doped. 369. The solar cell module of any one of clauses 334 to 368, wherein the silver contact pads of the first conductive multilayer stack in the at least two conductive multilayer stacks of the first conductive multilayer line are separated from the silver contact pads of the second conductive multilayer stack in the at least two conductive multilayer stacks by a distance of 200 µm to 2 mm, 300 µm to 2 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 370. The solar cell module of any one of clauses 334 to 369, wherein the metal layer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 371. The solar cell module of any one of clauses 334 to 370, wherein the metal layer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 372. The solar cell module of any one of clauses 334 to 371, wherein the substrate has a thickness ranging from 120 µm to 180 µm. 373. The solar cell module of any one of clauses 334 to 372, wherein the metal layer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) comprises, is composed of, or is substantially composed of Cu. 374. The solar cell module of any one of clauses 334 to 372, wherein the metal layer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) comprises, is composed of, or is substantially composed of coated aluminum. 375. The solar cell module as described in clause 374, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the solderable layer. 376. The solar cell module as described in Clause 375, wherein the coated aluminum does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 377. The solar cell module as described in clauses 375 or 376, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal: Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; or Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 378. The solar cell module of any one of clauses 375 to 377 further includes a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 379. The solar cell module as described in Clause 378, wherein the second metal layer comprises copper. 380. A solar cell module as described in any one of clauses 375 to 379, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 381. The solar cell module of any one of clauses 334 to 380, wherein the metal layer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) has a surface roughness Ra ranging from 100 nm to 500 nm; from 200 nm to 500 nm; or from 300 nm to 500 nm. 382. The solar cell module as described in any one of clauses 334 to 381, wherein the metal layers of the first and / or second fine grid lines and the first and / or second interconnect pads (if present) are laser-cut. 383. The solar cell module as described in Clause 382, ​​wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 384. The solar cell module as described in clauses 382 or 383, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 385. The solar cell module of any one of clauses 382 to 384, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 386. The solar cell module of any one of clauses 382 to 385, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 387. The solar cell module of any one of clauses 382 to 386, wherein the metal layer has a slag roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 388. The solar cell module of any one of clauses 334 to 387, wherein the solderable layer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) has a thickness of less than 40 µm, less than 30 µm, less than 25 µm, less than 20 µm, or less than 10 µm. 389. The solar cell module of any one of clauses 334 to 388, wherein the silver contact pads of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) have a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 390. A solar cell module as described in any one of clauses 334 to 389, wherein the glass paste sublayer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 391. The solar cell module as described in any one of clauses 334 to 390, wherein the solderable layer of the first and / or second fine grid lines and the first and / or second interconnect pads (when present) is a solder layer containing solder material. 392. The solar cell module as described in Clause 391, wherein the solder material is silver-aluminum-copper (SAC) solder material. 393. A method for forming a conductive multilayer stack, comprising: A silicon substrate is provided, the silicon substrate having at least one passivation layer on the front and / or rear surface of the silicon substrate; A silver contact pad is formed, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; A solderable layer is formed by applying solderable paste to the silver contact pads; A metal layer comprising copper (Cu) or coated aluminum is applied to the solderable layer; and The metal layer is heated to mechanically bond the metal layer to the solderable layer and the solderable layer to the silver contact pads; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, at least a portion of the at least one passivation layer, or a combination thereof. 394. The method of claim 393, wherein forming the silver contact pad comprises: A silver metallization paste comprising silver particles and a glass paste is applied to at least a portion of the silicon substrate or to at least a portion of the at least one passivation layer. The silver metal paste was co-fired. 395. A method for forming a conductive multilayer wire, comprising: A silicon substrate is provided, the silicon substrate having at least one passivation layer; A discontinuity line is formed for silver contact pads, wherein the silver contact pads in the discontinuity line include a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; Discontinuities in the solderable pad are formed by applying solderable paste along the discontinuities of the silver contact pad, aligned with the discontinuities of the silver contact pad. A metal layer comprising copper (Cu) or coated aluminum is applied to the discontinuity line of the solderable pad; and The metal layer is heated to mechanically bond the metal layer to the discontinuity of the solderable pad and to mechanically bond the discontinuity of the solderable pad to the discontinuity of the silver contact pad. The glass paste sublayer of the discontinuous line of the silver contact pad contacts at least a portion of the silicon substrate, at least a portion of the at least one passivation layer, or a combination thereof. 396. The method of claim 395, wherein forming the discontinuity of the silver contact pad comprises: Discontinuous lines of silver metallization paste, comprising silver particles and glass paste, are applied to at least a portion of the silicon substrate or to at least a portion of the at least one passivation layer; and Discontinuous lines of the silver metal paste are co-fired. 397. The method as described in clauses 395 or 396, wherein the discontinuity of the silver contact pad comprises a first silver contact pad and a second silver contact pad, and wherein the first silver contact pad is separated from the second silver contact pad by a distance of 200 µm to 2 mm, 300 µm to 1 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm. 398. The method of any one of clauses 395 to 397, wherein the front surface and / or the rear surface has a total surface area, wherein the silver contact pads have a combined surface area, and wherein the combined surface area ranges from 0.5% to 7%, 0.5% to 6%, 0.5% to 5%, 0.5% to 4%, 0.5% to 3%, 0.5% to 2%, 0.5% to 1%, or 0.5% to 0.75% of the total surface area. 399. The method of any one of clauses 395 to 398, wherein the silver contact pad has a thickness of 3 µm to 30 µm, 4 µm to 25 µm, 4 µm to 20 µm, 4 µm to 15 µm, 4 µm to 12 µm, 4 µm to 10 µm, 4 µm to 8 µm, or 4 µm to 5 µm. 400. The method of any one of clauses 393 to 399, wherein the glass slurry sublayer has a thickness of 1 nm to 3 µm, 1 nm to 1 µm, or 1 nm to 200 nm. 401. The method of any one of clauses 393 to 400, wherein the glass paste sublayer is on the silicon substrate at least a portion thereon, on the at least a portion thereon of the at least one passivation layer, or on a combination thereof. 402. The method of any one of clauses 393 to 401, wherein the metal layer has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 403. The method of any one of clauses 393 to 402, wherein the metal layer has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 404. The method of any one of clauses 393 to 403, wherein the silicon substrate has a thickness ranging from 120 µm to 180 µm. 405. The method of any one of clauses 393 to 404 further comprises laser-cutting the metal layer into a pattern prior to applying the metal layer. 406. The method of claim 405, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 407. The method as described in clause 405 or 406, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 408. The method of any one of clauses 405 to 407, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 409. The method of any one of clauses 405 to 408, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 410. The method of any one of clauses 405 to 409, wherein the metal layer has a slag roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 411. The method of any one of clauses 393 to 410, wherein the conductive multilayer line is a fine mesh line or a busbar. 412. The method as described in any one of clauses 393 to 411, further comprising: The busbar is mechanically bonded to the metal layer of the conductive multilayer stack or the conductive multilayer line, wherein the busbar includes a metal core and a solder coating, and wherein the metal layer of the conductive multilayer stack or the conductive multilayer line comprises, is composed of, or is substantially composed of Cu. 413. The method as described in clause 412, wherein the busbar is welded to the metal layer. 414. The method as described in clause 412 or 413, wherein the metal core comprises: Copper, aluminum, carbon, tin or iron; or alloys thereof, compounds thereof, or combinations thereof. 415. The method of any one of clauses 412 to 414, wherein the metal core comprises copper. 416. The method of any one of clauses 412 to 415, wherein the busbar has a diameter of 80 µm to 1000 µm, 100 µm to 300 µm, or 120 µm to 200 µm. 417. The method of any one of clauses 412 to 416, wherein the solder coating has a thickness of 0.5 µm to 100 µm or 10 µm to 50 µm. 418. The method of any one of clauses 412 to 417, wherein the solder coating comprises: Tin, lead, silver, bismuth, copper, zinc, antimony, manganese or indium; or alloys thereof, complexes thereof, or combinations thereof. 419. A conductive multilayer stack on a solar cell, the conductive multilayer stack comprising: A metal layer comprising copper (Cu) or coated aluminum; A silver contact layer, wherein the silver contact layer does not contain glass paste; and A solderable layer is provided between and in contact with the metal layer and the silver contact layer; and The solar cell has a doped silicon substrate, the doped silicon substrate having a front surface and a rear surface, wherein the front surface of the doped silicon substrate is the light-facing surface, and wherein the rear surface of the doped silicon substrate is opposite to the light-facing surface of the doped silicon substrate; The doped silicon substrate has at least one passivation layer on its front and / or rear surfaces. The at least one passivation layer includes an intrinsic amorphous layer on at least a portion of the doped silicon substrate and a doped layer on at least a portion of the intrinsic amorphous layer. The solar cell has a transparent conductive oxide layer on at least a portion of the doped layer; and The silver contact layer of the conductive multilayer stack contacts at least a portion of the transparent conductive oxide layer. 420. The conductive multilayer stack as described in Clause 419, wherein the doped layer of the at least one passivation layer contains a different dopant, a different dopant type, and / or a different dopant concentration than the doped silicon substrate. 421. The conductive multilayer stack as described in clauses 419 or 420, wherein the intrinsic amorphous layer of the at least one passivation layer comprises intrinsic amorphous silicon (a-Si:H(i)). 422. The conductive multilayer stack as described in any one of clauses 419 to 421, wherein the doped layer of the at least one passivation layer comprises p-type doped hydrogenated amorphous silicon (a-Si:H(p)). 423. The conductive multilayer stack as described in any one of clauses 419 to 421, wherein the doped layer of the at least one passivation layer comprises n-type doped hydrogenated amorphous silicon (a-Si:H(n)). 424. The conductive multilayer stack as described in any one of clauses 419 to 423, wherein the transparent conductive oxide layer comprises indium tin oxide. 425. A conductive multilayer stack as described in any one of clauses 418 to 424, wherein the intrinsic amorphous layer of the at least one passivation layer contacts at least a portion of the doped silicon substrate, the doped layer of the at least one passivation layer contacts at least a portion of the intrinsic amorphous layer of the at least one passivation layer, and the transparent conductive oxide layer contacts at least a portion of the doped layer of the at least one passivation layer. 426. The conductive multilayer stack as described in any one of clauses 419 to 425, wherein the at least one passivation layer is on the front surface of the doped silicon substrate. 427. The conductive multilayer stack as described in any one of clauses 419 to 425, wherein the at least one passivation layer is on the back surface of the doped silicon substrate. 428. The conductive multilayer stack as described in Clause 427, wherein the doped layer of the at least one passivation layer comprises at least one doped region and at least one oppositely doped region. 429. The conductive multilayer stack as described in Clause 428, wherein the at least one doped region comprises a p-type dopant, and the at least one oppositely doped region comprises an n-type dopant. 430. The conductive multilayer stack as described in clauses 428 or 429, wherein the transparent conductive oxide layer is between and contacts at least a portion of the at least one doped region and at least a portion of the silver contact layer. 431. The conductive multilayer stack as described in clauses 428 or 429, wherein the transparent conductive oxide layer is between and contacts at least a portion of the at least one oppositely doped region and at least a portion of the silver contact layer. 432. The conductive multilayer stack as described in any one of clauses 419 to 431, wherein the thickness of the intrinsic amorphous layer of the at least one passivation layer is 2 nm to 5 nm. 433. The conductive multilayer stack as described in any one of clauses 419 to 432, wherein the thickness of the doped layer of the at least one passivation layer is from 10 nm to 50 nm. 434. The conductive multilayer stack as described in any one of clauses 419 to 433, wherein the thickness of the transparent conductive oxide layer is 50 nm to 100 nm. 435. The conductive multilayer stack as described in any one of clauses 419 to 434, wherein the doped silicon substrate comprises an n-type dopant. 436. The conductive multilayer stack as described in any one of clauses 419 to 435, wherein the doped silicon substrate comprises a p-type dopant. 437. The conductive multilayer stack as described in any one of clauses 419 to 436, wherein the metal layer has a thickness ranging from 4 µm to 100 µm, from 4 µm to 50 µm, from 4 µm to 25 µm, from 4 µm to 10 µm, or from 4 µm to 6 µm. 438. The conductive multilayer stack as described in any one of clauses 419 to 437, wherein the metal layer has a width of 30 µm to 500 µm, 30 µm to 450 µm, 30 µm to 400 µm, 30 µm to 350 µm, 30 µm to 300 µm, 30 µm to 250 µm, 30 µm to 200 µm, 30 µm to 150 µm, 40 µm to 125 µm, 40 µm to 100 µm, 50 µm to 100 µm, or 50 µm to 75 µm. 439. The conductive multilayer stack as described in any one of clauses 419 to 438, wherein the substrate has a thickness ranging from 120 µm to 180 µm. 440. A conductive multilayer stack as described in any one of clauses 419 to 439, wherein the metal layer comprises, is composed of, or is substantially composed of Cu. 441. The conductive multilayer stack as described in any one of clauses 419 to 439, wherein the metal layer comprises, is composed of, or is substantially composed of coated aluminum. 442. The conductive multilayer stack as described in clause 441, wherein the coated aluminum comprises an aluminum layer and includes at least one corrosion-resistant bonding layer on at least one side of the aluminum layer that contacts the solderable layer. 443. The conductive multilayer stack as described in Clause 442, wherein the coated aluminum does not contain natural oxides between the aluminum layer and the at least one corrosion-resistant bonding layer. 444. The conductive multilayer stack as described in clause 442 or 443, wherein the at least one corrosion-resistant bonding layer is: An alloy of aluminum and a metal, wherein the metal: Selected from copper (Cu), magnesium (Mg), manganese (Mn), silicon (Si), tin (Sn), zinc (Zn), and combinations thereof; or Selected from chromium (Cr), cobalt (Co), molybdenum (Mo), nickel (Ni), tantalum (Ta), titanium (Ti), tungsten (W), their alloys, their nitrides, their borides, their complexes, and combinations thereof; or Selected from Ti, its alloys, its nitrides, its borides, its complexes, and combinations thereof. 445. The conductive multilayer stack as described in any one of clauses 442 to 444, further comprising a second metal layer between and in contact with the at least one corrosion-resistant bonding layer and the solderable layer. 446. The conductive multilayer stack as described in clause 445, wherein the second metal layer comprises copper. 447. The conductive multilayer stack as described in any one of clauses 442 to 446, wherein the at least one corrosion-resistant bonding layer has a thickness, width, or both ranging from 50 nm to 200 nm, or from 20 nm to 100 nm. 448. A conductive multilayer stack as described in any one of clauses 419 to 447, wherein the metal layer has a surface roughness Ra ranging from 100 nm to 500 nm, from 200 nm to 500 nm, or from 300 nm to 500 nm. 449. The conductive multilayer stack as described in any one of clauses 419 to 448, wherein the metal layer is laser-cut. 450. The conductive multilayer stack as described in Clause 449, wherein the metal layer has a burr roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 451. The conductive multilayer stack as described in clauses 449 or 450, wherein the metal layer has an in-plane edge roughness ranging from 0.5 µm to 50 µm, from 0.5 µm to 20 µm, from 0.5 µm to 10 µm, from 0.5 µm to 5 µm, from 0.5 µm to 2.5 µm, or from 0.1 µm to 1.5 µm. 452. The conductive multilayer stack as described in any one of clauses 449 to 451, wherein the metal layer has an average burr height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 453. The conductive multilayer stack as described in any one of clauses 449 to 452, wherein the metal layer has an average scum height ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 454. The conductive multilayer stack as described in any one of clauses 449 to 453, wherein the metal layer has a scum roughness ranging from 200 nm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 5 µm. 455. The conductive multilayer stack as described in any one of c...

Claims

1. A conductive multilayer stack, comprising: A metal layer comprising copper or coated aluminum; A silver contact layer, the silver contact layer comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between and in contact with the metal layer and the silver contact layer; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of at least one passivation layer on the silicon substrate, or contacts a combination thereof.

2. A conductive multilayer wire, comprising: At least two conductive multilayer stacks on a silicon substrate having at least one passivation layer, wherein the conductive multilayer stacks comprise: A metal layer comprising copper or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting both the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks.

3. A conductive multilayer stack on a solar cell, the conductive multilayer stack comprising: A metal layer comprising copper or coated aluminum; A silver contact layer, the silver contact layer comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between and in contact with the metal layer and the silver contact layer; and The solar cell has a doped silicon substrate, the doped silicon substrate having a front surface and a rear surface, wherein the front surface of the doped silicon substrate is the light-facing surface, and wherein the rear surface of the doped silicon substrate is opposite to the light-facing surface of the doped silicon substrate; The doped silicon substrate has at least one passivation layer on its front and / or rear surfaces; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the front and / or back surfaces of the doped silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination of both.

4. A symmetrical solar cell, comprising: A doped silicon substrate having a front surface and a rear surface; At least one passivation layer on at least a portion of the front and / or rear surfaces of the doped silicon substrate, wherein the front surface of the doped silicon substrate is a light-facing surface, and the rear surface is opposite to the light-facing surface; and At least one fine grid line on a portion of the front and / or rear surface of the doped silicon substrate; Wherein, the at least one fine grid line is a conductive multilayer line comprising at least two conductive multilayer stacks, wherein the conductive multilayer stacks in the at least two conductive multilayer stacks include: A metal layer comprising copper or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting both the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least a portion of the at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer connecting at least two conductive multilayer stacks in the conductive multilayer line.

5. The symmetrical solar cell as described in claim 4, wherein, The silver contact pads of the first conductive multilayer stack in the at least two conductive multilayer stacks of the at least one fine grid line are separated from the silver contact pads of the second conductive multilayer stacks by a distance of 200 µm to 2 mm, 300 µm to 2 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm.

6. An asymmetric solar cell, comprising: A silicon substrate having a front surface and a rear surface, the front surface being a light-facing surface, wherein the rear surface is opposite to the light-facing surface; At least one passivation layer directly on at least a portion of the rear surface of the silicon substrate; At least one first fine grid line on at least a portion of the rear surface of the silicon substrate; At least one second fine grid line on at least a portion of the rear surface of the silicon substrate; Wherein, the at least one first fine grid line or the at least one second fine grid line is a first conductive multilayer line comprising at least two conductive multilayer stacks; Wherein, the conductive multilayer stack in the at least two conductive multilayer stacks includes: A metal layer comprising copper or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting both the metal layer and the silver contact pad; The glass paste sublayer of the conductive multilayer stack contacts the back surface of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and Wherein, the metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the first conductive multilayer line.

7. The asymmetric solar cell as claimed in claim 6, wherein, The silver contact pads of the first conductive multilayer stack in the at least two conductive multilayer stacks of the at least one first fine grid line are separated from the silver contact pads of the second conductive multilayer stacks by a distance of 200 µm to 2 mm, 300 µm to 2 mm, 300 µm to 1 mm, 400 µm to 1 mm, or 400 µm to 900 µm.

8. A solar cell module, comprising: First solar cell and second solar cell; An interconnect connecting the first solar cell and the second solar cell; Wherein, the first solar cell and the second solar cell include: A doped silicon substrate having a front surface and a rear surface, wherein the front surface is a light-facing surface and the rear surface is opposite to the light-facing surface; At least one passivation layer directly on at least a portion of the front and / or rear surfaces of the doped silicon substrate; and At least one fine grid line on a portion of the front and / or rear surface of the doped silicon substrate; Wherein, the at least one fine grid line is a conductive multilayer line comprising at least two conductive multilayer stacks, wherein the conductive multilayer stacks in the at least two conductive multilayer stacks include: A metal layer comprising copper or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer is provided between the metal layer and the silver contact pads, and contacts both the metal layer and the silver contact pads; and The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, contacts at least one passivation layer, or contacts a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer of the at least two conductive multilayer stacks that connect the conductive multilayer lines.

9. A solar cell module, comprising: First solar cell and second solar cell; An interconnect connecting the first solar cell and the second solar cell; Wherein, the first solar cell and the second solar cell include: A silicon substrate having a front surface and a rear surface, the front surface being a light-facing surface, wherein the rear surface is opposite to the light-facing surface; At least one passivation layer directly on at least a portion of the rear surface of the silicon substrate; At least one first fine grid line on at least a portion of the rear surface of the silicon substrate; and At least one second fine grid line on at least a portion of the rear surface of the silicon substrate; Wherein, at least one of the at least one first fine mesh line or the at least one second fine mesh line is a first conductive multilayer line comprising at least two conductive multilayer stacks; and Wherein, the conductive multilayer stack in the at least two conductive multilayer stacks includes: A metal layer comprising copper or coated aluminum; A silver contact pad, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; and A solderable layer, the solderable layer being between the metal layer and the silver contact pad and contacting both the metal layer and the silver contact pad; Wherein, the glass paste sublayer of the conductive multilayer stack is on the silicon substrate, on the at least one passivation layer, or on a combination thereof; and The metal layer of the conductive multilayer stack is a continuous layer connecting the at least two conductive multilayer stacks.

10. A method for forming a conductive multilayer stack, comprising: A silicon substrate is provided, the silicon substrate having at least one passivation layer on the front and / or rear surface of the silicon substrate; A silver contact pad is formed, the silver contact pad comprising a silver sublayer and a glass paste sublayer, wherein the silver layer is on the glass paste sublayer; A solderable layer is formed by applying solderable paste to the silver contact pads; A metal layer comprising copper or coated aluminum is applied to the solderable layer; and The metal layer is heated to mechanically bond the metal layer to the solderable layer and the solderable layer to the silver contact pads; The glass paste sublayer of the conductive multilayer stack contacts at least a portion of the silicon substrate, at least a portion of the at least one passivation layer, or a combination thereof.

Images