A back contact solar cell and a method of manufacturing the same

Abstract

The application provides a back contact solar cell and a preparation method thereof. The back contact solar cell comprises a silicon substrate, a back surface of the silicon substrate is provided with N regions and P regions which are alternately and spacedly arranged along a first direction, and a self-isolation groove is arranged between adjacent N regions and P regions; the N region comprises a first tunneling layer, a first passivation layer and an n-type doped silicon-based oxide layer; the P region comprises a second tunneling layer, a second passivation layer and a p-type microcrystalline / amorphous mixed phase silicon layer; an insulating oxide layer is arranged in the self-isolation groove; a back surface protection layer is continuously arranged on surfaces of the n-type doped silicon-based oxide layer, the p-type microcrystalline / amorphous mixed phase silicon layer and the insulating oxide layer; and a first electrode and a second electrode are arranged on surfaces of the back surface protection layer corresponding to the N region and the P region respectively. The back contact solar cell provided by the application has excellent passivation performance and carrier selectivity, exhibits extremely low interface state density and surface recombination rate, and can significantly improve the photoelectric conversion efficiency of the cell.

Description

Technical Field

[0001] This application belongs to the field of photovoltaic technology, specifically relating to a back-contact solar cell and its preparation method. Background Technology

[0002] Currently, tunneling oxide passivated back contact solar cells (TBC cells) have become a key research direction for high-efficiency photovoltaic cells due to their advantages of no front-side grating, high optical utilization, and high upper limit of conversion efficiency. Existing TBC cell technologies mainly have the following two improvement trends: 1) Based on the traditional TOPCon back contact structure doped with polycrystalline silicon, relying on low-pressure chemical vapor deposition (LPCVD) to deposit n at high temperature. + / p + 1) Polycrystalline silicon enables carrier transport contacts; 2) Improved structure, namely, pure hydrogenated amorphous silicon (a-Si:H) is used to replace polycrystalline silicon to reduce the process temperature.

[0003] However, existing technologies have the following drawbacks: ① Traditional polycrystalline silicon-based TBC cells require high-temperature LPCVD deposition of polycrystalline silicon at temperatures above 550℃ and high-temperature doping annealing processes, resulting in extremely high energy consumption. High-temperature thermal stress easily leads to warping and damage of thin silicon wafers, reducing cell yield. Simultaneously, polycrystalline silicon thin films suffer from severe edge-wrap plating problems, causing severe edge carrier recombination and hindering improvements in open-circuit voltage. ② While using a-Si:H as a hole collection contact layer lowers the process temperature, pure amorphous silicon thin films have low carrier mobility, high contact resistance, and poor thermal stability, leading to performance degradation over long-term service. ③ Existing TBC cell N / P region isolation structures generally employ photolithography etching and step-by-step thin film deposition processes, which are complex and costly. Furthermore, the isolation region cannot completely eliminate edge interface recombination, leaving significant room for improvement in cell fill factor and open-circuit voltage. ④ TBC cells only use alumina / silicon nitride stacked passivation on the front side, resulting in high interface carrier recombination rates and low long-wavelength light absorption utilization, limiting further breakthroughs in cell conversion efficiency.

[0004] Therefore, how to achieve low-resistance hole collection in the P-region, reduce interface recombination loss, and improve device performance while avoiding the negative impacts of high-temperature energy consumption, thermal stress, and high contact resistance caused by high-temperature processes is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application aims to provide a back-contact solar cell and its fabrication method. On one hand, this application incorporates a tunneling layer and a passivation layer in the N-region and P-region respectively. The combination of these two layers significantly reduces the interface state density and suppresses carrier recombination at the silicon wafer surface and edges. On the other hand, a p-type microcrystalline / amorphous mixed-phase silicon layer is used as a hole collection layer in the P-region. This mixed-phase material combines the high carrier mobility of microcrystalline silicon with the wide bandgap of amorphous silicon, exhibiting excellent electrical conductivity, low contact resistance, and good thermal stability and anti-attenuation capabilities, thus significantly improving the hole collection efficiency and long-term reliability of the cell. Simultaneously, an n-type doped silicon-based oxide layer is used as an electron collection layer in the N-region. This layer, together with the first tunneling layer and the first passivation layer, forms a high-quality electron-selective contact, further reducing interface recombination losses while ensuring low contact resistance. It also forms a good carrier transport match with the mixed-phase silicon layer in the P-region, thereby synergistically improving device performance. Furthermore, a self-isolating groove is provided between adjacent N-regions and P-regions. The groove is filled with an insulating oxide layer and contains no doped conductive film. This structure achieves electrical self-isolation of the N / P regions without complex photolithography processes, fundamentally eliminating edge leakage and interface recombination losses. In summary, the back-contact solar cell provided in this application possesses excellent passivation performance and carrier selectivity, exhibiting extremely low interface state density and surface recombination rate, which can significantly improve the photoelectric conversion efficiency of the cell.

[0006] To achieve this objective, the present application adopts the following technical solution: In a first aspect, this application provides a back-contact solar cell, the back-contact solar cell comprising: A silicon substrate having opposing front and back sides.

[0007] The back side of the silicon substrate is provided with N-regions and P-regions arranged alternately along a first direction, and a self-isolating groove is provided between adjacent N-regions and P-regions; wherein, the first direction is perpendicular to the thickness direction of the silicon substrate.

[0008] The N region, along its thickness direction away from the silicon substrate, sequentially includes a first tunneling layer, a first passivation layer, and an n-type doped silicon-based oxide layer.

[0009] The P-region includes a second tunneling layer, a second passivation layer, and a p-type microcrystalline / amorphous mixed-phase silicon layer along the thickness direction away from the silicon substrate.

[0010] The self-isolating groove is provided with an insulating oxide layer.

[0011] A back protective layer continuously covers the surfaces of the n-type doped silicon-based oxide layer, the p-type microcrystalline / amorphous mixed-phase silicon layer, and the insulating oxide layer.

[0012] The first electrode and the second electrode are respectively disposed on the surfaces of the back protective layer corresponding to the N region and the P region.

[0013] This application employs a tunneling layer and a passivation layer in the N-region and P-region, respectively. The tunneling layer enables selective carrier tunneling transport, while the passivation layer effectively passivates dangling bonds on the silicon substrate surface and shields against field effects. Together, these two elements significantly reduce the interface state density and suppress carrier recombination at the silicon wafer surface and edges. Furthermore, a p-type microcrystalline / amorphous mixed-phase silicon layer is used as a hole collection layer in the P-region. This mixed-phase material combines the high carrier mobility of microcrystalline silicon with the wide bandgap of amorphous silicon, exhibiting excellent conductivity, low contact resistance, and good thermal stability and anti-attenuation capabilities, thus significantly improving the hole collection efficiency and long-term reliability of the battery. Simultaneously, an n-type doped silicon-based oxide layer is used as an electron collection layer in the N-region. This layer, together with the first tunneling layer and the first passivation layer, forms a high-quality electron-selective contact, further reducing interface recombination losses while ensuring low contact resistance. It also forms a good carrier transport match with the mixed-phase silicon layer in the P-region, thereby synergistically improving device performance. Furthermore, a self-isolating groove is provided between adjacent N-regions and P-regions. The groove is filled with an insulating oxide layer and contains no doped conductive film. This structure achieves electrical self-isolation of the N / P regions without complex photolithography processes, fundamentally eliminating edge leakage and interface recombination losses. In summary, the back-contact solar cell provided in this application possesses excellent passivation performance and carrier selectivity, exhibiting extremely low interface state density and surface recombination rate, which can significantly improve the photoelectric conversion efficiency of the cell.

[0014] In this application, the p-type microcrystalline / amorphous mixed-phase silicon layer refers to a mixed layer of microcrystalline and amorphous phases.

[0015] In some embodiments, the first tunneling layer and the second tunneling layer each independently comprise any one or a combination of at least two of the following: a silicon oxynitride layer, a silicon dioxide layer, a titanium oxide layer, an aluminum oxide layer, or a zinc oxide layer.

[0016] In some embodiments, the thickness of the first tunneling layer and the second tunneling layer are each independently 1-2 nm, for example, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm or 2 nm.

[0017] In some embodiments, the first passivation layer comprises alternating layers of silicon oxide and titanium oxide.

[0018] In this application, the alternately stacked silicon oxide and titanium oxide layers serve as the back passivation layer of the N-region, situated between the tunneling layer and the n-type doped silicon-based oxide layer. This helps to reduce the interface state density, effectively suppress carrier recombination on the silicon substrate surface, and simultaneously prevent excessive diffusion of impurities from subsequent doping processes into the silicon substrate, thus stabilizing the tunneling contact interface. Furthermore, this composite stack can regulate the bandgap arrangement, optimize electron transport channels, enhance electron selective transport capabilities, reduce the probability of hole reverse tunneling, and ultimately improve the open-circuit voltage and fill factor of the battery, thereby increasing the photoelectric conversion efficiency of the device.

[0019] In some embodiments, the second passivation layer comprises alternating layers of aluminum oxide and zinc oxide.

[0020] In this application, the alternating alumina and zinc oxide layers serve as the back passivation layer of the P-region, situated between the tunneling layer and the p-type microcrystalline / amorphous mixed-phase silicon layer. This helps overcome the shortcomings of excessively high insulation from a single alumina layer and insufficient passivation capability from a single zinc oxide layer. The alternating multilayer structure balances field passivation effect and carrier conductivity, optimizes the band structure of the tunneling interface, suppresses carrier recombination at the interface, and buffers the interfacial stress caused by the deposition of the upper p-type microcrystalline / amorphous mixed-phase silicon layer, thereby improving the interlayer bonding strength and long-term device reliability.

[0021] In some embodiments, the thickness of the first passivation layer is 5-8 nm, for example, it can be 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm or 8 nm.

[0022] In some embodiments, the thickness of the second passivation layer is 6-10 nm, for example, it can be 6 nm, 7 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm or 10 nm.

[0023] In some embodiments, the thickness ratio of the silicon oxide layer to the titanium oxide layer is (0.08-0.12):(0.06-0.1), wherein the silicon oxide layer is selected in the range of "0.08-0.12", for example, 0.08, 0.09, 0.10, 0.11 or 0.12, and the titanium oxide layer is selected in the range of "0.06-0.1", for example, 0.06, 0.07, 0.08, 0.09 or 0.1.

[0024] In some embodiments, the thickness ratio of the alumina layer to the zinc oxide layer is (0.08-0.12):(0.16-0.2), wherein the alumina layer thickness range of "0.08-0.12" can be, for example, 0.08, 0.09, 0.10, 0.11, or 0.12, and the zinc oxide layer thickness range of "0.16-0.2" can be, for example, 0.16, 0.17, 0.18, 0.19, or 0.2.

[0025] In some embodiments, the n-type doped silicon-based oxide layer includes a phosphorus-doped silicon dioxide layer.

[0026] In some embodiments, the doping concentration of the doping element in the n-type doped silicon-based oxide layer is 5 × 10⁻⁶. 19 cm -3 -2×10 20 cm -3 For example, it could be 5×10 19 cm -3 1×10 20 cm -3 1.5×10 20 cm -3 Or 2×10 20 cm -3 wait.

[0027] In some embodiments, the thickness of the n-type doped silicon-based oxide layer is 30-50 nm, for example, it can be 30 nm, 35 nm, 40 nm, 42 nm, 45 nm, 48 nm or 50 nm.

[0028] In some embodiments, the thickness of the p-type microcrystalline / amorphous mixed-phase silicon layer is 15-25 nm, for example, it can be 15 nm, 18 nm, 20 nm, 22 nm, 23 nm or 25 nm.

[0029] In some embodiments, the volume percentage of the microcrystalline phase in the p-type microcrystalline / amorphous mixed-phase silicon layer is 60-80%, for example, it can be 60%, 65%, 70%, 75% or 80%, etc.

[0030] In the p-type microcrystalline / amorphous mixed-phase silicon layer used in this application, the volume ratio between the microcrystalline phase and the amorphous phase is within a suitable range, which helps to avoid the disadvantages of poor conductivity of pure amorphous silicon and excessive grain boundary defects of pure microcrystalline silicon. By controlling the ratio of the two phases, excellent interface characteristics are maintained while constructing continuous conductive channels, reducing recombination centers inside the film and between layers, improving hole selectivity, suppressing electron backflow, and achieving synergistic optimization of optoelectronic performance and device stability.

[0031] In some embodiments, the p-type microcrystalline / amorphous mixed-phase silicon layer includes a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer.

[0032] This application further specifies that the p-type microcrystalline / amorphous mixed-phase silicon layer is a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer. "Hydrogenation" helps to compensate for the large number of grain boundary defects caused by the coexistence of microcrystalline and amorphous phases. Hydrogen atoms saturate silicon dangling bonds to weaken nonradiative recombination. Furthermore, it can control the band structure of the thin film, optimize hole tunneling extraction conditions, alleviate interface damage introduced by the deposition of the upper thin film, and balance the conductivity of the thin film with the level of interface passivation.

[0033] In some embodiments, the insulating oxide layer comprises a silicon oxide layer.

[0034] In some embodiments, the width of the self-isolating groove in the first direction is 25-45 μm, for example, it can be 25 μm, 30 μm, 35 μm, 40 μm, 42 μm or 45 μm.

[0035] In some embodiments, the depth of the self-isolating groove is 3-5 nm, for example, it can be 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm.

[0036] In some embodiments, the first electrode and the second electrode are each made of a metal independently. For example, they could be silver or the like.

[0037] In some embodiments, the front side of the silicon substrate sequentially includes a passivation barrier layer, a front surface field, and a front antireflection layer along the thickness direction away from the silicon substrate.

[0038] In some embodiments, the passivation barrier layer comprises a silicon oxynitride layer. Exemplarily, the thickness may be, for example, 1.5 nm.

[0039] In some embodiments, the back protective layer includes a silicon hydrogen nitride layer.

[0040] In some embodiments, the thickness of the back protective layer is 60-80 nm, for example, it can be 60 nm, 70 nm or 80 nm.

[0041] In some embodiments, the thickness of the front antireflection layer is 70-90 nm, for example, it can be 70 nm, 75 nm, 80 nm, 85 nm or 90 nm, and the refractive index is 2.05-2.15, for example, it can be 2.05, 2.08, 2.10, 2.12 or 2.15.

[0042] In some embodiments, the thickness of the passivation barrier layer is 1-1.8 nm, for example, it can be 1 nm, 1.2 nm, 1.4 nm, 1.6 nm or 1.8 nm.

[0043] In some embodiments, the front surface field is a gradient front field doped structure.

[0044] In some embodiments, the front surface field is an aluminum-gradient-doped zinc oxide front surface field, wherein the aluminum doping concentration increases in a gradient direction away from the silicon substrate.

[0045] In this application, the front surface field is an aluminum-doped zinc oxide front surface field, wherein the aluminum doping concentration increases in a gradient direction away from the silicon substrate, which helps to optimize carrier transport and improve the open-circuit voltage of the device.

[0046] In some embodiments, the aluminum doping concentration in the aluminum-gradient-doped zinc oxide front surface field is 1 × 10⁻⁶. 19 cm -3 -5×10 19 cm -3 For example, it could be 1×10 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 Or 5×10 19 cm -3 wait.

[0047] In some embodiments, the thickness of the front surface field is 20-40 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm or 40 nm.

[0048] Secondly, this application provides a method for fabricating a back-contact solar cell as described in the first aspect, the method comprising the following steps: Provides silicon substrate.

[0049] A tunneling dielectric layer is fabricated over the entire back surface of the silicon substrate.

[0050] A first passivation layer and an n-type doped silicon-based oxide layer are sequentially formed on the surface of the N-region corresponding to the tunneling dielectric layer, and a second passivation layer and a p-type microcrystalline / amorphous mixed-phase silicon layer are sequentially formed on the surface of the P-region corresponding to the tunneling dielectric layer.

[0051] All functional layers within the preset self-isolation groove area are removed to expose the silicon substrate, forming a self-isolation groove, and then an insulating oxide layer is formed in situ within the self-isolation groove.

[0052] A back protective layer is prepared, which continuously covers the surfaces of the n-type doped silicon-based oxide layer, the p-type microcrystalline / amorphous mixed-phase silicon layer, and the insulating oxide layer.

[0053] A first electrode is fabricated on the surface of the back protective layer corresponding to the N region, and a second electrode is fabricated on the surface of the back protective layer corresponding to the P region.

[0054] The fabrication process provided in this application features low temperature and low energy consumption, high mass production yield, and a maximum process temperature of ≤350℃ throughout the process. It eliminates high-energy-consuming steps such as high-temperature deposition and high-temperature annealing in traditional LPCVD, resulting in a significant reduction in process energy consumption. Without the effect of high-temperature thermal stress, the silicon substrate is less prone to warping and breakage, improving the mass production yield of cells and significantly reducing production costs. It also eliminates complex steps such as traditional photolithography, step-by-step etching, and independent isolation layer deposition, simplifying the process flow, reducing equipment investment and consumable costs, and making it suitable for large-scale industrial mass production.

[0055] In some embodiments, prior to fabricating the tunneling dielectric layer, a patterning preprocessing is performed on the back side of the silicon substrate to form N-region prototypes and P-region prototypes that are alternately spaced along a first direction, as well as self-isolating groove prototypes disposed between adjacent N-region prototypes and P-region prototypes.

[0056] The purpose of the patterning preprocessing in this application is to predefine the P-region and N-region on the back side, and to construct an isolation structure using the groove prototype to prevent leakage caused by lateral conduction between the subsequently formed p-type contact layer and n-type contact layer; it also facilitates the subsequent preparation of passivation layer and selective contact film layer in sections, ensuring that the two types of contact regions independently play the selective transport function of charge carriers, and suppressing edge leakage and lateral recombination of charge carriers.

[0057] In some embodiments, the method for preparing the tunneling dielectric layer includes PECVD, and the process parameters satisfy at least one of the following conditions: process temperature 190-210℃, for example, 190℃, 195℃, 200℃, 205℃ or 210℃; process time 50-70s, for example, 50s, 55s, 60s, 65s or 70s.

[0058] In some embodiments, the deposition method of the p-type microcrystalline / amorphous mixed-phase silicon layer includes PECVD, and the process parameters meet at least one of the following conditions: process temperature 220-280℃, for example, 220℃, 240℃, 250℃, 260℃ or 280℃; process time 5-8min, for example, 5min, 6min, 7min or 8min.

[0059] In some embodiments, a passivation barrier layer, a front surface field of a gradient front field doped structure, and a front antireflection layer are sequentially formed on the front side of the silicon substrate.

[0060] The passivation barrier layer is prepared by PECVD, and the process parameters meet at least one of the following conditions: chamber pressure 8-10 Pa, for example, 8 Pa, 8.5 Pa, 9 Pa, 9.5 Pa or 10 Pa; process temperature 180-200℃, for example, 180℃, 190℃ or 200℃; process time 40-60 s, for example, 40 s, 45 s, 50 s, 55 s or 60 s; radio frequency power 80-100 W, for example, 80 W, 85 W, 90 W, 95 W or 100 W.

[0061] The preparation steps of the front surface field include: alternatingly introducing a zinc source and an oxygen source in an atomic layer deposition reaction chamber to deposit a zinc oxide front surface field; wherein, during each cycle of the zinc oxide front surface field deposition, a doped aluminum source with an increasing flow rate gradient is introduced to achieve an increasing distribution of aluminum doping concentration gradient.

[0062] In some embodiments, the preparation method includes the following steps: (1) Provide a silicon substrate.

[0063] The silicon substrate is pretreated by cleaning.

[0064] (2) Preparation of the front functional layer: A passivation barrier layer with a thickness of 1-1.8 nm is prepared on the front side of the silicon substrate using the PECVD method. The process parameters include: chamber pressure of 8-10 Pa, for example; deposition temperature of 180-200℃; radio frequency power of 80-100W, for example; deposition time of 40-60s; and working gas including silicon source (e.g., silane), nitrogen source (e.g., ammonia) and oxygen source (e.g., nitrous oxide).

[0065] An aluminum-gradient-doped zinc oxide front surface field is prepared on the surface of the passivation barrier layer using the ALD (atomic layer deposition) method; the steps of the ALD method include: Within the atomic layer deposition reaction chamber, the deposition temperature is controlled at 150-160℃ (e.g., 150℃, 155℃, or 160℃), and the deposition time is 120-180s (e.g., 120s, 140s, 160s, or 180s). A zinc source (e.g., diethylzinc) and an oxygen source (e.g., pure water) are alternately introduced to deposit a zinc oxide front surface field with a thickness of 20-40nm. During each cycle of the zinc oxide front surface field deposition, a doped aluminum source (e.g., trimethylaluminum) with an increasing flow gradient is introduced to achieve an aluminum doping concentration increasing from 1×10⁻⁶ along the direction away from the silicon substrate. 19 cm -3 Gradient increments to 5×10 19 cm -3.

[0066] A 70-90 nm thick hydrogenated silicon nitride layer is prepared on the surface of the zinc oxide front surface field using PECVD as a front antireflection layer. The process parameters include: process temperature 200-240℃ (e.g., 200℃, 210℃, 220℃, 230℃, or 240℃); chamber pressure 10-14 Pa (e.g., 10 Pa, 11 Pa, 12 Pa, 13 Pa, or 14 Pa); RF power 160-200 W (e.g., 160 W, 170 W, 180 W, 190 W, or 200 W); and working gases including a silicon source (e.g., silane) and a nitrogen source (e.g., ammonia).

[0067] (3) Using an ultraviolet nanosecond laser device, the laser power is controlled to be 3.5-4.5W (e.g., 3.5W, 3.8W, 4W, 4.2W or 4.5W, etc.), and the scanning speed is 800-1000mm / s (e.g., 800mm / s, 850mm / s, 900mm / s, 950mm / s or 1000mm / s, etc.) to perform patterning preprocessing on the entire back surface of the silicon substrate, so as to alternately etch out N-region prototypes and P-region prototypes that are alternately distributed along the first direction, as well as self-isolating groove prototypes provided between adjacent N-region prototypes and P-region prototypes.

[0068] (4) A silicon oxynitride layer is prepared on the back side of the silicon substrate as a tunneling dielectric layer using the PECVD method. The process parameters include: chamber pressure 8-10 Pa (e.g., 8 Pa, 9 Pa or 10 Pa); deposition temperature 190-210℃ (e.g., 190℃, 200℃ or 210℃); radio frequency power 80-100 W (e.g., 80 W, 90 W or 100 W); deposition time 50-70 s (e.g., 50 s, 60 s or 70 s); working gas includes silicon source (e.g., silane), nitrogen source (e.g., ammonia) and oxygen source (e.g., nitrous oxide).

[0069] (5) Using the ALD method, the deposition temperature is controlled at 140-180℃ (e.g., 140℃, 150℃, 160℃, 170℃ or 180℃, etc.). A silicon oxide layer and a titanium oxide layer are alternately deposited on the surface of the N region corresponding to the tunneling dielectric layer to form a first passivation layer. Then, using the PECVD method, a phosphorus-doped silicon dioxide layer with a thickness of 30-50nm is deposited on the surface of the first passivation layer. The process parameters include: chamber pressure 9-11Pa (e.g., 9Pa, 10Pa or 11Pa, etc.); deposition temperature 190-210℃ (e.g., 190℃, 200℃ or 210℃, etc.); RF power 100-140W (e.g., 100W, 120W or 140W, etc.); deposition time 5-7min (e.g., 5min, 6min or 7min, etc.); working gas includes silicon source (e.g., silane, etc.), oxygen source (e.g., nitrous oxide, etc.) and phosphorus source (e.g., phosphine, etc.).

[0070] Using the ALD method, the deposition temperature is controlled at 150-160℃ (e.g., 150℃, 155℃, or 160℃). Alumina and zinc oxide layers are alternately deposited on the surface of the P-region corresponding to the tunneling dielectric layer to form a second passivation layer. Then, using the PECVD method, a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer with a thickness of 15-25 nm is deposited on the surface of the second passivation layer. Process parameters include: chamber pressure of 10-14 Pa (e.g., 10 Pa, 12 Pa, or 1...). 4Pa, etc.); deposition temperature 220-280℃ (e.g., 220℃, 240℃, 250℃, 260℃ or 280℃, etc.); RF power 80-120W (e.g., 80W, 100W or 120W, etc.); deposition time 5-8min (e.g., 5min, 6min, 7min or 8min, etc.); working gas includes silicon source (e.g., silane, etc.), hydrogen source (e.g., hydrogen, etc.) and boron source (e.g., diborane, etc.).

[0071] (6) Using laser processing, all functional layers in the preset self-isolation groove area are removed to expose the silicon substrate and form a self-isolation groove. Then, in-situ oxidation is performed to generate a silicon dioxide layer in-situ on the surface of the self-isolation groove.

[0072] (7) Using the PECVD method, a hydrogenated silicon nitride layer with a thickness of 60-80 nm is deposited over the entire back surface of the silicon substrate. The process parameters include: chamber pressure 10-12 Pa (e.g., 10 Pa, 11 Pa or 12 Pa); deposition temperature 200-220℃ (e.g., 200℃, 210℃ or 220℃); RF power 140-180 W (e.g., 140 W, 160 W or 180 W); deposition time 6-8 min (e.g., 6 min, 7 min or 8 min).

[0073] (8) Using screen printing, metal electrodes are printed on the back side of the silicon substrate, and then annealed in an inert atmosphere (e.g., nitrogen or argon) at 250-300℃ (e.g., 25 min, 30 min or 35 min) for 25-35 min to complete the fabrication of the back contact solar cell.

[0074] The fabrication process provided in step (6) of this application ensures that there are no doped conductive films in the self-isolation groove, achieving a photolithography-free self-isolation effect in the N and P regions, and completely eliminating edge leakage and recombination losses.

[0075] The numerical range described in this application includes not only the point values ​​listed above, but also any point values ​​between the above numerical ranges that are not listed. Due to space limitations and for the sake of brevity, this application will not exhaustively list the specific point values ​​included in the range.

[0076] Compared with the prior art, this application has the following advantages: This application employs a tunneling layer and a passivation layer in the N-region and P-region, respectively. The tunneling layer enables selective carrier tunneling transport, while the passivation layer effectively passivates dangling bonds on the silicon substrate surface and shields against field effects. Together, these two elements significantly reduce the interface state density and suppress carrier recombination at the silicon wafer surface and edges. Furthermore, a p-type microcrystalline / amorphous mixed-phase silicon layer is used as a hole collection layer in the P-region. This mixed-phase material combines the high carrier mobility of microcrystalline silicon with the wide bandgap of amorphous silicon, exhibiting excellent conductivity, low contact resistance, and good thermal stability and anti-attenuation capabilities, thus significantly improving the hole collection efficiency and long-term reliability of the battery. Simultaneously, an n-type doped silicon-based oxide layer is used as an electron collection layer in the N-region. This layer, together with the first tunneling layer and the first passivation layer, forms a high-quality electron-selective contact, further reducing interface recombination losses while ensuring low contact resistance. It also forms a good carrier transport match with the mixed-phase silicon layer in the P-region, thereby synergistically improving device performance. Furthermore, a self-isolating groove is provided between adjacent N-regions and P-regions. The groove is filled with an insulating protective layer and contains no doped conductive film. This structure achieves electrical self-isolation of the N / P regions without complex photolithography processes, fundamentally eliminating edge leakage and interface recombination losses. In summary, the back-contact solar cell provided in this application possesses excellent passivation performance and carrier selectivity, exhibiting extremely low interface state density and surface recombination rate, which can significantly improve the photoelectric conversion efficiency of the cell.

[0077] The fabrication process provided in this application features low temperature and low energy consumption, high mass production yield, and a maximum process temperature of ≤350℃ throughout the process. It eliminates high-energy-consuming steps such as high-temperature deposition and high-temperature annealing in traditional LPCVD, resulting in a significant reduction in process energy consumption. Without the effect of high-temperature thermal stress, the silicon substrate is less prone to warping and breakage, improving the mass production yield of cells and significantly reducing production costs. It also eliminates complex steps such as traditional photolithography, step-by-step etching, and independent isolation layer deposition, simplifying the process flow, reducing equipment investment and consumable costs, and making it suitable for large-scale industrial mass production. Attached Figure Description

[0078] Figure 1 This is a schematic diagram of the structure of the back-contact solar cell provided in Embodiment 1 of this application.

[0079] Figure 2 This is a schematic diagram of the back-contact solar cell provided in Comparative Example 1 of this application.

[0080] Wherein, 1-silicon substrate; 2-first tunneling layer; 3-second tunneling layer; 4-first passivation layer; 5-second passivation layer; 6-n-type doped silicon-based oxide layer; 7-p-type microcrystalline / amorphous mixed-phase silicon layer; 8-insulating oxide layer; 9-backside protective layer; 11-silicon substrate; 12-first tunneling oxide layer; 13-second tunneling oxide layer; 14-n-type doped polycrystalline silicon layer; 15-p-type doped polycrystalline silicon layer; 16-backside passivation layer; 17-backside antireflection layer. Detailed Implementation

[0081] The technical solution of this application will be further described below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely to help understand this application and should not be regarded as specific limitations on this application.

[0082] The scope of this application can be defined by lower and upper limits. The selected lower and upper limits define the boundaries of a specific range. The range defined in this way can be defined by the inclusion or exclusion of endpoints. Any endpoint can be independently selected for inclusion or exclusion, and all lower and upper limits can be arbitrarily combined to form new ranges. That is, any lower limit can be combined with any upper limit to form a valid range. For example, if the ranges of 60~120 and 80~110 are listed for specific parameters, it should be understood that the ranges of 60~110 and 80~120 also fall within the scope of this application. In addition, if the minimum range values ​​1 and 2 are listed, and the maximum range values ​​3, 4 and 5 are also listed, then all ranges of 1~3, 1~4, 1~5, 2~3, 2~4 and 2~5 fall within the scope of this application. In this application, the numerical range "a~b" represents a shortened representation of any combination of real numbers between a and b, where a and b are both real numbers. For example, the numerical range "0~5" means that all real numbers between 0 and 5 have been fully listed in this document, and "0~5" is only a shortened representation of this set of numerical combinations. When a parameter is expressed as an integer ≥2, it is equivalent to listing positive integers that meet the requirements, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, etc. When a parameter is expressed as an integer selected from "2~10", it is equivalent to listing any integer among 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0083] In this application, "at least two combinations" refers to a quantity greater than or equal to 2 unless otherwise specified. For example, "any one or at least two combinations" means any one of the listed items, or a combination of at least two of the listed items formed in a manner that does not conflict and enables the implementation of this application. In this application, unless otherwise specified, the features or solutions corresponding to "and / or" cover any one of two or more related listed items, as well as any and all combinations of the related listed items. The arbitrary and all combinations include any two related listed items, any more related listed items, or a combination of all related listed items. For example, "A and / or B" represents a set consisting of A, B, and combinations of A and B, where "containing A and / or B" can be understood, depending on the context of the statement, as containing A, containing B, or simultaneously containing both A and B. In this application, "optional" means that the corresponding feature, component, step or solution is not necessary, that is, it is selected from either "with" or "without". If there are multiple "optional" limitations in a technical solution, unless otherwise specified and there is no technical conflict or mutual constraint, each "optional" limitation is independent and does not affect the others.

[0084] In this application, technical features or solutions described using open-ended terms such as "comprising" or "including" do not exclude additional non-conflicting elements beyond those listed unless otherwise specified. They are considered to disclose both closed-ended features or solutions consisting solely of the listed elements and open-ended features or solutions that may include additional non-conflicting elements beyond the listed elements. For example, if A includes a1, a2, and a3, unless otherwise specified, this means that A can consist only of a1, a2, and a3, or it can include other non-conflicting elements based on a1, a2, and a3. This corresponds to the disclosure of technical solutions such as "A consists of a1, a2, and a3," "A is selected from a1, a2, and a3," and "A not only includes a1, a2, and a3, but may also include other non-conflicting elements." All embodiments and optional embodiments of this application, unless otherwise specified and without technical conflict, can be combined to form new technical solutions, and such combinations fall within the scope of this application. The term "embodiment" as used in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment or implementation of this application. The appearance of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can explicitly and implicitly understand that the embodiments described in this application can be combined with other embodiments that do not conflict with existing technologies. The ordinal numbers "first," "second," "third," and "fourth," etc., used in this application in the expressions "first aspect," "second aspect," "third aspect," and "fourth aspect," are for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly specifying the importance or quantity of the indicated technical features. They serve only as a non-exhaustive enumeration and do not constitute a closed limitation on quantity.

[0085] In this application, the order in which the steps are written in the methods described in the various embodiments does not imply a strict execution order. The actual execution order of each step should be determined according to its function and possible internal logic. Unless otherwise specified, all steps in this application can be executed in the order they are written, or in any order without technical conflict. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) executed sequentially, or it may include steps (b) and (a) executed sequentially. If the method also includes step (c), then step (c) can be added to the method in any order without conflict, including but not limited to the execution order of steps (a), (b), and (c), steps (a), (c), and (b), steps (c), (a), and (b), etc.

[0086] Example 1 This embodiment provides a back-contact solar cell, the structural schematic of which is shown below. Figure 1 As shown, the back-contact solar cell includes: A silicon substrate 1 having a front side and a back side; the silicon substrate 1 is an n-type CZ single crystal silicon wafer.

[0087] The back side of the silicon substrate 1 is provided with N-regions and P-regions arranged alternately along a first direction, and a self-isolating groove is provided between adjacent N-regions and P-regions; wherein, the first direction is perpendicular to the thickness direction of the silicon substrate 1.

[0088] The N region includes, along the thickness direction away from the silicon substrate 1, a first tunneling layer 2, a first passivation layer 4, and an n-type doped silicon-based oxide layer 6 in sequence.

[0089] The P-region includes a second tunneling layer 3, a second passivation layer 5, and a p-type microcrystalline / amorphous mixed-phase silicon layer 7 along the thickness direction away from the silicon substrate 1.

[0090] An insulating oxide layer 8 is provided inside the self-isolating groove.

[0091] The back protective layer 9 continuously covers the surfaces of the n-type doped silicon-based oxide layer 6, the p-type microcrystalline / amorphous mixed-phase silicon layer 7, and the insulating oxide layer 8.

[0092] The first electrode and the second electrode are respectively disposed on the surfaces of the back protective layer 9 corresponding to the N region and the P region.

[0093] The first tunneling layer 2 and the second tunneling layer 3 are both silicon oxynitride layers with a thickness of 1.5 nm. The first passivation layer 4 comprises alternating layers of silicon oxide and titanium oxide, with a single-layer thickness ratio of 0.1:0.08. The thickness of the first passivation layer 4 is 7 nm. The second passivation layer 5 comprises alternating layers of aluminum oxide and zinc oxide, with a single-layer thickness ratio of 0.1:0.18. The thickness of the second passivation layer 5 is 8 nm. The n-type doped silicon-based oxide layer 6 comprises a phosphorus-doped silicon dioxide layer with a doping concentration of 9 × 10⁻⁶. 19 cm -3 The n-type doped silicon-based oxide layer 6 has a thickness of 40 nm; the p-type microcrystalline / amorphous mixed-phase silicon layer 7 has a thickness of 20 nm; in the p-type microcrystalline / amorphous mixed-phase silicon layer 7, the volume percentage of the microcrystalline phase is 70%; the p-type microcrystalline / amorphous mixed-phase silicon layer 7 is doped with boron at a concentration of 5 × 10⁻⁶. 19 cm -3The p-type microcrystalline / amorphous mixed-phase silicon layer 7 is a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer; the insulating oxide layer 8 is a silicon oxide layer with a thickness of 1 nm; the width of the self-isolating groove in the first direction is 35 μm, and the depth of the self-isolating groove is 4 nm; the back protective layer 9 is a hydrogenated silicon nitride layer with a thickness of 70 nm; the first electrode and the second electrode are both Ag electrodes.

[0094] The silicon substrate 1 comprises, along its thickness direction away from the silicon substrate 1, a passivation barrier layer, a front surface field, and a front antireflection layer. The passivation barrier layer is a silicon oxynitride layer with a thickness of 1.4 nm. The front antireflection layer is a silicon oxynitride layer with a thickness of 80 nm and a refractive index of 2.1. The front surface field is a graded-doped front surface field structure, specifically an aluminum-gradient-doped zinc oxide front surface field, wherein the aluminum doping concentration gradually increases along the direction away from the silicon substrate 1, from 1 × 10⁻⁶. 19 cm -3 Increase to 5×10 19 cm -3 The thickness of the front surface field is 30 nm.

[0095] This embodiment also provides a method for fabricating the above-mentioned back-contact solar cell, the method comprising the following steps: (1) An n-type CZ single crystal silicon wafer with a thickness of 135 μm and a resistivity of 3 Ω·cm was selected as the silicon substrate.

[0096] The silicon substrate is subjected to a cleaning pretreatment, which includes sequential alkaline washing (ammonia water + hydrogen peroxide + pure water, temperature 80℃, time 10min), acid washing (hydrochloric acid + hydrogen peroxide + pure water, temperature 70℃, time 8min) and water washing (pure water, time 5min).

[0097] The back side of the silicon substrate was subjected to alkaline polishing (20wt% KOH solution, temperature 87℃, time 5min).

[0098] The front side of the silicon substrate was texturized (the reagents included 4 wt% KOH solution and 2 vol% IPA additive, the texturization temperature was 83℃, and the texturization time was 17 min) to form a composite textured surface structure of micron-level pyramid + submicron-level pyramid, with a front reflectivity of 13%. After texturization, the substrate was washed with water and dried with hot air at 60℃ for 10 min.

[0099] (2) Preparation of the front functional layer: A 1.4 nm thick silicon oxynitride layer was prepared on the front side of the silicon substrate using a low-frequency, low-temperature PECVD method as a passivation barrier layer. The process parameters included: chamber pressure 9 Pa; deposition temperature 190 °C; RF power 90 W; deposition time 50 s; and working gases including silane at a flow rate of 15 sccm, ammonia at a flow rate of 8 sccm, and nitrous oxide at a flow rate of 20 sccm.

[0100] An aluminum gradient-doped zinc oxide front surface field is prepared on the surface of the passivation barrier layer using the ALD method; the steps of the ALD method include: Within the atomic layer deposition reaction chamber, the deposition temperature was controlled at 155°C, and the deposition time was 150 s. Diethylzinc and pure water were alternately introduced to deposit a zinc oxide front surface field with a thickness of 30 nm. During each cycle of the zinc oxide front surface field deposition, trimethylaluminum was introduced with an increasing flow rate gradient to achieve an aluminum doping concentration increasing from 1 × 10⁻⁶ along the direction away from the silicon substrate. 19 cm -3 Gradient increments to 5×10 19 cm -3 .

[0101] A hydrogenated silicon nitride layer with a thickness of 80 nm was prepared on the surface of the zinc oxide front surface field using the PECVD method as a front antireflection layer. The process parameters included: process temperature 220℃; chamber pressure 12 Pa; RF power 180 W; working gas including silane with a flow rate of 25 sccm and ammonia with a flow rate of 60 sccm; and process time 8 min.

[0102] (3) Using a 355nm ultraviolet nanosecond laser device, the laser power is controlled at 4W, the scanning speed is 900mm / s, the repetition frequency is 80kHz, and the spot diameter is 20μm. The entire back surface of the silicon substrate is patterned and pre-processed to alternately etch out N-region prototypes and P-region prototypes that are alternately distributed along the first direction, as well as self-isolation groove prototypes located between adjacent N-region prototypes and P-region prototypes.

[0103] After the graphic pretreatment is completed, Ar plasma is used for cleaning. The process parameters include: power 150W, chamber pressure 15Pa, Ar flow rate 50sccm, and cleaning time 3min.

[0104] (4) A silicon oxynitride layer with a thickness of 1.5 nm was prepared on the back side of the silicon substrate using the PECVD method as a tunneling dielectric layer. The process parameters included: chamber pressure 9 Pa; deposition temperature 200 °C; radio frequency power 90 W; deposition time 60 s; and working gas including silane with a flow rate of 18 sccm, ammonia with a flow rate of 10 sccm and nitrous oxide with a flow rate of 22 sccm.

[0105] (5) Using the ALD method, the deposition temperature is controlled at 160°C. A silicon oxide layer with a thickness of 0.1 nm and a titanium oxide layer with a thickness of 0.08 nm are alternately deposited on the surface of the N region corresponding to the tunneling dielectric layer to form a first passivation layer with a thickness of 7 nm. Then, using the PECVD method, a phosphorus-doped silicon dioxide layer with a thickness of 40 nm is deposited on the surface of the first passivation layer. The process parameters include: chamber pressure 10 Pa; deposition temperature 200°C; RF power 120 W; deposition time 6 min; and working gas including silane with a flow rate of 20 sccm, nitrous oxide with a flow rate of 30 sccm and phosphine with a flow rate of 3 sccm.

[0106] Using the ALD method, with the deposition temperature controlled at 155℃, aluminum oxide and zinc oxide layers were alternately deposited on the surface of the P-region corresponding to the tunneling dielectric layer to form a second passivation layer with a thickness of 8nm. Then, using the PECVD method, a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer with a thickness of 20nm was deposited on the surface of the second passivation layer. The process parameters included: chamber pressure 12Pa; deposition temperature 250℃; RF power 100W; deposition time 7min; and working gases including silane at a flow rate of 12sccm, hydrogen at a flow rate of 80sccm, and diborane at a flow rate of 2.5sccm.

[0107] (6) A 355nm ultraviolet laser is used to locally ablate the preset self-isolation groove area. The laser power is 4W and the scanning speed is 900mm / s to remove all functional layers in the groove to expose the silicon substrate and form a self-isolation groove with a depth of 4nm. Then, it is placed in a low-temperature oxidation furnace for in-situ oxidation. The oxidation temperature is 150℃, the oxidation time is 25min, and the oxygen flux is 10L / min to generate a silicon dioxide layer in-situ on the surface of the self-isolation groove.

[0108] (7) A 70 nm thick hydrogenated silicon nitride layer is deposited on the back side of the silicon substrate using the PECVD method. The process parameters include: chamber pressure 11 Pa; deposition temperature 210 °C; RF power 160 W; deposition time 7 min.

[0109] (8) The silver paste was printed using a fully automatic screen printing equipment. The screen mesh number was controlled at 325 mesh, the printing speed at 150 mm / s, and the squeegee pressure at 0.3 MPa. The electrode patterns corresponded to the N-region and the P-region, respectively. Finally, the back contact solar cell was prepared by annealing in a low-temperature annealing furnace under a nitrogen atmosphere. The annealing temperature was controlled at 275℃ and the annealing time was 30 min.

[0110] Example 2 This embodiment provides a back-contact solar cell, the back-contact solar cell comprising: A silicon substrate having opposing front and back sides; the silicon substrate is an n-type CZ single-crystal silicon wafer.

[0111] The back side of the silicon substrate is provided with N-regions and P-regions arranged alternately along a first direction, and a self-isolating groove is provided between adjacent N-regions and P-regions; wherein, the first direction is perpendicular to the thickness direction of the silicon substrate.

[0112] The N region, along its thickness direction away from the silicon substrate, sequentially includes a first tunneling layer, a first passivation layer, and an n-type doped silicon-based oxide layer.

[0113] The P-region includes a second tunneling layer, a second passivation layer, and a p-type microcrystalline / amorphous mixed-phase silicon layer along the thickness direction away from the silicon substrate.

[0114] The self-isolating groove is provided with an insulating oxide layer.

[0115] A back protective layer continuously covers the surfaces of the n-type doped silicon-based oxide layer, the p-type microcrystalline / amorphous mixed-phase silicon layer, and the insulating oxide layer.

[0116] The first electrode and the second electrode are respectively disposed on the surfaces of the back protective layer corresponding to the N region and the P region.

[0117] The first and second tunneling layers are both silicon oxynitride layers with a thickness of 1 nm. The first passivation layer comprises alternating layers of silicon oxide and titanium oxide, with a single-layer thickness ratio of 0.08:0.1. The thickness of the first passivation layer is 5 nm. The second passivation layer comprises alternating layers of aluminum oxide and zinc oxide, with a single-layer thickness ratio of 0.08:0.16. The thickness of the second passivation layer is 6 nm. The n-type doped silicon-based oxide layer comprises a phosphorus-doped silicon dioxide layer with a doping concentration of 5 × 10⁻⁶. 19 cm -3 The thickness of the n-type doped silicon-based oxide layer is 30 nm; the thickness of the p-type microcrystalline / amorphous mixed-phase silicon layer is 15 nm; the volume percentage of the microcrystalline phase in the p-type microcrystalline / amorphous mixed-phase silicon layer is 60%; the p-type microcrystalline / amorphous mixed-phase silicon layer is doped with boron at a concentration of 3 × 10⁻⁶. 19 cm -3 -; The p-type microcrystalline / amorphous mixed-phase silicon layer is a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer; the insulating oxide layer is a silicon oxide layer with a thickness of 0.8 nm; the width of the self-isolating groove in the first direction is 25 μm, and the depth of the self-isolating groove is 3 nm; the back protective layer is a hydrogenated silicon nitride layer with a thickness of 60 nm; the first electrode and the second electrode are both Ag electrodes.

[0118] The silicon substrate comprises, along its thickness direction away from the silicon substrate, a passivation barrier layer, a front surface field, and a front antireflection layer. The passivation barrier layer is a silicon oxynitride layer with a thickness of 1 nm. The front antireflection layer is a silicon oxynitride layer with a thickness of 70 nm and a refractive index of 2.05. The front surface field is a graded-doped front field structure, specifically an aluminum-gradient-doped zinc oxide front surface field, wherein the aluminum doping concentration gradually increases along the direction away from the silicon substrate, from 1 × 10⁻⁶. 19 cm -3 Increase to 5×10 19 cm -3 The thickness of the front surface field is 20 nm.

[0119] This embodiment also provides a method for fabricating the above-mentioned back-contact solar cell, the method comprising the following steps: (1) An n-type CZ single crystal silicon wafer with a thickness of 135 μm and a resistivity of 3 Ω·cm was selected as the silicon substrate.

[0120] The silicon substrate is subjected to a cleaning pretreatment, which includes sequential alkaline washing (ammonia water + hydrogen peroxide + pure water, temperature 80℃, time 10min), acid washing (hydrochloric acid + hydrogen peroxide + pure water, temperature 70℃, time 8min) and water washing (pure water, time 5min).

[0121] The back side of the silicon substrate was subjected to alkaline polishing (20wt% KOH solution, temperature 87℃, time 5min).

[0122] The front side of the silicon substrate was texturized (the reagents included 4 wt% KOH solution and 2 vol% IPA additive, the texturization temperature was 83℃, and the texturization time was 17 min) to form a composite textured surface structure of micron-level pyramid + submicron-level pyramid, with a front reflectivity of 13%. After texturization, the substrate was washed with water and dried with hot air at 60℃ for 10 min.

[0123] (2) Preparation of the front functional layer: A 1 nm thick silicon oxynitride layer was prepared on the front side of the silicon substrate using a low-frequency, low-temperature PECVD method as a passivation barrier layer. The process parameters included: chamber pressure 9 Pa; deposition temperature 190 °C; RF power 90 W; deposition time 40 s; and working gases including silane at a flow rate of 15 sccm, ammonia at a flow rate of 8 sccm, and nitrous oxide at a flow rate of 20 sccm.

[0124] An aluminum gradient-doped zinc oxide front surface field is prepared on the surface of the passivation barrier layer using the ALD method; the steps of the ALD method include: Within the atomic layer deposition reaction chamber, the deposition temperature was controlled at 150°C, and the deposition time was 180 s. Diethylzinc and pure water were alternately introduced to deposit a zinc oxide front surface field with a thickness of 20 nm. During each cycle of the zinc oxide front surface field deposition, trimethylaluminum was introduced with an increasing flow rate gradient to achieve an aluminum doping concentration increasing from 1 × 10⁻⁶ along the direction away from the silicon substrate. 19 cm -3 Gradient increments to 5×10 19 cm -3 .

[0125] A hydrogenated silicon nitride layer with a thickness of 80 nm was prepared on the surface of the zinc oxide front surface field using the PECVD method as a front antireflection layer. The process parameters included: process temperature 200℃; chamber pressure 10 Pa; RF power 160 W; working gas including silane with a flow rate of 25 sccm and ammonia with a flow rate of 60 sccm; and process time 8 min.

[0126] (3) Using a 355nm ultraviolet nanosecond laser device, the laser power is controlled at 4W, the scanning speed is 900mm / s, the repetition frequency is 80kHz, and the spot diameter is 20μm. The entire back surface of the silicon substrate is patterned and pre-processed to alternately etch out N-region prototypes and P-region prototypes that are alternately distributed along the first direction, as well as self-isolation groove prototypes located between adjacent N-region prototypes and P-region prototypes.

[0127] After the graphic pretreatment is completed, Ar plasma is used for cleaning. The process parameters include: power 150W, chamber pressure 15Pa, Ar flow rate 50sccm, and cleaning time 3min.

[0128] (4) A silicon oxynitride layer with a thickness of 1 nm was prepared on the back side of the silicon substrate using the PECVD method as a tunneling dielectric layer. The process parameters included: chamber pressure 8 Pa; deposition temperature 190 °C; radio frequency power 80 W; deposition time 50 s; and working gas including silane with a flow rate of 18 sccm, ammonia with a flow rate of 10 sccm and nitrous oxide with a flow rate of 22 sccm.

[0129] (5) Using the ALD method, the deposition temperature is controlled at 140°C. A silicon oxide layer with a thickness of 0.08 nm and a titanium oxide layer with a thickness of 0.1 nm are alternately deposited on the surface of the N region corresponding to the tunneling dielectric layer to form a first passivation layer with a thickness of 5 nm. Then, using the PECVD method, a phosphorus-doped silicon dioxide layer with a thickness of 30 nm is deposited on the surface of the first passivation layer. The process parameters include: chamber pressure 10 Pa; deposition temperature 200°C; RF power 120 W; deposition time 5 min; working gas includes silane with a flow rate of 20 sccm, nitrous oxide with a flow rate of 30 sccm and phosphine with a flow rate of 3 sccm.

[0130] Using the ALD method, with the deposition temperature controlled at 150℃, aluminum oxide and zinc oxide layers were alternately deposited on the surface of the P-region corresponding to the tunneling dielectric layer to form a second passivation layer with a thickness of 6nm. Then, using the PECVD method, a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer with a thickness of 15nm was deposited on the surface of the second passivation layer. The process parameters included: chamber pressure 10Pa; deposition temperature 220℃; RF power 80W; deposition time 5min; and working gases including silane at a flow rate of 12sccm, hydrogen at a flow rate of 80sccm, and diborane at a flow rate of 2.5sccm.

[0131] (6) A 355nm ultraviolet laser is used to locally ablate the preset self-isolation groove area. The laser power is 4W and the scanning speed is 900mm / s to remove all functional layers in the groove to expose the silicon substrate and form a self-isolation groove with a depth of 3nm. Then, it is placed in a low-temperature oxidation furnace for in-situ oxidation. The oxidation temperature is 150℃, the oxidation time is 20min, and the oxygen flux is 10L / min to generate a silicon dioxide layer in-situ on the surface of the self-isolation groove.

[0132] (7) A 60 nm thick hydrogenated silicon nitride layer is deposited on the back side of the silicon substrate using the PECVD method. The process parameters include: chamber pressure 11 Pa; deposition temperature 210 °C; RF power 160 W; deposition time 6 min.

[0133] (8) The silver paste was printed using a fully automatic screen printing equipment. The screen mesh number was controlled at 325 mesh, the printing speed at 150 mm / s, and the squeegee pressure at 0.3 MPa. The electrode patterns corresponded to the N-region and the P-region, respectively. Finally, the back contact solar cell was prepared by annealing in a low-temperature annealing furnace under a nitrogen atmosphere. The annealing temperature was controlled at 25°C and the annealing time was 35 min.

[0134] Example 3 This embodiment provides a back-contact solar cell, the back-contact solar cell comprising: A silicon substrate having opposing front and back sides; the silicon substrate is an n-type CZ single-crystal silicon wafer.

[0135] The back side of the silicon substrate is provided with N-regions and P-regions arranged alternately along a first direction, and a self-isolating groove is provided between adjacent N-regions and P-regions; wherein, the first direction is perpendicular to the thickness direction of the silicon substrate.

[0136] The N region, along its thickness direction away from the silicon substrate, sequentially includes a first tunneling layer, a first passivation layer, and an n-type doped silicon-based oxide layer.

[0137] The P-region includes a second tunneling layer, a second passivation layer, and a p-type microcrystalline / amorphous mixed-phase silicon layer along the thickness direction away from the silicon substrate.

[0138] The self-isolating groove is provided with an insulating oxide layer.

[0139] A back protective layer continuously covers the surfaces of the n-type doped silicon-based oxide layer, the p-type microcrystalline / amorphous mixed-phase silicon layer, and the insulating oxide layer.

[0140] The first electrode and the second electrode are respectively disposed on the surfaces of the back protective layer corresponding to the N region and the P region.

[0141] The first and second tunneling layers are both silicon oxynitride layers with a thickness of 2 nm. The first passivation layer comprises alternating layers of silicon oxide and titanium oxide, with a single-layer thickness ratio of 0.12:0.06. The thickness of the first passivation layer is 8 nm. The second passivation layer comprises alternating layers of aluminum oxide and zinc oxide, with a single-layer thickness ratio of 0.12:0.2. The thickness of the second passivation layer is 10 nm. The n-type doped silicon-based oxide layer comprises a phosphorus-doped silicon dioxide layer with a doping concentration of 2 × 10⁻⁶. 20 cm -3 The thickness of the n-type doped silicon-based oxide layer is 50 nm; the thickness of the p-type microcrystalline / amorphous mixed-phase silicon layer is 25 nm; the volume percentage of the microcrystalline phase in the p-type microcrystalline / amorphous mixed-phase silicon layer is 80%; the p-type microcrystalline / amorphous mixed-phase silicon layer is doped with boron at a concentration of 8 × 10⁻⁶. 19 cm -3 The p-type microcrystalline / amorphous mixed-phase silicon layer is a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer; the insulating oxide layer is a silicon oxide layer with a thickness of 1.2 nm; the width of the self-isolating groove in the first direction is 45 μm, and the depth of the self-isolating groove is 5 nm; the back protective layer is a hydrogenated silicon nitride layer with a thickness of 80 nm; the first electrode and the second electrode are both Ag electrodes.

[0142] The silicon substrate comprises, along its thickness direction away from the silicon substrate, a passivation barrier layer, a front surface field, and a front antireflection layer. The passivation barrier layer is a silicon oxynitride layer with a thickness of 1.8 nm. The front antireflection layer is a silicon oxynitride layer with a thickness of 90 nm and a refractive index of 2.15. The front surface field is a graded-doped front surface field structure, specifically an aluminum-gradient-doped zinc oxide front surface field, wherein the aluminum doping concentration gradually increases along the direction away from the silicon substrate, from 1 × 10⁻⁶ to 1 × 10⁻⁶. 19 cm -3 Increase to 5×10 19 cm-3 The thickness of the front surface field is 40 nm.

[0143] This embodiment also provides a method for fabricating the above-mentioned back-contact solar cell, the method comprising the following steps: (1) An n-type CZ single crystal silicon wafer with a thickness of 135 μm and a resistivity of 3 Ω·cm was selected as the silicon substrate.

[0144] The silicon substrate is subjected to a cleaning pretreatment, which includes sequential alkaline washing (ammonia water + hydrogen peroxide + pure water, temperature 80℃, time 10min), acid washing (hydrochloric acid + hydrogen peroxide + pure water, temperature 70℃, time 8min) and water washing (pure water, time 5min).

[0145] The back side of the silicon substrate was subjected to alkaline polishing (20wt% KOH solution, temperature 87℃, time 5min).

[0146] The front side of the silicon substrate was texturized (the reagents included 4 wt% KOH solution and 2 vol% IPA additive, the texturization temperature was 83℃, and the texturization time was 17 min) to form a composite textured surface structure of micron-level pyramid + submicron-level pyramid, with a front reflectivity of 13%. After texturization, the substrate was washed with water and dried with hot air at 60℃ for 10 min.

[0147] (2) Preparation of the front functional layer: A 1.8 nm thick silicon oxynitride layer was prepared on the front side of the silicon substrate using a low-frequency, low-temperature PECVD method as a passivation barrier layer. The process parameters included: chamber pressure 9 Pa; deposition temperature 190 °C; RF power 90 W; deposition time 60 s; and working gases including silane at a flow rate of 15 sccm, ammonia at a flow rate of 8 sccm, and nitrous oxide at a flow rate of 20 sccm.

[0148] An aluminum gradient-doped zinc oxide front surface field is prepared on the surface of the passivation barrier layer using the ALD method; the steps of the ALD method include: Within the atomic layer deposition reaction chamber, the deposition temperature was controlled at 160°C, and the deposition time was 120 s. Diethylzinc and pure water were alternately introduced to deposit a zinc oxide front surface field with a thickness of 40 nm. During each cycle of the zinc oxide front surface field deposition, trimethylaluminum was introduced with an increasing flow rate gradient to achieve an aluminum doping concentration increasing from 1 × 10⁻⁶ along the direction away from the silicon substrate. 19 cm -3 Gradient increments to 5×10 19 cm -3 .

[0149] A hydrogenated silicon nitride layer with a thickness of 80 nm was prepared on the surface of the zinc oxide front surface field using the PECVD method as a front antireflection layer. The process parameters included: process temperature 240℃; chamber pressure 14 Pa; RF power 200 W; working gas including silane with a flow rate of 25 sccm and ammonia with a flow rate of 60 sccm; and process time 8 min.

[0150] (3) Using a 355nm ultraviolet nanosecond laser device, the laser power is controlled at 4W, the scanning speed is 900mm / s, the repetition frequency is 80kHz, and the spot diameter is 20μm. The entire back surface of the silicon substrate is patterned and pre-processed to alternately etch out N-region prototypes and P-region prototypes that are alternately distributed along the first direction, as well as self-isolation groove prototypes located between adjacent N-region prototypes and P-region prototypes.

[0151] After the graphic pretreatment is completed, Ar plasma is used for cleaning. The process parameters include: power 150W, chamber pressure 15Pa, Ar flow rate 50sccm, and cleaning time 3min.

[0152] (4) A silicon oxynitride layer with a thickness of 2 nm was prepared on the back side of the silicon substrate using the PECVD method as a tunneling dielectric layer. The process parameters included: chamber pressure 10 Pa; deposition temperature 210 °C; radio frequency power 100 W; deposition time 70 s; and working gas including silane with a flow rate of 18 sccm, ammonia with a flow rate of 10 sccm and nitrous oxide with a flow rate of 22 sccm.

[0153] (5) Using the ALD method, the deposition temperature is controlled at 180°C. A silicon oxide layer with a thickness of 0.12 nm and a titanium oxide layer with a thickness of 0.06 nm are alternately deposited on the surface of the N region corresponding to the tunneling dielectric layer to form a first passivation layer with a thickness of 8 nm. Then, using the PECVD method, a phosphorus-doped silicon dioxide layer with a thickness of 50 nm is deposited on the surface of the first passivation layer. The process parameters include: chamber pressure 10 Pa; deposition temperature 200°C; RF power 120 W; deposition time 7 min; and working gas including silane with a flow rate of 20 sccm, nitrous oxide with a flow rate of 30 sccm and phosphine with a flow rate of 3 sccm.

[0154] Using the ALD method, with the deposition temperature controlled at 160℃, aluminum oxide and zinc oxide layers were alternately deposited on the surface of the P-region corresponding to the tunneling dielectric layer to form a second passivation layer with a thickness of 10nm. Then, using the PECVD method, a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer with a thickness of 25nm was deposited on the surface of the second passivation layer. The process parameters included: chamber pressure 14Pa; deposition temperature 280℃; RF power 120W; deposition time 8min; and working gases including silane at a flow rate of 12sccm, hydrogen at a flow rate of 80sccm, and diborane at a flow rate of 2.5sccm.

[0155] (6) A 355nm ultraviolet laser is used to locally ablate the preset self-isolation groove area. The laser power is 4W and the scanning speed is 900mm / s to remove all functional layers in the groove to expose the silicon substrate and form a self-isolation groove with a depth of 5nm. Then, it is placed in a low-temperature oxidation furnace for in-situ oxidation. The oxidation temperature is 150℃, the oxidation time is 30min, and the oxygen flux is 10L / min to generate a silicon dioxide layer in-situ on the surface of the self-isolation groove.

[0156] (7) A hydrogenated silicon nitride layer with a thickness of 80 nm was deposited on the back side of the silicon substrate using the PECVD method. The process parameters included: chamber pressure 11 Pa; deposition temperature 210 °C; RF power 160 W; deposition time 8 min.

[0157] (8) The silver paste was printed using a fully automatic screen printing equipment. The screen mesh number was controlled at 325 mesh, the printing speed at 150 mm / s, and the squeegee pressure at 0.3 MPa. The electrode patterns corresponded to the N-region and the P-region, respectively. Finally, the back contact solar cell was annealed in a low-temperature annealing furnace under a nitrogen atmosphere. The annealing temperature was controlled at 300℃ and the annealing time was 25 min to complete the preparation of the back contact solar cell.

[0158] Example 4 The difference between this embodiment and Embodiment 1 is that the first passivation layer is a silicon oxide layer with a thickness of 7 nm.

[0159] The remaining preparation methods and parameters are consistent with those in Example 1.

[0160] Example 5 The difference between this embodiment and Embodiment 1 is that the second passivation layer is an aluminum oxide layer with a thickness of 8 nm.

[0161] The remaining preparation methods and parameters are consistent with those in Example 1.

[0162] Example 6 The difference between this embodiment and embodiment 1 is that the preparation process parameters of the p-type hydrogenated microcrystalline / amorphous mixed phase silicon layer in step (5) are adjusted so that the volume ratio of the microcrystalline phase in the p-type microcrystalline / amorphous mixed phase silicon layer is 50%.

[0163] The remaining preparation methods and parameters are consistent with those in Example 1.

[0164] Example 7 The difference between this embodiment and embodiment 1 is that the preparation process parameters of the p-type hydrogenated microcrystalline / amorphous mixed phase silicon layer in step (5) are adjusted so that the volume ratio of the microcrystalline phase in the p-type microcrystalline / amorphous mixed phase silicon layer is 90%.

[0165] The remaining preparation methods and parameters are consistent with those in Example 1.

[0166] Example 8 The difference between this embodiment and Embodiment 1 is that the front surface field is a zinc oxide front surface field uniformly doped with aluminum, with a doping concentration of 3×10⁻⁶. 19 cm -3 .

[0167] The remaining preparation methods and parameters are consistent with those in Example 1.

[0168] Comparative Example 1 This comparative example provides a back-contact solar cell, the schematic diagram of which is shown below. Figure 2 As shown, the back-contact solar cell includes: The silicon substrate 11 has a front side and a back side; the silicon substrate 11 is an n-type CZ single crystal silicon wafer.

[0169] The back side of the silicon substrate 11 is provided with N-regions and P-regions arranged alternately along a first direction, and an isolation groove is provided between adjacent N-regions and P-regions; wherein, the first direction is perpendicular to the thickness direction of the silicon substrate 11.

[0170] The N region includes a first tunneling oxide layer 12 and an n-type doped polysilicon layer 14 in sequence along the thickness direction away from the silicon substrate 11; the first tunneling oxide layer 12 is a silicon oxide layer.

[0171] The P region includes a second tunneling oxide layer 13 and a p-type doped polysilicon layer 15 along the thickness direction away from the silicon substrate 11; the second tunneling oxide layer 13 is a silicon oxide layer.

[0172] A back passivation dielectric layer continuously covers the surfaces of the n-type doped polysilicon layer 14, the isolation groove, and the p-type doped polysilicon layer 15; the back passivation dielectric layer includes a back passivation layer 16 and a back antireflection layer 17 in sequence along the thickness direction away from the silicon substrate 11; the back passivation layer 16 is an aluminum oxide layer, and the back antireflection layer 17 is a silicon nitride layer.

[0173] A first silver electrode and a second silver electrode are disposed on the surface of the back antireflection layer 17 corresponding to the N region; the first silver electrode is disposed on the surface of the back antireflection layer 17 corresponding to the P region.

[0174] Performance testing 1. Photovoltaic performance tests were conducted on the back-contact solar cells provided in the above embodiments and comparative examples. The test method was as follows: A standard solar simulator was used, and a dedicated photovoltaic IV tester was used to apply a continuously adjustable bias voltage to the BC solar cell, and the corresponding current value was collected simultaneously to generate a current-voltage (IV) curve. The open-circuit voltage, short-circuit current density, fill factor, and photoelectric conversion efficiency were extracted from the curve.

[0175] Test conditions were: AM1.5G, 1000±50W / m 2 25℃, one standard atmosphere.

[0176] 2. Stability tests were conducted on the back-contact solar cells provided in the above embodiments and comparative examples. The test conditions included: 85°C, placement for 1000 hours, and recording of efficiency degradation rate.

[0177] The test results are shown in Table 1.

[0178] Table 1 analyze: As shown in Table 1, this application employs a tunneling layer and a passivation layer in the N-region and P-region respectively. The tunneling layer enables selective carrier tunneling transport, while the passivation layer effectively passivates dangling bonds on the silicon substrate surface and shields against field effects. Together, they significantly reduce the interface state density and suppress carrier recombination at the silicon wafer surface and edges. Furthermore, a p-type microcrystalline / amorphous mixed-phase silicon layer is used as a hole collection layer in the P-region. This mixed-phase material combines the high carrier mobility of microcrystalline silicon with the wide bandgap of amorphous silicon, exhibiting excellent conductivity, low contact resistance, and good thermal stability and anti-attenuation capabilities, thus significantly improving the hole collection efficiency and long-term reliability of the battery. Simultaneously, an n-type doped silicon-based oxide layer is used as an electron collection layer in the N-region. This layer, together with the first tunneling layer and the first passivation layer, forms a high-quality electron-selective contact, further reducing interface recombination losses while ensuring low contact resistance. It also forms a good carrier transport match with the mixed-phase silicon layer in the P-region, thereby synergistically improving device performance. Furthermore, a self-isolating groove is provided between adjacent N-regions and P-regions. The groove is filled with an insulating protective layer and contains no doped conductive film. This structure achieves electrical self-isolation of the N / P regions without complex photolithography processes, fundamentally eliminating edge leakage and interface recombination losses. In summary, the back-contact solar cell provided in this application possesses excellent passivation performance and carrier selectivity, exhibiting extremely low interface state density and surface recombination rate, which can significantly improve the photoelectric conversion efficiency of the cell.

[0179] A comparison of Examples 1 and 4-5 shows that if the first passivation layer is only a silicon oxide layer, there is no composite passivation structure, the thin film passivation capability is insufficient, it is difficult to effectively reduce the interface state density of the silicon substrate, and the carrier tunneling matching becomes worse, increasing the electron transport barrier, which is not conducive to reducing the surface recombination rate and improving the minority carrier lifetime. If the second passivation layer is only an aluminum oxide layer, there is no ZnO synergistic composite passivation structure, the aluminum oxide has poor interface compatibility with the subsequent boron-doped hydrogenated microcrystalline silicon, the interface contact barrier increases, which is not conducive to hole collection, resulting in an increase in contact resistance, and a significant decrease in fill factor and open circuit voltage.

[0180] A comparison of Examples 1 and 6-7 shows that if the volume ratio of the microcrystalline phase in the p-type microcrystalline / amorphous mixed-phase silicon layer is too small, the conductive microcrystalline channels in the film are scarce, the carrier mobility is low, the contact resistance increases significantly, which is not conducive to efficient hole tunneling and collection. If the volume ratio of the microcrystalline phase in the p-type microcrystalline / amorphous mixed-phase silicon layer is too large, the internal grain boundary defects of the film increase, the interface roughness increases, the interface state density increases, and the carrier recombination on the silicon substrate surface is aggravated, which is not conducive to maintaining a high open-circuit voltage.

[0181] As can be seen from the comparison between Example 1 and Example 8, if the front surface field is a zinc oxide front surface field uniformly doped with aluminum, then there is a lack of a doping concentration gradient that gradually changes from the silicon interface to the surface layer, making it difficult to construct a smooth built-in electric field. The carrier interface transport barrier is high, which is not conducive to suppressing carrier recombination at the front interface. At the same time, it will cause a decrease in the collection efficiency of photogenerated carriers corresponding to long-wavelength photons, and both the open-circuit voltage and short-circuit current of the battery will decrease.

[0182] As can be seen from the comparison between Example 1 and Comparative Example 1, the device provided in this application has superior photoelectric performance and stability compared to the conventional TBC battery provided in Comparative Example 1.

[0183] It should be noted that this application illustrates the process method through the above embodiments, but this application is not limited to the above process steps, that is, it does not mean that this application must rely on the above process steps to be implemented. Those skilled in the art should understand that any improvements to this application, equivalent substitutions of the raw materials used in this application, addition of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of this application.

Claims

1. A back-contact solar cell, characterized in that, The back-contact solar cell includes: A silicon substrate having opposing front and back sides; The back side of the silicon substrate is provided with N-regions and P-regions arranged alternately along a first direction, and a self-isolating groove is provided between adjacent N-regions and P-regions; wherein, the first direction is perpendicular to the thickness direction of the silicon substrate; The N region, along the thickness direction away from the silicon substrate, sequentially includes a first tunneling layer, a first passivation layer, and an n-type doped silicon-based oxide layer; The P-region includes a second tunneling layer, a second passivation layer, and a p-type microcrystalline / amorphous mixed-phase silicon layer along the thickness direction away from the silicon substrate; The self-isolating groove is provided with an insulating oxide layer; A back protective layer continuously covers the surfaces of the n-type doped silicon-based oxide layer, the p-type microcrystalline / amorphous mixed-phase silicon layer, and the insulating oxide layer; The first electrode and the second electrode are respectively disposed on the surfaces of the back protective layer corresponding to the N region and the P region.

2. The back-contact solar cell according to claim 1, characterized in that, The first tunneling layer and the second tunneling layer each independently include any one or a combination of at least two of the following: a silicon oxynitride layer, a silicon dioxide layer, a titanium oxide layer, an aluminum oxide layer, or a zinc oxide layer; And / or, the thickness of the first tunneling layer and the second tunneling layer are each independently 1-2 nm; And / or, the first passivation layer comprises alternating layers of silicon oxide and titanium oxide; And / or, the second passivation layer comprises alternating layers of aluminum oxide and zinc oxide; And / or, the thickness of the first passivation layer is 5-8 nm; And / or, the thickness of the second passivation layer is 6-10 nm.

3. The back-contact solar cell according to claim 2, characterized in that, The thickness ratio of the silicon oxide layer to the titanium oxide layer is (0.08-0.12):(0.06-0.1); And / or, the thickness ratio of the alumina layer to the zinc oxide layer is (0.08-0.12):(0.16-0.2); And / or, the n-type doped silicon-based oxide layer includes a phosphorus-doped silicon dioxide layer; And / or, in the n-type doped silicon-based oxide layer, the doping concentration of the doping element is 5 × 10⁻⁶. 19 cm -3 -2×10 20 cm -3 ; And / or, the thickness of the n-type doped silicon-based oxide layer is 30-50 nm.

4. The back-contact solar cell according to any one of claims 1-3, characterized in that, The thickness of the p-type microcrystalline / amorphous mixed-phase silicon layer is 15-25 nm; And / or, in the p-type microcrystalline / amorphous mixed-phase silicon layer, the volume percentage of the microcrystalline phase is 60-80%; And / or, the p-type microcrystalline / amorphous mixed-phase silicon layer includes a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer.

5. The back-contact solar cell according to any one of claims 1-4, characterized in that, The insulating oxide layer includes a silicon oxide layer; And / or, the width of the self-isolating groove in the first direction is 25-45 μm; And / or, the depth of the self-isolating groove is 3-5 nm; And / or, the first electrode and the second electrode are each made of metal independently; And / or, the front side of the silicon substrate includes, in sequence along the thickness direction away from the silicon substrate, a passivation barrier layer, a front surface field, and a front antireflection layer.

6. The back-contact solar cell according to claim 5, characterized in that, The back protective layer includes a hydrogenated silicon nitride layer; And / or, the thickness of the back protective layer is 60-80 nm; And / or, the thickness of the front antireflection layer is 70-90 nm, and the refractive index is 2.05-2.15; And / or, the thickness of the passivation barrier layer is 1-1.8 nm; And / or, the front surface field is a gradient front field doped structure; And / or, the front surface field is an aluminum-gradient-doped zinc oxide front surface field, wherein the aluminum doping concentration increases in a gradient direction away from the silicon substrate; And / or, in the aluminum-gradient-doped zinc oxide front surface field, the aluminum doping concentration is 1 × 10⁻⁶. 19 cm -3 -5×10 19 cm -3 ; And / or, the thickness of the front surface field is 20-40 nm.

7. A method for preparing a back-contact solar cell as described in any one of claims 1-6, characterized in that, The preparation method includes the following steps: Provide silicon substrate; A tunneling dielectric layer is fabricated over the entire back surface of the silicon substrate; A first passivation layer and an n-type doped silicon-based oxide layer are sequentially formed on the surface of the N-region corresponding to the tunneling dielectric layer, and a second passivation layer and a p-type microcrystalline / amorphous mixed-phase silicon layer are sequentially formed on the surface of the P-region corresponding to the tunneling dielectric layer. All functional layers within the preset self-isolation groove area are removed to expose the silicon substrate, forming a self-isolation groove, and then an insulating oxide layer is formed in situ within the self-isolation groove. A back protective layer is prepared, which continuously covers the surfaces of the n-type doped silicon-based oxide layer, the p-type microcrystalline / amorphous mixed-phase silicon layer, and the insulating oxide layer; A first electrode is fabricated on the surface of the back protective layer corresponding to the N region, and a second electrode is fabricated on the surface of the back protective layer corresponding to the P region.

8. The preparation method according to claim 7, characterized in that, Before preparing the tunneling dielectric layer, a patterning preprocessing is performed on the back side of the silicon substrate to form N-region prototypes and P-region prototypes that are alternately distributed along a first direction, as well as self-isolating groove prototypes provided between adjacent N-region prototypes and P-region prototypes. And / or, the method for preparing the tunneling dielectric layer includes PECVD, and the process parameters meet the following conditions: process temperature 190-210℃; process time 50-70s; And / or, the deposition method of the p-type microcrystalline / amorphous mixed-phase silicon layer includes PECVD, and the process parameters meet at least one of the following conditions: process temperature 220-280℃; process time 5-8min.

9. The preparation method according to claim 7 or 8, characterized in that, A passivation barrier layer, a front surface field with a gradient front field doping structure, and a front antireflection layer are sequentially fabricated on the front side of the silicon substrate. The passivation barrier layer is prepared by PECVD, and the process parameters meet the following conditions: chamber pressure 8-10 Pa; process temperature 180-200℃; process time 40-60 s; radio frequency power 80-100 W. The preparation steps of the front surface field include: alternatingly introducing a zinc source and an oxygen source in an atomic layer deposition reaction chamber to deposit a zinc oxide front surface field; wherein, during each cycle of the zinc oxide front surface field deposition, a doped aluminum source with an increasing flow rate gradient is introduced to achieve an increasing distribution of aluminum doping concentration gradient.

10. The preparation method according to any one of claims 7-9, characterized in that, The preparation method includes the following steps: (1) Provide a silicon substrate; The silicon substrate is pretreated by cleaning. (2) Preparation of the front functional layer: A passivation barrier layer with a thickness of 1-1.8 nm was prepared on the front side of the silicon substrate using the PECVD method. The working gas included a silicon source, a nitrogen source, and an oxygen source. An aluminum gradient-doped zinc oxide front surface field is prepared on the surface of the passivation barrier layer using the ALD method; the steps of the ALD method include: Within the atomic layer deposition reaction chamber, the deposition temperature is controlled at 150-160℃, and the deposition time is 120-180s. Zinc and oxygen sources are alternately introduced to deposit a zinc oxide front surface field with a thickness of 20-40nm. During each cycle of the zinc oxide front surface field deposition, a doped aluminum source with an increasing flow rate gradient is introduced to achieve an aluminum doping concentration increasing from 1×10⁻⁶ along the direction away from the silicon substrate. 19 cm -3 Gradient increments to 5×10 19 cm -3 ; A hydrogenated silicon nitride layer with a thickness of 70-90 nm was prepared on the surface of the zinc oxide front surface field using the PECVD method as a front antireflection layer. (3) Using an ultraviolet nanosecond laser device, the entire back surface of the silicon substrate is patterned and pre-processed to alternately etch out N-region prototypes and P-region prototypes that are alternately distributed along the first direction, as well as self-isolating groove prototypes provided between adjacent N-region prototypes and P-region prototypes. (4) A silicon oxynitride layer is prepared on the back side of the silicon substrate using PECVD as a tunneling dielectric layer. The process parameters include: chamber pressure 8-10 Pa; deposition temperature 190-210 °C; radio frequency power 80-100 W; deposition time 50-70 s; and working gases including silicon source, nitrogen source and oxygen source. (5) Using the ALD method, silicon oxide and titanium oxide layers are alternately deposited on the surface of the N region corresponding to the tunneling dielectric layer to form a first passivation layer; then using the PECVD method, a phosphorus-doped silicon dioxide layer with a thickness of 30-50 nm is deposited on the surface of the first passivation layer. Using the ALD method, alternating layers of aluminum oxide and zinc oxide are deposited on the surface of the P-region corresponding to the tunneling dielectric layer to form a second passivation layer. Then, using the PECVD method, a p-type hydrogenated microcrystalline / amorphous mixed-phase silicon layer with a thickness of 15-25 nm is deposited on the surface of the second passivation layer. The process parameters include: chamber pressure 10-14 Pa; deposition temperature 220-280℃; RF power 80-120 W; deposition time 5-8 min; and working gases including silicon source, hydrogen source, and boron source. (6) Using laser processing, all functional layers in the preset self-isolation groove area are removed to expose the silicon substrate and form a self-isolation groove. Then, in-situ oxidation is performed to generate a silicon dioxide layer in-situ on the surface of the self-isolation groove. (7) A hydrogenated silicon nitride layer with a thickness of 60-80 nm is deposited over the entire back surface of the silicon substrate using the PECVD method; (8) Using screen printing, metal electrodes are printed on the back side of the silicon substrate, and then annealed in an inert atmosphere at 250-300°C for 25-35 minutes to complete the preparation of the back contact solar cell.

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