A solar cell and a method of manufacturing the same

Abstract

The application discloses a solar cell and a preparation method thereof. The solar cell can include: a crystalline silicon substrate; a first carrier collection layer arranged on the front surface of the crystalline silicon substrate, the first carrier collection layer having an opposite conductive type to that of the crystalline silicon substrate; a radiation-resistant passivation layer arranged on the side of the first carrier collection layer away from the crystalline silicon substrate, the radiation-resistant passivation layer being used for passivating the first carrier collection layer and blocking high-energy particles for the crystalline silicon substrate and the first carrier collection layer; and a first electrode penetrating the radiation-resistant passivation layer in the thickness direction and being electrically connected with the first carrier collection layer. The solar cell can effectively reduce the damage of high-energy particles to the functional layer of the solar cell, so as to prolong the service life of the solar cell.

Description

Technical Field

[0001] This invention relates to a solar cell and a method for its fabrication. Background Technology

[0002] The working principle of a solar cell is mainly as follows: light enters the front of the solar cell, causing photons to reach the crystalline silicon substrate. The photon energy is absorbed and utilized by the silicon substrate, generating electron-hole pairs, which are then separated and collected by the carrier collection layer. However, in addition to photons that can be absorbed and utilized by the silicon substrate, sunlight also contains high-energy particles. Especially in the space environment, there are even more high-energy space particles. These high-energy particles or space particles can easily bombard the functional layer and silicon substrate of the solar cell, causing lattice damage and increased defects, leading to severe radiation degradation in the solar cell. Summary of the Invention

[0003] In view of this, the present invention provides a solar cell and a method for preparing the same. The solar cell provides a radiation-resistant passivation layer on the side of the first carrier collection layer away from the crystalline silicon substrate. By blocking high-energy particles through the radiation-resistant passivation layer, the solar cell can avoid being bombarded and damaged by high-energy particles, thereby achieving radiation protection for the solar cell and reducing or even avoiding radiation attenuation of the functional layer and the crystalline silicon substrate of the solar cell.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a solar cell, comprising: Crystalline silicon substrate; A first carrier collection layer is disposed on the front side of the crystalline silicon substrate, and the conductivity type of the first carrier collection layer is opposite to that of the crystalline silicon substrate. A radiation-resistant passivation layer is disposed on the side of the first carrier collection layer away from the crystalline silicon substrate, for passivating the first carrier collection layer and blocking high-energy particles for the crystalline silicon substrate and the first carrier collection layer; The first electrode penetrates the radiation-resistant passivation layer in the thickness direction and is electrically connected to the first carrier collection layer.

[0005] Secondly, embodiments of the present invention provide a method for preparing a solar cell, comprising: Step S1: Provide a crystalline silicon substrate; Step S2: A first carrier collection layer and a radiation passivation layer are sequentially stacked on the front side of the crystalline silicon substrate, wherein the conductivity type of the first carrier collection layer is opposite to that of the crystalline silicon substrate; Step S3: Form a first electrode that penetrates the radiation-resistant passivation layer in the thickness direction and is electrically connected to the first carrier collection layer.

[0006] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: by providing an anti-radiation passivation layer on the side of the first carrier collection layer away from the crystalline silicon substrate on the front side of the crystalline silicon substrate, the anti-radiation passivation layer can passivate the first carrier collection layer and reduce defects in the solar cell. On the other hand, the anti-radiation passivation layer blocks high-energy particles from the crystalline silicon substrate and the first carrier collection layer, thereby reducing or even avoiding the bombardment and damage of high-energy particles to the crystalline silicon substrate and the first carrier collection layer, achieving anti-radiation protection for the solar cell, and reducing or even avoiding radiation attenuation of the functional layer and the crystalline silicon substrate of the solar cell. Attached Figure Description

[0007] Figure 1 This is a partial cross-sectional structural diagram of a solar cell with the first structure provided in the embodiments of the present invention; Figure 2 This is a partial cross-sectional structural diagram of a solar cell with the second structure provided in an embodiment of the present invention; Figure 3 This is a partial cross-sectional structural diagram of a solar cell with the third structure provided in this embodiment of the invention; Figure 4 This is a schematic diagram of the main process of a method for preparing a solar cell according to an embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the structural changes corresponding to each step in the preparation method according to an embodiment of the present invention; Figure 6 This is a schematic cross-sectional view of the structural changes corresponding to step S2 in the preparation method according to an embodiment of the present invention; Figure 7 This is a schematic cross-sectional view of the structural changes corresponding to steps S1, S1', and S2 in the preparation method according to an embodiment of the present invention.

[0008] The attached figures are labeled as follows: 10 - Crystalline silicon substrate; 20 - First carrier collection layer; 30 - Radiation-resistant passivation layer; 31 - Semiconductor layer; 32 - First passivation layer; 40 - First electrode; 50 - Anti-reflection layer; 60 - Second carrier collection layer; 61 - Second passivation layer; 62 - Doped polycrystalline silicon layer; 70 - Second electrode; 80 - Third passivation layer; A - Template. Detailed Implementation

[0009] Existing front-side PN junction solar cells (hereinafter referred to as existing solar cells) mainly consist of a carrier collection layer with the opposite conductivity type to that of the crystalline silicon substrate 10 on the front side of the substrate 10, and an anti-reflection layer on the carrier collection layer. The purpose of the anti-reflection layer is to reduce light reflection loss and allow more light to enter the crystalline silicon substrate 10. However, the light entering the crystalline silicon substrate 10 contains not only photons that can be absorbed and utilized by the substrate 10, but also a large number of high-energy particles. These high-energy particles bombard and damage the carrier collection layer and the crystalline silicon substrate 10, leading to increased defects and carrier recombination in the front-side PN junction solar cell, resulting in reduced photoelectric conversion efficiency and lifespan. Especially in the space environment, which contains a large number of high-energy particles, if existing front-side PN junction solar cells are directly applied to the space environment, the carrier collection layer and the crystalline silicon substrate 10 will be bombarded by a large number of high-energy particles, leading to severe radiation attenuation, reduced photoelectric conversion efficiency, and a significantly shortened on-orbit lifespan.

[0010] To address the aforementioned problems of existing solar cells, embodiments of the present invention provide a novel solar cell structure and a new method for fabricating the novel solar cell structure.

[0011] It should be noted that the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," and "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0012] In the embodiments of the present invention, the front side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 facing sunlight during the operation of the solar cell. The back side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 facing away from sunlight during the operation of the solar cell.

[0013] Unless otherwise contradictory, the doping concentration and content involved in the embodiments of the present invention are generally calculated as the amount of activated doping atoms and / or doping ions. Specifically, the doping concentration involved in the embodiments of the present invention generally refers to the number of doping atoms and / or doping ions contained in a unit volume or unit area of ​​any cross-section of a certain film layer or structure (such as the first doped diffusion layer). The content of doped atoms and / or doped ions involved in the embodiments of the present invention generally refers to the number of doped atoms and / or doped ions per 1 million parts of silicon (the silicon unit of measurement is generally the number or the amount of substance) in a certain film layer or structure (such as the first doped diffusion layer). For example, if the content of doped atoms and / or doped ions in a certain film layer or structure is X ppm, it means that X or X moles of doped atoms and / or doped ions are doped per 1 million silicon atoms or 1 million moles of silicon.

[0014] In the embodiments of the present invention, one film layer is located on another film layer. This film layer may be located on the side of the other film layer away from the crystalline silicon substrate 10. In the absence of other conflicting descriptions, the one film layer and the other film layer may be in direct contact, and other film layers may also be included between the one film layer and the other film layer.

[0015] In the embodiments of this invention, an n-type doped or n-type conductive film generally means that the film is doped with n-type doped atoms such as phosphorus atoms, antimony atoms, or arsenic atoms. A p-type doped or p-type conductive film generally means that the film is doped with p-type doped atoms such as boron atoms or gallium atoms.

[0016] Specifically, embodiments of the present invention provide a solar cell with a novel structure. More specifically, as... Figures 1 to 3 As shown, the solar cell may include: a crystalline silicon substrate 10, a first carrier collection layer 20, a radiation-resistant passivation layer 30, and a first electrode 40, wherein, The first carrier collection layer 20 is disposed on the front side of the crystalline silicon substrate 10, and the conductivity type of the first carrier collection layer 20 is opposite to that of the crystalline silicon substrate 10. The radiation-resistant passivation layer 30 is disposed on the side of the first carrier collection layer 20 away from the crystalline silicon substrate 10, for passivating the first carrier collection layer 20 and blocking high-energy particles for the crystalline silicon substrate 10 and the first carrier collection layer 20. The first electrode 40 penetrates the radiation-resistant passivation layer 30 in the thickness direction and is electrically connected to the first carrier collection layer 20.

[0017] The silicon substrate 10 can be an n-type silicon substrate or a p-type silicon substrate. Preferably, the silicon substrate is an n-type silicon substrate, which has fewer defects compared to a p-type silicon substrate.

[0018] The conductivity type of the first carrier collecting layer 20 is opposite to that of the crystalline silicon substrate 10. Specifically, if the crystalline silicon substrate is n-type, the conductivity type of the first carrier collecting layer 20 is p-type; if the crystalline silicon substrate is p-type, the conductivity type of the first carrier collecting layer 20 is n-type. This first carrier collecting layer 20 is primarily used to separate and collect electron carriers or hole carriers. When the conductivity type of the first carrier collecting layer 20 is p-type, it is primarily used to separate and collect hole carriers; when the conductivity type of the first carrier collecting layer 20 is n-type, it is primarily used to separate and collect electron carriers.

[0019] By passivating the first carrier collection layer 20 with the radiation-resistant passivation layer 30, the defects of the first carrier collection layer 20 can be reduced. Furthermore, by blocking high-energy particles from the crystalline silicon substrate 10 and the first carrier collection layer 20 with the radiation-resistant passivation layer 30, the bombardment and damage of high-energy particles to the first carrier collection layer 20 and the crystalline silicon substrate 10 can be reduced or even avoided, thereby reducing lattice damage and interface defect proliferation.

[0020] Therefore, the solar cell provided in this embodiment of the invention provides a radiation-resistant passivation layer 30 on the side of the first carrier collection layer 20 away from the crystalline silicon substrate 10 on the front side of the crystalline silicon substrate 10. This radiation-resistant passivation layer 30 can passivate the first carrier collection layer 20 and reduce defects in the solar cell. On the other hand, the radiation-resistant passivation layer 30 blocks high-energy particles from the crystalline silicon substrate 10 and the first carrier collection layer 20, thereby reducing or even preventing high-energy particles from bombarding and damaging the crystalline silicon substrate 10 and the first carrier collection layer 20, achieving radiation protection for the solar cell, and reducing or even preventing radiation attenuation of the functional layer and the crystalline silicon substrate 10 of the solar cell.

[0021] In particular, when this solar cell is applied in a space environment, the radiation-resistant passivation layer 30 can prevent high-energy particles generated in the space environment from bombarding and damaging the crystalline silicon substrate 10 and the carrier collection layer and other functional layers, thereby protecting the crystalline silicon substrate 10 and the carrier collection layer and other functional layers, effectively reducing the radiation attenuation of the solar cell, and improving the photoelectric conversion efficiency and on-orbit lifespan of the solar cell in the space environment.

[0022] In one embodiment, the radiation-resistant passivation layer 30 includes at least one semiconductor layer 31 and a first passivation layer 32, wherein the semiconductor layer 31 generally comprises a variable valence transition metal oxide, and the effective electron number density of the semiconductor layer 31 is greater than or equal to 8.0 × 10⁻⁶.22 cm 3 Furthermore, for light in the wavelength range of 380nm to 1100nm, the average transmittance of the semiconductor layer 31 is greater than or equal to 75%. On the other hand, the semiconductor layer 31 comprises a variable valence transition metal oxide, and its effective electron number density is greater than or equal to 8.0 × 10⁻⁶. 22 cm 3 Combined with an average transmittance greater than or equal to 75%, the semiconductor layer 31 is conductive while containing a dense cloud of electrons in the variable-valence transition metal oxide. This allows for the rapid dissipation of the kinetic energy of high-energy particles, ensuring their retention within the semiconductor layer 31. In other words, the semiconductor layer 31 effectively absorbs and blocks high-energy particles (such as space protons and space electrons), preventing them from penetrating the first carrier collection layer 20, intruding into and bombarding the crystalline silicon substrate 10. This avoids damage to the crystal lattice of the first carrier collection layer 20 and the crystalline silicon substrate 10, thereby reducing defect proliferation in both layers and improving the photoelectric conversion efficiency and lifespan of the solar cell. Furthermore, the variable-valence transition metal oxide in the semiconductor layer 31 possesses self-healing defect properties, capable of repairing defects caused by high-energy particles to ensure the effectiveness, stability, and reliability of the semiconductor layer 31. In addition, the average transmittance of the semiconductor layer 31 in the 380nm~1100nm light range is greater than or equal to 75%, which can ensure that most of the light in the 380nm~1100nm band can reach the crystalline silicon substrate 10 and be used by the crystalline silicon substrate 10 to generate electron-hole pairs, thereby ensuring the photoelectric conversion efficiency of the solar cell.

[0023] The effective electron number density refers to the density of electrons per unit volume in semiconductor layer 31 that participate in blocking high-energy particles. The effective electron number density of semiconductor layer 31 is greater than or equal to 8.0 × 10⁻⁶. 22 cm 3 This ensures that the electron cloud of the variable valence transition metal oxide can rapidly dissipate the kinetic energy of high-energy particles.

[0024] For example, the effective electron number density of semiconductor layer 31 can be 8.0 × 10⁻⁶. 22 cm 3 9.0×10 22 cm 3 1.0×10 23 cm 3 3.0×10 23 cm 3 5.0×10 23 cm 3 7.0×10 23 cm 3 5.0×10 24 cm3 Or 3.0×10 25 cm 3 wait.

[0025] For example, the average transmittance of the semiconductor layer 31 can be 75%, 78%, 80%, 82%, 85%, 88%, 90%, 92%, 95%, or 98%, etc.

[0026] In one embodiment of the present invention, the variable valence transition metal oxide may include one or more of nickel oxide, cobalt oxide, tungsten oxide, and vanadium pentoxide. In a preferred embodiment, the semiconductor layer 31 may be composed of one or more of nickel oxide, cobalt oxide, tungsten oxide, and vanadium pentoxide to give the semiconductor layer 31 a high effective electron number density and a high average transmittance in the wavelength range of 380 nm to 1100 nm.

[0027] In one embodiment, the thickness of the first passivation layer 32 is 14nm to 16nm. By controlling the thickness of the first passivation layer 32, it can be ensured that it can passivate the surface of the first carrier collection layer 20 relatively well, thereby reducing surface defects of the first carrier collection layer 20. At the same time, it can reduce the shading of light by the first passivation layer 32, allowing more light that can be absorbed and utilized by the crystalline silicon substrate 10 to reach the crystalline silicon substrate 10, thus ensuring the light utilization rate and photoelectric conversion efficiency of the solar cell. For example, the thickness of the first passivation layer 32 can be 14nm, 14.5nm, 15nm, 15.5nm, or 16nm, etc.

[0028] There are two possible relative relationships between the semiconductor layer 31 and the first passivation layer 32 and the first carrier collection layer 20. The first relative relationship is as follows: Figure 1 As shown, the semiconductor layer 31 is located between the first passivation layer 32 and the first carrier collection layer 20. In this first relative relationship, the semiconductor layer 31 is electrically connected to the first electrode 40. On one hand, the semiconductor layer 31 has high conductivity, which can accelerate the lateral collection and rapid transport of carriers. It can quickly transport carriers from the first carrier collection layer 20 to the first electrode 40, thereby reducing carrier recombination losses and significantly improving the photoelectric conversion efficiency and conductivity of the solar cell. On the other hand, the semiconductor layer 31 can dissipate the kinetic energy of high-energy particles, thereby blocking and absorbing high-energy particles, reducing or even preventing high-energy particles from damaging the first carrier collection layer 20 and the crystalline silicon substrate 10. The second relative relationship is as follows: Figure 2As shown, the semiconductor layer 31 is located on the side of the first passivation layer 32 away from the first carrier collection layer 20. In a preferred embodiment, with the semiconductor layer 31 located on the side of the first passivation layer 32 away from the first carrier collection layer 20, the semiconductor layer 31 is electrically isolated from the first electrode 40. This allows the semiconductor layer 31 to effectively block and absorb high-energy particles while avoiding leakage problems caused by the semiconductor layer 31 being away from the first carrier collection layer 20. Specifically, the semiconductor layer 31 located on the side of the first passivation layer 32 away from the first carrier collection layer 20 can better block high-energy particles. It should be noted that, compared to the first relative relationship, the second relative relationship can produce better performance in blocking high-energy particles.

[0029] Furthermore, in a preferred embodiment, the radiation-resistant passivation layer 30 includes two semiconductor layers 31. The first semiconductor layer 31 is disposed between the first carrier collection layer 20 and the first passivation layer 32, and is electrically connected to the first electrode 40. The second semiconductor layer 31 is disposed on the side of the first passivation layer 32 away from the crystalline silicon substrate 10. By cooperating the first semiconductor layer 31 disposed between the first passivation layer 32 and the first carrier collection layer 20, the second semiconductor layer 31 disposed on the side of the first passivation layer 32 away from the crystalline silicon substrate 10, and the first passivation layer 32, not only can high-energy particles be better blocked, but the first semiconductor layer 31 can also be electrically connected to the first electrode 40 to improve the lateral transport efficiency of carriers, thereby improving the carrier collection efficiency and reducing carrier recombination.

[0030] In a preferred embodiment, such as Figure 3 As shown, the second semiconductor layer 31 is electrically isolated from the first electrode 40, which can avoid leakage problems caused by the second semiconductor layer 31, thereby reducing the leakage of the solar cell and improving the fill factor of the solar cell.

[0031] Understandably, both the first semiconductor layer 31 and the second semiconductor layer 31 may include one or more of nickel oxide, cobalt oxide, tungsten oxide and vanadium pentoxide.

[0032] In one embodiment, when the first semiconductor layer 31 is composed of nickel oxide and / or vanadium pentoxide, the thickness of the first semiconductor layer 31 is 10 nm to 30 nm. For example, the thickness of the first semiconductor layer 31 composed of nickel oxide and / or vanadium pentoxide can be 10 nm, 12 nm, 20 nm, 25 nm, or 30 nm, etc.

[0033] In one embodiment, when the first semiconductor layer 31 is composed of cobalt oxide, the thickness of the first semiconductor layer 31 is 5 nm to 10 nm. For example, the thickness of the first semiconductor layer 31 composed of cobalt oxide can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, etc.

[0034] In one embodiment, when the first semiconductor layer 31 is made of tungsten oxide, the thickness of the first semiconductor layer 31 is 30nm to 70nm. For example, the thickness of the first semiconductor layer 31 made of tungsten oxide can be 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, or 70nm, etc.

[0035] By controlling the thickness of the first semiconductor layer 31, it is possible to effectively block high-energy particles while the variable-valence transition metal oxide used to form the semiconductor layer 31 enables the semiconductor layer 31 to have high light transmittance (the transmittance of light in the 380nm~1100nm band can exceed 75%). This allows most of the light in the 380nm~1100nm band to reach the crystalline silicon substrate 10, thereby reducing the blocking of photons that can be utilized by the crystalline silicon substrate 10 (i.e., effective photons), reducing the loss of effective photons, and enabling more effective photons to be absorbed and utilized by the crystalline silicon substrate 10 to generate effective electron-hole pairs.

[0036] In one embodiment, when the second semiconductor layer 31 is composed of nickel oxide and / or vanadium pentoxide, the thickness of the second semiconductor layer 31 is 10 nm to 30 nm. For example, the thickness of the second semiconductor layer 31 composed of nickel oxide and / or vanadium pentoxide can be 10 nm, 12 nm, 20 nm, 25 nm, or 30 nm, etc.

[0037] In one embodiment, when the second semiconductor layer 31 is composed of cobalt oxide, the thickness of the second semiconductor layer 31 is 5 nm to 10 nm. For example, the thickness of the second semiconductor layer 31 composed of cobalt oxide can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, etc.

[0038] In one embodiment, when the second semiconductor layer 31 is made of tungsten oxide, the thickness of the second semiconductor layer 31 is 30 nm to 70 nm. For example, the thickness of the second semiconductor layer 31 made of tungsten oxide can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, or 70 nm, etc.

[0039] By controlling the thickness of the second semiconductor layer 31, in conjunction with the first semiconductor layer 31 and the first passivation layer 32, the ability of the radiation-resistant passivation layer 30 to block high-energy particles can be further optimized. By controlling the thickness of the first semiconductor layer 31 and the thickness of the second semiconductor layer 31, the two stacked semiconductor layers 31 can still have high light transmittance (the transmittance of light in the 380nm~1100nm band can exceed 75%), so that most of the light in the 380nm~1100nm band can reach the crystalline silicon substrate 10, thereby reducing the blocking of effective photons.

[0040] In one embodiment, the density of the first semiconductor layer 31 is greater than that of the second semiconductor layer 31, so that the first semiconductor layer 31, the second semiconductor layer 31, and the first passivation layer 32 work together to effectively block high-energy particles. At the same time, it allows most of the light in the wavelength range of 380nm~1100nm to reach the crystalline silicon substrate 10. That is, the first semiconductor layer 31, the first passivation layer 32, and the second semiconductor layer 31 work together to ensure the transmittance of effective light, thereby ensuring the efficiency of effective photons reaching the crystalline silicon substrate 10 and reducing the loss of effective photons. In addition, the relatively dense density of the first semiconductor layer 31 is also conducive to improving the conductivity of the first semiconductor layer 31, thereby improving the lateral transport efficiency of the charge carriers in the first semiconductor layer 31, which is beneficial to the transport and collection of charge carriers.

[0041] It is worth noting that the first passivation layer 32 in any of the above-mentioned radiation-resistant passivation layers 30 is generally formed of an insulating material, such as an aluminum oxide layer, a gallium oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0042] Furthermore, such as Figures 1 to 3 As shown, the solar cell further includes an antireflection layer 50, which is disposed on the side of the radiation-resistant passivation layer 30 away from the crystalline silicon substrate 10; the first electrode 40 also penetrates the antireflection layer 50 in the thickness direction. This antireflection layer 50 can reduce light reflection, allowing more photons to reach the crystalline silicon substrate 10, thereby improving the light utilization efficiency of the crystalline silicon substrate 10. The antireflection layer 50 can be made of silicon dioxide, silicon nitride, silicon oxynitride, magnesium fluoride, or lithium fluoride, etc.

[0043] The antireflection layer 50 has a thickness of 70nm to 80nm to reduce light reflection while minimizing the loss of kinetic energy of effective photons, ensuring that effective photons can be absorbed and utilized by the crystalline silicon substrate 10. For example, the thickness of the antireflection layer 50 can be 70nm, 72nm, 75nm, 78nm, or 80nm.

[0044] Furthermore, in this embodiment of the invention, the first carrier collection layer 20 may include: a first doped diffusion layer whose conductivity type is opposite to that of the crystalline silicon substrate 10. The first doped diffusion layer is formed by doping the front side of the crystalline silicon substrate 10 with doped atoms of the opposite conductivity type to the substrate. For example, for an n-type crystalline silicon substrate 10, it is formed by doping the front side with p-type doped atoms (such as boron or gallium) to a certain depth; for a p-type crystalline silicon substrate 10, it is formed by doping the front side with n-type doped atoms (such as phosphorus, arsenic or antimony) to a certain depth.

[0045] In a preferred embodiment, for a structure in which a semiconductor layer 31 is disposed between the first carrier collection layer 20 and the first passivation layer 32, the first doped diffusion layer is further doped with germanium and / or tin. Studies have found that the semiconductor layer 31 and single-crystal silicon have different crystal structures, making it difficult to achieve coherent epitaxial adaptation in single crystals. Taking the semiconductor layer 31 as being composed of nickel oxide as an example, the silicon-nickel oxide interface easily forms a Si-O-Ni interface configuration. This interface has poor stability and is prone to interfacial bond breaking and redox side reactions, easily resulting in poor film formation of the semiconductor layer 31 and interface mismatch defects between the semiconductor layer 31 and the first doped diffusion layer. By further doping the first doped diffusion layer with germanium (Ge) and / or tin (Sn), germanium and / or tin are enriched on the surface of the first doped diffusion layer, a more stable Ge / Sn-O-Ni interface bonding state can be formed at the interface between the semiconductor layer 31 and the first doped diffusion layer. This can saturate the dangling bonds on the surface of the first doped diffusion layer, suppress surface side reactions, and reduce surface defects. Furthermore, germanium and / or tin occupy interfacial sites, reducing direct contact between silicon atoms and nickel oxide and weakening localized stress concentration induced by interfacial chemical reactions. Additionally, the combination of a first doped diffusion layer containing germanium and / or tin with the semiconductor layer 31 effectively suppresses interfacial microcracks, vacancy defects, and film desorption due to the better compatibility between germanium and / or tin and nickel oxide. Compared to the extremely unstable Si-O-Ni, which is prone to interfacial bond breakage and redox side reactions, the combination of a first doped diffusion layer containing germanium and / or tin with the semiconductor layer 31 forms a Ge / Sn-ONi interfacial bonding state with higher bonding energy and a more stable structure, effectively saturating surface dangling bonds, eliminating unsaturated surface active sites, and significantly suppressing interfacial mismatch and interfacial side reactions. Furthermore, the combination of a first doped diffusion layer containing germanium and / or tin with the semiconductor layer 31 effectively improves the contact characteristics between the first doped diffusion layer and the semiconductor layer 31, eliminates inherent interfacial defects, and ensures the structural stability of the semiconductor layer 31.

[0046] In one embodiment of the present invention, the germanium and / or tin content in the first doped diffusion layer is 1 ppm to 650 ppm. By controlling the germanium and / or tin content in the first doped diffusion layer, a better structural fit can be effectively ensured between the first doped diffusion layer and the semiconductor layer 31, and the risk of germanium and / or tin agglomeration in the first doped diffusion layer can be reduced. For example, the germanium and / or tin content in the first doped diffusion layer can be 1 ppm, 5 ppm, 10 ppm, 50 ppm, 100 ppm, 150 ppm, 200 ppm, 250 ppm, 260 ppm, 280 ppm, 300 ppm, 400 ppm, 500 ppm, 550 ppm, 600 ppm, or 650 ppm, etc. In addition, by doping germanium and / or tin in the first doped diffusion layer and controlling the content of germanium and / or tin in the first doped diffusion layer, the mechanical strength of the solar cell can be improved. Furthermore, germanium and / or tin can directionally fill a small amount of lattice vacancies generated by high-energy particles bombarding the first doped diffusion layer through the anti-radiation passivation layer 30, thereby blocking the diffusion of defects into the interior of the crystalline silicon substrate 10, reducing minority carrier lifetime decay, and improving the reliability of the solar cell.

[0047] In addition, germanium and / or tin have lower work functions than silicon, resulting in a lower potential barrier (lower resistance) when in contact with the first electrode. This helps to improve the fill factor of the solar cell and further enhances the cell efficiency.

[0048] In this embodiment of the invention, the junction depth of the first doped diffusion layer is 0.2 μm to 0.5 μm. By controlling the junction depth of the first doped diffusion layer, in conjunction with the radiation-resistant passivation layer 30, it can be ensured that effective photons can reach the crystalline silicon substrate 10 and be utilized by the crystalline silicon substrate 10. This ensures the formation of a stable and reliable PN junction between the first doped diffusion layer and the crystalline silicon substrate 10, guaranteeing carrier separation and collection efficiency. For example, the junction depth of the first doped diffusion layer can be 0.2 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, or 0.5 μm, etc.

[0049] In one embodiment of the present invention, the depth of germanium and / or tin doping in the first doped diffusion layer is 25nm~35nm. By controlling the depth of germanium and / or tin doping in the first doped diffusion layer, germanium and / or tin can be directionally filled with a small number of lattice vacancies generated by high-energy particles bombarding the first doped diffusion layer through the radiation-resistant passivation layer 30, thereby blocking the diffusion of defects into the first doped diffusion layer and the interior of the crystalline silicon substrate 10, reducing minority carrier lifetime decay, and improving the reliability of the solar cell.

[0050] In this embodiment of the invention, the solar cell further includes: a second carrier collection layer 60 disposed on the back side of the crystalline silicon substrate 10, and a second electrode 70 disposed on the side of the second carrier collection layer 60 away from the crystalline silicon substrate 10 and electrically connected to the second carrier collection layer 60. The conductivity type of the second carrier collection layer 60 is the same as that of the crystalline silicon substrate 10. For example, if the conductivity type of the crystalline silicon substrate 10 is n-type, the conductivity type of the second carrier collection layer 60 is n-type; or if the conductivity type of the crystalline silicon substrate 10 is p-type, the conductivity type of the second carrier collection layer 60 is p-type.

[0051] The structure of the second carrier collection layer 60 can be varied.

[0052] Specifically, the first structure of the second carrier collection layer 60 includes a second doped diffusion layer with the same conductivity type as the crystalline silicon substrate 10.

[0053] The second structure of the second carrier collection layer 60 includes: a second passivation layer 61 and a doped polycrystalline silicon layer 62 disposed on the side of the second passivation layer 61 away from the crystalline silicon substrate 10.

[0054] In this embodiment of the invention, the density of the second passivation layer 61 is greater than or equal to 97% and less than 100%. Since the back side of the solar cell receives relatively little radiation, the radiation protection benefit brought by setting the aforementioned anti-radiation passivation layer 30 on the back side of the solar cell is not significant. Therefore, the solar cell provided in this embodiment of the invention, through the high-density second passivation layer 61, reduces the entry of high-energy particles from the back side of the solar cell into the crystalline silicon substrate 10 while ensuring the efficiency of the solar cell. The second passivation layer 61 is generally a silicon oxide layer. For example, the density of the second passivation layer 61 can be 97%, 97.5%, 98%, or 99%, etc.

[0055] In this embodiment of the invention, the doped polysilicon layer 62 includes hydrogen atoms, which can passivate defects in the doped polysilicon layer 62, thereby reducing carrier recombination.

[0056] In one embodiment of the present invention, the solar cell may further include a third passivation layer 80 disposed on the side of the second carrier collection layer 60 away from the crystalline silicon substrate 10, wherein the second electrode 70 penetrates the third passivation layer 80 in the thickness direction. By providing the third passivation layer 80, the surface of the doped polycrystalline silicon layer 62 can be better passivated, thereby effectively reducing carrier recombination.

[0057] Furthermore, embodiments of the present invention provide a method for fabricating a solar cell. For example... Figure 4 As shown, the preparation method may include: Step S1: Provide a crystalline silicon substrate 10.

[0058] The silicon substrate 10 can be an n-type silicon substrate or a p-type silicon substrate. Preferably, the silicon substrate 10 is an n-type silicon substrate.

[0059] Step S2: A first carrier collection layer 20 and a radiation-resistant passivation layer 30 are sequentially stacked on the front side of the crystalline silicon substrate 10. The conductivity type of the first carrier collection layer 20 is opposite to that of the crystalline silicon substrate 10.

[0060] Step S3: Form a first electrode 40 that penetrates the radiation-resistant passivation layer 30 in the thickness direction and is electrically connected to the first carrier collection layer 20.

[0061] The structural change corresponding to steps S1 to S3 is as follows: Figure 5 As shown.

[0062] The solar cell prepared by the above method has a radiation-resistant passivation layer 20 disposed on the side of the first carrier collection layer 30 away from the crystalline silicon substrate 10 on the front side of the crystalline silicon substrate 10. The radiation-resistant passivation layer 20 can passivate the first carrier collection layer 30 and reduce defects in the solar cell. On the other hand, the radiation-resistant passivation layer 20 blocks high-energy particles from the crystalline silicon substrate 10 and the first carrier collection layer 30, which can reduce or even avoid the bombardment and damage of high-energy particles to the crystalline silicon substrate 10 and the first carrier collection layer 30, thereby achieving radiation protection for the solar cell and reducing or even suppressing the radiation decay of the functional layer and the crystalline silicon substrate 10 of the solar cell.

[0063] Furthermore, the preparation method provided in this embodiment of the invention also injects germanium and / or tin into the first carrier collection layer 20. On the one hand, after a small amount of high-energy particles bombard the first carrier collection layer 20 or the crystalline silicon substrate 10, germanium and / or tin can directionally fill lattice vacancies, which can avoid the accumulation of irradiation defects and effectively block the diffusion of defects caused by high-energy particle bombardment, thereby mitigating irradiation damage from the root. On the other hand, injecting germanium and / or tin into the first carrier collection layer 20 can improve the formation of a stable Ge / Sn-O-Ni between the first carrier collection layer 20 and the radiation-resistant passivation layer 30, improve interface matching, and ensure the uniformity and reliability of the radiation-resistant passivation layer 30 formed in step S2.

[0064] Specifically, there are two possible implementation schemes for injecting germanium and / or tin into the first carrier collection layer 20.

[0065] The first specific implementation scheme includes, after step S1 and before step S2, step S1': implanting germanium and / or tin to a certain depth into the silicon substrate 10 from the front side, followed by annealing and activation. Correspondingly, step S2 includes: diffusing dopant atoms of the opposite conductivity type to the silicon substrate 10 on the front side of the germanium and / or tin-doped silicon substrate 10 to form a first doped diffusion layer, the diffusion depth H2 being greater than the implantation depth H1 of germanium and / or tin. The structural changes corresponding to the combination of steps S1, S1', and S2 are as follows: Figure 7 As shown.

[0066] More specifically, the specific implementation scheme of step S1' includes: at room temperature and in a vacuum ≤ 1×10 -6 Torr, beam current density ≤1μA / cm 2 Under these conditions, germanium and / or tin are implanted into the crystalline silicon substrate 10 via ion implantation. Based on this, the first doped diffusion layer, which subsequently forms the first carrier collection layer 20, is doped with germanium and / or tin. Generally, the depth of the implanted germanium and / or tin is less than the junction depth of the formed first doped diffusion layer.

[0067] The second specific implementation includes: Step S2 includes: diffusing doping atoms of the opposite conductivity type to the crystalline silicon substrate 10 on the front side of the crystalline silicon substrate 10 to form a first doped diffusion layer, and ion implanting germanium and / or tin into the first doped diffusion layer, followed by annealing and activation.

[0068] Annealing activation mainly involves gradient heating under a nitrogen atmosphere (heating to 750℃ for 30s; continuing to heat to 900℃ for 10-15s; continuing to heat to 1050℃ for 5s) to repair damage and achieve an activation rate of germanium and / or tin ≥90%.

[0069] By implanting germanium and / or tin into the first doped diffusion layer, a high surface content of the first doped diffusion layer can be achieved, effectively mitigating the problems of minority carrier lifetime decay and increased leakage current induced by high-energy particle irradiation. Furthermore, doping with germanium and / or tin can also improve the mechanical strength of the solar cell, balancing strong radiation resistance of the surface layer with high stability of the first doped diffusion layer. Moreover, compared to uniformly doping with germanium and / or tin within the crystalline silicon substrate 10, gradient implantation of germanium and / or tin into the first doped diffusion layer can solve the problem of excessive residual stress caused by uniform doping.

[0070] In this embodiment of the invention, there are three implementation schemes for forming the anti-radiation passivation layer 30 in step S2.

[0071] The first embodiment of forming the radiation-resistant passivation layer 30 in step S2 includes the following steps S22-1 and S22-2: Step S21-1: A semiconductor layer 31 comprising a variable valence transition metal oxide is sputtered on the side of the first carrier collection layer 20 away from the crystalline silicon substrate 10 by magnetron sputtering.

[0072] Step S22-1: Using a plasma-enhanced atomic layer deposition apparatus, deposit a first passivation layer 32 on the side of the semiconductor layer 31 away from the first carrier collection layer 20.

[0073] Based on this first implementation scheme, the following can be obtained: Figure 1 The relationship between the semiconductor layer 31, the first passivation layer 32, and the first carrier collection layer 20 in the structure shown.

[0074] A second embodiment of forming the radiation-resistant passivation layer 30 in step S2, based on steps S21-1 and S22-1 of the first embodiment described above, further includes the following after step S22-1: Step S23-1: Cover the area of ​​the first passivation layer 32 corresponding to the first electrode 40 with template A, and further sputter a semiconductor layer 31 in the area of ​​the first passivation layer 32 not covered by template A by magnetron sputtering. The width of the area covered by template A corresponding to the first electrode 40 is greater than the width of the first electrode 40.

[0075] Based on this second implementation scheme, we can obtain Figure 3 The relationship between the two semiconductor layers 31, the first passivation layer 32, and the first carrier collection layer 20 in the structure shown.

[0076] The third embodiment of forming the radiation-resistant passivation layer 30 in step S2 includes the following steps S21-2 and S22-2: Step S21-2: Using a plasma-enhanced atomic layer deposition (PEALD) device, deposit a first passivation layer 32 on the first carrier collection layer 20.

[0077] Step S22-2: Cover the area of ​​the first passivation layer 32 corresponding to the first electrode 40 with template A, and further sputter a semiconductor layer 31 in the area of ​​the first passivation layer 32 not covered by template A by magnetron sputtering. The width of the area covered by template A corresponding to the first electrode 40 is greater than the width of the first electrode 40.

[0078] Based on this third implementation scheme, we can obtain Figure 2 The relationship between the semiconductor layer 31, the first passivation layer 32, and the first carrier collection layer 20 in the structure shown.

[0079] The following example illustrates the second embodiment of forming the radiation-resistant passivation layer 30 in conjunction with forming the first doped diffusion layer as the first carrier collection layer 20. Step S2 may include steps S21 to S26: Step S21: Diffuse doping atoms with the opposite conductivity type to the crystalline silicon substrate 10 on the front side of the crystalline silicon substrate 10 to form a first doped diffusion layer.

[0080] Step S22: A first semiconductor layer 31 is formed on the side of the first carrier collection layer 20 away from the crystalline silicon substrate 10 by magnetron sputtering.

[0081] Step S23: Deposit the first passivation layer 32 using plasma-enhanced atomic layer deposition.

[0082] Step S24: Cover the region of the first passivation layer 32 corresponding to the first electrode 40 with template A.

[0083] Step S25: Form a second semiconductor layer 31 on the first passivation layer 32 by magnetron sputtering.

[0084] Step S26: Remove template A.

[0085] The structural changes corresponding to steps S21 to S26 are as follows: Figure 6 As shown. Based on the structure formed in steps S21 to S26 above, the first electrode formed thereon in the subsequent step S3 is electrically isolated from the second semiconductor layer 31.

[0086] Furthermore, based on any of the above embodiments for forming the radiation-resistant passivation layer 30, step S2 may further include: forming a second carrier collection layer 60 on the back side of the crystalline silicon substrate 10, and a second electrode 70 located on the side of the second carrier collection layer 60 away from the crystalline silicon substrate 10 and electrically connected to the second carrier collection layer 60.

[0087] More specifically, the second carrier collection layer 60 is a second doped diffusion layer with the same conductivity type as the crystalline silicon substrate 10. It is formed by diffusing doping on the back side of the crystalline silicon substrate 10 with doping atoms of the same conductivity type as the crystalline silicon substrate 10 (e.g., if the conductivity type of the crystalline silicon substrate 10 is n-type, the doping atoms for diffusion doping are phosphorus, arsenic, or antimony, etc.; if the conductivity type of the crystalline silicon substrate 10 is p-type, the doping atoms for diffusion doping are boron or gallium, etc.).

[0088] The second carrier collection layer 60 includes a second passivation layer 61 and a doped polycrystalline silicon layer 62 disposed on the side of the second passivation layer 61 away from the crystalline silicon substrate 10. The specific method for forming the second carrier collection layer 60 is as follows: a dense SiO2 tunneling oxide layer (i.e., the second passivation layer 61) with a thickness of 1.2 nm to 2.0 nm is prepared on the back side of the crystalline silicon substrate 10 using high-temperature dry oxygen thermal oxidation at 850℃ to 900℃. This prepared dense SiO2 tunneling oxide layer has no microscopic pores and also... It possesses tunneling transport and resistance to penetration by a small number of high-energy particles. Subsequently, a doped polycrystalline silicon layer with the same conductivity type as the crystalline silicon substrate 10 is deposited on the dense SiO2 tunneling oxide layer. After annealing and activation, the doped polycrystalline silicon layer undergoes in-situ hydrogen passivation. The H2 flow rate is 50 sccm~100 sccm, and the temperature is 400℃~450℃ for 30min~60min, saturating the dangling bonds on the surface of the doped polycrystalline silicon layer and reducing the defect density. The high-temperature dry oxygen thermal oxidation temperature can be 850℃, 870℃, or 900℃, etc., and the thickness of the formed dense SiO2 tunneling oxide layer can be 1.2nm, 1.5nm, 1.8nm, or 2.0nm, etc. During the in-situ hydrogen passivation process, the H2 flow rate can be 50 sccm, 80 sccm or 100 sccm, the temperature can be 400℃, 420℃ or 450℃, and the holding time can be 30 min, 40 min, 50 min or 60 min.

[0089] Furthermore, step S2 may further include forming an antireflection layer 50 on the anti-radiation passivation layer 30.

[0090] It is worth noting that during the formation of each of the above-mentioned film layers, a wrap-around coating corresponding to each film layer will also be formed. The wrap-around coating can be removed by the existing wet etching method. The removal process of the wrap-around coating for each film layer will not be described in detail here.

[0091] Further, the specific implementation of step S3 above may include: printing silver grid line electrodes on the front side and silver-aluminum full back field electrodes on the back side, and sintering them in segments. Specifically, the temperature is preheated to 300°C for 5 minutes, then increased to 500°C and held for 3 minutes, further increased to 850°C and held for 2 minutes, then gradually decreased to 200°C and held for 5 minutes to form a good ohmic contact. The contact resistance between the formed first electrode 40 and the first carrier collection layer 20 is ≤5mΩ·cm², and there are no phenomena such as electrode detachment, false printing, or grid breakage.

[0092] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to several examples and comparative examples.

[0093] Example 1: Step A: Provide an n-type crystalline silicon substrate with a resistivity of 3 Ω·cm and a thickness of 130 μm, with crystal orientation... <100> The silicon wafers are free from surface damage, dislocation defects, and microcracks, with a purity of ≥99.999%.

[0094] Step B: Using a 2.5% NaOH solution, the surface of the n-type crystalline silicon substrate is texturized at a texturing temperature of 82℃ for 18 minutes. After texturing, the substrate is rinsed with overflow pure water and then neutralized and cleaned with dilute hydrochloric acid to remove surface alkali residue and metal ion impurities. Finally, a uniform and dense pyramid textured surface is formed on the n-type crystalline silicon substrate.

[0095] Step C: Using a tube diffusion furnace, boron diffusion is performed on the front side of the n-type silicon substrate to prepare a p-type emitter via a back-to-back wafer insertion method. The diffusion source is boron tribromide (BBr3), the process temperature is set at 920℃, and the isothermal diffusion time is 40 minutes. During diffusion, high-purity nitrogen (N2) is used as the carrier gas to carry BBr3 into the furnace tube, while oxygen and water vapor are simultaneously introduced to promote the complete reaction of BBr3 to form a uniform borosilicate glass (BSG) layer, which drives boron atom substitution doping to form a dense p-type emitter. After diffusion, a laser edge isolation process is used to etch the periphery of the n-type silicon substrate to completely remove the edge-mounted boron layer and PN junction.

[0096] Step D involves sequentially performing alkaline cleaning to remove oil, acidic cleaning to remove metal impurities, hydrogen peroxide oxidation cleaning, and multi-stage overflow cleaning with pure water. Subsequently, the product is immersed in 5% dilute hydrofluoric acid at room temperature for 90 seconds to thoroughly remove the natural oxide layer and residual borosilicate glass layer on the surface. Finally, it is dried with high-purity nitrogen and kept in an 80°C oven for 10 minutes to ensure that the product prepared in step C has a clean surface free of impurities and oxidation residues.

[0097] Step E: High-temperature thermal oxidation of the back side of the product after step D, oxidation temperature 920℃, pure oxygen atmosphere, oxygen flow rate 200 sccm, holding oxidation time 25 min, to prepare an ultrathin dense tunneling oxide layer with a thickness of 2 nm; Low-pressure chemical vapor deposition (LPCVD) process is used to deposit an in-situ phosphorus-doped polycrystalline silicon layer on the surface of the tunneling oxide layer, deposition temperature 620℃, silane gas flow rate 45 sccm, deposition time 40 min, to obtain a phosphorus-doped polycrystalline silicon layer with a thickness of 100 nm.

[0098] Step F: Germanium ions are implanted into the P-type emitter using ion implantation at an energy of 40 keV and a dose of 3 × 10⁻⁶ ions / cm². 2 The doping depth is 30 nm. After doping, the mixture is kept at 880 °C for 25 min under a nitrogen atmosphere with a flow rate of 300 sccm, and then subjected to high-temperature annealing and activation treatment, followed by natural cooling in the furnace.

[0099] Step G: A dense nickel oxide layer is deposited on the p-type emitter implanted with germanium ions using magnetron sputtering. The nickel oxide layer is deposited using a 99.99% high-purity nickel oxide ceramic target at a temperature of 180℃ and a base vacuum of 3×10⁻⁶. -4 Pa, working gas is high-purity argon, argon flow rate is 40 sccm, sputtering power is 180 W, deposition time is 20 min; the thickness of the first dense nickel oxide layer (i.e. the first semiconductor layer 31 mentioned above) is 65 nm.

[0100] Step H: A 15 nm thick aluminum oxide passivation layer is deposited on the first nickel oxide layer using plasma enhanced atomic layer deposition (PEALD) at a deposition temperature of 250 °C.

[0101] Step 1: Cover the first electrode area with a metal template, use magnetron sputtering process, temperature 160℃, argon flow rate 35sccm, sputtering power 140W, deposition time 12min, deposit a second nickel oxide layer with a thickness of 40nm (i.e. the second semiconductor layer 31 mentioned above) on the part of the alumina passivation layer not covered by the metal template, and remove the metal template on the front side.

[0102] Step J: Using tubular plasma-enhanced chemical vapor deposition, a silicon nitride antireflective layer with a thickness of 75 nm is deposited on the front side of the product prepared in Step I at a deposition temperature of 360°C. A silicon nitride passivation layer with a thickness of 80 nm is deposited on the back side of the product at a deposition temperature of 380°C.

[0103] Step K: Silver metal grid lines on the front and back sides are prepared using electron beam evaporation, with a vacuum level of 5×10⁻⁶. -4 Pa, evaporation rate 0.8 nm / s, front-side grid line width 30 μm, height 1.2 μm, wherein the front-side silver metal grid line corresponds to the area where no second nickel oxide layer is set. After evaporation, high-temperature rapid sintering is carried out in an infrared chain sintering furnace with a peak sintering temperature of 850℃, belt speed of 300 mm / min, and holding sintering for 12 s.

[0104] Step L: The product obtained in step K is uniformly coated and encapsulated using aerospace-grade silicone anti-radiation encapsulant with a layer thickness of 150μm and cured at room temperature for 24 hours.

[0105] Example 2

[0106] The difference from Example 1 is that step F is omitted.

[0107] Example 3

[0108] The difference from Example 1 is that steps F and G are omitted.

[0109] Example 4

[0110] The difference from Example 1 is that step I is omitted.

[0111] Example 5

[0112] The difference from Example 1 is that the use of a metal template to cover the first electrode area in step I is omitted, that is, Example 5 forms a second nickel oxide layer on the entire surface.

[0113] Comparative Example 1

[0114] The difference from Example 1 is that steps F, G and I are omitted.

[0115] During the testing of Examples 1 to 5 and Comparative Example 1, the high-energy electron radiation environment of low-Earth orbit space was accurately simulated. A high-energy electron beam irradiation test device was used, with an electron energy of 1 MeV and a cumulative irradiation dose of 1 × 10⁻⁶ e / cm. Under a standard test environment (AM1.5G) at room temperature (25°C) and normal pressure, the photoelectric performance of the cells was tested before and after 30 minutes of static stabilization. The initial conversion efficiency, initial open-circuit voltage, initial short-circuit current, and initial fill factor before irradiation were statistically analyzed. The conversion efficiency, efficiency decay rate, and fill factor after irradiation were also statistically analyzed. The efficiency decay rate... The statistical results are shown in Table 1 below.

[0116] Table 1

[0117] As can be seen from the table above, the performance (conversion efficiency and fill factor after irradiation) of Examples 1 to 5 is significantly better than that of the existing solar cell (Comparative Example 1), and the efficiency degradation rate of Examples 1 to 5 is significantly lower than that of the existing solar cell (Comparative Example 1).

[0118] The difference between Example 1 and Example 2 lies in whether germanium ions are doped at the emitter. Comparing the test results of Example 1 and Example 2, it can be seen that when germanium ions are doped at the emitter, the efficiency decay rate is 3.70% (Example 1), while when germanium ions are not doped at the emitter, the efficiency decay rate is 5.90% (Example 2). This indicates that doping germanium ions at the emitter can effectively improve the initial photoelectric conversion efficiency of the battery, while significantly reducing the conversion efficiency decay caused by irradiation. The principle is that the nickel oxide layer (i.e., the semiconductor layer 31 formed by variable valence transition metal oxides) has a different crystal structure from that of single-crystal silicon, making it difficult to achieve single-crystal coherent epitaxial adaptation. The interface between silicon and variable valence transition metal oxides such as nickel oxide is prone to forming a Si-O-Ni interface bonding structure with poor stability, which is very easy to cause interface bond breaking and redox side reactions. This not only degrades the film quality of semiconductor layer 31, but also generates a large number of interface defects between semiconductor layer 31 and the first doped diffusion layer. After germanium doping of the emitter, germanium atoms accumulate on the surface of the first doped diffusion layer, forming a more stable Ge-O-Ni interface structure at the interface between the semiconductor layer 31 and the first doped diffusion layer. This effectively saturates the dangling bonds on the surface of the first doped diffusion layer, suppresses various surface side reactions such as interface redox, and significantly reduces interface defects. In Example 2, the undoped germanium emitter contacts the first nickel oxide layer. The lattice constant difference between the undoped germanium emitter and the first nickel oxide layer is significant. During the deposition of the first nickel oxide layer on the undoped germanium emitter, severe lattice distortion easily occurs, inducing structural problems such as interface microcracks and vacancy defects in the formed first nickel oxide layer. Furthermore, the surface of the undoped germanium emitter contains a large number of silicon dangling bonds, which form weak Si-O-Ni bonds with the first nickel oxide layer. These bonds have extremely poor stability and are prone to interface bond breakage and redox side reactions, directly leading to a significant decrease in the deposition uniformity, adhesion, and structural stability of the first nickel oxide layer.

[0119] Furthermore, although Example 2 retains the double-layer nickel oxide and the leakage-proof structure between the second nickel oxide layer and the first electrode, the poor molding quality of the first nickel oxide layer and numerous interface defects prevent it from fully utilizing its auxiliary conductivity and radiation resistance capabilities. This not only limits its initial photoelectric output performance but also significantly weakens its radiation resistance stability compared to Example 1 and Example 5, which has a more stable interface. Therefore, doping the emitter with germanium ions can effectively reduce conversion efficiency decay and effectively improve the uniformity of the first nickel oxide layer deposition, interface adhesion, and overall structural stability.

[0120] The difference between Examples 2 and 3 lies in whether a first semiconductor layer 31 is fabricated. As shown in Table 1, Example 3 lacks germanium doping in its emitter and does not have a first semiconductor layer 31. Compared to Examples 1, 2, and 4, Example 3 has the lowest initial conversion efficiency (23.86%), an irradiation attenuation rate of 13.48%, and radiation resistance performance only better than Example 4 (lacking a second semiconductor layer) and Comparative Example 1. This is because the first semiconductor layer 31 has a dual core role in assisting radiation resistance and lateral carrier transport, and is a key auxiliary structure to ensure high initial photoelectric efficiency of the battery. On the one hand, the first semiconductor layer 31 can construct a continuous, low-resistance lateral carrier transport channel, quickly collect and conduct photogenerated electrons, significantly reduce carrier recombination loss and transport loss, and significantly improve the battery fill factor and photoelectric conversion efficiency; on the other hand, it can work with the second semiconductor layer 31 to form a double-layer radiation shielding system, absorb residual penetrating high-energy particles, and strengthen the battery's radiation resistance redundancy. Furthermore, compared to Example 2, Example 3 completely lacks the first semiconductor layer 31, resulting in high resistance to photogenerated carrier transport and severe recombination losses, directly leading to a significant decrease in initial power generation performance and thus a lower initial conversion efficiency. Additionally, the efficiency degradation rate of Example 3 is lower than that of Example 4, which completely lacks the second semiconductor layer 31, indicating that the second semiconductor layer 31 is the core radiation-resistant structure of the battery. Comparative Example 1, which lacks any radiation-resistant structure, has the highest efficiency degradation rate among all groups.

[0121] The difference between Example 1 and Example 4 lies in whether a second semiconductor layer 31 is provided. Example 4 retains the germanium-doped emitter and the first semiconductor layer 31 completely, but does not provide a second semiconductor layer 31. The initial conversion efficiency of Example 4 is 25.42%, slightly higher than that of Example 1 (25.36%), indicating excellent initial electrical performance. However, the irradiation efficiency decay rate of Example 4 is as high as 17.04%, showing severe decay and a precipitous deterioration in radiation resistance. This further illustrates that in the structure provided by the embodiments of the present invention, the core function of the second semiconductor layer 31 (i.e., the semiconductor layer 31 located on the side of the first passivation layer away from the first carrier collection layer) is radiation protection, and the second semiconductor layer 31 has little impact on the battery's electrical output performance. The initial conversion efficiency of Example 4 is slightly higher than that of Example 1 because the initial photoelectric performance of the battery mainly depends on the carrier transport efficiency and the quality of the interface structure. Example 4 has a well-optimized interface structure of germanium-doped emitter and a highly efficient lateral transport channel of the first semiconductor layer 31, with fewer interface defects and lower carrier transport loss, while lacking the influence of the second semiconductor layer 31 on light. However, comparing the test results after irradiation of Examples 1 and 4, it can be seen that in the structure provided by the present invention, the core protective barrier against space radiation attenuation is the second semiconductor layer 31, which can directly intercept and absorb most of the high-energy protons and electrons in space, blocking the bombardment of radiated particles on the crystalline silicon substrate 10 and the first carrier collection layer 20 from the source. Compared with Example 1, Example 4 completely lacks the second semiconductor layer 31, relying only on the limited auxiliary radiation resistance of the first semiconductor layer 31, which cannot resist the penetrating bombardment of high-intensity high-energy particles in space. High-energy particles directly invade the battery, continuously inducing lattice damage to the crystalline silicon substrate and rapid proliferation of interface defects, ultimately leading to a significant performance degradation after irradiation.

[0122] Furthermore, the difference between Example 1 and Example 5 lies in whether the second semiconductor layer is electrically isolated from the first electrode. Example 5 fully retains the germanium-doped emitter, the first semiconductor layer 31, and the second semiconductor layer 32, only removing the portion of the metal template covering the first electrode area, and adopts full-area full-coverage deposition of the second semiconductor layer 32. The initial conversion efficiency of Example 5 (24.58%) and the conversion efficiency after irradiation (23.73%) are both lower than those of Example 1, indicating significant electrical losses; however, the irradiation efficiency decay rate of Example 5 is only 3.46%, showing low irradiation decay and excellent radiation resistance stability. This further illustrates that the second semiconductor layer 31 is the core radiation-resistant functional layer. Example 5 adopts full-area full-coverage deposition without electrode openings, and the second semiconductor layer 31 completely covers the battery surface without any protective blind spots, achieving optimal shielding and blocking effect against high-energy particles from space. Therefore, it has the lowest efficiency decay and the best radiation resistance performance after irradiation. However, the second semiconductor layer 31, which is in direct contact with the metal electrode, causes battery leakage and carrier loss, directly reducing the battery fill factor and initial photoelectric conversion efficiency. This results in weaker initial performance and a lower fill factor after irradiation compared to Example 1. Example 1's process of patterning a metal template to cover a portion of the area precisely achieves "windowed electrical isolation of the second semiconductor layer 31 for the electrode area and full coverage protection for non-electrode areas." While retaining the core radiation resistance of the second semiconductor layer 31, it completely solves the leakage defect of the entire second semiconductor layer 31, perfectly balancing radiation protection performance and electrical output performance. Ultimately, it achieves superior initial battery efficiency and irradiation stability. Therefore, Example 1 has the best overall structural performance.

[0123] The above steps are provided only to help understand the method, structure, and core ideas of this invention. Those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A solar cell, characterized in that, include: Crystalline silicon substrate (10); A first carrier collection layer (20) is disposed on the front side of the crystalline silicon substrate (10), and the conductivity type of the first carrier collection layer (20) is opposite to that of the crystalline silicon substrate (10). Radiation-resistant passivation layer (30) is disposed on the side of the first carrier collection layer (20) away from the crystalline silicon substrate (10) to passivate the first carrier collection layer (20) and block high-energy particles for the crystalline silicon substrate (10) and the first carrier collection layer (20). The first electrode (40) penetrates the radiation-resistant passivation layer (30) in the thickness direction and is electrically connected to the first carrier collection layer (20).

2. The solar cell according to claim 1, characterized in that, The radiation-resistant passivation layer (30) comprises at least one semiconductor layer (31) and a first passivation layer (32), wherein the semiconductor layer (31) comprises a variable valence transition metal oxide, and the effective electron number density of the semiconductor layer (31) is greater than or equal to 8.0 × 10⁻⁶. 22 cm 3 Furthermore, for light in the wavelength range of 380nm~1100nm, the average transmittance of the semiconductor layer (31) is greater than or equal to 75%; Optionally, the variable valence transition metal oxide includes one or more of nickel oxide, cobalt oxide, tungsten oxide, and vanadium pentoxide; Optionally, the thickness of the first passivation layer (32) is 14nm~16nm.

3. The solar cell according to claim 2, characterized in that, The radiation-resistant passivation layer (30) comprises two semiconductor layers (31), wherein, The first semiconductor layer (31) is disposed between the first carrier collection layer (20) and the first passivation layer (32), and the first semiconductor layer (31) is electrically connected to the first electrode (40); The second semiconductor layer (31) is disposed on the side of the first passivation layer (32) away from the crystalline silicon substrate (10); Optionally, the second semiconductor layer (31) is electrically isolated from the first electrode (40); Optionally, when the first semiconductor layer (31) is composed of nickel oxide and / or vanadium pentoxide, the thickness of the first semiconductor layer (31) is 10 nm to 30 nm; or, when the first semiconductor layer (31) is composed of cobalt oxide, the thickness of the first semiconductor layer (31) is 5 nm to 10 nm; or, when the first semiconductor layer (31) is composed of tungsten oxide, the thickness of the first semiconductor layer (31) is 30 nm to 70 nm. Optionally, when the second semiconductor layer (31) is composed of nickel oxide and / or vanadium pentoxide, the thickness of the second semiconductor layer (31) is 10 nm to 30 nm; or, when the second semiconductor layer (31) is composed of cobalt oxide, the thickness of the second semiconductor layer (31) is 5 nm to 10 nm; or, when the second semiconductor layer (31) is composed of tungsten oxide, the thickness of the second semiconductor layer (31) is 30 nm to 70 nm. Optionally, the density of the first semiconductor layer (31) is greater than the density of the second semiconductor layer (31).

4. The solar cell according to any one of claims 1 to 3, characterized in that, Also includes: Anti-reflective layer (50) The antireflection layer (50) is disposed on the side of the anti-radiation passivation layer (30) away from the crystalline silicon substrate (10); In the thickness direction, the first electrode (40) also penetrates the antireflection layer (50); Optionally, the thickness of the antireflection layer (50) is 70nm~80nm.

5. The solar cell according to any one of claims 1 to 3, characterized in that, The first carrier collection layer (20) includes a first doped diffusion layer whose conductivity type is opposite to that of the crystalline silicon substrate (10); Optionally, the first doped diffusion layer is further doped with germanium and / or tin; Optionally, the germanium and / or tin content in the first doped diffusion layer is 1 ppm to 650 ppm; Optionally, the junction depth of the first doped diffusion layer is 0.2 μm to 0.5 μm.

6. The solar cell according to claim 5, characterized in that, The first doped diffusion layer is doped with germanium and / or tin to a depth of 25 nm to 35 nm.

7. The solar cell according to any one of claims 1 to 3 and 6, characterized in that, Also includes: A second carrier collection layer (60) disposed on the back side of the crystalline silicon substrate (10), and a second electrode (70) disposed on the side of the second carrier collection layer (60) away from the crystalline silicon substrate (10) and electrically connected to the second carrier collection layer (60), wherein the conductivity type of the second carrier collection layer (60) is the same as that of the crystalline silicon substrate (10); Optionally, the second carrier collection layer (60) includes a second doped diffusion layer with the same conductivity type as the crystalline silicon substrate (10); or, the second carrier collection layer (60) includes a second passivation layer (61) and a doped polycrystalline silicon layer (62) disposed on the side of the second passivation layer (61) away from the crystalline silicon substrate (10). Optionally, the density of the second passivation layer (61) is greater than or equal to 97% and less than 100%; Optionally, the doped polycrystalline silicon layer (62) includes hydrogen atoms; Optionally, the solar cell further includes a third passivation layer (80) disposed on the side of the second carrier collection layer (60) away from the crystalline silicon substrate (10), wherein the second electrode (70) penetrates the third passivation layer (80) in the thickness direction.

8. The solar cell according to claim 7, characterized in that, The crystalline silicon substrate (10) has an n-type conductivity, the first carrier collection layer (20) has a p-type conductivity, and the second carrier collection layer (60) has an n-type conductivity.

9. A method for preparing a solar cell, characterized in that, include: Step S1: Provide a crystalline silicon substrate (10); Step S2: A first carrier collection layer (20) and a radiation passivation layer (30) are sequentially stacked on the front side of the crystalline silicon substrate (10), wherein the conductivity type of the first carrier collection layer (20) is opposite to that of the crystalline silicon substrate (10); Step S3: Form a first electrode (40) that penetrates the anti-radiation passivation layer (30) in the thickness direction and is electrically connected to the first carrier collection layer (20).

10. The preparation method according to claim 9, characterized in that, After step S1 and before step S2, the method further includes: step S1', implanting germanium and / or tin to a certain depth into the crystalline silicon substrate (10) from the front side of the crystalline silicon substrate (10), and annealing to activate it; Step S2 includes: diffusing doping atoms of the opposite conductivity type to the silicon substrate (10) doped with germanium and / or tin on the front side of the silicon substrate (10) to form a first doped diffusion layer as the first carrier collection layer (20), the diffusion depth being greater than the implantation depth of the germanium and / or tin. or, Step S2 includes: diffusing doping atoms with the opposite conductivity type to the silicon substrate (10) on the front side of the silicon substrate (10) to form a first doped diffusion layer as the first carrier collection layer (20), and ion implanting germanium and / or tin into the first doped diffusion layer, annealing and activating it, wherein the diffusion depth of the first doped diffusion layer is greater than the implantation depth of germanium and / or tin. Optionally, forming the radiation-resistant passivation layer (30) in step S2 includes: Step S21-1: A semiconductor layer (31) comprising a variable valence transition metal oxide is sputtered on the side of the first carrier collection layer (20) away from the crystalline silicon substrate (10) by magnetron sputtering. Step S22-1: Using a plasma-enhanced atomic layer deposition apparatus, deposit a first passivation layer (32) on the side of the semiconductor layer (31) away from the first carrier collection layer (20). Optionally, in step S2, after step S22-1, the following is further included: Step S23-1: Cover the area of ​​the first passivation layer (32) corresponding to the first electrode (40) with a template (A), and further sputter a semiconductor layer (31) in the area of ​​the first passivation layer (32) not covered by the template (A) by magnetron sputtering. The width of the area covered by the template (A) corresponding to the first electrode (40) is greater than the width of the first electrode (40). Alternatively, forming the radiation-resistant passivation layer (30) in step S2 includes: Step S21-2: Using a plasma-enhanced atomic layer deposition apparatus, a first passivation layer (32) is deposited on the side of the semiconductor layer (31) away from the first carrier collection layer (20). Step S22-2: Cover the area of ​​the first passivation layer (32) corresponding to the first electrode (40) with a template (A), and further sputter a semiconductor layer (31) in the area of ​​the first passivation layer (32) not covered by the template (A) by magnetron sputtering. The width of the area covered by the template (A) corresponding to the first electrode (40) is greater than the width of the first electrode (40).

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