Semiconductor element and semiconductor device
Patent Information
- Application Number
- CN202610032811.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-04-02
- Filing Date
- 2026-01-12
- Publication Date
- 2026-10-16
Smart Images
Figure CN122934989A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor element and a semiconductor device, and more particularly to a semiconductor element and a semiconductor device comprising the thereof. Background Technology
[0002] Semiconductor components can include various semiconductor light-emitting elements such as light-emitting diodes (LEDs), laser diodes (LDs), photodetectors, solar cells, or power devices. Semiconductor components are used in various fields such as lighting, medical applications, displays, communications, sensing, and power systems. Taking an LED as an example, its basic structure can include a p-type semiconductor, an n-type semiconductor, and an active region located between the two. When current is applied, electrons and holes recombine in the active region to emit light, and the wavelength of the emitted light depends on the material used, such as III-V semiconductor materials containing group III and group V elements. In recent years, with technological advancements, there are still many technological research and development needs for semiconductor components, such as further improvements required in structure, manufacturing processes, or material design. Summary of the Invention
[0003] This invention provides a semiconductor device including a first semiconductor structure, a second semiconductor structure, an active region, and a first electrode. The first semiconductor structure includes a first semiconductor layer and a second semiconductor layer located beneath the first semiconductor layer. The first semiconductor structure has an upper surface. The upper surface has a first region and a second region. The second semiconductor structure and the active region are located in the first region but not on the second region. The active region is located between the first semiconductor structure and the second semiconductor structure. The first electrode is located on the second region and is in direct contact with the first semiconductor layer to form an electrical connection. The first semiconductor layer has an n-type conductivity and is the thickest layer in the first semiconductor structure. The first semiconductor layer includes a first III-V group semiconductor material. The first III-V group semiconductor material includes ternary or quaternary arsenides or phosphides.
[0004] According to one embodiment of the present invention, the material of the second semiconductor layer comprises a second III-V group semiconductor material.
[0005] According to one embodiment of the present invention, the first III-V semiconductor material includes AlGaAs or AlGaInP.
[0006] According to one embodiment of the present invention, the thickness of the first semiconductor layer is in the range of 2 μm to 8 μm.
[0007] According to one embodiment of the present invention, the first semiconductor layer includes a first dopant, and the concentration of the first dopant in the first semiconductor layer is 5 × 10⁻⁶.17 cm -3 Up to 5×10 18 cm -3 The range.
[0008] According to one embodiment of the present invention, the first semiconductor structure further includes a third semiconductor layer located between the first semiconductor layer and the active region.
[0009] According to one embodiment of the present invention, a second electrode is further included, located on the second semiconductor structure.
[0010] According to one embodiment of the present invention, the second semiconductor structure further includes a fourth semiconductor layer and a fifth semiconductor layer located below the fourth semiconductor layer, and the second electrode is in direct contact with the fourth semiconductor layer to form an electrical connection.
[0011] According to one embodiment of the present invention, the width of the fifth semiconductor layer is greater than the width of the fourth semiconductor layer.
[0012] According to one embodiment of the present invention, the first III-V semiconductor material is different from the second III-V semiconductor material. Attached Figure Description
[0013] Figure 1 This is a cross-sectional schematic diagram of a semiconductor epitaxial structure according to an embodiment of the present invention;
[0014] Figure 2A This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;
[0015] Figure 2B for Figure 2A A schematic cross-sectional view of a semiconductor device along line X-X';
[0016] Figure 3A This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;
[0017] Figure 3B for Figure 3A A schematic cross-sectional view of a semiconductor device along line AB;
[0018] Figure 3C for Figure 3A A schematic cross-sectional view of a semiconductor device along line CD;
[0019] Figure 3D for Figure 3A A schematic cross-sectional view of a semiconductor device along line EF;
[0020] Figure 4 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;
[0021] Figure 5 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;
[0022] Figure 6 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;
[0023] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.
[0024] Symbol explanation:
[0025] 10: Semiconductor epitaxial structure
[0026] 20, 30, 40, 50, 60, 701: Semiconductor components
[0027] 30a: First side view
[0028] 30b: Second side view
[0029] 30c: Third side
[0030] 30d: Fourth side view
[0031] 100: Growth substrate
[0032] 110: First semiconductor structure
[0033] 110a: First semiconductor layer
[0034] 110b: Second semiconductor layer
[0035] 110b1: Lower surface
[0036] 110c: Third semiconductor layer
[0037] 120: Second semiconductor structure
[0038] 120a: Fourth semiconductor layer
[0039] 120b: Fifth semiconductor layer
[0040] 120c: Sixth semiconductor layer
[0041] 120d: Seventh semiconductor layer
[0042] 120e: Eighth semiconductor layer
[0043] 130: Active region
[0044] 130a: Semiconductor stack
[0045] 130a1: Barrier layer
[0046] 130a2: Trap layer
[0047] 130a1': Additional barrier layer
[0048] 130b: First restricted structure
[0049] 130c: Second restricted structure
[0050] 200, 300: Bonding substrate
[0051] 201, 301: Joint structure
[0052] 202, 302, 302': First electrode
[0053] 204, 304, 304', 304”: Second electrode
[0054] 206: Insulation Structure
[0055] 206a, 310a, 310a”: First opening
[0056] 206b, 310b, 310b': Second opening
[0057] 302a, 304a, 302a', 304a': Main body
[0058] 304a1: First Main Body
[0059] 304a2: Second Main Body
[0060] 302b, 304b, 302b', 304b': Extension
[0061] 302b1, 302b2, 302b3, 304b1, 304b2, 304b3, 302b2', 302b3', 304b1', 304b2', 304b3': Finger electrodes
[0062] 306: First electrode pad
[0063] 308: Second electrode pad
[0064] 310, 310': First insulation structure
[0065] 312: Conductive layer
[0066] 314: Metal Reflective Structure
[0067] 316, 316': Second insulation structure
[0068] 316a, 316a': Third opening
[0069] 316b, 316b': Fourth opening
[0070] B1: First Extension
[0071] B2: Second Extension
[0072] C, C', C”: concave part
[0073] D m D n :distance
[0074] P, P': Platform Department
[0075] R1: Zone 1
[0076] R2: Second District
[0077] S1, S2: Sidewalls
[0078] x, y: axes Detailed Implementation
[0079] To provide a more detailed and complete description of the present invention, the following will be written in conjunction with the accompanying drawings. It should be noted that the following illustrations are examples of semiconductor elements used to illustrate the present invention and are not intended to limit the invention to these embodiments. In the drawings and descriptions, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or dimensions of the elements in the drawings are illustrative and not actually limited thereto. It should be particularly noted that elements not depicted in the figures may be in forms known to those skilled in the art.
[0080] Unless otherwise specified, the general formula InGaP represents Inx0Ga1-x0P, where 0<x0<1; the general formula AlInP represents Alx1In1-x1P, where 0<x1<1; the general formula InGaN represents Inx2Ga1-x2N, where 0<x2<1; the general formula AlGaN represents Alx3Ga1-x3N, where 0<x3<1; the general formula AlGaInP represents Alx4Gax5In1-x4-x5P, where 0<x4<1 and 0<x5<1; the general formula InGaAsP represents Inx6Ga1-x6Asx7P1-x7, where 0<x6<1, 0<x7<1; the general formula AlGaInAs represents Alx8Gax9In1-x8-x9As, where 0<x8<1, 0<x9<1; the general formula InGaNAs represents Inx10Ga1-x10Nx11As1-x11, where 0<x10<1, 0<x11<1; the general formula InGaAs represents Inx12Ga1-x12As, where 0<x12<1; the general formula AlGaAs represents Alx13Ga1-x13As, where 0<x13<1; the general formula AlInGaN represents Al x14Inx15Ga1-x14-x15N, where 0<x14<1, 0<x15<1; the general formula AlGaAsP represents Alx16Ga1-x16Asx17P1-x17, where 0<x16<1, 0<x17<1. The content of each element can be adjusted for different purposes, such as but not limited to adjusting the band gap size, or when the semiconductor element is a light-emitting element, the dominant wavelength or peak wavelength of the light-emitting element can be adjusted thereby.
[0081] The semiconductor element described in this invention is, for example, a semiconductor optoelectronic element, such as a light-emitting element (e.g., a light-emitting diode or laser diode) or a light-absorbing element (e.g., a photodiode or solar cell), or a non-optoelectric device. The composition of each layer and the dopant in the semiconductor element described in this invention can be analyzed using any suitable method, such as secondary ion mass spectrometry (SIMS), and the thickness of each layer can also be analyzed using any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM). Those skilled in the art will understand that other components can be added to the embodiments described below. For example, unless otherwise specified, descriptions such as "the first layer (structure) is located on the second layer (structure)" can include embodiments where the first layer (structure) and the second layer (structure) are in direct contact, or embodiments where the first layer (structure) and the second layer (structure) have other structures between them and are not in direct contact. In addition, it should be understood that the vertical relationship between the layers (structures) may change depending on the orientation from which they are viewed.
[0082] Figure 1 This is a cross-sectional schematic diagram of a semiconductor epitaxial structure 10 according to an embodiment of the present invention. Figure 1As shown, the semiconductor epitaxial structure 10 includes a first semiconductor structure 110, a second semiconductor structure 120, and an active region 130. The active region 130 is located between the first semiconductor structure 110 and the second semiconductor structure 120. The first semiconductor structure 110 and the second semiconductor structure 120 may have different conductivity types; for example, each layer in the first semiconductor structure 110 may be n-type and each layer in the second semiconductor structure 120 may be p-type, or each layer in the first semiconductor structure 110 may be p-type and each layer in the second semiconductor structure 120 may be n-type. In one embodiment, the first semiconductor structure 110 and the second semiconductor structure 120 may respectively provide electrons and holes (or holes and electrons), and the electrons and holes may combine in the active region 130 to emit light of a specific wavelength. The light may include visible light or invisible light. The conductivity type of each layer in the first semiconductor structure 110 and the second semiconductor structure 120 can be adjusted by adding different dopants. The dopant may include elements from Group II, Group IV, or Group VI of the periodic table, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si), or tellurium (Te). The semiconductor epitaxial structure 10 may be formed by methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor deposition (HVPE).
[0083] The semiconductor epitaxial structure 10 may also optionally include a growth substrate 100. For example... Figure 1 As shown, the growth substrate 100 may be adjacent to the second semiconductor structure 120. A semiconductor epitaxial structure 10 may be formed on the growth substrate 100. Figure 1 As shown, the growth substrate 100 is located below the first semiconductor structure 110, the second semiconductor structure 120, and the active region 130. The growth substrate 100 can be used for epitaxial growth, for example, as a sapphire, gallium nitride (GaN), silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), or gallium phosphide (GaP) substrate. According to some embodiments, the growth substrate 100 and the second semiconductor structure 120 may have different conductivity types. For example, the growth substrate 100 may be n-type and each layer in the second semiconductor structure 120 may be p-type, or the growth substrate 100 may be p-type and each layer in the second semiconductor structure 120 may be n-type. In some embodiments, a p-type second semiconductor structure 120 and an n-type first semiconductor structure 110 may be sequentially formed on a growth substrate 100 with an n-type conductivity type.
[0084] The semiconductor epitaxial structure 10 may include a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum well (MQW) structure. Each layer in the first semiconductor structure 110, the second semiconductor structure 120, and the active region 130 may respectively contain a group III-V semiconductor material. The aforementioned group III-V semiconductor material may contain elements such as aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). In some embodiments, the first semiconductor structure 110, the active region 130, and the second semiconductor structure 120 may not contain nitrogen (N). The aforementioned group III-V semiconductor material may be a binary compound semiconductor (such as GaAs, GaP, or GaN), a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaNAs, or AlGaAsP). When the semiconductor epitaxial structure 10 is used as a light-emitting element, the light emitted by the active region 130 depends on the material composition of the active region 130. For example, when the material of the active region 130 contains AlGaN, it can emit ultraviolet light with a peak wavelength of 250 nm to 400 nm; when the material of the active region 130 contains InGaN, it can emit deep blue or blue light with a peak wavelength of 400 nm to 490 nm, or green or yellow light with a peak wavelength of 490 nm to 550 nm, or red light with a peak wavelength of 560 nm to 650 nm; when the material of the active region 130 contains InGaP or AlGaInP, it can emit yellow, orange, or red light with a peak wavelength of 530 nm to 700 nm; when the material of the active region 130 contains InGaAs, InGaAsP, AlGaAs, or AlGaInAs, it can emit infrared light with a peak wavelength of 700 nm to 1700 nm.
[0085] The first semiconductor structure 110 and the second semiconductor structure 120 can each be a single-layer or multi-layer structure. For example... Figure 1 As shown, the first semiconductor structure 110 may include a first semiconductor layer 110a, a second semiconductor layer 110b, and a third semiconductor layer 110c. The second semiconductor structure 120 may include a fourth semiconductor layer 120a, a fifth semiconductor layer 120b, a sixth semiconductor layer 120c, a seventh semiconductor layer 120d, and an eighth semiconductor layer 120e. Figure 1As shown, the third semiconductor layer 110c and the seventh semiconductor layer 120d may be adjacent to the active region 130. In some embodiments, the second semiconductor structure 120 may optionally include a fifth semiconductor layer 120b and an eighth semiconductor layer 120e.
[0086] The first semiconductor layer 110a and the sixth semiconductor layer 120c serve as window layers, for example. The first semiconductor layer 110a and the sixth semiconductor layer 120c may be transparent to light emitted from the active region 130, which helps to increase the light extraction efficiency and / or the uniformity of current distribution of the semiconductor epitaxial structure 10. According to some embodiments, the first semiconductor layer 110a and the sixth semiconductor layer 120c may comprise the same or different III-V semiconductor materials, such as ternary or quaternary arsenides or phosphides. According to some embodiments, the first semiconductor layer 110a comprises a first III-V semiconductor material. The first III-V semiconductor material may comprise a ternary or quaternary arsenide or phosphide, such as a ternary III-V semiconductor compound (e.g., AlGaAs or AlInP) or a quaternary III-V semiconductor compound (e.g., AlGaInP). According to some embodiments, the sixth semiconductor layer 120c comprises a sixth III-V semiconductor material. The sixth group III-V semiconductor materials may include ternary or quaternary arsenides or phosphides, such as ternary III-V semiconductor compounds (e.g., AlGaAs) or quaternary III-V semiconductor compounds (e.g., AlGaInP).
[0087] In some embodiments, the first semiconductor layer 110a may also serve as a contact layer to form good contact (e.g., ohmic contact) with a metal material. Specifically, the first semiconductor layer 110a may be the thickest semiconductor layer in the first semiconductor structure 110, and may have both current diffusion and contact functions. According to some embodiments, the first III-V semiconductor material may be an n-type semiconductor compound (such as n-AlGaAs or n-AlGaInP), which may have a lower band gap and better carrier mobility, for example, compared to a p-type semiconductor compound (such as GaP). According to some embodiments, the band gap of the first III-V semiconductor material may be larger than the band gap of the growth substrate 100 (such as GaAs) but smaller than the band gap of GaP, and / or the difference between the lattice constant of the first III-V semiconductor material and the lattice constant of the growth substrate 100 material may be smaller than the difference between the lattice constant of GaP and the lattice constant of the growth substrate 100 material. As a result, the epitaxial quality of the first semiconductor layer 110a can be further improved, and the first semiconductor layer 110a can more easily form good contact with the metal material (e.g., ohmic contact).
[0088] According to some embodiments, the thickness of the first semiconductor layer 110a may be in the range of 2 μm to 8 μm. This is beneficial for improving the diffusion of current in the first semiconductor layer 110a. The first semiconductor layer 110a may include a first dopant, and the concentration of the first dopant is, for example, at 5×10 17 cm -3 to 5×10 18 cm -3 range. For example: the first III-V group semiconductor material comprises Al y1 Ga 1-y1 As, where 0<y1<0.2, and the concentration of the first dopant in the first semiconductor layer 110a is at 5×10 17 cm -3 or more; the first III-V group semiconductor material comprises Al y2 In 1-y2 P, where 0.45<y2<0.55, and the concentration of the first dopant in the first semiconductor layer 110a is at 1×10 18 cm -3 or more; alternatively, the first III-V group semiconductor material comprises (Al y3 Ga (1-y3) ) 1- y4 In y4 P, where 0<y3<0.6, 0.45<y4<0.55, and the concentration of the first dopant in the first semiconductor layer 110a is at 1×10 18 cm -3 or more. According to some embodiments, by setting the thickness of the first semiconductor layer 110a and / or the concentration of the first dopant within the above ranges, it can help reduce the forward voltage of a semiconductor device fabricated from the semiconductor epitaxial structure 10, and help improve brightness and enhance photoelectric conversion efficiency (Wall-Plug-Efficiency, WPE).
[0089] The second semiconductor layer 110b serves, for example, as a bonding support layer. According to some embodiments, the second semiconductor layer 110b includes a second III-V semiconductor material. The second III-V semiconductor material may differ from the first III-V semiconductor material. According to some embodiments, the second III-V semiconductor material may include a binary III-V semiconductor compound (such as GaP, GaAs), a ternary (such as AlGaAs), or a quaternary III-V semiconductor compound (such as AlGaInP). The thickness of the second semiconductor layer 110b may be less than the thickness of the first semiconductor layer 110a, for example, in the range of 1 μm to 3 μm. When the first semiconductor structure 110 needs to be bonded to a bonding substrate (not shown), the structure with the second semiconductor layer 110b in the first semiconductor structure 110 can further improve the stability of the bonding fabrication process. The second semiconductor layer 110b may or may not include dopants. According to some embodiments, the second semiconductor layer 110b may include a second dopant. The second dopant may be the same as or different from the first dopant. According to some embodiments, the concentration of the second dopant in the second semiconductor layer 110b is, for example, 1 × 10⁻⁶. 16 cm -3 Below or 1×10 15 cm -3 the following.
[0090] According to some embodiments, the third semiconductor layer 110c and the seventh semiconductor layer 120d are adjacent to the active region 130 and can serve as cladding layers to provide electrons and holes (or holes or electrons), respectively. The third semiconductor layer 110c may be located between the first semiconductor layer 110a and the active region 130. According to some embodiments, the third semiconductor layer 110c and the seventh semiconductor layer 120d may comprise the same or different III-V semiconductor materials, such as ternary or quaternary arsenides or phosphides. The third semiconductor layer 110c may comprise a third III-V semiconductor material, while the seventh semiconductor layer 120d may comprise a seventh III-V semiconductor material. In some embodiments, the third III-V semiconductor material and the seventh III-V semiconductor material may comprise ternary III-V semiconductor compounds (such as AlGaAs). The third semiconductor layer 110c may comprise a third dopant. The third dopant may be the same as or different from the first or second dopant. In the third semiconductor layer 110c, the concentration of the third dopant is, for example, 1 × 10⁻⁶. 17 cm -3 Up to 1×10 18 cm -3The scope. According to some embodiments, the first dopant, the second dopant, and the third dopant may be Group II, Group IV, or Group VI elements in the Periodic Table of the Elements, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si), sulfur (S), selenium (Se), germanium (Ge), or tellurium (Te). According to some embodiments, the first dopant, the second dopant, and the third dopant may be selected from silicon (Si), sulfur (S), selenium (Se), germanium (Ge), or tellurium (Te).
[0091] The fourth semiconductor layer 120a can serve as a contact layer to form a good contact (for example, an ohmic contact) with a metal material. The fourth semiconductor layer 120a may include a fourth III-V semiconductor material. In some embodiments, the fourth III-V semiconductor material comprises a binary III-V semiconductor compound (such as GaAs or GaP) or a ternary III-V semiconductor compound (such as AlGaAs). In some embodiments, the fourth III-V semiconductor material may comprise Al y5 Ga 1-y5 As, and 0<y5<0.2. The fourth semiconductor layer 120a may include a fourth dopant. In the fourth semiconductor layer 120a, the concentration of the fourth dopant is, for example, in 5×10 18 cm -3 to 5×10 19 cm -3 The scope.
[0092] The semiconductor epitaxial structure 10 may optionally further include a fifth semiconductor layer 120b and an eighth semiconductor layer 120e therebetween. As Figure 1 shown, in this embodiment, the fourth semiconductor layer 120a is located between the fifth semiconductor layer 120b and the eighth semiconductor layer 120e. In some embodiments, the fifth semiconductor layer 120b and the eighth semiconductor layer 120e serve as, for example, transition layers. For example, when the lattices between the materials of the fourth semiconductor layer 120a and the sixth semiconductor layer 120c are mismatched, the fifth semiconductor layer 120b can act as a transition layer to reduce stress and stabilize the structure; when the lattices between the materials of the fourth semiconductor layer 120a and the growth substrate 100 are mismatched, the eighth semiconductor layer 120e can act as a transition layer to reduce stress and stabilize the structure. In some embodiments, the fifth semiconductor layer 120b and the eighth semiconductor layer 120e serve as, for example, etch stop layers. The fifth semiconductor layer 120b may include a fifth III-V semiconductor material, and the eighth semiconductor layer 120e may include an eighth III-V semiconductor material. According to some embodiments, the fifth III-V semiconductor material and the eighth III-V semiconductor material may include a ternary III-V semiconductor compound (such as indium gallium phosphide (InGaP)). The thicknesses of the fifth semiconductor layer 120b and the eighth semiconductor layer 120e may be greater than the thickness of the fourth semiconductor layer 120a.
[0093] According to some embodiments, the fifth semiconductor layer 120b, the sixth semiconductor layer 120c, the seventh semiconductor layer 120d, and the eighth semiconductor layer 120e may respectively include a fifth dopant, a sixth dopant, a seventh dopant, and an eighth dopant. Any two of the fourth, fifth, sixth, seventh, and eighth dopants may be the same or different. According to some embodiments, in the fifth semiconductor layer 120b, the concentration of the fifth dopant is, for example, 8 × 10⁻⁶. 17 cm -3 Up to 8×10 18 cm -3 The range. In the sixth semiconductor layer 120c, the concentration of the sixth dopant is, for example, 1 × 10⁻⁶. 17 cm -3 Up to 2×10 19 cm -3 The concentration of the seventh dopant in the seventh semiconductor layer 120d is, for example, 5 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The range of ranges. In the eighth semiconductor layer 120e, the concentration of the eighth dopant is, for example, 8 × 10⁻⁶. 17 cm -3 Up to 8×10 18 cm -3 The range is defined. According to some embodiments, the fourth, fifth, sixth, seventh, and eighth dopants can be elements from Group II, Group IV, or Group VI of the periodic table, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si), beryllium (Be), sulfur (S), selenium (Se), germanium (Ge), or tellurium (Te). According to some embodiments, the fourth, fifth, sixth, seventh, and eighth dopants can be selected from magnesium (Mg), zinc (Zn), beryllium (Be), or carbon (C).
[0094] The semiconductor epitaxial structure 10 may optionally include a buffer layer (not shown) located between the growth substrate 100 and the second semiconductor structure 120. The buffer layer may be used, for example, to compensate for lattice constant differences between the growth substrate 100 and the second semiconductor structure 120 or to suppress epitaxial defects, preventing epitaxial defects from extending from the growth substrate 100 to the second semiconductor structure 120 to improve epitaxial quality, or to reduce the impact of dopants in the growth substrate 100 on subsequent epitaxial growth. According to some embodiments, the buffer layer 101 may also include a III-V semiconductor material, such as a binary III-V semiconductor compound like gallium arsenide (GaAs).
[0095] In this embodiment, the active region 130 is illustrated using a multiple quantum well (MQW) structure as an example. Figure 1As shown, the active region 130 may include a semiconductor stack 130a. The semiconductor stack 130a may include N pairs of interleaved barrier layers 130a1 and well layers 130a2. In some embodiments, N may be a positive integer greater than or equal to 1 and less than or equal to 15. Figure 1 As shown, the semiconductor stack 130a may optionally include an additional barrier layer 130a1', adjacent to the well layer 130a2 in the Nth pair of barrier layers 130a1 and well layers 130a2. The active region 130 may optionally include a first confinement structure 130b and a second confinement structure 130c. The first confinement structure 130b and the second confinement structure 130c may be single-layer or multi-layer structures, respectively.
[0096] Furthermore, the semiconductor epitaxial structure 10 can be used to fabricate semiconductor components and semiconductor devices. Figures 2A to 7 The structure of semiconductor components and semiconductor devices will be illustrated in the following sections. Figure 2A This is a top view schematic diagram of a semiconductor element 20 according to an embodiment of the present invention. Figure 2B for Figure 2A A schematic cross-sectional view of semiconductor device 20 along line X-X'. (See diagram below.) Figure 2A and Figure 2B As shown, the semiconductor device 20 may include a semiconductor epitaxial structure 10. The semiconductor device 20 also includes a first electrode 202 and a second electrode 204. Figure 2A As shown, the semiconductor epitaxial structure 10 may have a recess C. The recess C is formed, for example, by removing the second semiconductor structure 120, the active region 130, and a portion of the first semiconductor structure 110 using wet etching or dry etching. The bottom of the recess C may be formed by a first semiconductor layer 110a. In this embodiment, as... Figure 2A As shown, the second semiconductor structure 120, the active region 130, and another portion of the first semiconductor structure 110 form the platform portion P. Specifically, as... Figure 2B As shown, the first semiconductor layer 110a has an upper surface 110s. The upper surface 110s has a first region R1 and a second region R2. The second semiconductor structure 120 and the active region 130 are located in the first region R1 but not in the second region R2. According to some embodiments, the second region R2 may surround the first region R1. The active region 130 is located between the first semiconductor structure 110a and the second semiconductor structure 120.
[0097] like Figure 2BAs shown, the first electrode 202 is located on the second region R2. Specifically, the first electrode 202 is located on the first semiconductor layer 110a and is in direct contact with the first semiconductor layer 110a to form an electrical connection. The second electrode 204 is located on the second semiconductor structure 120. The second electrode 204 is located on the fourth semiconductor layer 120a and is in direct contact with the fourth semiconductor layer 120a. From a top view, the first electrode 202 and the second electrode 204 can be circular, elliptical, rectangular, or other polygonal in shape. In this embodiment, the fourth semiconductor layer 120a can be a patterned semiconductor layer, and the fourth semiconductor layer 120a, for example, has the same width as the second electrode 204. The width of the fifth semiconductor layer 120b can be greater than the width of the fourth semiconductor layer 120a. According to some embodiments, when the material of the fourth semiconductor layer 120a absorbs the light emitted by the active region 130, patterning the fourth semiconductor layer 120a can reduce the absorption of light emitted by the active region 130 by its material, thereby increasing the light-emitting intensity of the device.
[0098] The semiconductor element 20 may further selectively include an insulating structure 206 covering the semiconductor epitaxial structure 10. In this embodiment, the insulating structure 206 may have a first opening 206a and a second opening 206b corresponding to the first electrode 202 and the second electrode 204, respectively. The insulating structure 206 provides insulation, protection, and / or reflection functions, such as isolating external moisture or contamination, preventing damage to the active region 130 in the semiconductor epitaxial structure 10, and preventing leakage paths in the element. The insulating structure 206 may have a single-layer or multi-layer structure and may include a dielectric material, such as an oxide, nitride, or polymer, or a combination thereof. The oxide may include aluminum oxide (Al₂O₃). x ), silicon dioxide (SiO) x Titanium oxide (TiO) x Niobium pentoxide (Nb₂O₅) or tantalum pentoxide (Ta₂O₅) may be present. Nitrides may include aluminum nitride (AlN) or silicon nitride (SiN). xThe polymer may contain polyimide or benzocyclobutane (BCB). In some embodiments, the insulating structure 206 may further have a reflective function, for example, comprising a distributed Bragg reflector (DBR). The distributed Bragg reflector may comprise multiple overlapping first dielectric layers and multiple second dielectric layers (not shown), with the first and second dielectric layers having different refractive indices. The first and second dielectric layers may comprise silicon dioxide (SiO2), titanium dioxide (TiO2), or niobium pentoxide (Nb2O5), for example, combinations of the first and second dielectric layers such as SiO2 / Al2O3, SiO2 / TiO2, or SiO2 / Nb2O5. Due to the reflective function of the insulating structure 206, the light emitted from the active region 130 can be primarily emitted from the first semiconductor structure 110 side.
[0099] According to some embodiments, the materials of the first electrode 202 and the second electrode 204 may comprise conductive oxides, metals, or alloys. Examples of conductive oxides include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), or combinations thereof. Examples of metals include titanium (Ti), germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), silver (Ag), platinum (Pt), nickel (Ni), or copper (Cu). Alloys may comprise at least two selected from the group consisting of the aforementioned metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), titanium gold (TiAu), etc. The materials of the first electrode 202 and the second electrode 204 may be different or the same. According to some embodiments, the first electrode 202 comprises germanium gold (GeAu), and the second electrode 204 comprises beryllium gold (BeAu) or titanium gold (TiAu). According to some embodiments, the second electrode 204 may comprise indium tin oxide (ITO), indium zinc oxide (IZO), gold (Au), or silver (Ag).
[0100] Semiconductor element 20 may also optionally include a bonding substrate 200 and a bonding structure 201. The bonding substrate 200 is located below the first semiconductor structure 110. The bonding structure 201 is located between the bonding substrate 200 and the first semiconductor structure 110 to connect the two. The bonding substrate 200 may be an insulating material, such as sapphire or glass. The bonding structure 201 may be an insulating material, such as a nitride or oxide (e.g., tantalum oxide (TaOx), aluminum oxide (AlOx)). x), silicon dioxide (SiO) x Titanium oxide (TiO) x ), silicon nitride (SiN) x Alternatively, polymers such as benzocyclobutene (BCB), epoxy resin, polyimide, or silicone resin can be used. According to some embodiments, when the first semiconductor layer 110a has an n-type conductivity and is the thickest layer in the first semiconductor structure, the lateral current conduction capability of the first semiconductor structure 110 can be further optimized, providing the required charge carriers, current diffusion, and contact characteristics (such as reduced forward voltage) for the semiconductor element 20. For example, compared to a semiconductor element where the first semiconductor layer 110a includes a p-type compound semiconductor (such as p-GaP), a semiconductor element where the first semiconductor layer 110a includes an n-type compound semiconductor (such as n-AlGaAs or n-AlGaInP) can have better current diffusion performance, achieving lower forward voltage and better brightness.
[0101] In some embodiments, a method for manufacturing a semiconductor element 20 may include the following steps: providing a semiconductor epitaxial structure 10; performing a bonding process to bond a first semiconductor structure 110 to a bonding substrate 200 via a bonding structure 201; removing a growth substrate 100 from the semiconductor epitaxial structure 10; removing a portion of the first semiconductor structure 110, the second semiconductor structure 120, and the active region 130 to form a recess C and a platform portion P; forming a first electrode 202 in the recess C; and forming a second electrode 204 on a fourth semiconductor layer 120a. In some embodiments, the method for manufacturing a semiconductor element 20 may also optionally include removing the bonding substrate 200 and the bonding structure 201 after forming the first electrode 202 and the second electrode 204. Figure 2B As shown, the lower surface 110b1 of the second semiconductor layer 110b can be roughened to form an uneven structure to further improve the light extraction efficiency of the semiconductor device 20. In some embodiments, the average roughness (Ra) of the lower surface 110b1 can be less than 0.15 µm, for example, in the range of 0.09 µm to 0.14 µm. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in the previous embodiments and will not be repeated here.
[0102] Figure 3A This is a top view of a semiconductor element 30 according to an embodiment of the present invention. Figure 3B for Figure 3A A schematic cross-sectional view of semiconductor element 30 along line AB. Figure 3C for Figure 3A A schematic cross-sectional view of semiconductor element 30 along line CD. Figure 3D for Figure 3A A schematic cross-sectional view of semiconductor device 30 along line EF. (See attached diagram.) Figure 3A As shown, viewed from above, the semiconductor element 30 has a first side surface 30a, a second side surface 30b, a third side surface 30c, and a fourth side surface 30d. The first side surface 30a and the third side surface 30c are opposite to each other, and the second side surface 30b and the fourth side surface 30d are opposite to each other. The semiconductor element 30 includes a semiconductor epitaxial structure 10. In this embodiment, the semiconductor epitaxial structure 10 has a platform portion P' and a recess portion C'. The semiconductor element 30 also includes a first electrode 302 and a plurality of second electrodes 304 that are separated from each other. The first electrode 302 is located in the recess portion C' and is in direct contact with the first semiconductor layer 110a, and the plurality of second electrodes 304 that are separated from each other are in direct contact with the fourth semiconductor layer 120a.
[0103] like Figure 3A As shown, the first electrode 302 may have a main body 302a and an extension 302b. In this embodiment, the extension 302b may include a plurality of finger electrodes 302b1, 302b2, and 302b3. The cross-sectional width of each finger electrode 302b1, 302b2, and 302b3 may be smaller than the cross-sectional width of the main body 302a. Specifically, finger electrode 302b1 is directly connected to the main body 302a and extends towards the third side 30c; finger electrode 302b2 is directly connected to the main body 302a, extends first along the first side 30a, and then turns to extend along the second side 30b; while finger electrode 302b3 is directly connected to the main body 302a, extends first along the first side 30a, and then turns to extend along the fourth side 30d. According to some embodiments, by having the above-described extension design, current diffusion in the semiconductor element 30 can be further improved, which helps to improve luminous efficiency.
[0104] like Figures 3A to 3D As shown, a plurality of second electrodes 304 can be arranged in a two-dimensional array. The shape of each second electrode 304 is, for example, circular, elliptical, rounded rectangular, or other shapes. The maximum width of each second electrode 304 is, for example, in the range of 7 µm to 20 µm. According to some embodiments, the shortest distance between the second electrode 304 and the extension 302b of the first electrode 302 (e.g., Figure 3A Distance D indicated by the middle mark m The distance can be in the range of 25 µm to 70 µm. According to some embodiments, the shortest distance between the main body 302a of the first electrode 302 and the second electrode 304 (e.g.) Figure 3A and Figure 3C Distance D indicated by the middle mark nThe aperture can be in the range of 25 µm to 70 µm. According to some embodiments, the current diffusion in the semiconductor element 30 can be further improved by having a plurality of second electrodes 304 arranged in a two-dimensional array, which helps to improve the luminous efficiency.
[0105] like Figures 3A to 3D As shown, the semiconductor element 30 further includes a first electrode pad 306 and a second electrode pad 308, covering the semiconductor epitaxial structure 10. The first electrode pad 306 is electrically connected to the first electrode 302, and the second electrode pad 308 is electrically connected to a plurality of second electrodes 304. The semiconductor element 30 may also include a first insulating structure 310, covering the semiconductor epitaxial structure 10 and having a plurality of first openings 310a and second openings 310b. One of the plurality of first openings 310a corresponds to one of the plurality of second electrodes 304, that is, the plurality of first openings 310a and the plurality of second electrodes 304 have a one-to-one correspondence. The second opening 310b corresponds to the first electrode 302. Figure 3C As shown, the first electrode pad 306 can be filled into the second opening 310b to directly contact the first electrode 302. The first electrode pad 306 and the second electrode pad 308 may contain metallic materials, such as nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), tin (Sn), copper (Cu), bismuth (Bi), indium (In), or combinations thereof.
[0106] The semiconductor element 30 may also optionally include a conductive layer 312, a metal reflective structure 314, and / or a second insulating structure 316. The second insulating structure 316 may cover the first insulating structure 310, the conductive layer 312, and the metal reflective structure 314. Figures 3B to 3C As shown, the first insulating structure 310 and the second insulating structure 316 may cover the sidewall S1 of the platform portion P', the sidewall S2 of the first semiconductor structure 110, and the bottom of the recess C'. The first insulating structure 310 and / or the second insulating structure 316 may have a single-layer or multi-layer structure and may contain a dielectric material, such as an oxide, a nitride, or a polymer, or a combination thereof. The oxide may contain aluminum oxide (Al₂O₃). x ), silicon dioxide (SiO) x Titanium oxide (TiO) x Niobium pentoxide (Nb₂O₅) or tantalum pentoxide (Ta₂O₅) may be present. Nitrides may include aluminum nitride (AlN) or silicon nitride (SiN). xThe polymer may comprise polyimide (PI) or benzocyclobutane (BCB). In some embodiments, the first insulating structure 310 and / or the second insulating structure 316 may further have a reflective function, for example, comprising a dispersed Bragg mirror (DBR). Specific structures of dispersed Bragg mirrors can be found in the foregoing embodiments. According to some embodiments, the first insulating structure 310 may include a DBR, while the second insulating structure 316 may not include a DBR. Figures 3A to 3D As shown, the second insulating structure 316 may have a third opening 316a and a fourth opening 316b. The third opening 316a may be located below the second electrode pad 308 and correspond to a plurality of first openings 310a. The fourth opening 316b may be located below the first electrode pad 306 and correspond to the second opening 310b. The size of the third opening 316a may be larger than the size of the fourth opening 316b. By providing a plurality of first openings 310a, second openings 310b, third openings 316a and fourth openings 316b, in conjunction with other conductive structures (such as conductive layer 312 and metal reflective structure 314), an effective current path can be formed in the semiconductor element 30, and current diffusion can be facilitated.
[0107] The conductive layer 312 may be located between the first insulating structure 310 and the metal reflective structure 314. The conductive layer 312 may include, for example, conductive oxides such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), or combinations thereof. In this embodiment, since the plurality of second electrodes 304 are separated from each other, the conductive layer 312 allows the plurality of second electrodes 304 to form an electrical connection with the second electrode pad 308. In some embodiments, the conductive layer 312 may facilitate current diffusion and may serve as an adhesive layer to improve adhesion between the first insulating structure 310 and the metal reflective structure 314, thereby improving structural stability. In some embodiments, the semiconductor element 30 may also not have the conductive layer 312, and the metal reflective structure 314 may be in direct contact with the first insulating structure 310.
[0108] A metal reflective structure 314 may be located between the conductive layer 312 and the second insulating structure 316. Specifically, the metal reflective structure 314 may include gold (Au), silver (Ag), or aluminum (Al). The metal reflective structure 314 can help improve the lateral current conduction capability in the semiconductor element 30. According to some embodiments, by covering the first insulating structure 310 (e.g., DBR) with the metal reflective structure 314, an omnidirectional reflector (ODR) structure can be formed, further increasing the reflection effect and improving the luminous efficiency of the element. The semiconductor element 30 may also optionally include a bonding substrate 300 and a bonding structure 301. The bonding substrate 300 is located below the first semiconductor structure 110. The bonding structure 301 is located between the bonding substrate 300 and the first semiconductor structure 110 to connect the two. Regarding the bonding substrate 300 and the bonding structure 301, refer to the foregoing description of the bonding substrate 200 and the bonding structure 201.
[0109] In some embodiments, a method for manufacturing a semiconductor element 30 may include the following steps: providing a semiconductor epitaxial structure 10; performing a bonding fabrication process to bond a first semiconductor structure 110 to a bonding substrate 300 via a bonding structure 301; removing a growth substrate 100 from the semiconductor epitaxial structure 10; removing a portion of the first semiconductor structure 110, the second semiconductor structure 120, and the active region 130 to form a recess C' and a platform portion P'; forming a first electrode 302 in the recess C', and forming a second electrode 304 on a fourth semiconductor layer 120a. The method for manufacturing a semiconductor element 30 may further include the following steps: forming a first insulating structure 310 having a plurality of first / second openings on the semiconductor epitaxial structure 10; forming a conductive layer 312 on the first insulating structure 310; forming a metal reflective structure 314 on the conductive layer 312; forming a second insulating structure 316 having a plurality of third / fourth openings on the metal reflective structure 314; and forming a first electrode pad 306 and a second electrode pad 308 on the second insulating structure 316. According to some embodiments, the manufacturing method of the semiconductor element 30 may also optionally include removing the bonding substrate 300 and the bonding structure 301 after forming the first electrode pad 306 and the second electrode pad 308. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in the previous embodiments and will not be repeated here.
[0110] Figure 4 This is a top view schematic diagram of a semiconductor element 40 according to an embodiment of the present invention. The main difference between semiconductor element 40 and semiconductor element 30 lies in the design of the second electrode. Figure 4As shown, in this embodiment, the second electrode 304' in the semiconductor element 40 includes a main body portion 304a and an extension portion 304b. In this embodiment, the main body portion 304a includes a first main body portion 304a1 and a second main body portion 304a2. The extension portion 304b may include a plurality of finger electrodes 304b1, 304b2, and 304b3. The cross-sectional width of each finger electrode 304b1, 304b2, and 304b3 may be smaller than the cross-sectional width of the first main body portion 304a1 and / or the second main body portion 304a2. Specifically, the finger electrode 304b1 may be directly connected to the first main body portion 304a1 and the second main body portion 304a2, and extends along the direction of the third side surface 30c. The finger electrode 304b2 may be directly connected to the first main body portion 304a1, and extends along the direction of the second side surface 30b. In this embodiment, both the first electrode 302 and the second electrode 304' have a finger electrode design. From a top view, the finger electrode 304b2 in the second electrode 304' is located between the finger electrodes 302b1 and 302b3 in the first electrode 302, while the finger electrode 304b3 is located between the finger electrodes 302b1 and 302b2 in the first electrode 302. In some embodiments, this staggered arrangement also facilitates current diffusion. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in previous embodiments and will not be repeated here.
[0111] Figure 5 This is a top view schematic diagram of a semiconductor element 50 according to an embodiment of the present invention. The main difference between semiconductor element 50 and semiconductor element 30 lies in the design of the platform portion and the first / second electrodes. Figure 5 As shown, in the semiconductor element 50, the recess C” is located at a corner (e.g., where the first side 30a and the fourth side 30d meet). The first electrode 302' has a main body 302a' and an extension 302b'. In this embodiment, the extension 302b' may include a plurality of finger electrodes 302b2' and 302b3'. The cross-sectional width of each finger electrode 302b2' and 302b3' may be smaller than the cross-sectional width of the main body 302a'. The main body 302a' is located in the recess C”; the finger electrodes 302b2' are directly connected to the main body 302a' and extend first along the direction of the first side 30a, then turn and extend along the direction of the second side 30b; the finger electrodes 302b3' are directly connected to the main body 302a' and extend first along the direction of the fourth side 30d, then turn and extend along the direction of the third side 30c. Since this embodiment does not have such Figure 3A or Figure 4 The recess C' extends to the center of the component, so a greater number of separate second electrodes 304 can be provided on the platform portion P'. Figure 5As shown, among the multiple second electrodes 304” arranged in a two-dimensional pattern, the second electrodes 304” in any row are staggered with the second electrodes 304” in the adjacent rows.
[0112] like Figure 5 As shown, the first insulating structure 310' may have a plurality of first openings 310a" and second openings 310b'. One of the plurality of first openings 310a" corresponds to one of the plurality of second electrodes 304". The second opening 310b' corresponds to the main body portion 302a' of the first electrode 302'. The second insulating structure 316' may have a third opening 316a' and a fourth opening 316b'. The third opening 316a' may be located below the second electrode pad 308 and corresponds to the plurality of first openings 310a". The fourth opening 316b' may be located below the first electrode pad 306 and corresponds to the second opening 310b'. In this embodiment, the platform portion P' has a protruding portion P1, located at the corner opposite to the recess C" (e.g., where the second side surface 30b and the third side surface 30c meet). The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in previous embodiments and will not be repeated here.
[0113] Figure 6 This is a top view schematic diagram of a semiconductor element 60 according to an embodiment of the present invention. The main difference between semiconductor element 60 and semiconductor element 50 lies in the design of the second electrode. Figure 6 As shown, the second electrode 304' in the semiconductor element 60 includes a main body portion 304a' and an extension portion 304b'. In this embodiment, the extension portion 304b' may include a plurality of finger electrodes 304b1', 304b2', and 304b3'. The cross-sectional width of each finger electrode 304b1', 304b2', and 304b3' may be smaller than the cross-sectional width of the main body portion 304a'. In detail, the finger electrode 304b1' can be directly connected to the main body 304a' and extends towards the recess C". In this embodiment, the finger electrode 304b1' further includes a base B, a first extension B1, and a second extension B2. The first extension B1 is directly connected to the base B, extending first along the +y direction and then turning to extend along the +x direction, while the second extension B2 is directly connected to the base B, extending first along the +x direction and then turning to extend along the +y direction. The finger electrode 304b2' is directly connected to the finger electrode 304b1', extending first along the +y direction and then turning to extend along the +x direction. The finger electrode 304b3' is directly connected to the finger electrode 304b1', extending first along the +x direction and then turning to extend along the +y direction. Figure 6As shown, the finger electrode 304b2' and the second extension B2 can be arranged parallel to each other, and the finger electrode 304b3' and the first extension B1 can be arranged parallel to each other. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in previous embodiments and will not be repeated here.
[0114] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device 70 according to an embodiment of the present invention. Figure 7 As shown, the semiconductor device 70 includes a carrier substrate 700 and a semiconductor element 701 located on the carrier substrate 700. Specifically, the semiconductor element 701 may be a semiconductor element described in any of the embodiments of the present invention (such as semiconductor element 20, 30, 40, 50, or 60). For ease of explanation, Figure 7 The following description uses semiconductor element 20 as an example. The carrier substrate 700 is, for example, a package submount or a printed circuit board (PCB). The carrier substrate 800 can be a single-layer or multi-layer structure. The material of the carrier substrate 800 can include polyester, polyimide (PI), BT resin (Bismaleimide Triazine), PTFE resin (Polytetrafluoroethylene), phenolic resins (PF), or glass fiber epoxy. The material of the multiple conductive connections can include metals, such as tin (Sn). Figure 7 As shown, the semiconductor device 70 further includes a first conductive connection portion 700a and a second conductive connection portion 700b. The semiconductor element 701 can be bonded to the carrier substrate 700 via the first conductive connection portion 700a and the second conductive connection portion 700b in a flip-chip manner. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in previous embodiments and will not be repeated here.
[0115] In summary, this invention provides a semiconductor epitaxial structure, a semiconductor element, and a semiconductor device, which can improve current diffusion and increase luminous efficiency. For example, the design of the electrical properties, material, thickness, and / or dopant concentration of the first semiconductor layer helps to further improve the forward voltage, increase brightness, and improve photoelectric conversion efficiency; the provision of a second semiconductor layer can further improve the stability of the bonding fabrication process; roughening the lower surface of the second semiconductor layer can further improve the light extraction efficiency of the element; the arrangement or shape design of the first / second electrodes, and / or the opening position design of the first / second insulating structure, can further improve current diffusion in the element, helping to improve luminous efficiency; the inclusion of a conductive layer, a metal reflective structure, etc., in the element can further improve current diffusion in the element, increase reflection effect, and thus improve the luminous efficiency of the element. The semiconductor element of this invention can exhibit good performance in high-temperature operation life (HTOL) tests, for example. Specifically, the semiconductor element and semiconductor device of this invention can be applied to products in the fields of lighting, display, communication, and power systems, such as lamps, monitors, automotive dashboards, televisions, computers, traffic lights, and outdoor displays.
[0116] Although the present invention has been disclosed above with reference to embodiments, some modifications or changes may be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. The above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the present invention.
Claims
1. A semiconductor element, comprising: Semiconductor epitaxial structures include: A first semiconductor structure includes a first semiconductor layer and a second semiconductor layer located below the first semiconductor layer, and the first semiconductor structure has an upper surface having a first region and a second region. A second semiconductor structure and an active region, located within the first region but not on the second region, wherein the active region is located between the first semiconductor structure and the second semiconductor structure; and The first electrode is located on the second region and is in direct contact with the first semiconductor layer to form an electrical connection; The first semiconductor layer has an n-type conductivity and is the thickest layer in the first semiconductor structure. The first semiconductor layer includes a first III-V group semiconductor material, which includes ternary or quaternary arsenides or phosphides.
2. The semiconductor device of claim 1, wherein the material of the second semiconductor layer comprises a second III-V group semiconductor material.
3. The semiconductor device of claim 1, wherein the first III-V semiconductor material comprises AlGaAs or AlGaInP.
4. The semiconductor device of claim 1, wherein the thickness of the first semiconductor layer is in the range of 2 μm to 8 μm.
5. The semiconductor device of claim 1, wherein the first semiconductor layer comprises a first dopant, and the concentration of the first dopant in the first semiconductor layer is 5 × 10⁻⁶. 17 Up to 5×10 18 The range.
6. The semiconductor device of claim 1, wherein the first semiconductor structure further comprises a third semiconductor layer located between the first semiconductor layer and the active region.
7. The semiconductor element of claim 1 further includes a second electrode located on the second semiconductor structure.
8. The semiconductor device of claim 7, wherein the second semiconductor structure further includes a fourth semiconductor layer and a fifth semiconductor layer located below the fourth semiconductor layer, and the second electrode is in direct contact with the fourth semiconductor layer to form an electrical connection.
9. The semiconductor element of claim 8, wherein the width of the fifth semiconductor layer is greater than the width of the fourth semiconductor layer.
10. The semiconductor element of claim 2, wherein the first III-V semiconductor material is different from the second III-V semiconductor material.