Micro-led light source module and preparation method

Abstract

The application provides a micro LED light source structure and a preparation method thereof. A temporary carrier is provided, a plurality of micro LED chips are transferred to the temporary carrier and rearranged into a plurality of light emitting units; a first redistribution layer is prepared, chip electrodes of the micro LED chips in each light emitting unit are fanned out to form a plurality of first fan-out electrode units; a unit driving chip is arranged in a region surrounded by each first fan-out electrode unit; a second redistribution layer is prepared, driving electrodes of the unit driving chip are electrically connected with the first fan-out electrode units, and a plurality of second fan-out electrode units are formed; and the temporary carrier is removed to form the micro LED light source structure. By vertically stacking the unit driving chip of the micro LED chip on one side thereof, the application effectively solves the problem of low yield of redistribution in the micro LED chip packaging process caused by the large difference between the thickness of the micro LED chip and the thickness of the unit driving chip, light shielding, large packaging size, and realizes high-density, thin, and high-efficiency micro LED light source packaging.

Description

Technical Field

[0001] This invention relates to the field of light-emitting technology, and in particular to a micro-LED light source module and its preparation method. Background Technology

[0002] In recent years, microLED chips have developed rapidly as an active-emitting micro-display technology, with applications covering all display fields, such as large commercial displays, televisions, mobile phones, automotive displays, AR and VR, etc. Besides the display field, microLED chips can also be used in non-display fields such as printing (2D and 3D) and optical interconnects.

[0003] In recent years, the field of LED packaging has seen the rise of micro-LED packaging technology—MIP (Micro LED in Package), which enables passive displays (PM). Subsequently, the technology of integrating driver chips with micro-LED packages—DMIP (Drive & Micro LED in Package)—emerged, enabling active displays (AM).

[0004] However, most mainstream DMIP technologies currently place the driver chip and the microLED chip horizontally, which presents the following problems: 1. Driver chips are mostly silicon-based chips with a thickness of 50-200μm, while the thickness of microLED chips is only 5-10μm. The huge thickness difference between the two leads to a low yield of wafer-level packaging redistribution (RDL) process; 2. The horizontal placement of the packaging makes it difficult to further reduce the size of the package in the planar direction; 3. The size of the driver chip is usually larger than that of the microLED chip, and horizontal placement will affect the light emission spatial distribution of the microLED.

[0005] Therefore, the technical problem to be solved by this invention is how to solve the above problems and provide a micro-LED light source structure and preparation method that can effectively reduce the packaging thickness, improve the RDL yield and optimize the light emission distribution. Summary of the Invention

[0006] This application provides a micro-LED light source structure and its fabrication method to solve the problems of low yield, large size, and poor light extraction efficiency in the packaging process of existing silicon-based driver chips and micro-LED chips.

[0007] This application provides a method for fabricating a micro-LED light source structure, the method comprising: A temporary carrier is provided, and multiple microLED chips are transferred from one side of the growth substrate to the receiving area of ​​the temporary carrier. The multiple microLED chips are rearranged into multiple light-emitting units in the receiving area. A first redistribution layer is prepared, which covers the plurality of light-emitting units and fans out the chip electrodes of the microLED chips in each of the light-emitting units to form a plurality of first fan-out electrode units; Within the area enclosed by each of the first fan-out electrode units, a unit driving chip is provided; A second redistribution layer is fabricated, covering the first redistribution layer and the cell driver chip, and electrically interconnecting the driving electrodes of the cell driver chip with the first fan-out electrode units. Simultaneously, a plurality of second fan-out electrode units are formed, and the plurality of second fan-out electrode units are electrically connected to corresponding plurality of first fan-out electrode units; and Remove the temporary carrier plate to form the micro-LED light source structure.

[0008] As an optional technical solution, each of the light-emitting units includes at least three microLED chips for generating red light, green light and blue light respectively.

[0009] As an optional technical solution, the light-emitting surface of each microLED chip faces the temporary carrier, and the chip electrode of each microLED chip is away from the temporary carrier and exposed.

[0010] As an optional technical solution, transferring multiple microLED chips from one side of the growth substrate to the receiving area of ​​the temporary carrier includes: A transparent adhesive layer is provided on the temporary carrier, and the light-emitting surfaces of the plurality of microLED chips are fixed to the temporary carrier through the transparent adhesive layer.

[0011] As an optional technical solution, the steps for fabricating the first redistribution layer include: A first planarization layer is prepared on the temporary carrier plate, the first planarization layer covering the plurality of light-emitting units; The first planar layer is patterned, and the chip electrodes of the microLED chips in each of the light-emitting units are exposed from the top surface of the patterned first planar layer; A first metal layer is formed on the first planarization layer, and the first metal layer is patterned to obtain a first metal interconnect layer and the plurality of first fan-out electrode units. The first metal interconnect layer is electrically connected to the chip electrodes of the microLED chip in the plurality of first fan-out electrode units and the plurality of light-emitting units. Each of the first fan-out electrode units corresponds to one of the light-emitting units, and each of the first fan-out electrode units includes a first number of first fan-out sub-electrodes, the first number being less than the number of chip electrodes of the microLED chip in the corresponding light-emitting unit.

[0012] As an optional technical solution, each light-emitting unit has a peripheral boundary, and a first number of the first fan-out sub-electrodes are arranged around the peripheral boundary.

[0013] As an optional technical solution, a unit driving chip is provided within the area enclosed by each of the first fan-out electrode units, including: A motherboard is provided, wherein multiple unit driver chips are provided on the motherboard; A first bonding layer is provided in the area enclosed by the first fan-out electrode unit corresponding to the first flat layer; The plurality of unit driving chips are transferred from the motherboard to the first bonding layer, so that the plurality of unit driving chips are respectively stacked and fixed on the corresponding plurality of light-emitting units.

[0014] As an optional technical solution, the vertical projection of each unit driver chip on the temporary carrier is located within the vertical projection of the corresponding area enclosed by the first fan-out electrode unit on the temporary carrier.

[0015] As an optional technical solution, the fabrication of the second redistribution layer includes: A second planarization layer is fabricated, which covers the first metal interconnect layer, the plurality of first fan-out electrode units, and the plurality of unit driver chips; The second planarization layer is patterned to form a plurality of first vias, and each of the first fan-out sub-electrodes is exposed from the corresponding first via; A second metal layer is formed on the second planarization layer, and the second metal layer is patterned to obtain a second metal interconnect layer and the plurality of second fan-out electrode units; The second metal layer includes a lower metal layer, the second metal interconnect layer includes a lower metal interconnect layer, the lower metal layer is patterned to form the lower metal interconnect layer, and the lower metal interconnect layer is filled in the plurality of first vias for electrically connecting the driving electrodes of the plurality of unit driving chips and the corresponding plurality of first fan-out sub-electrodes.

[0016] As an optional technical solution, the fabrication of the second redistribution layer further includes: An isolation layer is prepared, wherein the isolation layer covers the underlying metal interconnect layer; The isolation layer is patterned to form a plurality of second vias, and the connection electrodes of the lower metal interconnect layer are exposed from the corresponding second vias. The second metal layer includes an upper metal layer, which is formed on the isolation layer. The upper metal layer is patterned to obtain an upper metal interconnect layer and the plurality of second fan-out electrode units. The upper metal interconnect layer is filled in the plurality of second vias to allow the plurality of second fan-out electrode units to be electrically connected to the corresponding plurality of first fan-out electrode units through the upper metal interconnect layer.

[0017] As an optional technical solution, the upper metal interconnect layer and the second fan-out electrode unit are an integral structure, and the second fan-out electrode unit is a part of the upper metal interconnect layer.

[0018] This application also provides a micro-LED light source structure, characterized in that the micro-LED light source structure is prepared by the preparation method described above, wherein the micro-LED light source structure includes multiple light-emitting units and multiple unit driving chips, each of the unit driving chips is used to drive a corresponding light-emitting unit, and each of the unit driving chips is stacked on one side of a corresponding light-emitting unit.

[0019] As an optional technical solution, each of the light-emitting units, each of the first fan-out electrode units includes a first number of first fan-out sub-electrodes, and each of the light-emitting units includes a plurality of microLED chips, wherein the size of the first fan-out sub-electrodes is larger than the chip electrode size of the microLED chips; and the first number is less than the sum of the number of chip electrodes of the plurality of microLED chips in each light-emitting unit.

[0020] As an optional technical solution, each of the unit driver chips is located within the area enclosed by a corresponding first fan-out electrode unit.

[0021] As an optional technical solution, it also includes a plurality of second fan-out electrode units, each second fan-out electrode unit corresponding to one of the light-emitting units, wherein the vertical projection of each second fan-out electrode unit is located in the plane of the corresponding unit driving chip.

[0022] As an optional technical solution, it also includes a first metal interconnect layer, which is electrically connected to the chip electrode in each of the light-emitting units corresponding to the plurality of first fan-out electrode units.

[0023] As an optional technical solution, it further includes a second metal interconnect layer, which is stacked on the side of the plurality of unit driving chips away from the light-emitting unit. The second metal interconnect layer includes an electrically isolated lower metal interconnect layer and an upper metal interconnect layer. The lower metal interconnect layer is electrically connected to the plurality of first fan-out electrode units and the chip electrodes of the plurality of unit driving chips. The upper metal interconnect layer is electrically connected to the lower metal interconnect layer, so that the plurality of first fan-out electrode units, the driving electrodes of the plurality of unit driving chips, and the plurality of second fan-out electrode units are electrically connected.

[0024] In summary, this application provides a micro-LED light source structure and its fabrication method. A first redistribution layer, a unit driver chip, and a second redistribution layer are sequentially stacked on the non-light-emitting side of multiple micro-LED chips to form the micro-LED light source structure. Specifically, by first vertically stacking the unit driver chips of the micro-LED chips on one side of the light-emitting unit, and then performing a secondary redistribution process, the problem of low redistribution yield during micro-LED chip packaging due to the large difference in thickness between the micro-LED chip and the unit driver chip is effectively solved. Furthermore, since the unit driver chip and its wiring layer are located on the opposite side of the light-emitting surface, the light emission shading of the micro-LED chip can be significantly improved. In the vertically stacked structure, the unit driver chip is located within the area enclosed by the first fan-out electrode unit, reducing the package volume and achieving high-density, thin, and high-efficiency micro-LED light source packaging. Attached Figure Description

[0025] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating the fabrication method of a micro-LED light source structure in one embodiment of the present invention.

[0027] Figure 2 This is a cross-sectional schematic diagram of transferring a microLED chip to a temporary substrate in one embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of the unit driver chip and its driver electrode distribution in one embodiment of the present invention.

[0029] Figure 4 This is a cross-sectional schematic diagram of the preparation and etching of the first planarization layer in one embodiment of the present invention.

[0030] Figure 5 This is a schematic diagram of the fabrication of the first metal interconnect layer in one embodiment of the present invention.

[0031] Figure 6 This is a schematic diagram of the preparation of the first adhesive layer in one embodiment of the present invention.

[0032] Figure 7 This is a schematic diagram of a unit driving chip being disposed on a first adhesive layer in one embodiment of the present invention.

[0033] Figure 8 This is a cross-sectional schematic diagram of the fabrication of the second planarization layer and the lower metal interconnect layer in one embodiment of the present invention.

[0034] Figure 9 for Figure 8 A top view of the middle and lower metal interconnect layers.

[0035] Figure 10 This is a cross-sectional schematic diagram of the metal interconnect layer above the isolation layer in one embodiment of the present invention.

[0036] Figure 11 for Figure 10 A top view of the upper and middle metal interconnect layers.

[0037] Figure 12 This is a cross-sectional view of the temporary carrier plate being removed.

[0038] Figure 13 This is a schematic diagram of a micro-LED light source structure in one embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0041] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0042] This application provides a micro-LED light source structure and its fabrication method. The core inventive point lies in: vertically stacking micro-LED chips and unit driver chips, combined with a two-stage fan-out process involving a first and second rewiring layer, effectively solving problems such as driver chip obstruction of light emission, limited package size, and low RDL process yield due to thickness differences in traditional horizontal layouts, while achieving electrical interconnection. More importantly, after completing all packaging processes, this application removes the temporary carrier board using laser lift-off technology, forming a substrate-free, ultra-thin self-supporting package. The above technical solution not only achieves high-density integration of the micro-LED light source structure but also significantly improves the thinness and luminous efficiency of the package.

[0043] like Figure 1 As shown, firstly, multiple microLED chips are transferred from one side of the growth substrate to the receiving area of ​​the temporary carrier, and the multiple microLED chips are rearranged into multiple light-emitting units in the receiving area.

[0044] like Figure 1 and Figure 2 As shown, a temporary carrier plate 20 is first provided. The temporary carrier plate is made of sapphire, quartz, or glass, and has a thickness of 20-1000 μm. This temporary carrier plate serves as the supporting base for subsequent processes, and its transparency facilitates the implementation of subsequent laser ablation processes.

[0045] Based on this, multiple microLED chips 11 are transferred from one side of the growth substrate 10 to the receiving area of ​​the temporary carrier 20. The microLED chips 11 are flip-chip structures with two electrodes, positive and negative, with a thickness of 4-10 μm and chip size ranging from 10 μm * 10 μm to 100 μm * 100 μm. The advantage of using a flip-chip structure is that the electrodes are located on the same side of the chip, which facilitates the implementation of subsequent rewiring processes.

[0046] In this embodiment, multiple micro-LED chips 11 are transferred to a preset position on a temporary carrier board 20 using mass transfer technology. The multiple micro-LED chips 11 are rearranged into multiple light-emitting units 11a within the receiving area. For example, each light-emitting unit 11a includes at least three micro-LED chips 11 for generating red light, green light, and blue light respectively. Each light-emitting unit 11a can be driven independently, and each micro-LED chip 11 within each light-emitting unit 11a can also be driven individually. The micro-LED light source structure composed of multiple light-emitting units 11a can perform full-color display function.

[0047] In this embodiment, the light-emitting surface 11c of each microLED chip 11 faces the temporary carrier 20, and the chip electrode 11b of each microLED chip 11 is away from the temporary carrier 20 and exposed. Specifically, a transparent adhesive layer 21 is provided on the temporary carrier 20, and the light-emitting surfaces 11c of multiple microLED chips 11 are fixed to the temporary carrier 20 by the transparent adhesive layer 21. The transparent adhesive layer 21 is made of materials such as silicone, epoxy resin, benzocyclobutene, or polyimide, and has a thickness of 1-10 μm. By setting the light-emitting surface 11c to face the temporary carrier 20, subsequent wiring processes can be performed on the non-light-emitting side (i.e., the chip electrode side) of the microLED chip without affecting the light-emitting efficiency of the light-emitting surface 11c.

[0048] like Figure 1 As shown, step 2: Prepare a first redistribution layer, which covers the plurality of light-emitting units and fans out the chip electrodes of the microLED chips in each light-emitting unit to form a plurality of first fan-out electrode units.

[0049] like Figure 4 and Figure 5 As shown, the first redistribution layer covers multiple light-emitting units 11a. Through the redistribution process, the chip electrode 11b of the microLED chip 11 is fanned out from a smaller size to a larger first fan-out sub-electrode 3121, providing sufficient connection space for electrical interconnection after the subsequent vertical stacking of unit driver chips 111.

[0050] The fabrication of the first redistribution layer includes preparing a first planarization layer 31 on a temporary carrier 20, the first planarization layer 31 covering a plurality of light-emitting units 11a. The first planarization layer 31 is, for example, a non-conductive film layer formed from an inorganic insulating material (oxide or nitride) or an organic insulating material (silicone, epoxy resin, polyimide, etc.). Inorganic insulating materials, such as oxides or nitrides, can be formed by chemical vapor deposition or atomic layer deposition; organic insulating materials, such as silicone, epoxy resin, polyimide, etc., can be formed by spin coating. The first planarization layer 31 not only serves as insulation but also provides a smooth process surface.

[0051] Next, the first planarization layer 31 is patterned, and the chip electrode 11b of the microLED chip 11 in each light-emitting unit 11a is exposed from the top surface 311 of the patterned first planarization layer 31.

[0052] Then, a first metal layer (not shown) is prepared on the first planarization layer 31. The first metal layer is deposited by means of vapor deposition, sputtering, electroplating, or chemical plating. The metal material of the first metal layer is, for example, one or more metals selected from chromium, aluminum, titanium, gold, copper, and platinum. In other embodiments of this application, the first metal layer may also be composed of multiple layers of metal materials stacked together. Multiple metal stacks can optimize the conductivity, adhesion, and oxidation resistance of the first metal layer.

[0053] Combination Figure 4 and Figure 5 The first metal layer is patterned to obtain a first metal interconnect layer and multiple first fan-out electrode units 312, wherein the first metal interconnect layer includes bridging electrodes 3122 and 3123. In this embodiment, a light-emitting unit 11a includes three micro-LED chips 11, and the three micro-LED chips 11 include six chip electrodes 11b, namely three positive chip electrodes and three negative chip electrodes. According to the driving principle of the micro-LED chips, a common cathode or common anode fan-out method is adopted to fan out the six chip electrodes of the micro-LED chips 11. The fan-out is achieved through four bridging electrodes: three anode bridging electrodes 3122 and one common cathode bridging electrode 3123 (or three cathode bridging electrodes and one common anode bridging electrode). The four bridging electrodes are electrically connected to four first fan-out sub-electrodes 3121, and the fan-out size of the first fan-out sub-electrodes is larger than the size of the chip electrodes 11b of the micro-LED chips 11. Through the rewiring process, the size of the chip electrode 11b of the microLED chip 11 is fanned out and enlarged, which reduces the requirements for electrical connection accuracy in subsequent packaging processes and improves the packaging yield.

[0054] like Figure 5 As shown, four first fan-out sub-electrodes 3121 constitute a first fan-out electrode unit 312, and each first fan-out electrode unit 312 corresponds to a light-emitting unit 11a. In this embodiment, the number of first fan-out sub-electrodes 3121 is four, which is less than the number of chip electrodes 11b in a corresponding light-emitting unit 11a (6). That is, the fan-out process of the first redistribution layer makes the first number of first fan-out sub-electrodes 3121 in the first fan-out electrode unit 312 less than the sum of the number of chip electrodes 11b of the microLED chip 11 in the corresponding light-emitting unit 11a.

[0055] Continue to refer to Figure 5Each light-emitting unit 11a has an outer boundary according to the arrangement of the micro-LED chip 11, wherein a first number of first fan-out sub-electrodes 3121 are arranged around the outer boundary. This outer arrangement allows the first fan-out electrode units 312 to form a region, reserving a central region for the subsequent placement of the driver chip and avoiding the driver chip from blocking the light-emitting space of the micro-LED chip 11.

[0056] Step S3: Set the unit driver chip to the area enclosed by the first fan-out electrode unit 312.

[0057] After the first redistribution layer is completed, each first fan-out electrode unit 312 has formed a central region with a certain area. A unit driver chip 110 is set in the central region, so that the unit driver chip 110 and the light-emitting unit 11a composed of the micro LED chip 11 are vertically stacked.

[0058] like Figure 3 , Figure 6 and Figure 7 As shown, a motherboard 100, such as a silicon wafer, is provided, on which multiple unit driver chips 110 are provided. Figure 3 As shown, the unit driver chip 110 is a silicon-based driver chip with a thickness of 5-100 μm and dimensions ranging from 40 μm * 40 μm to 300 μm * 300 μm. The unit driver chip 110 has seven driving electrodes 111, each with dimensions ranging from 5 μm * 5 μm to 50 μm * 50 μm, and the distance between any two electrodes is greater than or equal to 5 μm. Compared to LTPS or IGZO, silicon-based driver chips have higher carrier mobility, enabling them to support larger driving currents and improving the luminous efficiency of micro-LEDs.

[0059] Figure 3 The functions of the seven driving electrodes 111 shown are as follows: SDI, Serial Data Input, is used to receive digital signal data that controls the brightness and color of the display. CLK, the clock signal, is used to synchronize data transmission and coordinate the timing of the SDI input signal. VDD, positive power input, is the positive terminal that supplies power to the internal logic circuits of the driver chip; VSS, negative power input (or ground), is the negative / ground terminal that supplies power to the driver chip; R-, the negative drive terminal of the red micro-LED, is used to output a PWM drive signal to control the brightness of the red LED; G-, the negative drive terminal of the green micro LED, is used to output a PWM drive signal to control the brightness of the green LED; B-, the negative drive terminal of the blue micro-LED, is used to output a PWM drive signal to control the brightness of the blue LED.

[0060] like Figure 6 As shown, a first bonding layer 40 is disposed in the area enclosed by the first fan-out electrode unit 312 corresponding to the first planarization layer 31. The first bonding layer 40 is made of silicone, epoxy resin, benzocyclobutene, or polyimide, and has a thickness of 1-10 μm. The first bonding layer 40 allows the driving chip to be firmly fixed to one side of the light-emitting unit 11a. The first bonding layer 40 also electrically isolates the unit driving chip from the first metal interconnect layer on the light-emitting unit 11a.

[0061] Multiple unit driving chips 110 are transferred from the motherboard 100 to the first bonding layer 40, so that the multiple unit driving chips 110 are respectively stacked and fixed on one side of the corresponding multiple light-emitting units 11a.

[0062] In this embodiment, the size of the unit driver chip 110 is smaller than the area enclosed by the first fan-out electrode unit 312, ensuring that the unit driver chip 110 can be accommodated within the area enclosed by the first fan-out sub-electrode 3121. That is, the vertical projection of each unit driver chip 110 on the temporary carrier 20 is located within the vertical projection of the corresponding area enclosed by the first fan-out electrode unit 312 on the temporary carrier 20. This arrangement allows the unit driver chip 110 to be located directly above the side of the light-emitting unit 11a away from the light-emitting surface, which reduces the horizontal area occupied and avoids the driver chip blocking the light-emitting space of the micro-LED, effectively improving the packaging density and luminous efficiency.

[0063] like Figure 1 As shown, step S4: Prepare a second redistribution layer, and electrically interconnect the driving electrode 111 of the unit driving chip 110 with the first fan-out electrode unit 312 through the second redistribution layer, and at the same time form a plurality of second fan-out electrode units 81, which are electrically connected to the corresponding plurality of first fan-out electrode units 312.

[0064] After setting up the unit driver chip, an electrical connection needs to be established between the unit driver chip 110 and the first fan-out electrode unit 312, forming an external interface such as the second fan-out electrode unit 81. To this end, a second redistribution layer needs to be fabricated to cover the first redistribution layer and the unit driver chip 110, achieving electrical interconnection and forming an external electrode fan-out onto the top of the micro-LED light source structure package.

[0065] like Figure 8As shown, a second planarization layer 50 is fabricated, covering the first metal interconnect layer, multiple first fan-out electrode units 312, and multiple unit driver chips 110. The second planarization layer 50 is made of materials such as silicone, epoxy resin, benzocyclobutene, or polyimide, with a thickness of 10-150 μm, and is formed by spin coating or molding processes. The second planarization layer 50 encapsulates the unit driver chips 110, serving both insulating protection and planarization functions.

[0066] The second planarization layer 50 is further patterned to form a first via 51, and each first fan-out sub-electrode 3121 is exposed from the corresponding first via 51. The patterning process is, for example, by photolithography, etching or laser ablation.

[0067] A second metal layer is formed on the top surface of the patterned second flat layer 50, and the second metal layer is patterned to obtain a second metal interconnect layer and a plurality of second fan-out electrode units 80.

[0068] Continue to refer to Figure 8 and Figure 9 The second metal layer includes a lower metal layer (not shown), and the second metal interconnect layer includes a lower metal interconnect layer 60, wherein the lower metal layer is patterned to form the lower metal interconnect layer 60. The lower metal interconnect layer 60 fills a plurality of first vias 51 for electrically connecting the driving electrodes 111 of the plurality of unit driving chips 110 and the corresponding plurality of first fan-out sub-electrodes 3121, so that the control signals of the driving chips 110 can be transmitted to the first fan-out sub-electrodes 3121 through the lower metal interconnect layer 60.

[0069] In this embodiment, the process of filling the lower metal layer to the first through hole 51 includes, for example, electroplating or electroless plating. The metal may be one or more of copper, gold, nickel, and titanium.

[0070] like Figure 10 and Figure 11 As shown, an isolation layer 70 is prepared, which covers the underlying metal interconnect layer 60. The material of the isolation layer 70 is selected from organic insulating materials such as polyimide and benzocyclobutene, or inorganic insulating materials such as oxides and nitrides. The isolation layer 70 is patterned by photolithography and etching processes to form a plurality of second vias 71.

[0071] In the via 71 of the isolation layer 70, the connection electrode 61 (or pad) of the lower metal interconnect layer 60 is exposed through the corresponding second via 71. The isolation layer 70 is provided to provide electrical isolation between the upper metal interconnect layer and the lower metal layer to avoid short circuits, while the second via 71 provides an electrical interconnection channel for the subsequent upper metal interconnect layer 80 and the second fan-out electrode unit 81.

[0072] The process of further forming an upper metal interconnect layer 80 and second fan-out electrode units 81 on the patterned isolation layer 70 includes: forming an upper metal layer of a second metal layer on the isolation layer 70, patterning the upper metal layer, and obtaining the upper metal interconnect layer 80 and a plurality of second fan-out electrode units 81. The upper metal interconnect layer 80 fills a plurality of second vias 71 for electrically connecting the plurality of second fan-out electrode units 81 to the corresponding plurality of first fan-out electrode units 312 through the upper metal interconnect layer 80. The fabrication process of the upper metal interconnect layer is, for example, one or more of vapor deposition, sputtering, electroplating, or electroless plating; its metal material is, for example, one or more metals selected from chromium, aluminum, titanium, gold, copper, and platinum. In some embodiments of this application, a composite multilayer metal is formed by vapor deposition of multiple metal materials as the upper metal layer.

[0073] In this embodiment, the signal of the upper metal interconnect layer 80 is fanned out to the top of the micro-LED light source structure package through the second fan-out electrode unit 81, thereby facilitating the subsequent electrical connection between the micro-LED light source structure and the external circuit.

[0074] In this embodiment, the upper metal interconnect layer 80 and the second fan-out electrode unit 81 are integrally structured, with the second fan-out electrode unit 81 being a part of the upper metal interconnect layer 80. The multiple second fan-out sub-electrodes 811 in the second fan-out electrode unit 81 are electrically connected to the first fan-out sub-electrode 3121 via the metal conductive pillars of the upper metal interconnect layer 80 and the lower metal interconnect layer 60, thereby achieving electrical interconnection with the corresponding micro-LED chip 11 and the driving electrode 111 of the unit driving chip 110.

[0075] like Figure 11 As shown, the vertical projection of the second fan-out electrode unit 81 is located in the plane of the corresponding unit driver chip 110.

[0076] Step S5: Remove the temporary carrier board.

[0077] After completing the packaging process of steps 1-4, the temporary carrier board 20 has fulfilled its supporting function and no longer needs to be retained.

[0078] like Figure 12 As shown, the temporary carrier board 20 is removed by a semi-cutting process or laser lift-off technology. The preferred solution is to semi-cut the transparent substrate and then use a laser to lift off the transparent substrate, thereby reducing the thickness of the device and effectively avoiding the disadvantage of the device being very thick due to vertical stacking, thus achieving the ultimate thinness of the package.

[0079] After the above steps, the light-emitting surface of the microLED chip 11 is exposed, forming the final substrate-free microLED light source structure.

[0080] like Figure 13As shown, the micro-LED light source structure, from bottom to top, includes: a light-emitting unit 11a layer, a first redistribution layer, a unit driver chip layer, and a second redistribution layer; wherein, the light-emitting unit 11a layer is composed of multiple light-emitting units 11a, and each light-emitting unit 11a includes multiple micro-LED chips 11. In one embodiment of this application, each light-emitting unit 11a includes at least three micro-LED chips for generating red light, green light, and blue light respectively. The light-emitting surface of each micro-LED chip 11 faces the bottom layer (i.e., the direction where the original temporary carrier board was located, which has been removed), and the chip electrode 11b is exposed upwards.

[0081] The first redistribution layer is located above the light-emitting unit 11a layer and covers multiple light-emitting units 11a. The first redistribution layer includes a first planarization layer 31, a first metal interconnect layer, and multiple first fan-out electrode units 312. The first planarization layer 31 fills the spaces between the micro-LED chips 11, providing a flat process surface. The first metal interconnect layer is formed through a patterned first metal layer and electrically connects the chip electrodes 11b of the micro-LED chips 11 in the multiple light-emitting units 11a. Each first fan-out electrode unit 312 corresponds to one light-emitting unit 11a and includes a first number of first fan-out sub-electrodes 3121. The first fan-out sub-electrodes 3121 are arranged around the outer boundary of the light-emitting unit 11a, forming a region. The size of the first fan-out sub-electrodes 3121 is larger than the chip electrode size of the micro-LED chip 11, and the first number is less than the sum of the number of chip electrodes of the micro-LED chips 11 in each light-emitting unit 11a.

[0082] In one embodiment of this application, each first fan-out electrode unit 312 further includes a bridging electrode 3122 and a common cathode or common anode bridging electrode 3123; the bridging electrode 3122 is electrically connected to the first fan-out sub-electrode 3121 and the chip electrode 11b of the micro LED chip 11; the common cathode or common anode bridging electrode 3123 is used to realize the common cathode or common anode connection between multiple micro LED chips 11.

[0083] The unit driver chip layer is located above the first redistribution layer and includes multiple unit driver chips 110. Each unit driver chip 110 is disposed within the area enclosed by a corresponding first fan-out electrode unit 312, and the vertical projection of each unit driver chip 110 on the temporary carrier 20 lies within the vertical projection of the area enclosed by the corresponding first fan-out electrode unit 312 on the temporary carrier 20. The unit driver chip 110 is fixed to the first planarization layer 31 by a first bonding layer 40, forming a vertical stacking relationship with the light-emitting unit 11a below. Each unit driver chip 110 is used to drive a corresponding light-emitting unit 11a.

[0084] The second redistribution layer is located above the cell driver chip layer. The second redistribution layer includes a second planarization layer 50, a second metal interconnect layer, an isolation layer 70, a plurality of second fan-out electrode units 81, and a plurality of second fan-out sub-electrodes 811. The second planarization layer 50 covers the first metal interconnect layer, the plurality of first fan-out electrode units 312, and the plurality of cell driver chips 110, and encapsulates the cell driver chips 110 to provide insulation protection and planarization.

[0085] The second metal interconnect layer includes an electrically isolated lower metal interconnect layer 60 and an upper metal interconnect layer 80. The lower metal interconnect layer 60 fills a plurality of first vias 51 in the second planarization layer 50, and the first vias 51 expose the corresponding first fan-out sub-electrode 3121. The bottom of the lower metal interconnect layer 60 contacts the first fan-out sub-electrode 3121, and the top contacts the driving electrode 111 of the unit driving chip 110, thereby realizing electrical conduction between the first fan-out sub-electrode 3121 and the driving electrode 111 of the unit driving chip 110.

[0086] An isolation layer 70 covers the lower metal interconnect layer 60 and has multiple second vias 71 thereon, through which the connection electrodes 61 of the lower metal interconnect layer 60 are exposed. An upper metal interconnect layer 80 is located on the isolation layer 70, filling the multiple second vias 71, and is electrically connected to the connection electrodes 61 of the lower metal interconnect layer 60. The upper metal interconnect layer 80 connects multiple second fan-out sub-electrodes 811 to the corresponding lower metal interconnect layer 60 via metal conductive pillars (i.e., the portions filled in the second vias 71), thereby achieving electrical interconnection with the corresponding first fan-out sub-electrodes 3121 and the driving electrodes 111 of the unit driver chip 110. In one embodiment of this application, the upper metal interconnect layer 80 and the second fan-out electrode unit 81 are an integral structure, the second fan-out electrode unit 81 is a part of the upper metal interconnect layer 80, and the second fan-out sub-electrodes 811 are located on top of the second fan-out electrode unit 81.

[0087] Each second fan-out sub-electrode 811 corresponds to one light-emitting unit 11a, and the vertical projection of each second fan-out sub-electrode 811 lies in the plane of the corresponding unit driving chip 110. This layout facilitates surface mount connection with external circuit boards and improves the assemblability of the package.

[0088] In this configuration, the chip electrode 11b of the microLED chip 11 is electrically connected to the second fan-out sub-electrode 811 via the first fan-out sub-electrode 3121, the lower metal interconnect layer 60, the upper metal interconnect layer 80, and a metal via (within the second through-hole 71). Simultaneously, the driving electrode 111 of the unit driver chip 110 is electrically connected to the first fan-out sub-electrode 3121 via the lower metal interconnect layer 60. Thus, the driving signal originates from the unit driver chip 110, is transmitted through the lower metal interconnect layer 60 to the first fan-out sub-electrode 3121, and then via the first fan-out sub-electrode 3121 and the bridging electrode 3122 to the chip electrode 11b of the microLED chip 11, enabling the driver chip to control the microLED chip. Simultaneously, external signals can be transmitted to the unit driver chip 110 through the second fan-out sub-electrode 811, the upper metal interconnect layer 80, and the lower metal interconnect layer 60, forming a complete signal path.

[0089] like Figure 13 As shown, the micro-LED light source structure does not include the temporary carrier 20. It consists of a first planarization layer 31, a second planarization layer 50, an isolation layer 70, a first metal interconnect layer, a lower metal interconnect layer 60, and an upper metal interconnect layer 80, forming a self-supporting package that achieves thinning in the thickness direction.

[0090] In summary, this application provides a micro-LED light source structure and its fabrication method. A first redistribution layer, a unit driver chip, and a second redistribution layer are sequentially stacked on the non-light-emitting side of multiple micro-LED chips to form the micro-LED light source structure. Specifically, by first vertically stacking the unit driver chips of the micro-LED chips on one side of the light-emitting unit 11a, and then performing a secondary redistribution process, the problem of low redistribution yield during micro-LED chip packaging due to the large difference in thickness between the micro-LED chips and the unit driver chips is effectively solved. Furthermore, since the unit driver chips and their wiring layers are located on the opposite side of the light-emitting surface, the light emission obstruction of the micro-LED chips can be significantly improved. In the vertically stacked structure, the unit driver chips are located within the area enclosed by the first fan-out electrode unit, reducing the package volume and achieving high-density, thin, and high-efficiency micro-LED light source packaging.

[0091] The present invention has been described by the above-described embodiments; however, these embodiments are merely examples for implementing the present invention. Furthermore, the technical features involved in the different embodiments of the present invention described above can be combined with each other as long as they do not conflict with each other. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, any modifications and refinements made without departing from the spirit and scope of the present invention are within the scope of patent protection of the present invention.

Claims

1. A method for fabricating a micro-LED light source structure, characterized in that, The preparation method includes: A temporary carrier is provided, and multiple microLED chips are transferred from one side of the growth substrate to the receiving area of ​​the temporary carrier. The multiple microLED chips are rearranged into multiple light-emitting units in the receiving area. A first redistribution layer is prepared, which covers the plurality of light-emitting units and fans out the chip electrodes of the microLED chips in each of the light-emitting units to form a plurality of first fan-out electrode units; Within the area enclosed by each of the first fan-out electrode units, a unit driving chip is provided; A second redistribution layer is fabricated, covering the first redistribution layer and the cell driver chip, and electrically interconnecting the driving electrodes of the cell driver chip with the first fan-out electrode units. Simultaneously, a plurality of second fan-out electrode units are formed, and the plurality of second fan-out electrode units are electrically connected to corresponding plurality of first fan-out electrode units; and Remove the temporary carrier plate to form the micro-LED light source structure.

2. The preparation method according to claim 1, characterized in that, Each of the light-emitting units includes at least three microLED chips for generating red, green, and blue light, respectively.

3. The preparation method according to claim 1, characterized in that, The light-emitting surface of each microLED chip faces the temporary carrier, and the chip electrode of each microLED chip is away from the temporary carrier and exposed.

4. The preparation method according to claim 3, characterized in that, The process of transferring multiple microLED chips from one side of the growth substrate to the receiving area of ​​the temporary carrier includes: A transparent adhesive layer is provided on the temporary carrier, and the light-emitting surfaces of the plurality of microLED chips are fixed to the temporary carrier through the transparent adhesive layer.

5. The preparation method according to claim 1, characterized in that, The steps for fabricating the first redistribution layer include: A first planarization layer is prepared on the temporary carrier plate, the first planarization layer covering the plurality of light-emitting units; The first planar layer is patterned, and the chip electrodes of the microLED chips in each of the light-emitting units are exposed from the top surface of the patterned first planar layer; A first metal layer is formed on the first planarization layer, and the first metal layer is patterned to obtain a first metal interconnect layer and the plurality of first fan-out electrode units. The first metal interconnect layer is electrically connected to the chip electrodes of the microLED chip in the plurality of first fan-out electrode units and the plurality of light-emitting units. Each of the first fan-out electrode units corresponds to one of the light-emitting units, and each of the first fan-out electrode units includes a first number of first fan-out sub-electrodes, the first number being less than the number of chip electrodes of the microLED chip in the corresponding light-emitting unit.

6. The preparation method according to claim 5, characterized in that, Each light-emitting unit has a peripheral boundary, and the first number of first fan-out sub-electrodes are arranged around the peripheral boundary.

7. The preparation method according to claim 6, characterized in that, The unit driving chip is disposed within the area enclosed by each of the first fan-out electrode units, including: A motherboard is provided, wherein multiple unit driver chips are provided on the motherboard; A first bonding layer is provided in the area enclosed by the first fan-out electrode unit corresponding to the first flat layer; The plurality of unit driving chips are transferred from the motherboard to the first bonding layer, so that the plurality of unit driving chips are respectively stacked and fixed on the corresponding plurality of light-emitting units.

8. The preparation method according to claim 6, characterized in that, The vertical projection of each of the unit driver chips on the temporary carrier is located within the vertical projection of the corresponding area enclosed by the first fan-out electrode unit on the temporary carrier.

9. The preparation method according to claim 7, characterized in that, Fabricating the second redistribution layer includes: A second planarization layer is fabricated, which covers the first metal interconnect layer, the plurality of first fan-out electrode units, and the plurality of unit driver chips; The second planarization layer is patterned to form a plurality of first vias, and each of the first fan-out sub-electrodes is exposed from the corresponding first via; A second metal layer is formed on the second planarization layer, and the second metal layer is patterned to obtain a second metal interconnect layer and the plurality of second fan-out electrode units; The second metal layer includes a lower metal layer, the second metal interconnect layer includes a lower metal interconnect layer, the lower metal layer is patterned to form the lower metal interconnect layer, and the lower metal interconnect layer is filled in the plurality of first vias for electrically connecting the driving electrodes of the plurality of unit driving chips and the corresponding plurality of first fan-out sub-electrodes.

10. The preparation method according to claim 9, characterized in that, Fabricating the second rewiring layer also includes: An isolation layer is prepared, the isolation layer covering the underlying metal interconnect layer; The isolation layer is patterned to form a plurality of second vias, and the connection electrodes of the lower metal interconnect layer are exposed from the corresponding second vias. The second metal layer includes an upper metal layer, which is formed on the isolation layer. The upper metal layer is patterned to obtain an upper metal interconnect layer and the plurality of second fan-out electrode units. The upper metal interconnect layer is filled in the plurality of second vias to allow the plurality of second fan-out electrode units to be electrically connected to the corresponding plurality of first fan-out electrode units through the upper metal interconnect layer.

11. The preparation method according to claim 10, characterized in that, The upper metal interconnect layer and the second fan-out electrode unit are an integral structure, and the second fan-out electrode unit is a part of the upper metal interconnect layer.

12. A micro-LED light source structure, characterized in that, The micro-LED light source structure is prepared by the preparation method according to any one of claims 1 to 11, wherein the micro-LED light source structure includes a plurality of light-emitting units and a plurality of unit driving chips, each of the unit driving chips is used to drive a corresponding light-emitting unit, wherein each of the unit driving chips is stacked on one side of a corresponding light-emitting unit.

13. The micro-LED light source structure according to claim 12, characterized in that, The micro-LED light source structure includes a plurality of first fan-out electrode units, each first fan-out electrode unit corresponding to one light-emitting unit, each first fan-out electrode unit including a first number of first fan-out sub-electrodes, and each light-emitting unit including a plurality of micro-LED chips, wherein the size of the first fan-out sub-electrodes is larger than the chip electrode size of the micro-LED chips; and the first number is less than the sum of the chip electrodes of the plurality of micro-LED chips in each light-emitting unit.

14. The micro-LED light source structure according to claim 13, characterized in that, Each of the aforementioned unit driver chips is located within the area enclosed by a corresponding first fan-out electrode unit.

15. The micro-LED light source structure according to claim 13, characterized in that, It also includes a plurality of second fan-out electrode units, each second fan-out electrode unit corresponding to one of the light-emitting units, wherein the vertical projection of each second fan-out electrode unit is located in the plane of the corresponding unit driving chip.

16. The micro-LED light source structure according to claim 15, characterized in that, It also includes a first metal interconnect layer, which is electrically connected to the chip electrode in each of the light-emitting units corresponding to the plurality of first fan-out electrode units.

17. The micro-LED light source structure according to claim 16, characterized in that, It also includes a second metal interconnect layer, which is stacked on the side of the plurality of unit driving chips away from the light-emitting unit. The second metal interconnect layer includes an electrically isolated lower metal interconnect layer and an upper metal interconnect layer. The lower metal interconnect layer is electrically connected to the plurality of first fan-out electrode units and the chip electrodes of the plurality of unit driving chips. The upper metal interconnect layer is electrically connected to the lower metal interconnect layer, so that the plurality of first fan-out electrode units, the driving electrodes of the plurality of unit driving chips and the plurality of second fan-out electrode units are electrically connected.

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