Semiconductor element arrangement structure

Abstract

A semiconductor device arrangement includes a carrier plate, an adhesive portion, and a semiconductor device. The adhesive portion is disposed on the carrier plate. The semiconductor device is disposed on the adhesive portion and includes a semiconductor stack, a protective layer, a first conductive layer, and a second conductive layer. The protective layer is disposed on the semiconductor stack and has a first portion and a second portion. The first conductive layer is disposed on the semiconductor stack. The second conductive layer is disposed on the first conductive layer. The first portion contacts the adhesive portion. The second portion is spaced apart from the adhesive portion by a distance.

Description

Technical Field

[0001] This invention relates to semiconductor element arrangement structures, and particularly to semiconductor element arrangement structures that can improve mass transfer yield. Background Technology

[0002] Due to size limitations, semiconductor devices such as light-emitting diodes (LEDs) are difficult to mass transfer efficiently. Therefore, there are still some issues to be overcome regarding the arrangement of semiconductor devices. Summary of the Invention

[0003] An embodiment of the present invention provides a semiconductor element arrangement structure. The semiconductor element arrangement structure includes a carrier plate, an adhesive portion, and semiconductor elements. The adhesive portion is disposed on the carrier plate. The semiconductor element is disposed on the adhesive portion and includes a semiconductor stack, a protective layer, a first conductive layer, and a second conductive layer. The protective layer is disposed on the semiconductor stack and has a first portion and a second portion. The first conductive layer is disposed on the semiconductor stack. The second conductive layer is disposed on the first conductive layer. The first portion is in contact with the adhesive portion. The second portion is spaced apart from the adhesive portion by a distance. Attached Figure Description

[0004] The following detailed description, in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It is worth noting that, according to industry standard practice, some features may not be drawn to scale. For clarity of description, the dimensions of different features may be enlarged or reduced.

[0005] Figure 1 and Figure 2 This is a cross-sectional schematic diagram of a semiconductor element arrangement structure according to an embodiment of the present invention;

[0006] Figure 3 This is a top view schematic diagram of a semiconductor element arrangement structure according to an embodiment of the present invention;

[0007] Figures 4 to 7 This is a flowchart illustrating the manufacturing process of a semiconductor cell according to an embodiment of the present invention;

[0008] Figure 8 for Figure 7 A top view of the semiconductor unit;

[0009] Figure 9 This is a schematic diagram of an embodiment of the present invention showing a process for fabricating a semiconductor element arrangement structure by irradiation;

[0010] Figures 10 to 12 This is a manufacturing process diagram illustrating the separation of a semiconductor element from an adhesive layer according to an embodiment of the present invention;

[0011] Figure 13 and Figure 14 This is a top view and a cross-sectional view of a semiconductor cell according to another embodiment of the present invention;

[0012] Figure 15 This is a top view schematic diagram of a semiconductor cell according to another embodiment of the present invention;

[0013] Figure 16 and Figure 17 This is a top view and a cross-sectional view of a semiconductor cell according to another embodiment of the present invention;

[0014] Figure 18 and Figure 19 This is a top view and a cross-sectional view of a semiconductor cell according to another embodiment of the present invention;

[0015] Figures 20 to 27 This is a top view schematic diagram of a semiconductor cell according to different embodiments of the present invention;

[0016] Figure 28 and Figure 29 This is a top view and a cross-sectional view of a semiconductor cell according to another embodiment of the present invention.

[0017] Figures 30 to 32 This is a top view and a cross-sectional view of a semiconductor cell according to another embodiment of the present invention;

[0018] Figure 33 This is a top view schematic diagram of a semiconductor cell according to another embodiment of the present invention.

[0019] Symbol explanation:

[0020] 1A, 1A': Semiconductor element arrangement

[0021] 2A, 2A', 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, 2O, 2P: Semiconductor unit

[0022] 10:Substrate

[0023] 20: Semiconductor stack

[0024] 20a: First semiconductor layer

[0025] 20b: Emissive layer

[0026] 20c: Second semiconductor layer

[0027] 20B: Top surface

[0028] 20S: Side surface

[0029] 20T, 40T, 50T: Top surface

[0030] 22: Protective layer

[0031] 22P1: Part 1

[0032] 22P2: Part Two

[0033] 32: First conductive layer

[0034] 32T, 34T, 34T': Surface

[0035] 34: Second conductive layer

[0036] 34a, 34b1, 34b2, 34b3, 34c1, 34c2, 34c3, 34d, 34e: Open

[0037] 36: Semiconductor components

[0038] 40: Carrier board

[0039] 42: Adhesive layer

[0040] 50: Adhesive part

[0041] 51: Connecting part

[0042] 52: Part Three

[0043] 54: Part Four

[0044] 60: Pickup Item

[0045] a1, a2: included angle

[0046] d1, s1, s2, s3, s4, s5, s6, s7, s8, s9, s9', s10, s10': Distance

[0047] D1: First Direction

[0048] D2: Second Direction

[0049] D20: First axis line

[0050] D3: Third direction

[0051] D40: Normal

[0052] H-H', I-I', II-II', III-III', IV-IV', V-V', VI-VI', VII-VII': line segments

[0053] P1: Curing process

[0054] P2: Irradiation process

[0055] P3: Pressure Manufacturing Process

[0056] t1, t1': First thickness

[0057] t2: Second thickness

[0058] w1: First width

[0059] w2: Second width Detailed Implementation

[0060] The following provides a detailed description of various embodiments of the present invention. The specific elements and arrangements described below are merely for illustrative purposes to clearly illustrate some embodiments of the invention. These are illustrative only and not intended to limit the scope of the invention. Similar and / or corresponding element symbols may be used in different embodiments to clearly describe the invention.

[0061] In this document, the terms "approximately," "about," and "substantially" generally indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantities are approximate; that is, without specific mention of "approximately," "about," or "substantially," their meaning is implied. The phrase "the range is between the first value and the second value" or "the first value ~ the second value" indicates that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error between the first and second values ​​that may be within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%. If the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 and 100 degrees. If the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 and 10 degrees.

[0062] In this invention, the directions are not limited to the three axes of a Cartesian coordinate system (X-axis, Y-axis, and Z-axis) and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis are perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness or height direction). In one embodiment, the cross-sectional view described herein is a cross-sectional view of the XZ plane, and the top view described herein is a view of the XY plane. In one embodiment, the third direction D3 is the normal direction of the carrier plate 40. In one embodiment, each layer in the semiconductor stack 20 is sequentially formed on the substrate 10 along the third direction D3 (e.g., ...). Figure 4 (As shown).

[0063] Reference Figure 1 The semiconductor element arrangement structure 1A includes a carrier plate 40, an adhesive portion 50, and semiconductor elements 36. In one embodiment, the carrier plate 40 comprises glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), or polypropylene (PP). In one embodiment, the carrier plate 40 comprises a wafer or chip.

[0064] The adhesive portion 50 is disposed on the carrier plate 40 and includes a body. In one embodiment, multiple bodies of the adhesive portion 50 are spaced apart from each other in the first direction D1 and / or the second direction D2. In another embodiment, the adhesive portion 50 is continuously disposed on the carrier plate 40 (see reference). Figure 2 In one embodiment, the adhesive portion 50 comprises an adhesive, which includes epoxy resin, polyethylene terephthalate (PET), or polyimide (PI).

[0065] like Figure 1 As shown, a semiconductor element 36 is disposed on an adhesive portion 50. One semiconductor element 36 is disposed on one main body of the adhesive portion 50. The semiconductor element 36 includes a main body, a protective layer 22, a first conductive layer 32, and a second conductive layer 34. The main body includes a semiconductor stack 20, which includes a first semiconductor layer 20a, a light-emitting layer 20b, and a second semiconductor layer 20c, with the light-emitting layer 20b disposed between the first semiconductor layer 20a and the second semiconductor layer 20c. In one embodiment, the first semiconductor layer 20a, the light-emitting layer 20b, and the second semiconductor layer 20c can be sequentially formed along the direction of the first axis D20 using an epitaxial growth process (see subsequent descriptions). Figure 4 In some embodiments, semiconductor element 36 includes three categories: horizontal chip, flip chip, and vertical chip.

[0066] In one embodiment, the first semiconductor layer 20a is a P-type semiconductor layer, and the second semiconductor layer 20c is an N-type semiconductor layer. In another embodiment, the first semiconductor layer 20a is a P-type semiconductor layer, and the second semiconductor layer 20c is an N-type semiconductor layer. The P-type semiconductor layer includes a Group II-VI material or a Group III-V material. Group II-VI materials include zinc selenide (ZnSe), and Group III-V materials include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN). In one embodiment, the P-type semiconductor layer includes a dopant, and the dopant contains magnesium (Mg) or carbon (C). In one embodiment, the light-emitting layer 20b includes an intrinsic semiconductor material, which includes indium gallium nitride (InGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN). In one embodiment, the light-emitting layer 20b comprises a multiple quantum well (MQW). In one embodiment, the N-type semiconductor layer comprises a group II-VI material or a group III-V material. In one embodiment, the N-type semiconductor layer comprises a dopant, and the dopant is such as silicon (Si) or germanium (Ge).

[0067] like Figure 1 As shown, a protective layer 22 is disposed on the semiconductor stack 20. In one embodiment, the protective layer 22 covers a portion of the top surface 20T of the semiconductor stack 20 and exposes another portion of the top surface 20T. The protective layer 22 covers the side surfaces 20S of the semiconductor stack 20 and exposes the top surface 20B of the semiconductor stack 20. In one embodiment, the protective layer 22 comprises an electrically insulating material.

[0068] like Figure 1 As shown, a first conductive layer 32 is disposed on the semiconductor stack 20, and a protective layer 22 exposes the first conductive layer 32. In one embodiment, the first conductive layer 32 is in contact with the protective layer 22. In another embodiment, a second conductive layer 34 is disposed on the first conductive layer 32 and is electrically connected to the first conductive layer 32.

[0069] The first conductive layer 32 and the second conductive layer 34 comprise conductive materials. Conductive materials include metals, oxides, or semiconductor materials. Metals include tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), alloys thereof, or combinations thereof. Oxides include transparent conductive oxides (TCOs), such as indium tin oxide (ITO). Semiconductor materials comprise gallium arsenide (GaAs). In one embodiment, the first conductive layer 32 comprises gold (Au), and the second conductive layer 34 comprises tin (Sn). In one embodiment, the melting point of the second conductive layer 34 is lower than the melting point of the first conductive layer 32.

[0070] like Figure 1 As shown, the protective layer 22 has a first portion 22P1 and a second portion 22P2, each covering a portion of the top surface 20T. The first portion 22P1 is in contact with the adhesive portion 50, and the second portion 22P2 is at least spaced from the adhesive portion 50 by a distance d1. In one embodiment, the second conductive layer 34 is in contact with the adhesive portion 50. Figure 1 As shown, the main body of the adhesive portion 50 has a third portion 52 and a fourth portion 54. The first portion 22P1 of the protective layer 22 is in contact with the third portion 52 of the adhesive portion 50, and the second portion 22P2 of the protective layer 22 is spaced apart from the fourth portion 54 of the adhesive portion 50 by a distance d1.

[0071] like Figure 1 As shown, in one embodiment, the adhesive portion 50 has a top surface 50T located on the side away from the carrier plate 40. The protective layer 22 and the second conductive layer 34 contact the top surface 50T of the adhesive portion 50. The contact surface between the protective layer 22 and the top surface 50T has a contact area A1, the contact surface between the second conductive layer 34 and the top surface 50T has a contact area A2, and the top surface 50T has a total area A3. In one embodiment, the sum of contact areas A1 and A2 is less than 80% of the total area A3. In another embodiment, the sum of contact areas A1 and A2 is greater than 5% of the total area A3. For example, (contact area A1 + contact area A2) / total area A3 is 79.9%, 79%, 75%, 70%, 60%, 50%, 40%, 30%, or 20%. In one embodiment, the proportional relationship between contact areas A1, A2, and the total area A3 is consistent with that of a cross-sectional view (e.g., ...). Figure 1 The contact interface between the protective layer 22 and the top surface 50T, the contact interface between the second conductive layer 34 and the top surface 50T, and the proportional relationship of the top surface 50T are all observed to be the same.

[0072] like Figure 1 As shown, the second conductive layer 34 has a protruding surface 34T that protrudes toward the adhesive portion 50. In one embodiment, in a cross-sectional view, the protruding surface 34T has an arcuate profile, and the top surface 50T of the adhesive portion 50 faces the protruding surface 34T. In one embodiment, the surface roughness of the protruding surface 34T is less than the surface roughness of the top surface 50T.

[0073] like Figure 1 As shown, in one embodiment, the second conductive layer 34 has a first thickness t1. The first thickness t1 is between 1 μm and 3 μm, for example, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm. In one embodiment, the semiconductor stack 20 has a second thickness t2, and the first thickness t1 is less than or equal to the second thickness t2.

[0074] like Figure 1 As shown, the carrier plate 40 has a top surface 40T, and the adhesive portion 50 is disposed on the top surface 40T. In one embodiment, the normal D40 of the top surface 40T extends along a third direction D3. An angle α1 is formed between the normal D40 and the first axis D20. In one embodiment, the angle α1 is less than or equal to 45 degrees. In another embodiment, the angle α1 is greater than or equal to 5 degrees, for example, between 10 and 35 degrees. In yet another embodiment, the angle α1 is 45, 40, 35, 30, 25, or 20 degrees. In one embodiment, the top surface 20B of the semiconductor element 36 is perpendicular to the first axis D20, and the top surface 20B forms an angle with two virtual extensions of the top surface 40T, this angle being the same as the angle α1. In one embodiment, the tangent direction tangent to the top of the protruding surface 34T forms an angle α2 with the extending direction of the carrier plate 40 (first direction D1), and the angle α2 is less than or equal to 45 degrees. In one embodiment, when viewed along the normal direction D40 (or the third direction D3), the outermost surface of the adhesive portion 50 does not exceed the outermost surface of the semiconductor element 36. In other words, when viewed along the normal direction D40 (or the third direction D3), the projection area of ​​the adhesive portion 50 onto the carrier plate 40 is located within the projection area of ​​the semiconductor element 36 onto the carrier plate 40.

[0075] In one embodiment, the semiconductor element arrangement structure 1A includes a plurality of semiconductor units 2A', each semiconductor unit 2A' including a carrier plate 40, an adhesive portion 50, and a semiconductor element 36. In one embodiment, adjacent semiconductor units 2A' share a carrier plate 40. In another embodiment, adjacent semiconductor units 2A' share an adhesive portion 50 (see below). Figure 2 ).

[0076] like Figure 2As shown, in one embodiment, the adhesive portion 50 of the semiconductor arrangement structure 1A' further includes a connecting portion 51 connecting the two main bodies of the adhesive portion 50, and the adhesive portion 50 is continuously disposed on the carrier plate 40. In one embodiment, the connecting portion 51 is located between two adjacent semiconductor units 2A' or between two adjacent semiconductor elements 36. In one embodiment, on the third direction D3, the height of the connecting portion 51 is greater than 0 and lower than the height of the third portion 52 and the fourth portion 54.

[0077] Reference Figure 3 This is a top view schematic diagram of a semiconductor element arrangement structure 1A or 1A' according to an embodiment of the present invention. In one embodiment, Figure 1 and Figure 2 show Figure 3 A schematic diagram of the cross section of line segment H-H'. For ease of explanation, Figure 3 The semiconductor stack 20, the first conductive layer 32, and the carrier plate 40 are shown in the semiconductor element arrangement structure 1A or 1A', with at least the adhesive portion 50 omitted. The semiconductor element arrangement structure 1A or 1A' includes a plurality of semiconductor units 2A', which are spaced apart from each other. In one embodiment, the semiconductor element arrangement structure 1A or 1A' includes semiconductor elements 36 arranged spaced apart from each other. In one embodiment, the semiconductor element 36 is a flip chip, and the two first conductive layers 32 serve as opposite electrodes of the semiconductor element 36 and are located between the semiconductor stack 20 and the carrier plate 40.

[0078] This invention provides a method for forming a semiconductor cell 2A. For example... Figure 4 As shown, firstly, a substrate 10 is provided. In one embodiment, the material of the substrate 10 may refer to the material of the aforementioned carrier plate 40. Next, a semiconductor element 36 is formed on the substrate 10 along the third direction D3. For simplicity, Figure 4 Only one semiconductor element 36 is shown for fabricating a semiconductor cell. In one embodiment, multiple semiconductor elements 36 are formed on the substrate 10, for example, 10, 100, or 1,000 semiconductor elements 36, to fabricate a semiconductor element arrangement structure (multiple semiconductor cells). In one embodiment, the semiconductor element 36 is formed by forming a semiconductor stack 20 on the substrate 10 and forming a protective layer 22 on the top surface 20T of the semiconductor stack 20. Next, a first conductive layer 32 is formed on the semiconductor stack 20, and a second conductive layer 34 is formed on the surface 32T of the first conductive layer 32. In one embodiment, the substrate 10 is a patterned sapphire substrate (PSS).

[0079] Reference Figure 5A carrier plate 40 is provided, and an adhesive layer 42 is located on the carrier plate 40. Then, it is flipped up and down as follows: Figure 4 Following the structure shown, the semiconductor element 36 is bonded to the adhesive layer 42. In other words, the semiconductor element 36 is located between the substrate 10 and the carrier plate 40. In one embodiment, the adhesive layer 42 has fluidity (the adhesive layer 42 is not fully cured).

[0080] Reference Figure 6 A curing process P1 is performed on the bonded structure to cure the adhesive layer 42 to form the adhesive portion 50. In one embodiment, a portion of the protective layer 22 is exposed outside the adhesive portion 50. In another embodiment, the adhesive portion 50 covers the sidewalls of the protective layer 22 (not shown). In one embodiment, the substrate 10 extends horizontally beyond the protective layer 22 (not shown), and the adhesive portion 50 extends upward and contacts the sidewalls of the substrate 10 and the protective layer 22. In one embodiment, the curing process P1 includes a photocuring process, which includes irradiation with laser light, infrared light, or ultraviolet light.

[0081] Reference Figure 7 After performing the curing process P1, the substrate 10 is removed to obtain the semiconductor element unit 2A. In one embodiment, an etching process is further included to reduce the width of the adhesive portion 50, making the width of the adhesive portion 50 smaller than the width of the semiconductor stack 20. In one embodiment, after the curing process P1, an adhesive portion 50 is formed between two adjacent semiconductor stacks 20, and the etching process is used to thin the adhesive portion 50 to form such a... Figure 2 The connecting portion 51 shown, or the main body of the adhesive portion 50 between two adjacent semiconductor stacks 20 is formed by removing the adhesive portion 50 between them to create an adhesive portion 50 that is separated from each other. Figure 1 The contour of the surface 34T' of the second conductive layer 34 matches the contour of the top surface 50T of the adhesive portion 50. In one embodiment, the second conductive layer 34 covers the second portion 22P2 of the protective layer 22 and the first conductive layer 32. In one embodiment, the adhesion of the third portion 52 to the semiconductor element 36 is greater than the adhesion of the fourth portion 54 to the semiconductor element 36. In one embodiment, the third portion 52 of the adhesive portion 50 contacts the first portion 22P1 of the protective layer 22, and the fourth portion 54 of the adhesive portion 50 contacts the second conductive layer 34. In one embodiment, the second conductive layer 34 has a first thickness t1'.

[0082] like Figure 7As shown, in one embodiment, in the cross-sectional view, the second conductive layer 34 has an asymmetrical structure along the first axis D20. In one embodiment, when viewed along a third direction D3, the projection plane of the first conductive layer 32 does not completely overlap with the projection plane of the second conductive layer 34. In one embodiment, when viewed along a third direction D3, the projected area of ​​the first conductive layer 32 may be less than, equal to, or greater than the projected area of ​​the second conductive layer 34.

[0083] Figure 8 show Figure 7 A top view schematic diagram of semiconductor cell 2A. In one embodiment, Figure 7 for Figure 8 A cross-sectional view of line segment I-I'. For simplicity, Figure 8 Only the first conductive layer 32, the second conductive layer 34, the carrier plate 40, and the adhesive portion 50 of the semiconductor unit 2A are shown. Figure 8 As shown, in one embodiment, the right side of the adhesive portion 50 is exposed outside the second conductive layer 34, and the left side of the adhesive portion 50 overlaps with the second conductive layer 34. In one embodiment, the right edge of the second conductive layer 34 is spaced apart from the right edge of the adhesive portion 50 by a distance. In one embodiment, the second conductive layer 34 is divided into upper and lower regions, separated by an opening 34a.

[0084] like Figure 9 As shown, for Figure 7 The semiconductor cell 2A shown undergoes an irradiation fabrication process P2, causing deformation of the second conductive layer 34. Irradiation fabrication process P2 applies energy to the semiconductor cell 2A, shaping the second conductive layer 34, which has a lower melting point. After irradiation fabrication process P2, a first portion 22P1 of the protective layer 22 contacts the adhesive portion 50, and a second portion 22P2 of the protective layer 22 is spaced from the adhesive portion 50 by a distance d1. In one embodiment, irradiation fabrication process P2 includes irradiating the semiconductor cell 2A with a laser, and the laser includes infrared (IR) laser light. In one embodiment, the laser is irradiated in the opposite direction to a third direction D3 to form the semiconductor cell 2A'. In another embodiment, the laser is irradiated along a third direction D3 (not shown) to form the semiconductor cell 2A'. In one embodiment, a portion of the laser can pass through the carrier plate 40 and irradiate the second conductive layer 34. In another embodiment, irradiation fabrication process P2 includes applying energy to the semiconductor cell 2A using an oven. In one embodiment, the second conductive layer 34 has a greater affinity for the first conductive layer 32 than for the protective layer 22. After performing the irradiation fabrication process P2, the second conductive layer 34 tends to accumulate on the first conductive layer 32, exposing the protective layer 22. Therefore, after performing the irradiation fabrication process P2, the second conductive layer 34 forms a protruding surface 34T that protrudes toward the adhesion portion 50. That is, the irradiation fabrication process P2 makes the second conductive layer 34 have a relatively rough surface 34T' (e.g., Figure 7 As shown) transforms into a smoother, protruding surface 34T (as shown) Figure 9 As shown). Since the volume of the second conductive layer 34 is approximately constant, the first thickness t1' of the second conductive layer 34 before performing the irradiation fabrication process P2 (as shown). Figure 7 (As shown) is less than the first thickness t1 of the second conductive layer 34 after performing the irradiation fabrication process P2 (as shown) Figure 9 (As shown). In one embodiment, the energy provided by the irradiation fabrication process P2 does not affect (damage) the first conductive layer 32, the protective layer 22, and the semiconductor stack 20, which have higher melting points. In one embodiment, the irradiation fabrication process P2 also includes using a limiter (not shown) to limit the angle at which the semiconductor element 36 is tilted (e.g., ...). Figure 1 The included angle a1). In one embodiment, the limiter is located above the semiconductor element 36 (not shown), and the bottom surface of the limiter is parallel to the upper surface of the carrier plate 40 (e.g., perpendicular to the third direction D3).

[0085] like Figure 10 As shown, in one embodiment, a stamp 60 is used to perform a transfer fabrication process on the semiconductor element 36. Figure 11 As shown, a pressure fabrication process P3 is performed to connect the pickup 60 to the top surface 20B of the semiconductor stack 20. In one embodiment, after the pickup 60 is pressed down in the opposite direction to the third direction D3, the first portion 22P1 of the protective layer 22 separates from the third portion 52 of the adhesive portion 50. In one embodiment, the lower surface of the pickup 60 is parallel to the upper surface of the carrier plate 40, and the pressure fabrication process P3 adjusts the angle between the semiconductor element 36 and the carrier plate 40 (e.g., ...). Figure 1 The included angle α1 is reduced to near 0 degrees. In another embodiment, the bottom surface of the separated semiconductor element 36 has residue of the adhesive portion 50. Figure 12 As shown, the pickup 60 can transfer the semiconductor element 36.

[0086] Reference Figure 13 and Figure 14 This is a top view and a cross-sectional view of semiconductor unit 2B according to another embodiment of the present invention. In one embodiment, Figure 7 for Figure 13 A cross-sectional schematic diagram of line segment I-I'. Figure 14 for Figure 13 A cross-sectional schematic diagram of line segment II-II'. In one embodiment, a portion of the right edge of the second conductive layer 34 of the semiconductor unit 2B is spaced apart from the right edge of the adhesive portion 50 by a distance ( Figure 7 Furthermore, another portion of the right edge of the second conductive layer 34 is flush with the right edge of the adhesive portion 50. Figure 14In one embodiment, the second conductive layer 34 has a plurality of openings 34b1, 34b2, and 34b3, and the plurality of openings 34b1, 34b2, and 34b3 are not connected to each other. In one embodiment, openings 34b2 and 34b3 are located at the corners of semiconductor cell 2B. Figure 14 As shown, in one embodiment, the second conductive layer 34 is located between the adhesive portion 50 and the protective layer 22, and also between the adhesive portion 50 and the first conductive layer 32. In other words, in the semiconductor cell 2B, at least a portion of the second conductive layer 34 extends between the first portion 22P1 of the protective layer 22 and the adhesive portion 50. After performing the irradiation fabrication process P2 on the semiconductor cell 2B, a structure as shown can be formed. Figure 1 The semiconductor element arrangement structure 1A shown is illustrated.

[0087] Figure 15 This is a top view schematic diagram of a semiconductor cell 2C according to another embodiment of the present invention. In one embodiment, Figure 7 for Figure 15 A cross-sectional schematic diagram of line segment I-I'. Figure 14 for Figure 15 A cross-sectional diagram of line segment II-II'. (See diagram below.) Figure 15 As shown, the second conductive layer 34 of the semiconductor cell 2C is a continuous structure and has multiple openings 34c1, 34c2, and 34c3. The multiple openings 34c1, 34c2, and 34c3 are not connected to each other and do not separate the second conductive layer 34 into multiple blocks. In one embodiment, after performing an irradiation fabrication process P2 on the semiconductor cell 2C, a structure as shown can be formed. Figure 1 The semiconductor unit 2A' shown.

[0088] Reference Figure 16 and Figure 17 This is a top view and a cross-sectional view of a 2D semiconductor cell according to an embodiment of the present invention. In one embodiment, Figure 17 for Figure 16 A cross-sectional view of line segment III-III'. (See diagram below.) Figure 16 and Figure 17 As shown, in semiconductor cell 2D, the right edge of the second conductive layer 34 extends beyond the right edge of the first conductive layer 32 and is spaced apart from the right edge of the adhesive portion 50 by a distance s1. Figure 17 As shown, the third portion 52 of the adhesive portion 50 has a first width w1 corresponding to the distance s1. After performing the irradiation fabrication process P2 on the semiconductor cell 2D, a structure like this can be formed. Figure 1 The semiconductor unit 2A' shown.

[0089] Reference Figure 18 and Figure 19 This is a top view and a cross-sectional view of a semiconductor unit 2E according to an embodiment of the present invention. Figure 19 for Figure 18 A cross-sectional diagram of line segment IV-IV'. (See diagram below.) Figure 18 As shown, in one embodiment, the second conductive layer 34 has an opening 34e, which divides the second conductive layer 34 into upper and lower regions. In one embodiment, the right edge of the second conductive layer 34 is spaced apart from the right edge of the adhesive portion 50 by a distance s1, and the left edge of the second conductive layer 34 is spaced apart from the left edge of the adhesive portion 50 by a distance s2. Figure 19 As shown, in one embodiment, the third portion 52 of the adhesive portion 50 has a first width w1 corresponding to a distance s1, and the fourth portion 54 of the adhesive portion 50 has a second width w2 corresponding to a distance s2, and the first width w1 is greater than the second width w2. Since the contact area between the third portion 52 and the protective layer 22 is different from the contact area between the fourth portion 54 and the protective layer 22, the adhesion force of the third portion 52 to the protective layer 22 is greater than the adhesion force of the fourth portion 54 to the protective layer 22. In one embodiment, the third portion 52 and the fourth portion 54 contact the protective layer 22, and the second conductive layer 34 contacts both the protective layer 22 and the first conductive layer 32. After performing the irradiation fabrication process P2 on the semiconductor cell 2E, a structure as shown can be formed. Figure 1 The semiconductor element arrangement structure 1A shown is illustrated.

[0090] Reference Figure 20 In one embodiment, the right edge of the second conductive layer 34 of the semiconductor cell 2F is spaced apart from the right edge of the adhesive portion 50 by a distance s1. The left edge of the second conductive layer 34 of the semiconductor cell 2F extends beyond the left edge of the adhesive portion 50 and is flush with the left edge of the semiconductor stack 20. After performing the irradiation fabrication process P2 on the semiconductor cell 2F, a structure as shown can be formed. Figure 1 The semiconductor element arrangement structure 1A shown is illustrated.

[0091] Reference Figure 21 In one embodiment, the right edge of the second conductive layer 34 of the semiconductor cell 2G is spaced apart from the right edge of the adhesive portion 50 by a distance s1, and the left edge of the second conductive layer 34 is flush with the left edge of the adhesive portion 50. The upper edge of the second conductive layer 34 is spaced apart from the upper edge of the adhesive portion 50 by a distance s3, and the lower edge of the second conductive layer 34 is spaced apart from the lower edge of the adhesive portion 50 by a distance s4, wherein the distances s3 and s4 may be the same or different. After performing the irradiation fabrication process P2 on the semiconductor cell 2G, a structure as shown can be formed. Figure 1 The semiconductor element arrangement structure 1A shown is illustrated.

[0092] Figures 22 to 27This diagram shows top views of semiconductor cells 2H-2M according to different embodiments of the present invention. In another embodiment, semiconductor element 36 is a vertical chip. Two electrodes with opposite electrical charges are located on opposite sides of the semiconductor stack 20, and a second conductive layer 34 is connected to one electrode.

[0093] like Figure 22 As shown, in one embodiment, the right edge of the second conductive layer 34 of the semiconductor unit 2H is spaced apart from the right edge of the adhesive portion 50 by a distance s1, and the left edge of the second conductive layer 34 is flush with the left edge of the adhesive portion 50. In one embodiment, the upper edge of the second conductive layer 34 is spaced apart from the upper edge of the adhesive portion 50 by a distance s5, and the upper edge of the second conductive layer 34 is flush with the upper edge of the first conductive layer 32. In one embodiment, the lower edge of the second conductive layer 34 is spaced apart from the lower edge of the adhesive portion 50 by a distance s6, and the lower edge of the second conductive layer 34 is flush with the lower edge of the first conductive layer 32.

[0094] Reference Figure 23 In one embodiment, the right edge of the second conductive layer 34 of the semiconductor unit 2I is spaced apart from the right edge of the adhesive portion 50 by a distance s1, and the left edge of the second conductive layer 34 is flush with the left edge of the semiconductor stack 20. In another embodiment, the upper edge of the second conductive layer 34 is flush with the upper edge of the semiconductor stack 20, and the lower edge of the second conductive layer 34 is flush with the lower edge of the semiconductor stack 20.

[0095] Reference Figure 24 In one embodiment, the second conductive layer 34 of the semiconductor cell 2J has an opening located at the right corner of the semiconductor element. A portion of the right edge of the second conductive layer 34 of the semiconductor cell 2J is flush with the right edge of the semiconductor stack 20.

[0096] Reference Figure 25 In one embodiment, the right edge of the second conductive layer 34 of the semiconductor cell 2K is spaced apart from the right edge of the adhesive portion 50 by a distance s1, and the lower edge of the second conductive layer 34 is spaced apart from the lower edge of the adhesive portion 50 by a distance s6. In one embodiment, the distance s1 may be the same as or different from the distance s6. In one embodiment, after performing the irradiation fabrication process P2 on the semiconductor cell 2K, the two sides (right edge and lower edge) of the adhesive portion 50 come into contact with the protective layer 22 (e.g., Figure 1 The third part 52 contacts the protective layer), and the other sides (left edge and upper edge) of the adhesive part 50 are separated from the protective layer 22 (e.g., Figure 1 The fourth part 54 separates from the protective layer 22.

[0097] Reference Figure 26In one embodiment, the right edge of the second conductive layer 34 of the semiconductor unit 2L is spaced apart from the right edge of the adhesive portion 50 by a distance s1, and the right edge of the second conductive layer 34 extends beyond the right edge of the first conductive layer 32. In another embodiment, the lower edge of the second conductive layer 34 is spaced apart from the lower edge of the adhesive portion 50 by a distance s6, and the lower edge of the second conductive layer 34 extends beyond the lower edge of the first conductive layer 32. In one embodiment, the distance s1 may be the same as or different from the distance s6.

[0098] Reference Figure 27 In one embodiment, the second conductive layer 34 of the semiconductor cell 2M has an opening located at a corner of the semiconductor stack 20. A portion of the right edge of the second conductive layer 34 is flush with the right edge of the semiconductor stack 20, and a portion of the lower edge of the second conductive layer 34 is flush with the lower edge of the carrier plate 40.

[0099] Reference Figure 28 and Figure 29 This is a top view and a cross-sectional view of a semiconductor cell 2N according to an embodiment of the present invention. In one embodiment, Figure 29 for Figure 28 A cross-sectional diagram of line segment V-V'. (See diagram below.) Figure 28 As shown, the right edge of the second conductive layer 34 is spaced s7 from the right edge of the first conductive layer 32, and the lower edge of the second conductive layer 34 is spaced s8 from the lower edge of the first conductive layer 32. Figure 29 As shown, in one embodiment, the second conductive layer 34 exposes a portion of the first conductive layer 32, and the third portion 52 of the adhesive portion 50 contacts the first conductive layer 32 and the protective layer 22.

[0100] Reference Figures 30 to 32 This is a top view and a cross-sectional view of a semiconductor unit 20 according to an embodiment of the present invention. In one embodiment, Figure 31 for Figure 30 A cross-sectional view of line segment VI-VI'. Figure 32 for Figure 30 A cross-sectional schematic diagram of line segment VII-VII'. In one embodiment, the right edge of the second conductive layer 34 is spaced s9 from the right edge of the first conductive layer 32, and the left edge of the second conductive layer 34 is spaced s10 from the left edge of the first conductive layer 32, with distance s10 being less than distance s9. Figure 30 As shown, in one embodiment, the right edge of the second conductive layer 34 is spaced s9' from the upper right corner of the semiconductor stack 20, and the left edge of the second conductive layer 34 is spaced s10' from the lower left corner of the semiconductor stack 20, with the distance s9' being greater than the distance s10'.

[0101] Reference Figure 33In one embodiment, the upper edge of the second conductive layer 34 of the semiconductor cell 2P is flush with the upper edge of the first conductive layer 32, and the lower edge of the second conductive layer 34 is flush with the lower edge of the first conductive layer 32. In one embodiment, in a top view, the area of ​​the second conductive layer 34 is smaller than the area of ​​the first conductive layer 32, and the second conductive layer 34 completely overlaps the first conductive layer 32.

[0102] In one embodiment, further details of the aforementioned semiconductor units 2B-2P can be found in the relevant paragraphs of the aforementioned semiconductor unit 2A, and the semiconductor units 2B-2P can be formed as follows after the irradiation fabrication process P2. Figure 9 The semiconductor unit 2A' shown is illustrated. In another embodiment, Figure 1 or Figure 2 The semiconductor element arrangement structure 1A' or 1A is formed by at least one or more semiconductor units 2A-2P through an irradiation fabrication process P2.

[0103] Accordingly, the present invention improves the reliability of mass transfer fabrication processes for semiconductor devices by adjusting the relative relationship between the adhesive portion and the semiconductor device (e.g., placement position, fabrication process sequence). For example, by performing a curing fabrication process first and then an irradiation fabrication process, the adhesive portion contacts a first part of the semiconductor device and separates from a second part of the semiconductor device. This improves the device pick-up rate, reduces the device drop rate, and / or reduces the device flip rate in the mass transfer fabrication process. For example, by adjusting the placement positions between the first and second conductive layers of the semiconductor device, the adhesive portion, and the carrier plate, the dimensions of the first and second parts, the tilt angle of the semiconductor device, etc., are adjusted, thereby adjusting the adhesion force of the adhesive portion to different parts of the semiconductor device. Therefore, the semiconductor device arrangement structure of the present invention can be widely applied in different transfer fabrication processes.

[0104] Components in the embodiments of this invention can be freely mixed and matched as long as they do not violate the spirit of the invention or conflict with it. Furthermore, the scope of protection of this invention is not limited to the manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps that are currently or will be developed can be understood from the disclosure of this invention, and can be used according to this invention as long as they can perform substantially the same function or obtain substantially the same result in the embodiments described herein. Therefore, the scope of protection of this invention includes the aforementioned manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. No embodiment or claim of this invention needs to achieve all the objects, advantages, and / or features disclosed in this invention.

[0105] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor element arrangement structure, comprising: Carrier plate, having a first top surface; An adhesive portion is disposed on the first top surface; and A semiconductor element is disposed on the adhesive portion and has a second top surface; Wherein, the two virtual extension lines of the first top surface and the second top surface have an angle between them, and the angle between them is greater than 5 degrees and less than 45 degrees.

2. The semiconductor element arrangement structure as claimed in claim 1, wherein the semiconductor element comprises a semiconductor stack and a protective layer, and the second top surface belongs to the semiconductor stack and is not covered by the protective layer.

3. The semiconductor element arrangement structure as claimed in claim 2, wherein the protective layer has a first portion and a second portion, the first portion being in direct contact with the adhesive portion, and the second portion not being in direct contact with the adhesive portion.

4. The semiconductor element arrangement structure as described in claim 3, wherein the semiconductor element further comprises a first conductive layer and a second conductive layer, the first conductive layer being connected to the semiconductor stack, and the second conductive layer covering the first conductive layer.

5. The semiconductor element arrangement structure as claimed in claim 4, wherein the second conductive layer directly contacts the adhesive portion.

6. The semiconductor element arrangement structure as claimed in claim 4, wherein the second conductive layer has a protruding surface that protrudes toward the adhesive portion.

7. The semiconductor element arrangement structure of claim 6, wherein the adhesive portion has a third top surface, the protruding surface protrudes toward the third top surface, and the roughness of the protruding surface is less than the roughness of the third top surface.

8. The semiconductor element arrangement structure as claimed in claim 4, wherein the melting point of the second conductive layer is lower than the melting point of the first conductive layer.

9. The semiconductor element arrangement structure of claim 4, wherein the second conductive layer has a first thickness, the semiconductor stack has a second thickness, and the first thickness is less than or equal to the second thickness.

10. The semiconductor element arrangement structure as described in claim 4, wherein, In the cross-sectional view, the first conductive layer is located between the first portion and the second portion.

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