Van der waals heterojunction memristor based on atomic intercalation molybdenum trioxide and preparation method

Abstract

A kind of van der Waals heterojunction memristor based on atomic intercalation molybdenum trioxide, construction method and regulation method, wherein the van der Waals heterojunction memristor includes bottom two-dimensional material layer, MoO3 nano layer with tin atom intercalated between layers, top two-dimensional material layer, dielectric layer, substrate and electrode;Dielectric layer is arranged on the substrate, and the bottom two-dimensional material layer is arranged on the dielectric layer;Part of MoO3 nano layer is arranged on the upper surface of bottom two-dimensional material layer and another part is arranged on the dielectric layer;Top two-dimensional material layer is partly arranged on MoO3 nano layer and another part is arranged on dielectric layer.The application can realize conductance regulation and synapse plasticity simulation;By changing the number, frequency, intensity and duration of electrical pulse, distinguishable synapse weight update is realized, which provides a new idea for the practical application of two-dimensional high-performance oxide memristor in neuromorphic computing, non-volatile memory, high-density integration and fast memory computing system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronics technology, and in particular to a van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide and its fabrication method. Background Technology

[0002] Memristors, as resistive switching devices with memory characteristics, have shown great potential in fields such as neuromorphic computing and in-memory computing. Van der Waals heterojunction memristors, with their atomically flat interfaces, weak interlayer interactions, and rich electrical controllability, have become an important direction for constructing high-performance memristor devices. Among them, molybdenum trioxide (MoO3), as a typical layered van der Waals material, has advantages such as tunable bandgap, high ion mobility, and structural stability, and is widely used in memristor research. However, pure-phase MoO3 memristors have several limitations: firstly, their high oxygen vacancy formation energy leads to a high operating voltage required for the resistive switching process, and poor switching uniformity and repeatability; secondly, the migration path of oxygen ions between layers is difficult to precisely control, easily causing device performance fluctuations, limiting their application in high-density storage and low-power computing. Furthermore, traditional a-MoO3 memristors are prone to irreversible reconstruction of the interlayer structure under long-term cycling or high-temperature environments, leading to storage state degradation and insufficient non-volatility and stability.

[0003] Therefore, in view of the shortcomings of the existing technology, there is an urgent need for a van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide, its construction method and control method to make up for the deficiencies of the existing technology. Summary of the Invention

[0004] One objective of this invention is to overcome at least one of the shortcomings of existing technologies by providing a van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide. This van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide can achieve conductance modulation and synaptic plasticity simulation; by changing the number, frequency, intensity, and duration of electrical pulses, it can achieve distinguishable synaptic weight updates, providing new ideas for the practical application of two-dimensional high-performance oxide memristors in neuromorphic computing, non-volatile memory, high-density integration, and fast memory computing systems.

[0005] The above-mentioned objectives of the present invention are achieved through the following technical measures: A van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide is provided, comprising a bottom two-dimensional material layer, a MoO3 nanolayer with tin atoms intercalated between the layers, a top two-dimensional material layer, a dielectric layer, a substrate, and electrodes. The dielectric layer is disposed on the upper surface of the substrate, and the bottom two-dimensional material layer is disposed on the upper surface of the dielectric layer. A portion of the MoO3 nanolayer is disposed on the upper surface of the bottom two-dimensional material layer, and another portion is disposed on the upper surface of the dielectric layer. A portion of the top two-dimensional material layer is disposed on the upper surface of the MoO3 nanolayer, and another portion is disposed on the upper surface of the dielectric layer, and the top two-dimensional material layer is not in contact with the bottom two-dimensional material layer. The electrodes include a first electrode and a second electrode, wherein the first electrode is disposed on the upper surface of the bottom two-dimensional material layer, and the second electrode is disposed on the upper surface of the top two-dimensional material layer.

[0006] Preferably, the top two-dimensional material layer is graphene or MoS2.

[0007] The thickness of the MoO3 nanolayer is 50.0 nm to 70.0 nm.

[0008] Preferably, the thickness of the bottom two-dimensional material layer is 2.0 nm to 5.5 nm.

[0009] Preferably, the thickness of the top two-dimensional material layer is 20.0 nm to 100.0 nm.

[0010] Preferably, the top two-dimensional material layer is a graphene nanolayer or a MoS2 nanolayer.

[0011] When the top two-dimensional material layer is a MoS2 nanolayer, the thickness of the top two-dimensional material layer is 20.0 nm to 30.0 nm; when the top two-dimensional material layer is a graphene nanolayer, the thickness of the top two-dimensional material layer is 60.0 nm to 100.0 nm.

[0012] Preferably, the dielectric layer is a SiO2 layer.

[0013] Preferably, the substrate is a Si layer.

[0014] Preferably, the bottom two-dimensional material layer is a graphene nanolayer.

[0015] The second objective of this invention is to overcome at least one of the shortcomings of existing technologies by providing a method for constructing a van der Waals heterojunction memristor. The van der Waals heterojunction memristor obtained by this method can achieve conductance modulation and synaptic plasticity simulation; by changing the number, frequency, intensity, and duration of electrical pulses, distinguishable synaptic weight updates can be achieved, providing new ideas for the practical application of two-dimensional high-performance oxide memristors in neuromorphic computing, non-volatile memory, high-density integration, and fast memory computing systems.

[0016] The above-mentioned objectives of the present invention are achieved through the following technical measures: A method for constructing a van der Waals heterojunction memristor as described above is provided, comprising the following steps: S1. Construct an unintercalated device containing a MoO3 nanolayer. The unintercalated device includes a bottom two-dimensional material layer, a MoO3 nanolayer, a top two-dimensional material layer, a dielectric layer, and a substrate. The dielectric layer is disposed on the upper surface of the substrate, and the bottom two-dimensional material layer is disposed on the upper surface of the dielectric layer. A portion of the MoO3 nanolayer is disposed on the upper surface of the bottom two-dimensional material layer, and another portion is disposed on the upper surface of the dielectric layer. A portion of the top two-dimensional material layer is disposed on the upper surface of the MoO3 nanolayer, and another portion is disposed on the upper surface of the dielectric layer. The top two-dimensional material layer and the bottom two-dimensional material layer are not in contact. S2. The unintercalated device from step S1 is completely immersed in an intercalated tin ion solution. Tin ions in the intercalated tin ion solution undergo a disproportionation reaction to generate tin atoms. Then, the tin atoms are intercalated into the interlayer of the MoO3 nanolayer in the unintercalated device to obtain a tin intercalated device. S3. An electrode is set on the upper surface of the tin intercalation device obtained in step S2 to obtain the van der Waals heterojunction memristor.

[0017] Preferably, the preparation method of the above-mentioned intercalated tin ion solution is as follows: A1. Tartaric acid is added to deionized water to obtain a tartaric acid solution; A2. Add stannous chloride to the tartaric acid solution from step A1 to obtain the intercalated tin ion solution.

[0018] In the intercalated tin ion solution, the concentration of stannous chloride is 1 mM to 10 mM.

[0019] In the intercalated tin ion solution, the concentration of stannous chloride is 3 mM to 5 mM, and the concentration of tartaric acid is 0.1 M.

[0020] Preferably, S2 specifically involves: completely immersing the unintercalated device in the intercalated tin ion solution, heating it at 78°C to 82°C for 18 to 22 minutes to cause the stannous chloride in the intercalated tin ion solution to undergo a disproportionation reaction to generate tin atoms, and then intercalating the tin atoms into the interlayer of the MoO3 nanolayer to obtain a tin-intercalated device.

[0021] Preferably, S1 includes the following steps: S1.1. Peel off the nano-layer of the crystal corresponding to the bottom two-dimensional material layer from the PDMS sheet to obtain a PDMS sheet with the bottom two-dimensional material layer attached; peel off the MoO3 nano-layer in the MoO3 crystal from the PDMS sheet to obtain a PDMS sheet with the MoO3 nano-layer attached; peel off the nano-layer of the crystal corresponding to the top two-dimensional material layer from the PDMS sheet to obtain a PDMS sheet with the top two-dimensional material layer attached. S1.2 Transfer the bottom two-dimensional material layer of the PDMS sheet with the attached bottom two-dimensional material layer and stack it on the upper surface of the dielectric layer in step S1.1; S1.3, a portion of the MoO3 nanolayer in the PDMS sheet with the attached MoO3 nanolayer is transferred and disposed on the upper surface of the bottom two-dimensional material layer in S1.2, and another portion is transferred and disposed on the upper surface of the dielectric layer in S1.2. S1.4. A portion of the top two-dimensional material layer of the PDMS sheet with the top two-dimensional material layer attached is transferred and disposed on the upper surface of the MoO3 nanolayer in step S1.3, and another portion is transferred and disposed on the upper surface of the dielectric layer in step S1.3, and the top two-dimensional material layer does not contact the bottom two-dimensional material layer, thus obtaining the unintercalated device.

[0022] Preferably, S3 specifically involves: setting electrodes on the upper surface of the bottom two-dimensional material layer and the upper surface of the top two-dimensional material layer in the tin intercalation device obtained in step S2 to obtain the van der Waals heterojunction memristor.

[0023] The third objective of this invention is to avoid at least one of the shortcomings of the prior art and to provide a method for controlling the memristor performance of a van der Waals heterojunction memristor to regulate the resistance response variation performance of the van der Waals heterojunction memristor.

[0024] The above-mentioned objectives of the present invention are achieved through the following technical measures: A method for regulating the performance of a van der Waals heterojunction memristor is provided. By adjusting the concentration of tin ions in the intercalation tin ion solution in the construction method of the van der Waals heterojunction memristor described above, at least one of the following can be regulated: the IV hysteresis window, the difference between high and low resistance currents, and the on / off ratio of the van der Waals heterojunction memristor.

[0025] The beneficial effects of this invention are: 1. Under the excitation of electrical pulses and optical pulses of different frequencies, amplitudes, pulse widths and quantities, non-volatile, reversible, continuous multi-level conductance control can be achieved, exhibiting LTP / LTD, weight update, temporal memory and cumulative response similar to biological synapses.

[0026] 2. It possesses excellent multi-state storage capability, good retention and cycle durability, and can achieve stable multi-level resistance state control.

[0027] 3. By leveraging the synergistic effect of the bottom two-dimensional material layer or the top two-dimensional material layer with the tin-intercalated molybdenum trioxide, the behavior of ion transport and charge trapping can be controlled, thereby improving the device's adaptability in neuromorphic computing and in-memory computing applications.

[0028] 4. By adjusting the concentration of tin ions in the intercalated tin ion solution, the IV hysteresis window, the difference between high and low resistance currents, and the on / off ratio of the van der Waals heterojunction memristor can be controlled, achieving non-volatile, reversible, and continuous multi-stage conductance control. Attached Figure Description

[0029] The invention will be further described with reference to the accompanying drawings, but the contents of the drawings do not constitute any limitation on the invention.

[0030] Figure 1 This is a schematic diagram of the structure of the van der Waals heterojunction memristor of the present invention.

[0031] Figure 2 This is a flowchart illustrating the construction method of the van der Waals heterojunction memristor of the present invention.

[0032] Figure 3 This is a microscope image showing the construction process of a van der Waals heterojunction memristor with a top two-dimensional material layer of MoS2 nanolayers. Figure 3 (a) is a microscope image of the MoO3 nanolayers stacked on the surface of the bottom two-dimensional material layer. Figure 3 (b) is a microscope image of MoS2 nanolayers stacked on MoO3 nanolayers and dielectric layers.

[0033] Figure 4 This is a microscope image of a tin intercalation device with a top two-dimensional material layer of MoS2 nanolayer.

[0034] Figure 5 This is a microscope image showing the construction process of a van der Waals heterojunction memristor with a graphene nanolayer as the top two-dimensional material layer. Figure 5 (a) is a microscope image of the bottom two-dimensional material layer stacked on the surface of the dielectric layer. Figure 5 (b) is a microscope image of the MoO3 nanolayers stacked on the surface of the bottom two-dimensional material layer. Figure 5 (c) is a microscope image of graphene nanolayers stacked on MoO3 nanolayers and a dielectric layer. Figure 5 (d) is a microscope image of the tin intercalation device after the MoO3 nanolayer is intercalated.

[0035] Figure 6 The image shows the IV characteristic curve of the van der Waals heterojunction memristor in Comparative Example 1.

[0036] Figure 7 The figures show the IV characteristic curves of the van der Waals heterojunction memristors from Examples 3 to 8, where... Figure 7(a) is the IV characteristic curve of Example 3. Figure 7 (b) shows the IV characteristic curve of Example 4. Figure 7 (c) shows the IV characteristic curve of Example 5. Figure 7 (d) shows the IV characteristic curve of Example 6. Figure 7 (e) shows the IV characteristic curve of Example 7. Figure 7 (f) is the IV characteristic curve of Example 8.

[0037] Figure 8 The figures show the IV characteristic curves of the van der Waals heterojunction memristors from Examples 9 to 14, where... Figure 8 (a) is the IV characteristic curve of Example 9. Figure 8 (b) is the IV characteristic curve of Example 10. Figure 8 (c) is the IV characteristic curve of Example 11. Figure 8 (d) shows the IV characteristic curve of Example 12. Figure 8 (e) is the IV characteristic curve of Example 13. Figure 8 (f) is the IV characteristic curve of Example 14.

[0038] Figure 9 The graph shows the conductivity modulation characteristics of the van der Waals heterojunction memristor in Example 4 under pulse stimulation at different frequencies.

[0039] Figure 10 The graph shows the conductivity modulation characteristics of the van der Waals heterojunction memristor in Example 4 under single-pulse stimulation of different amplitudes.

[0040] Figure 11 The graph shows the conductivity modulation characteristics of the van der Waals heterojunction memristor in Example 4 under pulse stimulation of different pulse widths.

[0041] Figure 12 The graph shows the conductivity modulation characteristics of the van der Waals heterojunction memristor in Example 4 under continuous stimulation with different numbers of pulses.

[0042] Figure 13 The diagram shows the plasticity of the van der Waals heterojunction memristor and its performance in handwritten digit recognition in Example 4. Figure 13 (a) is a graph showing the long-term suppression behavior under 100 pulses. Figure 13 (b) is a graph showing the results of MNIST handwritten digit recognition based on the conductance characteristics of van der Waals heterojunction memristors.

[0043] Figure 14 The current response of the van der Waals heterojunction memristor in Example 4 is shown in the figure under different numbers of pulses (12–42) and a frequency of 1 Hz continuous light pulse stimulation.

[0044] Figure 15 The diagram shows the current response of the van der Waals heterojunction memristor under light pulse stimulation of different pulse widths (1s–15s) in Example 4.

[0045] Figure 16 In Example 4, the van der Waals heterojunction memristor, under stimulation with 60 optical pulses at a frequency of 1 Hz, produced a light intensity of 515 mW / cm². 2 The short-time current response diagram of a van der Waals heterojunction memristor.

[0046] exist Figures 1 to 16 This includes: Substrate 100, dielectric layer 200, bottom two-dimensional material layer 300, MoO3 nanolayer 400, top two-dimensional material layer 500, electrode 600. Detailed Implementation

[0047] The technical solution of the present invention will be further described with reference to the following embodiments. Unless otherwise specified, the experimental methods in the following embodiments are conventional methods. Unless otherwise specified, the raw materials and reagents used in the following embodiments can be purchased from conventional biochemical reagent stores or pharmaceutical companies.

[0048] Example 1

[0049] A van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide, such as Figure 1 As shown, it includes a MoO3 nanolayer 400 with tin atoms intercalated between layers, a bottom two-dimensional material layer 300, a top two-dimensional material layer 500, a dielectric layer 200, and a substrate 100.

[0050] The dielectric layer 200 is disposed on the upper surface of the substrate 100, the bottom two-dimensional material layer 300 is disposed on the upper surface of the dielectric layer 200, a portion of the MoO3 nanolayer 400 is disposed on the upper surface of the bottom two-dimensional material layer 300 and another portion is disposed on the upper surface of the dielectric layer 200, a portion of the top two-dimensional material layer 500 is disposed on the upper surface of the MoO3 nanolayer 400 and another portion is disposed on the upper surface of the dielectric layer 200, and the top two-dimensional material layer 500 and the bottom two-dimensional material layer 300 are not in contact.

[0051] In this invention, the dielectric layer 200 is a SiO2 layer, and the substrate 100 is a Si layer. The bottom two-dimensional material layer 300 can be a two-dimensional layered material capable of forming van der Waals interfaces, preferably a graphene nanolayer. The top two-dimensional material layer 500 can be a variety of two-dimensional material layers, such as a graphene nanolayer or a MoS2 nanolayer.

[0052] In the van der Waals heterojunction memristor, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm to 5.5 nm; the thickness of the MoO3 nanolayer 400 is 50.0 nm to 70.0 nm; and the thickness of the top two-dimensional material layer 500 is 60.0 nm to 100.0 nm. When the top two-dimensional material layer 500 is MoS2, its thickness is 20.0 nm to 30.0 nm; when the top two-dimensional material layer 500 is graphene, its thickness is 60.0 nm to 100.0 nm.

[0053] This van der Waals heterojunction memristor can achieve non-volatile, reversible, and continuous multi-level conductance control under electrical pulse excitation of different frequencies, amplitudes, pulse widths, and numbers, exhibiting LTP / LTD, weight updates, temporal memory, and cumulative response similar to biological synapses. The memristor possesses excellent multi-state storage capability, good retention and cycle durability, and can achieve stable multi-level resistance state control. By leveraging the synergistic effect of the bottom two-dimensional material layer 300 or the top two-dimensional material layer 500 with tin-intercalated molybdenum trioxide, the memristor achieves control over ion transport and charge trapping behavior, improving the device's adaptability in neuromorphic computing and in-memory computing applications.

[0054] Example 2

[0055] An embodiment 1 describes a method for constructing a van der Waals heterojunction memristor, as follows: Figure 2 It includes the following steps: S1. Construct an unintercalated device containing a MoO3 nanolayer 400. The unintercalated device includes a MoO3 nanolayer 400, a bottom two-dimensional material layer 300, a top two-dimensional material layer 500, a dielectric layer 200, and a substrate 100. The dielectric layer 200 is disposed on the upper surface of the substrate 100, the bottom two-dimensional material layer 300 is disposed on the upper surface of the dielectric layer 200, a portion of the MoO3 nanolayer 400 is disposed on the upper surface of the bottom two-dimensional material layer 300, and another portion is disposed on the upper surface of the dielectric layer 200. A portion of the top two-dimensional material layer 500 is disposed on the upper surface of the MoO3 nanolayer 400, and another portion is disposed on the upper surface of the dielectric layer 200. The top two-dimensional material layer 500 is not in contact with the bottom two-dimensional material layer 300. The dielectric layer 200 is SiO2, and the substrate 100 is Si. The top two-dimensional material layer 500 is a graphene nanolayer or a MoS2 nanolayer. S2. The unintercalated device is completely immersed in an intercalated tin ion solution. Tin ions in the intercalated tin ion solution undergo a disproportionation reaction to generate tin atoms. Then, the tin atoms are intercalated into the interlayer of the MoO3 nanolayer 400 in the unintercalated device to obtain a tin intercalated device. S3. An electrode 600 is set on the upper surface of the tin intercalation device obtained in step S2 to obtain a van der Waals heterojunction memristor.

[0056] A van der Waals heterojunction memristor, constructed using the method of this invention, comprises a bottom two-dimensional material layer 300, a MoO3 nanolayer 400 with tin atoms intercalated between layers, a top two-dimensional material layer 500, a dielectric layer 200, a substrate 100, and an electrode 600. The dielectric layer 200 is disposed on the upper surface of the substrate 100, and the bottom two-dimensional material layer 300 is disposed on the upper surface of the dielectric layer 200. A portion of the MoO3 nanolayer 400 is disposed on the upper surface of the bottom two-dimensional material layer 300, and another portion is disposed on the upper surface of the dielectric layer 200. A portion of the top two-dimensional material layer 500 is disposed on the upper surface of the MoO3 nanolayer 400, and another portion is disposed on the upper surface of the dielectric layer 200, and the top two-dimensional material layer 500 is not in contact with the bottom two-dimensional material layer 300. The electrode 600 is disposed on the upper surfaces of both the bottom two-dimensional material layer 300 and the top two-dimensional material layer 500.

[0057] The intercalated tin ion solution is prepared by the following steps: A1. Tartaric acid is added to deionized water to obtain a tartaric acid solution; A2. Add stannous chloride to the tartaric acid solution from step A1 to obtain an intercalated tin ion solution.

[0058] In the intercalated tin ion solution, the concentration of stannous chloride is 1 mM to 10 mM, and the concentration of tartaric acid is 0.1 M. After preparation, the intercalated tin ion solution of this invention needs to be sealed and stored away from light.

[0059] It should be noted that the stannous chloride of the present invention generates tin atoms through a disproportionation reaction in an acidic solution. The concentration of tin atoms generated can be controlled by controlling the concentrations of stannous chloride and tartaric acid. After intercalation, the surface residual solution is gently rinsed with deionized water, and then the sample surface is completely dried with nitrogen before electrode 600 is set. Electrode 600 is specifically set by a mask vapor deposition method, and electrode 600 is a gold electrode with a thickness of 60 nm.

[0060] In this invention, the unintercalated device is completely immersed in the intercalation tin ion solution, meaning the liquid level of the intercalation tin ion solution is ≥2mm above the upper surface of the unintercalated device to ensure uniform intercalation. In actual operation, this involves placing five devices with a base area of ​​1cm². 2 The unintercalated devices were simultaneously immersed in 50 ml of intercalated tin ion solution, which was contained in a cylindrical container with a diameter of 3 cm.

[0061] S2 specifically involves: completely immersing the unintercalated device in an intercalated tin ion solution, heating it at 78℃~82℃ for 18min~22min to cause the stannous chloride in the intercalated tin ion solution to undergo a disproportionation reaction to generate tin atoms, and then intercalating the tin atoms into the 400 layers of the MoO3 nanolayer to obtain a tin intercalated device.

[0062] It should be noted that in this embodiment, the top two-dimensional material layer 500 is specifically a graphene nanolayer or a MoS2 nanolayer, and the bottom two-dimensional material layer 300 is specifically a graphene nanolayer. When the unintercalated device is immersed in an intercalated tin ion solution, the interlayer spacing of graphene is very small, only 0.34 nm, much smaller than the diameter of a tin atom. The interlayer spacing of MoS2 is a close-packed plane of S atoms, and the interlayer force is stronger than that of MoO3. Tin atoms have difficulty opening the MoS2 layer. Therefore, under the material system and processing conditions used in this embodiment, tin atoms mainly occur in the MoO3 nanolayer 400, while no significant corresponding changes are observed in the bottom two-dimensional material layer 300 and the top two-dimensional material layer 500. Experimental phenomena also verify that a color reaction occurs after tin atoms intercalate into the interlayer spacing of the MoO3 nanolayer 400, but no color change occurs in the bottom two-dimensional material layer 300 and the top two-dimensional material layer 500. Figure 4 .

[0063] S1 includes the following steps: S1.1. Peel off the nanolayer of the crystal corresponding to the bottom two-dimensional material layer from the PDMS sheet to obtain a PDMS sheet with the bottom two-dimensional material layer 300 attached; peel off the MoO3 nanolayer 400 in the MoO3 crystal from the PDMS sheet to obtain a PDMS sheet with the MoO3 nanolayer 400 attached; peel off the nanolayer of the crystal corresponding to the top two-dimensional material layer from the PDMS sheet to obtain a PDMS sheet with the top two-dimensional material layer 500 attached. S1.2 Transfer the bottom two-dimensional material layer 300 of the PDMS sheet to which the bottom two-dimensional material layer 300 is attached and stack it on the upper surface of the dielectric layer 200 in S1.1; S1.3, a portion of the MoO3 nanolayer 400 attached to the PDMS sheet is transferred and disposed on the upper surface of the bottom two-dimensional material layer 300 in S1.2, and another portion is transferred and disposed on the upper surface of the dielectric layer 200 in S1.2, as follows. Figure 3 (a); S1.4 A portion of the top two-dimensional material layer 500 of the PDMS wafer with the top two-dimensional material layer 500 attached is transferred and disposed on the upper surface of the MoO3 nanolayer 400 of step S1.3, and another portion is transferred and disposed on the upper surface of the dielectric layer 200 of step S1.3, wherein the top two-dimensional material layer 500 does not contact the bottom two-dimensional material layer 300, thereby obtaining the device, as shown. Figure 3 (b).

[0064] It should be noted that the PDMS sheet preparation method is as follows: Pour 10g of agent A (liquid PDMS) into a clean beaker, and slowly add agent B (polydimethylsiloxane curing agent) dropwise using a pipette. Stir on a magnetic stirrer at a constant speed of 500 rpm for 10 minutes to ensure thorough mixing of the two components. After stirring, allow the mixture to stand for a period of time to allow internal air bubbles to naturally dissipate. Then, pour it evenly into a petri dish and spread it out. Subsequently, place it in an 80℃ constant temperature oven for curing for 1 hour. After the PDMS is completely cured, remove it and cool it to room temperature. Cut it into 1cm pieces using a scalpel. 2 Thin slices are used to obtain PDMS sheets.

[0065] S1.1 includes the following steps: S1.1.1 Place the crystal on the adhesive side of the tape, fold the tape in half to completely wrap the crystal, and then tear the tape. Repeat this process 10 times to obtain tape with a crystal nanolayer adhered to it. Apply a pressure of 1 kPa to press the crystal each time the tape is folded in half. The tearing force when tearing the tape is 3 N / m, and the surface area of ​​the crystal is 3 mm². 2 The above describes the process: when the crystal is graphene, a tape with the bottom two-dimensional material layer 300 is obtained; when the crystal is MoO3, a tape with the MoO3 nanolayer 400 is obtained; when the top two-dimensional material layer 500 is a MoS2 nanolayer and the crystal is MoS2, the tape with the top two-dimensional material layer 500 is adhered to MoS2; when the top two-dimensional material layer 500 is a graphene nanolayer and the crystal is graphene, the tape with the top two-dimensional material layer 500 is adhered to graphene. S1.1.2 Attach the PDMS sheet to the tape with the crystalline nanolayer adhered to it, apply a pressure of 1 kPa, and then peel off the PDMS sheet at a speed of 15 mm / s to transfer the upper crystalline nanolayer to the PDMS sheet. When the crystal is graphene crystal, a PDMS sheet with the bottom two-dimensional material layer 300 is obtained; when the crystal is MoO3 crystal, a PDMS sheet with the MoO3 nanolayer 400 is obtained. When the top two-dimensional material layer 500 is a MoS2 nanolayer and the crystal is MoS2 crystal, then the PDMS sheet with the top two-dimensional material layer 500 has MoS2 crystals adhered to it; when the top two-dimensional material layer 500 is a graphene nanolayer and the crystal is graphene crystal, then the PDMS sheet with the top two-dimensional material layer 500 has graphene crystals adhered to it.

[0066] It should be noted that the tape used in this invention is specifically blue tape of the brand name Ultro Systems and model number HLS-30.

[0067] S1.2 Specifically, the PDMS sheet with the bottom two-dimensional material layer 300 attached is attached to the upper surface of the dielectric layer 200, thereby transferring and stacking the bottom two-dimensional material layer 300 onto the upper surface of the dielectric layer 200 by van der Waals forces.

[0068] Specifically, S1.3 involves attaching a PDMS sheet with a MoO3 nanolayer 400 attached to the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the dielectric layer 200 in S1.2. This causes a portion of the MoO3 nanolayer 400 to be transferred and disposed on the upper surface of the bottom two-dimensional material layer 300, and another portion to be transferred and disposed on the upper surface of the dielectric layer 200 in S1.2. Thus, the MoO3 nanolayer 400 is stacked on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the dielectric layer 200 by van der Waals forces.

[0069] S1.4 specifically involves attaching a PDMS sheet with a top two-dimensional material layer 500 attached to the upper surface of the MoO3 nanolayer 400 and the upper surface of the dielectric layer 200 from S1.3, so that a portion of the top two-dimensional material layer 500 is transferred and disposed on the upper surface of the MoO3 nanolayer 400, and another portion is transferred and disposed on the upper surface of the dielectric layer 200 from step S1.3, thereby stacking the top two-dimensional material layer 500 on the upper surface of the MoO3 nanolayer 400 and the upper surface of the dielectric layer 200 by van der Waals forces.

[0070] It should be noted that when the MoO3 nanolayer 400 is stacked between the bottom two-dimensional material layer 300 and the dielectric layer 200, the MoO3 nanolayer 400 located between the two will bend downwards and be adsorbed by the dielectric layer 200. Since the bottom two-dimensional material layer 300 is very thin, there will be no suspension phenomenon, and the bending amplitude will not cause the MoO3 nanolayer 400 to break. Similarly, the top two-dimensional material layer 500 will not experience suspension or breakage.

[0071] It should also be noted that the stacking of the PDMS sheet with the adhered nanolayer and the device were all performed under a microscope.

[0072] This embodiment is a general process description. Specific parameters can be adjusted by referring to the preferred range or optimal value of Embodiments 3-14 below.

[0073] Example 3

[0074] A method for constructing a van der Waals heterojunction memristor, which is otherwise identical to Example 2, except that it includes the following steps: S1. Construct unintercalated devices; S2. Immerse the unintercalated device in an intercalated tin ion solution and heat it at 82°C for 18 min to cause stannous chloride to undergo a disproportionation reaction to generate tin atoms. Then, the tin atoms are intercalated into the interlayer of the MoO3 nanolayer 400 to obtain a tin intercalated device. S3. Electrodes 600 are set on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the top two-dimensional material layer 500 of the tin intercalation device obtained in step S2 to obtain a van der Waals heterojunction memristor.

[0075] In the intercalated tin ion solution, the concentration of stannous chloride is 1 mM and the concentration of tartaric acid is 0.1 M.

[0076] In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm. The thickness of the MoO3 nanolayer 400 is 50.0 nm. The thickness of the top two-dimensional material layer 500 is 20.0 nm. Specifically, the top two-dimensional material layer 500 is a MoS2 nanolayer. The bottom two-dimensional material layer is a graphene nanolayer.

[0077] S1.1 includes the following steps: S1.1.1 Place the crystal on the adhesive side of the tape (Ultro Systems brand, model HLS-30 blue tape purchased from Zhongke Experimental Materials Store), fold the tape in half to completely wrap the crystal, and then tear the tape. Repeat this process 10 times to obtain tape with a crystal nanolayer adhering to it. Apply a pressure of 1 kPa to press the crystal each time the tape is folded in half. The tearing force when tearing the tape is 3 N / m, and the surface area of ​​the crystal is 3 mm². 2 above; S1.1.2 Attach the PDMS sheet to the tape with the crystalline nanolayer attached, apply a pressure of 1 kPa, and then peel off the PDMS sheet at a speed of 15 mm / s to transfer the crystalline nanolayer to the PDMS sheet, to obtain a PDMS sheet with a bottom two-dimensional material layer 300 attached, a PDMS sheet with a top two-dimensional material layer 500 attached, and a PDMS sheet with a MoO3 nanolayer 400 attached. S1.2, The PDMS sheet with the bottom two-dimensional material layer 300 attached is attached to the upper surface of the dielectric layer 200, thereby transferring and stacking the bottom two-dimensional material layer 300 onto the upper surface of the dielectric layer 200 by van der Waals forces; wherein the area of ​​the bottom two-dimensional material layer 300 is approximately 130 μm. 2 The bottom two-dimensional material layer 300 is a graphene nanolayer. S1.3 A PDMS sheet with an attached MoO3 nanolayer 400 is attached to the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the dielectric layer 200 in S1.2. This causes a portion of the MoO3 nanolayer 400 to be transferred and deposited on the upper surface of the bottom two-dimensional material layer 300, and another portion to be transferred and deposited on the upper surface of the dielectric layer 200 in S1.2. Thus, the MoO3 nanolayer 400 is stacked on the upper surfaces of the bottom two-dimensional material layer 300 and the upper surface of the dielectric layer 200 by van der Waals forces. The area of ​​the MoO3 nanolayer 400 is approximately 100 μm. 2 ; A PDMS sheet with a top two-dimensional material layer 500 attached is attached to the upper surface of the MoO3 nanolayer 400 and the upper surface of the dielectric layer 200 in step S1.3, such that a portion of the top two-dimensional material layer 500 is transferred and disposed on the upper surface of the MoO3 nanolayer 400, and another portion is transferred and disposed on the upper surface of the dielectric layer 200 in step S1.3, thereby stacking the top two-dimensional material layer 500 on the upper surfaces of the MoO3 nanolayer 400 and the dielectric layer 200 by van der Waals forces; wherein the area of ​​the top two-dimensional material layer 500 is approximately 150 μm. 2 The top two-dimensional material layer 500 is a MoS2 nanolayer.

[0078] Example 4

[0079] A method for constructing a van der Waals heterojunction memristor, which is otherwise identical to Example 3, except that it includes the following steps: S1. Construct an unintercalated device containing a 400-layer MoO3 nanoparticle; S2. Immerse the unintercalated device in an intercalated tin ion solution and heat it at 80°C for 20 min to cause stannous chloride to undergo a disproportionation reaction to generate tin atoms. Then, the tin atoms are intercalated into the interlayer of the MoO3 nanolayer 400 to obtain a tin intercalated device. S3. Electrodes 600 are respectively set on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the top two-dimensional material layer 500 of the tin intercalation device obtained in step S2 to obtain a van der Waals heterojunction memristor.

[0080] In the intercalated tin ion solution, the concentration of stannous chloride is 3 mM and the concentration of tartaric acid is 0.1 M.

[0081] In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 4 nm. The thickness of the MoO3 nanolayer 400 is 60.0 nm. The thickness of the top two-dimensional material layer 500 is 25.0 nm, and the top two-dimensional material layer 500 is specifically a MoS2 nanolayer. The bottom two-dimensional material layer 300 is a graphene nanolayer.

[0082] Example 5

[0083] A method for constructing a van der Waals heterojunction memristor, which is otherwise identical to Example 3, except that it includes the following steps: S1. Construct an unintercalated device containing a 400-layer MoO3 nanoparticle; S2. Immerse the device containing the MoO3 nanolayer 400 in an intercalated tin ion solution, heat it at 78°C for 22 min to cause the stannous chloride to undergo a disproportionation reaction to generate tin atoms, and then the tin atoms are intercalated into the interlayer of the MoO3 nanolayer 400 to obtain a tin intercalated device. S3. Electrodes 600 are respectively set on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the top two-dimensional material layer 500 of the tin intercalation device obtained in step S2 to obtain a van der Waals heterojunction memristor.

[0084] In the intercalated tin ion solution, the concentration of stannous chloride is 5 mM, and the concentration of tartaric acid is 0.1 M. In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 5.5 nm. The thickness of the MoO3 nanolayer 400 is 70.0 nm. The thickness of the top two-dimensional material layer 500 is 30.0 nm, and the top two-dimensional material layer 500 is specifically a MoS2 nanolayer. The bottom two-dimensional material layer 300 is a graphene nanolayer.

[0085] Example 6

[0086] A method for constructing a van der Waals heterojunction memristor, which is otherwise identical to Example 3, except that it includes the following steps: S1. Construct an unintercalated device containing a 400-layer MoO3 nanoparticle; S2. Immerse the device containing the MoO3 nanolayer 400 in an intercalated tin ion solution, heat it at 78°C for 22 min to cause the stannous chloride to undergo a disproportionation reaction to generate tin atoms, and then the tin atoms are intercalated into the interlayer of the MoO3 nanolayer 400 to obtain a tin intercalated device. S3. Electrodes 600 are respectively set on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the top two-dimensional material layer 500 of the tin intercalation device obtained in step S2 to obtain a van der Waals heterojunction memristor.

[0087] In the intercalated tin ion solution, the concentration of stannous chloride is 7 mM, and the concentration of tartaric acid is 0.1 M. In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 5.5 nm. The thickness of the MoO3 nanolayer 400 is 70.0 nm. The thickness of the top two-dimensional material layer 500 is 20.0 nm, and the top two-dimensional material layer 500 is specifically a MoS2 nanolayer. The bottom two-dimensional material layer 300 is a graphene nanolayer.

[0088] Example 7

[0089] A method for constructing a van der Waals heterojunction memristor, which is otherwise identical to Example 3, except that it includes the following steps: S1. Construct an unintercalated device containing a 400-layer MoO3 nanoparticle; S2. Immerse the device containing the MoO3 nanolayer 400 in an intercalated tin ion solution, heat it at 78°C for 22 min to cause the stannous chloride to undergo a disproportionation reaction to generate tin atoms, and then the tin atoms are intercalated into the interlayer of the MoO3 nanolayer 400 to obtain a tin intercalated device. S3. Electrodes 600 are respectively set on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the top two-dimensional material layer 500 of the tin intercalation device obtained in step S2 to obtain a van der Waals heterojunction memristor.

[0090] In the intercalated tin ion solution, the concentration of stannous chloride is 9 mM, and the concentration of tartaric acid is 0.1 M. In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 5.5 nm. The thickness of the MoO3 nanolayer 400 is 70.0 nm. The thickness of the top two-dimensional material layer 500 is 30.0 nm, and the top two-dimensional material layer 500 is specifically a MoS2 nanolayer. The bottom two-dimensional material layer 300 is a graphene nanolayer.

[0091] Example 8

[0092] A method for constructing a van der Waals heterojunction memristor, which is otherwise identical to Example 3, except that it includes the following steps: S1. Construct an unintercalated device containing a 400-layer MoO3 nanoparticle; S2. Immerse the unintercalated device in an intercalated tin ion solution and heat it at 78°C for 22 min to induce a disproportionation reaction of stannous chloride to generate tin atoms. Then, the tin atoms are intercalated into the interlayer of the MoO3 nanolayer 400 to obtain a tin intercalated device. S3. Electrodes 600 are respectively set on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the top two-dimensional material layer 500 of the tin intercalation device obtained in step S2 to obtain a van der Waals heterojunction memristor.

[0093] In the intercalated tin ion solution, the concentration of stannous chloride is 10 mM, and the concentration of tartaric acid is 0.1 M. In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 5.5 nm. The thickness of the MoO3 nanolayer 400 is 70.0 nm. The thickness of the top two-dimensional material layer 500 is 30.0 nm, and the top two-dimensional material layer 500 is specifically a MoS2 nanolayer. The bottom two-dimensional material layer 300 is a graphene nanolayer.

[0094] Example 9

[0095] A method for constructing van der Waals heterojunction memristors, such as Figure 5 Other features are the same as in Example 3, except that: in the intercalated tin ion solution, the concentration of stannous chloride is 1 mM and the concentration of tartaric acid is 0.1 M; the top two-dimensional material layer 500 and the bottom two-dimensional material layer 300 are uniform graphene nanolayers.

[0096] In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm. The thickness of the MoO3 nanolayer 400 is 50.0 nm. The thickness of the top two-dimensional material layer 500 is 60.0 nm.

[0097] Example 10

[0098] A method for constructing van der Waals heterojunction memristors, such as Figure 5 Other characteristics are the same as in Example 3, except that: in the intercalated tin ion solution, the concentration of stannous chloride is 3 mM and the concentration of tartaric acid is 0.1 M. In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm. The thickness of the MoO3 nanolayer 400 is 50.0 nm. The thickness of the top two-dimensional material layer 500 is 100.0 nm. Both the top two-dimensional material layer 500 and the bottom two-dimensional material layer 300 are homogeneous graphene nanolayers.

[0099] Example 11

[0100] A method for constructing van der Waals heterojunction memristors, such as Figure 5 Other features are the same as in Example 3, except that the concentration of stannous chloride in the intercalated tin ion solution is 5 mM and the concentration of tartaric acid is 0.1 M. The top two-dimensional material layer 500 and the bottom two-dimensional material layer 300 are homogeneous graphene nanolayers.

[0101] In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm. The thickness of the MoO3 nanolayer 400 is 70.0 nm. The thickness of the top two-dimensional material layer 500 is 80.0 nm.

[0102] Example 12

[0103] A van der Waals heterojunction memristor, with the same structure as in Example 1. The method for constructing this van der Waals heterojunction memristor is as follows: Figure 5 Other characteristics are the same as in Example 3, except that: in the intercalated tin ion solution, the concentration of stannous chloride is 7 mM and the concentration of tartaric acid is 0.1 M. In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm. The thickness of the MoO3 nanolayer 400 is 50.0 nm. The thickness of the top two-dimensional material layer 500 is 60.0 nm. Both the top two-dimensional material layer 500 and the bottom two-dimensional material layer 300 are graphene nanolayers.

[0104] Example 13

[0105] A van der Waals heterojunction memristor, with the same structure as in Example 1. The method for constructing this van der Waals heterojunction memristor is as follows: Figure 5 Other features are the same as in Example 3, except that the concentration of stannous chloride in the intercalated tin ion solution is 9 mM and the concentration of tartaric acid is 0.1 M. Both the top two-dimensional material layer 500 and the bottom two-dimensional material layer 300 are graphene nanolayers.

[0106] In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm. The thickness of the MoO3 nanolayer 400 is 50.0 nm. The thickness of the top two-dimensional material layer 500 is 100.0 nm.

[0107] Example 14

[0108] A van der Waals heterojunction memristor, with the same structure as in Example 1. The method for constructing this van der Waals heterojunction memristor is as follows: Figure 5 Other features are the same as in Example 3, except that the concentration of stannous chloride in the intercalated tin ion solution is 10 mM and the concentration of tartaric acid is 0.1 M. Both the top two-dimensional material layer 500 and the bottom two-dimensional material layer 300 are graphene nanolayers.

[0109] In the unintercalated device, the thickness of the bottom two-dimensional material layer 300 is 2.0 nm. The thickness of the MoO3 nanolayer 400 is 50.0 nm. The thickness of the top two-dimensional material layer 500 is 90.0 nm.

[0110] Comparative Example 1

[0111] A van der Waals heterojunction memristor, with other features the same as in Example 1, except that electrodes 600 are respectively disposed on the upper surface of the bottom two-dimensional material layer 300 and the upper surface of the top two-dimensional material layer 500 in an unintercalated device containing a MoO3 nanolayer 400, thus obtaining a van der Waals heterojunction memristor. The top two-dimensional material layer 500 is a MoS2 nanolayer; the bottom two-dimensional material layer 300 is a graphene nanolayer.

[0112] Example of effect

[0113] 1. IV characteristic curve

[0114] The memristor performance of the van der Waals heterojunction memristors obtained in Examples 3 to 14, and the van der Waals heterojunction memristor of Comparative Example 1, was tested using a Keithley 2612B digital source meter. The IV characteristic curves were obtained. Figure 6 , Figure 7 and Figure 8 .

[0115] from Figure 6 As can be seen, the IV characteristic curve of the unintercalated van der Waals heterojunction memristor has almost no obvious hysteresis loop, and its resistive switching behavior is very weak, indicating that the device itself does not possess effective memristor characteristics and is almost unable to distinguish between the high-resistivity state (HRS) and the low-resistivity state (LRS). Figure 7In the experiment, when the stannous chloride concentration was 1 mM (Example 3), the difference in current between the high-resistivity and low-resistivity states was small. When the stannous chloride concentration increased to 3 mM (Example 4), the difference in current between the high-resistivity and low-resistivity states became most significant, exhibiting a clear and large hysteresis window. As the stannous chloride concentration increased to 5 mM (Example 5), 7 mM (Example 6), 9 mM (Example 7), and 10 mM (Example 8), the hysteresis window of the IV curve showed a regular contraction, the high-resistivity current was significantly suppressed, and the on / off ratio of the device decreased gradually with increasing stannous chloride concentration. Figure 8 It can be seen that although the top two-dimensional material layer 500 is replaced with a graphene nanolayer, the V-value curve and the variation law of stannous chloride concentration of the van der Waals heterojunction memristor are consistent with those of the device where the top two-dimensional material layer 500 is a MoS2 nanolayer.

[0116] The above results demonstrate that this invention significantly modulates the memristor behavior of the device by introducing tin atom intercalation into the van der Waals heterojunction. The unintercalated device exhibits almost no obvious hysteresis loop and extremely weak resistive switching behavior. However, with increasing tin chloride concentration in the intercalated tin ion solution, the device's on / off ratio, hysteresis window, and high / low impedance current levels show significant and regular changes. At a concentration of 1 mM, the device already possesses memristor characteristics, but the distinction between high and low impedance states is limited. A concentration of 3 mM represents the optimal condition, where the hysteresis window is clearest, the difference between high and low impedance currents is greatest, and the device exhibits excellent resistive switching performance. When the tin chloride concentration is further increased to 5 mM, 7 mM, 9 mM, and 10 mM, the hysteresis window contracts regularly, the high impedance current is significantly suppressed, and the on / off ratio decreases gradient with increasing concentration. Figure 7 and Figure 8 In comparison, when the top two-dimensional material layer 500 is a MoS2 nanolayer, the device's on / off ratio, hysteresis window, and high and low resistance current levels are all superior to those when the top two-dimensional material layer 500 is a graphene nanolayer, under different stannous chloride concentrations.

[0117] This demonstrates that the present invention can control the concentration of stannous chloride to regulate the key performance parameters of memristors, providing a reliable technical path for the fabrication of high-performance, tunable van der Waals heterojunction memristors. Furthermore, memristors with a top two-dimensional material layer of 500 being a MoS2 nanolayer exhibit even better performance.

[0118] 2. Conductivity modulation characteristics

[0119] The conductance control characteristics of the van der Waals heterojunction memristor in Example 4 were tested using a Keithley 2612B digital source meter under different frequency pulses, different amplitude single pulses, different pulse width pulses, and different pulse numbers. Figures 9-12 .

[0120] in, Figure 9 Under pulse stimulation at different frequencies (0.9–3.3 Hz), the current response of the van der Waals heterojunction memristor exhibits obvious frequency-dependent characteristics: as the pulse frequency decreases, the current amplitude of the van der Waals heterojunction memristor gradually decreases, and it exhibits a more significant conductance retention effect after high-frequency stimulation, corresponding to the frequency-dependent plasticity of biological synapses.

[0121] Figure 10 Under single-pulse stimulation of different amplitudes (-5 to -9V), the conductance step (ΔG) of the van der Waals heterojunction memristor increases monotonically with the increase of pulse amplitude, exhibiting a typical voltage-dependent synaptic response, which can achieve linear and hierarchical control of weight changes.

[0122] Figure 11 Under pulse stimulation with different pulse widths (100ms–1.5s), the current response of the van der Waals heterojunction memristor increases with the extension of the pulse width, and the relaxation process of the conductance state slows down with the increase of the pulse width, reflecting the time-dependent synaptic weight update characteristics.

[0123] Figure 12 Under continuous stimulation with different numbers of pulses (1–16), the current of the van der Waals heterojunction memristor increases stepwise with the increase of the number of pulses, and the more pulses there are, the more stable the conductance state becomes. At the same time, it exhibits the transition characteristics from short-term enhancement (STM) to long-term enhancement (LTM), simulating the multi-pulse plasticity of biological synapses.

[0124] pass Figures 9-12 As can be seen, the conductance state of the van der Waals heterojunction memristor of this invention can be continuously controlled in multiple dimensions by the frequency, amplitude, width and number of pulses, thus reproducing the key plasticity behavior of biological synapses and providing a certain hardware foundation for building a neuromorphic computing system.

[0125] 3. Plasticity and handwritten digit recognition performance

[0126] The long-term ductility and handwritten digit recognition performance of the van der Waals heterojunction memristor in Example 4 were tested. With a read voltage of -0.6V, the source meter detected a gradual increase in the device's conductance after 50 consecutive 8V voltage pulses, and a gradual return to the initial state after 50 consecutive -8V pulses. Figure 13 (a) It can be seen that the van der Waals heterojunction memristor of the present invention exhibits continuous conductivity regulation capability.

[0127] exist Figure 13(b) utilizes the conductivity of the device to simulate the weights of the neural network. Different conductivity values ​​correspond to different "connection strengths." By adjusting the conductivity of the device through electrical pulses, the learning of digital features is achieved. The neural network constructed based on this conductivity characteristic achieved a maximum recognition accuracy of 95.28% in the MNIST handwritten digit recognition task, verifying the application potential of the van der Waals heterojunction memristor of this invention in neuromorphic computing.

[0128] In summary, this invention achieves the regulation of memristor performance through tin atom intercalation, significantly improving the device's resistive switching capability, synaptic plasticity, and neuromorphic application potential, providing an effective technical solution for the design and application of high-performance van der Waals heterojunction memristors.

[0129] 4. Laser pulse performance

[0130] In addition to electrical pulse modulation, the van der Waals heterojunction memristor of this invention also exhibits an adjustable current response under optical pulse stimulation. Therefore, its photosynaptic behavior was further investigated. A RIGOL DG4102 function generator was used to pulse a 405 nm laser. A Keithley 2612B digital source meter was used to test the photomodulation characteristics of the van der Waals heterojunction memristor of Example 4 under different numbers of optical pulses and different pulse widths. Figures 14-15 The laser intensity was 6.67 W / cm². 2 The memristor's performance was tested using a 405 nm laser modulation characteristic under 60 1 Hz optical pulses, and the results were obtained. Figure 16 The laser intensity is 515 mW / cm². 2 .

[0131] in Figure 14 As can be seen, under continuous light pulse stimulation at a frequency of 1 Hz, the device current response gradually increases as the number of light pulses increases from 12 to 42, exhibiting a clear cumulative upward trend. With the increase in the number of light pulses, the device's conductivity state retention capability is enhanced, indicating that the van der Waals heterojunction memristor of this invention can exhibit significant photoinduced synaptic enhancement behavior under light stimulation, and possesses a transitional characteristic from short-term enhancement (STM) to long-term enhancement (LTM), simulating the multi-pulse plasticity of biological synapses. Figure 15 It is evident that under different pulse widths of optical pulse stimulation, as the pulse width increases from 1 s to 15 s, the amplitude of the device's current response gradually increases, and the current level maintained after the optical pulse stops also increases accordingly. This indicates that the duration of optical stimulation can effectively regulate the synaptic response intensity of the device. These results demonstrate that the van der Waals heterojunction memristor of this invention is significantly dependent on the optical pulse width, and the photosynaptic behavior of the device can be controlled by adjusting the optical pulse width. Figure 16As can be seen, under continuous 60 1 Hz light pulses, the device current gradually increases with the light stimulation. After the light stimulation stops, the device current gradually decreases over time and tends to a lower stable value, exhibiting memory-forgetting behavior similar to that of biological synapses. This result shows that the van der Waals heterojunction memristor of the present invention can not only achieve short-term current enhancement under light stimulation, but also simulate the dynamic process of information retention and gradual forgetting, thus demonstrating the typical behavioral characteristics of photosynaptic devices.

[0132] pass Figures 14-16 It is evident that, under light pulse stimulation, the van der Waals heterojunction memristor of this invention can exhibit light-induced current accumulation, pulse width-dependent response, and memory-forgetting behavior, indicating that in addition to synaptic plasticity under electrical pulse regulation, it also possesses a certain ability to simulate photosynapses, which can provide experimental basis for the construction of multimodal neuromorphic devices.

[0133] Example 15

[0134] A method for performance control of a van der Waals heterojunction memristor is disclosed. Data from examples 3-14 show that changes in tin ion concentration in a tin ion solution have a regular and distinct effect on the resistance response of the van der Waals heterojunction memristor. Therefore, at least one of the following can be controlled by adjusting the tin ion concentration in the intercalated tin ion solution: the IV hysteresis window, the difference between high and low resistance currents, and the on / off ratio of the van der Waals heterojunction memristor. The tin ion concentration is specifically the stannous chloride concentration.

[0135] Specifically, based on the differences in resistive switching response corresponding to different intercalation tin ion concentrations, an appropriate intercalation tin ion concentration can be selected for device construction. The unintercalated device is immersed in the corresponding intercalation tin ion solution, and the unintercalated device contains a MoO3 nanolayer 400. During the immersion process, the tin ions in the intercalation tin ion solution undergo a disproportionation reaction to generate tin atoms. The tin atoms intercalate into the interlayer of the MoO3 nanolayer 400 in the unintercalated device, and finally obtain a van der Waals heterojunction memristor with adjustable performance.

[0136] The method for regulating the performance of van der Waals heterojunction memristors can adjust the resistance response of the memristors according to the concentration of intercalated tin ions in the solution. Specifically, by adjusting the concentration of tin ions in the intercalated tin ion solution, the resistance switching response characteristics of the van der Waals heterojunction memristors can be changed, thereby providing a means of adjustment for the construction of devices with different resistance switching responses.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide, characterized in that: It includes a bottom two-dimensional material layer (300), a MoO3 nanolayer with tin atoms intercalated between layers (400), a top two-dimensional material layer (500), a dielectric layer (200), a substrate (100), and an electrode (600). The dielectric layer (200) is disposed on the upper surface of the substrate (100), and the bottom two-dimensional material layer (300) is disposed on the upper surface of the dielectric layer (200); A portion of the MoO3 nanolayer (400) is disposed on the upper surface of the bottom two-dimensional material layer (300), and another portion is disposed on the upper surface of the dielectric layer (200); A portion of the top two-dimensional material layer (500) is disposed on the upper surface of the MoO3 nanolayer (400) and another portion is disposed on the upper surface of the dielectric layer (200), and the top two-dimensional material layer (500) is not in contact with the bottom two-dimensional material layer (300); The electrode (600) includes a first electrode and a second electrode, wherein the first electrode is disposed on the upper surface of the bottom two-dimensional material layer (300) and the second electrode is disposed on the upper surface of the top two-dimensional material layer (500).

2. The van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide according to claim 1, characterized in that: The thickness of the MoO3 nanolayer (400) is 50.0 nm to 70.0 nm; The thickness of the bottom two-dimensional material layer (300) is 2.0 nm to 5.5 nm; The thickness of the top two-dimensional material layer (500) is 20.0 nm to 100.0 nm.

3. The van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide according to claim 1, characterized in that: The top two-dimensional material layer (500) is a graphene nanolayer or a MoS2 nanolayer; When the top two-dimensional material layer (500) is a MoS2 nanolayer, the thickness of the top two-dimensional material layer (500) is 20.0 nm to 30.0 nm; When the top two-dimensional material layer (500) is a graphene nanolayer, the thickness of the top two-dimensional material layer (500) is 60.0 nm to 100.0 nm.

4. The van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide according to claim 1, characterized in that: The dielectric layer (200) is a SiO2 layer; The substrate (100) is a Si layer; The bottom two-dimensional material layer (300) is a graphene nanolayer.

5. A method for constructing a van der Waals heterojunction memristor as described in any one of claims 1-4, characterized in that: Includes the following steps: S1. Construct an unintercalated device containing a MoO3 nanolayer (400). The unintercalated device includes a bottom two-dimensional material layer (300), a MoO3 nanolayer (400), a top two-dimensional material layer (500), a dielectric layer (200), and a substrate (100). The dielectric layer (200) is disposed on the upper surface of the substrate (100), and the bottom two-dimensional material layer (300) is disposed on the upper surface of the dielectric layer (200). A portion of the MoO3 nanolayer (400) is disposed on the upper surface of the bottom two-dimensional material layer (300), and another portion is disposed on the upper surface of the dielectric layer (200). A portion of the top two-dimensional material layer (500) is disposed on the upper surface of the MoO3 nanolayer (400), and another portion is disposed on the upper surface of the dielectric layer (200). The top two-dimensional material layer (500) and the bottom two-dimensional material layer (300) are not in contact. S2. The unintercalated device from step S1 is completely immersed in an intercalated tin ion solution. Tin ions in the intercalated tin ion solution undergo a disproportionation reaction to generate tin atoms. Then, the tin atoms are intercalated into the interlayer of the MoO3 nanolayer in the unintercalated device to obtain a tin intercalated device. S3. An electrode is set on the upper surface of the tin intercalation device obtained in step S2 to obtain the van der Waals heterojunction memristor.

6. The method for constructing a van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide according to claim 5, characterized in that, The method for preparing the intercalated tin ion solution is as follows: A1. Tartaric acid is added to deionized water to obtain a tartaric acid solution; A2. Add stannous chloride to the tartaric acid solution from step A1 to obtain the intercalated tin ion solution; In the intercalated tin ion solution, the concentration of stannous chloride is 1 mM to 10 mM.

7. The method for constructing a van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide according to claim 6, characterized in that: In the intercalated tin ion solution, the concentration of stannous chloride is 3 mM to 5 mM, and the concentration of tartaric acid is 0.1 M.

8. The method for constructing a van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide according to claim 6 or 7, characterized in that, Specifically, S2 is: The unintercalated device is completely immersed in the intercalated tin ion solution, and heated at 78℃~82℃ for 18min~22min to cause the stannous chloride in the intercalated tin ion solution to undergo a disproportionation reaction to generate tin atoms. Then, the tin atoms are intercalated into the interlayer of the MoO3 nanolayer to obtain the tin intercalated device.

9. The method for constructing a van der Waals heterojunction memristor based on atomically intercalated molybdenum trioxide according to claim 6 or 7, characterized in that, S1 includes the following steps: S1.

1. Peel off the nanolayer of the crystal corresponding to the bottom two-dimensional material layer using a PDMS sheet to obtain a PDMS sheet with the bottom two-dimensional material layer attached; peel off the MoO3 nanolayer in the MoO3 crystal using a PDMS sheet to obtain a PDMS sheet with the MoO3 nanolayer attached; peel off the nanolayer of the crystal corresponding to the top two-dimensional material layer using a PDMS sheet to obtain a PDMS sheet with the top two-dimensional material layer attached. S1.2 Transfer the bottom two-dimensional material layer of the PDMS sheet with the attached bottom two-dimensional material layer to the upper surface of the dielectric layer in step S1.1; S1.3, a portion of the MoO3 nanolayer in the PDMS sheet with the attached MoO3 nanolayer is transferred and disposed on the upper surface of the bottom two-dimensional material layer in S1.2, and another portion is transferred and disposed on the upper surface of the dielectric layer in S1.

2. S1.

4. A portion of the top two-dimensional material layer of the PDMS sheet with the top two-dimensional material layer attached is transferred and disposed on the upper surface of the MoO3 nanolayer in step S1.3, and another portion is transferred and disposed on the upper surface of the dielectric layer in step S1.3, and the top two-dimensional material layer does not contact the bottom two-dimensional material layer, to obtain the unintercalated device. Specifically, S3 involves setting electrodes on the upper surface of the bottom two-dimensional material layer and the upper surface of the top two-dimensional material layer in the tin intercalation device obtained in step S2, thereby obtaining the van der Waals heterojunction memristor.

10. A method for performance control of a van der Waals heterojunction memristor, characterized in that: By adjusting the tin ion concentration in the intercalated tin ion solution in the construction method of the van der Waals heterojunction memristor as described in any one of claims 6-9, at least one of the following in the van der Waals heterojunction memristor can be controlled: the IV hysteresis window, the difference between high and low resistance currents, and the on / off ratio.

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