Lower electrode structure of a two-terminal switching device, two-terminal switching device and method of manufacture

Abstract

The application discloses a lower electrode structure of a two-terminal switching device, a two-terminal switching device and a preparation method. The lower electrode structure comprises a main body part located in a through hole of a substrate, an upper surface of the main body part is flush with an upper surface of the substrate, and the main body part has a gap in a depth direction along a central axis of the through hole; and a cover layer part comprising a planar part located on the upper surface of the substrate and covering the main body part and a first vertical part filling the gap of the main body part; wherein the main body part is in direct contact with the cover layer part, and in any width direction on the upper surface of the substrate, the size of the planar part is greater than or equal to the size of the main body part. Through the scheme of the application, the surface topography of the lower electrode connecting hole can be effectively repaired, the gap opening and the surface depression can be eliminated, and a flat and continuous deposition substrate is provided for subsequent film layers, so that the performance and yield of the device are improved.

Description

Technical Field

[0001] This application generally relates to the field of semiconductor technology. More specifically, this application relates to a lower electrode structure for a two-end switching device, the two-end switching device, and a method for fabricating the lower electrode structure for the two-end switching device. Background Technology

[0002] With the rapid development of semiconductor memory technology towards high density, low power consumption, and small size, novel non-volatile memories, represented by resistive random access memory ("RRAM"), have become a research focus. Two-terminal switching devices, such as two-terminal gating devices (e.g., selectors) and two-terminal storage devices (e.g., RRAM), are typically integrated between back-end copper interconnect structures due to their advantages such as simple structure and ease of three-dimensional integration. The lower electrode is connected to the surface of the underlying metal interconnect through a lower electrode connection hole.

[0003] However, with the evolution of process nodes and the need to meet the etching requirements of subsequent functional films, the thickness of the lower electrode film is constantly increasing, leading to a further increase in the aspect ratio of the lower electrode interconnects. Traditional physical vapor deposition (PVD) processes have weak filling capabilities and cannot meet the filling requirements of high aspect ratio vias. Although chemical vapor deposition (CVD) processes have high filling capabilities, they are prone to forming gaps inside the vias during growth, and subsequent chemical mechanical polishing (CMP) processes can cause problems such as rough surface morphology and sidewall depressions in the interconnects. These surface defects are seriously detrimental to the deposition integrity of subsequent functional films (such as resistive switching layers or selectable layers) and device performance.

[0004] In view of this, this application provides a lower electrode structure scheme for a two-end switching device, so as to effectively repair the surface morphology of the lower electrode connection hole, eliminate gap openings and surface depressions, and provide a flat and continuous deposition substrate for subsequent film layers, thereby improving the performance and yield of the device. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems mentioned above, this application proposes a lower electrode structure scheme for a two-end switching device in several aspects.

[0006] In a first aspect, this application provides a lower electrode structure for a two-end switching device, comprising: a main body portion located within a via of a substrate, the upper surface of the main body portion being flush with the upper surface of the substrate, the main body portion having a slit in a depth direction along the central axis of the via; and a capping layer portion comprising a planar portion located on the upper surface of the substrate and covering the main body portion, and a first vertical portion filling the slit of the main body portion; wherein the main body portion is in direct contact with the capping layer portion, and the size of the planar portion is greater than or equal to the size of the main body portion in any width direction within the upper surface of the substrate.

[0007] In some embodiments, the first vertical portion at least blocks the upper opening of the slit.

[0008] In some embodiments, a recess is formed at the junction of the main body portion and the upper surface of the substrate, and the capping layer portion further includes a second vertical portion filling the recess.

[0009] In some embodiments, the depth-to-width ratio of the main body portion is >5:1, wherein the depth of the main body portion refers to the dimension along the depth direction of the central axis of the through hole, and the width of the main body portion refers to the dimension along the width direction parallel to the upper surface of the substrate.

[0010] In some embodiments, the flatness of the planar portion of the capping layer is less than 0.2 nm.

[0011] In some embodiments, the system further includes one or more of the following features: the thickness of the capping layer is 10 Å to 500 Å; the width of the capping layer is 200 Å to 2000 Å; the depth of the main body is 100 Å to 1000 Å; and the width of the main body is 200 Å to 2000 Å.

[0012] In some embodiments, the materials of the body portion and the cover portion include any one or more of the following: metal, metal nitride, and metal oxide.

[0013] In some embodiments, wherein: the metal includes one or more of W, Ta, Ti, Cu, and Al; the metal nitride includes one or more of TiNx, WNx, TaNx, and AlNx; and / or the metal oxide includes one or more of TiOx, WOx, TaOx, and AlOx.

[0014] In some embodiments, the main body portion and the cover portion are made of the same material or include metal homologous materials or different materials.

[0015] In some embodiments, the body portion is formed by the following process: performing a first deposition in a via of the substrate to form an initial body portion; planarizing the initial body portion so that the upper surface of the initial body portion is flush with the upper surface of the substrate to form the body portion, wherein the body portion has a slit in the depth direction along the central axis of the via and a recess is formed at the junction with the upper surface of the substrate.

[0016] In some embodiments, the capping portion is formed by the following process: performing a second deposition on the substrate, wherein the deposited material fills the gaps and recesses of the body portion and forms a thin layer covering the body portion and the substrate; etching the thin layer such that the size of the thin layer is greater than or equal to the size of the body portion in any width direction along the upper surface of the substrate.

[0017] In some embodiments, the capping portion is further formed by a process of planarizing the upper surface of the thin layer.

[0018] In a second aspect, this application provides a two-end switching device, including a lower electrode structure as described in any of the first aspects above.

[0019] In some embodiments, the two-end switching device includes: a two-end gating device or a two-end storage device.

[0020] In a third aspect, this application provides a method for fabricating a lower electrode structure for a two-end switching device, comprising: providing a substrate having a through-hole; performing a first deposition in the through-hole of the substrate to form an initial body portion, wherein the initial body portion has a slit in a depth direction along the central axis of the through-hole; performing a second deposition on the substrate, wherein a deposition material fills the slit in the initial body portion and forms a thin layer covering the initial body portion and the substrate; and etching the thin layer such that the size of the thin layer is greater than or equal to the size of the body portion in any width direction along the upper surface of the substrate.

[0021] In some embodiments, prior to the second deposition, the method further includes: planarizing the initial body portion so that the upper surface of the initial body portion is flush with the upper surface of the substrate to form the body portion of the lower electrode structure, wherein the body portion has a recess formed at the junction with the upper surface of the substrate.

[0022] In some embodiments, the deposited material further fills the depression during the second deposition.

[0023] In some embodiments, the first deposition is chemical vapor deposition (CVD).

[0024] In some embodiments, the second deposition is physical vapor deposition (PVD).

[0025] In some embodiments, the preparation method further includes: planarizing the upper surface of the thin layer.

[0026] In some embodiments, the planarization process includes touch chemical mechanical polishing (TCM).

[0027] In some embodiments, the etching process is performed after the film stack structure of the two-end switching device is formed on the thin layer.

[0028] In some embodiments, the deposition materials used for the first deposition and the second deposition include metallic materials, which include one or more of W, Ta, Ti, Cu, and Al.

[0029] In some embodiments, the depth-to-width ratio of the through-hole is >5:1.

[0030] The lower electrode structure scheme for the two-end switching device described above, in this embodiment, involves setting a capping layer comprising a planar portion and a first vertical portion on top of the main body of the lower electrode structure. The first vertical portion effectively seals the gaps and openings in the main body caused by the CVD process, while the capping layer comprehensively covers and repairs surface roughness and sidewall depressions that may exist after the CMP process. This provides a smooth, continuous, and defect-free growth interface for the subsequently deposited functional film, thereby significantly improving the deposition quality of the functional film and device performance. Attached Figure Description

[0031] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein:

[0032] Figure 1 This is an exemplary schematic diagram illustrating an existing RRAM memory 100; Figure 2 This is an exemplary schematic diagram illustrating RRAM memory interconnects; Figure 3 This is an exemplary schematic diagram illustrating existing RRAM memory interconnect defects; Figure 4 This is an exemplary schematic diagram illustrating the lower electrode structure 400 for a two-end switching device according to an embodiment of this application; Figure 5 This is yet another exemplary schematic diagram illustrating the lower electrode structure 400 for a two-end switching device according to an embodiment of this application; Figure 6 This is an exemplary schematic diagram illustrating a two-end switching device 600 according to an embodiment of this application; Figure 7This is yet another exemplary schematic diagram illustrating the two-end switching device 600 according to an embodiment of this application; Figure 8 This is an exemplary flowchart illustrating a method 800 for fabricating a lower electrode structure for a two-end switching device according to an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] It should be understood that the terms "comprising" and "including" used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0035] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0036] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0037] Figure 1 This is an exemplary schematic diagram illustrating an existing RRAM memory 100. (See attached diagram.) Figure 1As shown, the RRAM memory 100 may include a lower electrode 101, a resistive switching layer 102, and an upper electrode 103. In some implementations, the materials of the lower electrode 101 and the upper electrode 103 may include inert metals (such as Pt, Au, W, TiN, etc.) and active metals (such as Ti, Ta, Ag, Cu, etc.). Inert metal electrodes have high chemical stability and avoid participating in redox reactions; active metal electrodes can serve as ion sources (such as Ag). + Cu 2+ ), adapted to specific resistive switching mechanisms.

[0038] The resistive switching layer 102 is the core functional layer, and its material is mainly transition metal oxide, such as, but not limited to, HfO2 and TaO. x TiO2, NiO, AlO x The key characteristic of resistive switching layers is their ability to reversibly switch between a high-resistivity state (HRS, MΩ~GΩ level) and a low-resistivity state (LRS, Ω~kΩ level) under electric or thermal excitation, enabling data storage. For example, by applying a specific voltage between the upper and lower electrodes, the formation and disconnection of the conductive filaments 104 in the resistive switching layer can be controlled, thereby achieving the switching between the low-resistivity and high-resistivity states of the memory cell.

[0039] As an example, when a positive set voltage is applied, oxygen ions or metal ions in the resistive switching layer migrate to form conductive filaments connecting the upper and lower electrodes, and the device changes from a high-resistivity state to a low-resistivity state, which is defined as binary data 1; when a negative reset voltage or a higher voltage in the same direction is applied, the conductive filaments break, and the device returns to a high-resistivity state, which is defined as binary data 0, thereby realizing the function of non-volatile memory.

[0040] As described in the background above, RRAM memory is typically placed between back-end copper interconnect structures, with the lower electrode connected to the surface of the underlying metal interconnect via a lower electrode connection hole. Figure 2 As shown in the image.

[0041] Figure 2 This is an exemplary schematic diagram illustrating RRAM memory interconnects. (See diagram below.) Figure 2As shown, the lower electrode 101 in the RRAM memory is connected to the surface of the lower metal interconnect 202 via a lower electrode connection hole 201. The lower metal interconnect 202 is disposed within the lower metal interlayer dielectric layer 203, and is flush with the surface of the lower metal interlayer dielectric layer 203. Sidewalls 204 cover the surfaces of the lower metal interlayer dielectric layer 203 and the lower metal interconnect 202, and the lower electrode connection hole 201 is formed within the sidewalls 204. Further, the upper electrode 103 in the RRAM memory is connected to the upper metal interconnect 205 via an upper electrode connection hole. The upper metal interconnect 205 is disposed within the upper metal interlayer dielectric layer 206. The lower electrode connection hole 201 is a key vertical interconnect structure for realizing the electrical connection between the lower metal interconnect 202 and the lower electrode 101; its filling quality directly determines the performance and reliability of the memory cell.

[0042] In practical applications, the filling material for the lower electrode connection hole can include Ti / TiN, Ta / TaN, WNx / W, etc. Ti, Ta, or WNx are typically used as an adhesion layer to improve the adhesion between the filling material (such as TiN, TaN, or W) and the dielectric material on the sidewall of the lower electrode connection hole, while also acting as a barrier layer to prevent metal diffusion. These materials are usually prepared using physical vapor deposition ("PVD") processes. However, PVD processes (such as magnetron sputtering) are less effective at filling vias with high aspect ratios (i.e., depth-to-width ratios) due to the pronounced directionality of the deposited particles. Traditional PVD processes can typically only reliably fill vias with aspect ratios less than 5:1. As semiconductor process nodes evolve from the micrometer scale to the nanometer scale (such as 90nm, 28nm, and even below 14nm), and to meet the increased lower electrode film thickness required for RRAM thin-film etching processes, the aspect ratio of the lower electrode connection hole has continuously increased, often exceeding 5:1 and even reaching 15:1. In this situation, the traditional PVD filling capability is no longer sufficient, and filling defects such as overhangs and voids are prone to occur, leading to poor device contact or open circuits.

[0043] Currently, to overcome the limitations of PVD filling capacity, chemical vapor deposition (CVD) has been used to fill high aspect ratio bottom electrode connection holes. CVD utilizes a gaseous precursor to chemically react on a heated substrate surface to generate a solid film, exhibiting excellent step coverage and conformal properties. CVD can achieve void-free filling of vias with aspect ratios less than 15:1, and is therefore widely used in the fabrication of tungsten (W) plugs. However, because the tungsten film grows simultaneously from the sidewalls and bottom of the via, the film layers on the left and right sidewalls gradually thicken and converge towards the center of the via over time. At the convergence interface, perfect bonding is often not achieved, resulting in a tiny gap along the depth direction near the central axis of the via, for example... Figure 3 As shown in the image. Figure 3This is an exemplary schematic diagram illustrating a defect in an existing RRAM memory interconnect. This gap ( Figure 3 The gap 301 shown will be exposed after a subsequent chemical mechanical polishing (“CMP”) process, forming an opening on the upper surface of the through hole.

[0044] Furthermore, when the sidewall of the current electrode connection hole contains an adhesive layer material such as WNx, the CMP polishing rates of WNx and W differ due to their different physicochemical properties. WNx typically polishes faster than W, therefore, after CMP, the WNx region on the sidewall will form a depression relative to the W body (e.g., Figure 3 (At positions a and b indicated by the middle arrows). Simultaneously, the CMP process itself may also cause the W surface to become rough due to the mechanical action of the abrasive particles and localized unevenness in chemical corrosion, for example... Figure 3 The W surface in the upper middle figure is convex. Figure 3 The lower figure shows surface irregularities such as unevenness. These morphological defects are detrimental to the integrity of subsequent RRAM functional film deposition. For example, at gap openings, the subsequently deposited film may not cover continuously, leading to pinholes or breaks; at rough surfaces and depressions, the film thickness is uneven, causing local electric field concentration or increased leakage current, severely reducing the reliability and yield of the memory.

[0045] Based on this, this application proposes a novel lower electrode structure scheme for a two-end switching device. By setting a cover layer containing a planar portion and a first vertical portion on the main body of the lower electrode structure, the first vertical portion effectively blocks the gap openings in the main body caused by the CVD process, and the cover layer covers and repairs the surface roughness and sidewall depressions that may exist after the CMP process.

[0046] The scheme of this application will be described in detail below with reference to the accompanying drawings.

[0047] Figure 4 This is an exemplary schematic diagram illustrating the lower electrode structure 400 for a two-end switching device according to an embodiment of this application. Figure 4 As shown, the lower electrode structure 400 includes a main body portion 401 and a capping layer portion 402 located within a via of the substrate. The upper surface of the main body portion 401 is flush with the upper surface of the substrate 403, and the main body portion 401 has a slit 405 in the depth direction along the central axis of the via 404. The capping layer portion 402 includes a planar portion located on the upper surface of the substrate 403, covering the main body portion 401, and a first vertical portion 406 filling the slit 405 of the main body portion 401. Further, the main body portion 401 is in direct contact with the capping layer portion 402, and the planar portion has a dimension greater than or equal to the dimension of the main body portion 401 along any width direction within the upper surface of the substrate 403.

[0048] It is understood that the aforementioned substrate may include the lower metal interlayer dielectric layer, lower metal interconnects, and lower electrode connection vias (i.e., vias in the context of this application), with the lower metal interconnects exposed at the bottom of the vias. The main body is a conductive material filled within the vias to achieve electrical connection between the lower metal interconnects and the subsequently formed lower electrode (or directly with the functional layer). The main body contains gaps, and the upper surface of the main body is covered by the planar portion of the capping layer, while the gaps are filled and sealed by the first vertical portion, effectively eliminating the surface defect of gap openings and providing a continuous, opening-free surface for the subsequent deposition of functional films.

[0049] In some embodiments, the aforementioned first vertical portion at least seals the upper opening of the gap. That is, the first vertical portion does not need to completely fill the entire gap, but at least covers the top region of the gap opening. This prevents subsequent films deposited from above from falling into the gap, avoids discontinuities due to the presence of the gap opening, and also avoids pinhole defects in the subsequent films.

[0050] In some implementations, due to the difference in CMP polishing rates between the sidewall adhesion layer or barrier layer material (e.g., WNx) and the host material (e.g., W), WNx polishes at a faster rate. During the CMP process, WNx is removed more quickly, resulting in a downwardly recessed region at the interface between the host portion and the upper surface of the substrate. This recess is typically annular around the top edge of the host portion. Therefore, in some embodiments, a recess is formed at the interface between the host portion and the upper surface of the substrate (see above). Figure 3 (at locations a and b in the original text), the capping layer also includes a second vertical portion that fills the recess. This second vertical portion extends downward from the planar portion, filling the edge recess, for example... Figure 5 As shown.

[0051] Figure 5 This is yet another exemplary schematic diagram illustrating the lower electrode structure 400 for a two-end switching device according to an embodiment of this application. Figure 5 As shown, the lower electrode structure 400 includes a main body portion 401 and a capping layer portion 402 located within a via of the substrate. The upper surface of the main body portion 401 is flush with the upper surface of the substrate 403, and the main body portion 401 has a slit 405 in the depth direction along the central axis of the via 404. The capping layer portion 402 includes a planar portion located on the upper surface of the substrate 403, covering the main body portion 401, and a first vertical portion 406 filling the slit 405 of the main body portion 401 and a second vertical portion 501 filling the recess. Further, the main body portion 401 is in direct contact with the capping layer portion 402, and the planar portion has a dimension greater than or equal to the dimension of the main body portion 401 along any width direction within the upper surface of the substrate 403.

[0052] Based on this, the capping layer simultaneously repairs the surface defects caused by CMP in both the central gap and the edge depressions. As a result, the entire upper surface of the lower electrode structure (including the central and edge regions) becomes continuous and smooth, eliminating defects such as gap openings, surface roughness, and edge depressions induced by CMP, thus providing a good deposition substrate for subsequent thin films.

[0053] In some embodiments, the depth-to-width ratio of the main body portion is greater than 5:1. Here, the depth of the main body portion refers to its dimension along the depth direction of the via's central axis, and the width of the main body portion refers to its dimension along the width direction parallel to the upper surface of the substrate. With this aspect ratio, the via filling, which previously could not achieve a good surface morphology due to its high aspect ratio, can be significantly improved by this solution, thereby expanding the feasibility of using high aspect ratio vias in the lower electrode structure.

[0054] In some embodiments, the flatness of the planar portion of the capping layer is less than 0.2 nm. This flatness reflects the surface micro-irregularity at the nanoscale, corresponding to a micro-roughness Ra of less than 0.20 nm on the upper surface of the capping layer. In some implementations, the roughness of the upper surface of the capping layer can be reduced to below 0.20 nm by introducing contact chemical mechanical polishing (e.g., touch CMP). This avoids thickness inconsistencies, pinholes, or lattice defects caused by surface protrusions or depressions, resulting in a dense, continuous functional film with extremely low defect density. Simultaneously, the smooth interface reduces local electric field concentration, lowers interface state density and leakage current, leading to a higher on / off ratio, better cycle stability, more consistent selector threshold voltage, and greater durability. Furthermore, it avoids localized failures of the functional film (such as short circuits or open circuits) caused by defects on the lower electrode surface, thereby significantly improving the overall manufacturing yield of the two-terminal switching device.

[0055] In some embodiments, the lower electrode structure may further include any one or more of the following features: the thickness of the capping layer is 10 Å to 500 Å; the width of the capping layer is 200 Å to 2000 Å; the depth of the main body is 100 Å to 1000 Å; and the width of the main body is 200 Å to 2000 Å. These features can be adjusted according to specific device requirements in the implementation scenario, and this application does not impose any limitations in this regard.

[0056] In some embodiments, the materials of the main body portion and the cover portion may include, but are not limited to, any one or more of the following: metal, metal nitride, and metal oxide. In some embodiments, the metal may include, but is not limited to, one or more of W, Ta, Ti, Cu, and Al; the metal nitride may include, but is not limited to, one or more of TiNx, WNx, TaNx, and AlNx; and the metal oxide may include, but is not limited to, one or more of TiOx, WOx, TaOx, and AlOx.

[0057] In some embodiments, the main body and the capping layer are made of the same material, or may include homologous metal materials, or may be made of different materials. Homologous metals refer to two materials containing the same metallic element but with different stoichiometric ratios or chemical forms; for example, the main body is W and the capping layer is WNx; or the main body is Ti and the capping layer is TiN. Homologous materials typically have good lattice matching and adhesion, few interface defects, and low contact resistance. In some implementations, they may also be made of different materials, such as W for the main body and TiN for the capping layer. This application does not impose any limitations in this regard.

[0058] In some embodiments, the aforementioned main body portion can be formed by the following process: performing a first deposition in a via of a substrate to form an initial main body portion; planarizing the initial main body portion so that the upper surface of the initial main body portion is flush with the upper surface of the substrate to form the main body portion, wherein the main body portion has a slit in the depth direction along the central axis of the via and a recess is formed at the interface with the upper surface of the substrate. In some implementations, the aforementioned first deposition can be, for example, CVD. The aforementioned planarization process can be, for example, CMP.

[0059] In some embodiments, the capping layer can be formed by the following process: performing a second deposition on a substrate, wherein the deposited material fills the gaps and recesses of the main portion, forming a thin layer covering the main portion and the substrate; etching the thin layer so that the size of the thin layer is greater than or equal to the size of the main portion in any width direction along the upper surface of the substrate. In some implementations, the second deposition can be, for example, PVD. PVD particles have a certain scattering ability, enabling them to cover and fill surface defects in the main portion. Filling the gaps forms a first vertical portion, filling the recesses forms a second vertical portion, and simultaneously forming planar portions on the surface.

[0060] Subsequent etching of this thin layer ensures it remains only in the lower electrode region, with a size equal to or greater than the main body, guaranteeing complete coverage of the main body (including edge recesses). In some implementations, etching can be dry (e.g., reactive ion etching using SF6 or Cl2-based gases) or wet (e.g., using hydrogen peroxide-based or nitric acid-based etching solutions). Based on this, the capping layer is precisely defined in the lower electrode region, ensuring complete coverage. This achieves physical filling and three-dimensional coverage of gaps and recesses, and avoids unnecessary electrical connections through graphical representation.

[0061] In some embodiments, the capping layer may be further formed by planarizing the upper surface of the thin layer. This planarization process can be, for example, touch CMP, which enables touch-based leveling, eliminating minute roughness or particles that may exist on the surface after PVD deposition, rather than removing a large amount of material. This results in a smooth surface for the final lower electrode structure, which greatly benefits the deposition quality of subsequent functional layers (such as resistive switching layers), including improving the crystalline order of the film, reducing defect density, and improving interface properties, thereby enhancing the on / off ratio and cycle life of the switching devices at both ends.

[0062] As described above, this application embodiment addresses the issue of insufficient PVD filling capacity by utilizing CVD technology to form the main body of the via with high aspect ratio. The planar portion of the capping layer fully covers the upper surface of the main body after CMP planarization, while the first vertical portion at least seals the openings in the main body caused by the CVD process, eliminating the risk of pinholes during subsequent film deposition. Simultaneously, the second vertical portion fills the edge depressions formed at the interface between the main body and the substrate upper surface due to differences in grinding rates of different materials during the CMP process, thereby simultaneously repairing both central gaps and edge depressions.

[0063] Furthermore, by controlling the capping layer to an extremely thin range to avoid increasing additional resistance and parasitic capacitance, and controlling the depth of the main body to within the typical back-end process node range, the materials of the main body and capping layer can be the same, of the same origin, or different. Furthermore, a dense and flat thin layer is formed through a second deposition, followed by further flattening using contact CMP, significantly improving the flatness of the capping layer's planar portion. Therefore, this application provides a continuous, open, recess-free, and atomically flat deposition interface for subsequent deposition of the resistive switching layer of the RRAM or the selector layer of the selector, significantly improving the film deposition quality, device reliability, and manufacturing yield of the switching devices at both ends.

[0064] In some embodiments, this application also provides a two-end switching device, including the lower electrode structure of the embodiments of this application. In some embodiments, the two-end switching device may include a two-end gating device or a two-end storage device.

[0065] In some implementation scenarios, a two-end switching device may include a lower electrode, a select layer, a resistive switching layer, an upper electrode, and a lower electrode structure. The select layer may be disposed on the lower electrode, the upper electrode may be disposed on the select layer, and the resistive switching layer may be disposed between the select layer and the lower electrode, or between the select layer and the upper electrode, or simultaneously between the select layer and the lower electrode and the select layer and the upper electrode. Furthermore, the lower electrode of the two-end switching device is in contact with the surface of the capping portion of the lower electrode structure, for example... Figure 6 As shown.

[0066] Figure 6 This is an exemplary schematic diagram illustrating a two-end switching device 600 according to an embodiment of this application. For example... Figure 6 As shown, the two-end switching device 600 may include a lower electrode 601, a select layer 602, a resistive switching layer 603, an upper electrode 604, a lower electrode structure 400, and a substrate 403. The lower electrode 601 is in contact with the surface of the capping layer portion 402 in the lower electrode structure 400. The figure exemplarily shows that the resistive switching layer 603 is simultaneously disposed between the select layer and the lower electrode, and between the select layer and the upper electrode.

[0067] It is necessary to understand that Figure 6 This is merely illustrative and not limiting. As mentioned earlier, the materials of the lower and upper electrodes can be, for example, Pt, Au, W, TiN, Ti, Ta, Ag, Cu, etc. The material of the resistive switching layer 603 can be, for example, HfO2, TaO, etc. x TiO2, NiO, AlO x In some implementation scenarios, the material selected for layer 602 can be, for example, NbO. x WO x TiO x GeSe, etc., enable reversible switching (high-resistance off state / low-resistance on state) to block crosstalk current. More details about the lower electrode structure 400 can be found above. Figure 4 The details described herein will not be repeated here.

[0068] Figure 7 This is yet another exemplary schematic diagram illustrating a two-end switching device 600 according to an embodiment of this application. For example... Figure 7 As shown, the two-end switching device 600 may include a lower electrode 601, a select layer 602, a resistive switching layer 603, an upper electrode 604, a lower electrode structure 400, and a substrate 403. The lower electrode 601 is in contact with the surface of the capping portion 402 in the lower electrode structure 400. Further, the upper electrode 604 may also be connected to the upper electrode structure 701. For example, as described above... Figure 2 The RRAM memory shown is shown.

[0069] Figure 8This is an exemplary flowchart illustrating a method 800 for fabricating a lower electrode structure for a two-end switching device according to an embodiment of this application. Figure 8 As shown, in step S801, a substrate is provided, the substrate having vias. The substrate may be an interlayer dielectric layer, and the vias are formed by photolithography and etching, having a depth-to-width ratio greater than 5:1, exposing the underlying metal layer at the bottom. In step S802, a first deposition is performed in the vias of the substrate to form an initial body portion, wherein the initial body portion has a slit in the depth direction along the central axis of the via. The first deposition is preferably performed by CVD, and the deposition material may be W.

[0070] Next, in step S803, a second deposition is performed on the substrate, wherein the deposited material fills the gaps in the initial main body portion and forms a thin layer covering the initial main body portion and the substrate, i.e., forming the aforementioned capping portion and the first vertical portion. The second deposition is preferably PVD, and the deposited material can be a thin layer of the same WPVD material covering and filling the gap openings. Further, in step S804, the thin layer is etched so that the size of the thin layer is greater than or equal to the size of the main body portion along any width direction within the upper surface of the substrate. The etching process forms the final boundary of the capping portion. Based on this, the gaps are sealed and the coverage area is precisely controlled.

[0071] In some embodiments, prior to the second deposition, the initial body portion is further planarized so that the upper surface of the initial body portion is flush with the upper surface of the substrate to form the body portion of the lower electrode structure, wherein the body portion has a recess at the interface with the upper surface of the substrate. As previously mentioned, the planarization process can be, for example, CMP.

[0072] In some embodiments, during the second deposition, the deposited material further fills the depression. That is, the second deposition also forms the aforementioned second vertical portion to fill the depression. In some embodiments, the first deposition is chemical vapor deposition (CVD). The second deposition is physical vapor deposition (PVD).

[0073] In some embodiments, the preparation method further includes planarizing the upper surface of the thin layer. This planarization process can be, for example, touch CMP. This achieves an atomically smooth surface without disrupting the three-dimensional structure of the capping layer, providing an optimal growth interface for subsequent functional films.

[0074] In some embodiments, the etching process is performed after the film layer stack structure of the two-terminal switching device has been formed on a thin layer. For example, after the lower electrode, select layer, resistive switching layer, upper electrode, and lower electrode structure of the two-terminal switching device are sequentially deposited, the etching process is performed to remove excess areas, such as... Figure 6 The trapezoidal shape formed after the etching process is shown in the figure.

[0075] In some embodiments, the deposition materials used for the first and second depositions include metallic materials. These metallic materials may include, but are not limited to, one or more of W, Ta, Ti, Cu, and Al. In some embodiments, the depth-to-width ratio of the via is greater than 5:1.

[0076] In summary, this application effectively eliminates problems such as gap openings, edge depressions, and surface roughness caused by CVD filling and CMP processes in the prior art by adding a thin capping layer with three-dimensional filling capability on the main body of the lower electrode structure and combining it with contact CMP for surface leveling. This provides a smooth, continuous, and defect-free growth interface for subsequent deposition of resistive switching layers of RRAM, selector layers of selectors, or other functional films, thereby significantly improving the film deposition quality, device performance, and manufacturing yield of two-terminal switching devices.

[0077] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A lower electrode structure for a two-end switching device, characterized in that, include: A main body portion located within a via of a substrate, the upper surface of the main body portion being flush with the upper surface of the substrate, the main body portion having a slit in the depth direction along the central axis of the via; as well as The capping layer includes a planar portion located on the upper surface of the substrate and covering the main body portion, and a first vertical portion filling the gaps in the main body portion; The main body portion is in direct contact with the capping layer portion, and the size of the planar portion is greater than or equal to the size of the main body portion along any width direction within the upper surface of the substrate.

2. The lower electrode structure according to claim 1, wherein, The first vertical portion at least blocks the upper opening of the gap.

3. The lower electrode structure according to any one of claims 1-2, wherein, A recess is formed at the junction of the main body portion and the upper surface of the substrate, and the cover layer portion further includes a second vertical portion that fills the recess.

4. The lower electrode structure according to any one of claims 1-3, wherein the depth-to-width ratio of the main body portion is >5:1, wherein the depth of the main body portion refers to the dimension along the depth direction of the central axis of the through hole, and the width of the main body portion refers to the dimension along the width direction parallel to the upper surface of the substrate.

5. The lower electrode structure according to any one of claims 1-4, wherein the flatness of the planar portion of the capping layer is less than 0.2 nm.

6. The lower electrode structure according to any one of claims 1-5, further comprising any one or more of the following features: The thickness of the capping layer is 10 Å to 500 Å; The width of the capping layer is 200 Å to 2000 Å; The depth of the main body is 100 Å to 1000 Å; and The width of the main body is 200 Å to 2000 Å.

7. The lower electrode structure according to any one of claims 1-6, wherein the material of the main body portion and the cover portion includes any one or more of the following: metal, metal nitride, metal oxide.

8. The lower electrode structure according to claim 7, wherein: The metal includes one or more of W, Ta, Ti, Cu, and Al; The metal nitride includes one or more of TiNx, WNx, TaNx, and AlNx; and / or The metal oxide includes one or more of TiOx, WOx, TaOx, and AlOx.

9. The lower electrode structure according to any one of claims 1-8, wherein, The main body and the cover layer are made of the same material, or include the same metal material, or are made of different materials.

10. The lower electrode structure according to any one of claims 1-9, wherein the main body portion is formed by the following process: A first deposition is performed in the through-hole of the substrate to form an initial body portion; The initial main body portion is planarized so that the upper surface of the initial main body portion is flush with the upper surface of the substrate to form the main body portion, wherein the main body portion has a gap in the depth direction along the central axis of the through hole and a recess is formed at the junction with the upper surface of the substrate.

11. The lower electrode structure according to claim 10, wherein the capping layer portion is formed by the following process: A second deposition is performed on the substrate, wherein the deposited material fills the gaps and recesses of the main body portion and forms a thin layer covering the main body portion and the substrate; The thin layer is etched so that the size of the thin layer is greater than or equal to the size of the main body portion along any width direction within the upper surface of the substrate.

12. The lower electrode structure according to claim 11, wherein the capping layer portion is further formed by the following process: The upper surface of the thin layer is planarized.

13. A two-end switching device, comprising the lower electrode structure as described in any one of claims 1-12.

14. The two-end switching device according to claim 13, wherein the two-end switching device comprises: Two-terminal gating devices or two-terminal storage devices.

15. A method for fabricating a lower electrode structure for a two-terminal switching device, characterized in that, include: A substrate is provided, wherein the substrate has through-holes; A first deposition is performed in a via of the substrate to form an initial body portion, wherein the initial body portion has a slit in the depth direction along the central axis of the via; A second deposition is performed on the substrate, wherein the deposited material fills the gaps in the initial body portion and forms a thin layer covering the initial body portion and the substrate; as well as The thin layer is etched so that the size of the thin layer is greater than or equal to the size of the main body portion along any width direction within the upper surface of the substrate.

16. The preparation method according to claim 15, wherein, Prior to the second deposition, the process also includes: The initial main body portion is planarized so that the upper surface of the initial main body portion is flush with the upper surface of the substrate to form the main body portion of the lower electrode structure, wherein the main body portion has a recess at the junction with the upper surface of the substrate.

17. The preparation method according to claim 16, wherein, In the second deposition, the deposition material also fills the depression.

18. The preparation method according to any one of claims 15-17, wherein, The first deposition was chemical vapor deposition (CVD).

19. The preparation method according to any one of claims 15-18, wherein, The second deposition is physical vapor deposition (PVD).

20. The preparation method according to any one of claims 15-19, further comprising: The upper surface of the thin layer is planarized.

21. The preparation method according to claim 20, wherein the planarization treatment comprises touch chemical mechanical polishing (TCM).

22. The preparation method according to any one of claims 15-21, wherein, The etching process is performed after the film stack structure of the two-end switching device is formed on the thin layer.

23. The preparation method according to any one of claims 15-22, wherein the deposition materials used for the first deposition and the second deposition include metallic materials, and the metallic materials include one or more of W, Ta, Ti, Cu, and Al.

24. The preparation method according to any one of claims 15-23, wherein the depth-to-width ratio of the through hole is >5:1.

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