Semiconductor structure manufacturing method, semiconductor structure, and electronic device

Abstract

Embodiments of the present application provide a semiconductor structure manufacturing method, a semiconductor structure and an electronic device. The method comprises: forming a mixed defect suppression layer above a substrate, wherein the mixed defect suppression layer is a mixed phase structure of a cubic phase and a hexagonal phase, and a misfit is formed at a phase interface between the cubic phase and the hexagonal phase; and forming a gallium nitride layer above the mixed defect suppression layer. Embodiments of the present application can reduce the dislocation density in the gallium nitride layer, improve the crystal quality of the gallium nitride layer, and improve the performance and reliability of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and an electronic device. Background Technology

[0002] Due to the lack of suitable homogeneous substrates, heteroepitaxial growth of nitride materials necessitates the use of heteroepitaxial methods. However, the heteroepitaxial process generates high-density dislocations and various point defects. These defects can negatively impact the performance of nitride-based optoelectronic and power electronic devices.

[0003] In related technologies, aluminum nitride nucleation layers are used to epitaxially grow gallium nitride (GaN) films on silicon carbide substrates. However, the nucleation layer technology cannot prevent dislocation lines from extending upwards, resulting in a high dislocation density in the GaN film, which affects the performance and reliability of electronic devices. How to improve the performance and reliability of semiconductor structures, thereby improving the performance of semiconductor devices using these structures, is a problem that urgently needs to be discussed and solved. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and an electronic device, aiming to improve the performance and reliability of the semiconductor structure, thereby improving the performance of semiconductor devices using the structure.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, the method comprising: forming a mixed defect suppression layer above a substrate, wherein the mixed defect suppression layer is a mixed phase structure of cubic and hexagonal phases, and stacking faults are formed at the phase interface between the cubic phase and the hexagonal phase; and forming a gallium nitride layer above the mixed defect suppression layer.

[0006] Secondly, embodiments of this application provide a semiconductor structure, including: a substrate; a mixed defect suppression layer disposed above the substrate, wherein the mixed defect suppression layer is a mixed phase structure of cubic and hexagonal phases, and stacking faults are formed at the phase interface between the cubic phase and the hexagonal phase; and a gallium nitride layer disposed above the mixed defect suppression layer.

[0007] Thirdly, embodiments of this application provide an electronic device, including: the semiconductor structure as described in the second aspect.

[0008] In this embodiment, a mixed defect suppression layer with a cubic and hexagonal mixed-phase structure is disposed between the substrate and the gallium nitride layer. During the fabrication process, the atomic stacking sequence of the mixed defect suppression layer leads to a mismatch in the lattice parameters between the cubic and hexagonal phases, resulting in stacking faults at the phase interface. These stacking faults are perpendicular to the growth direction of dislocation lines, forming a physical barrier. When a dislocation line encounters a stacking fault, the dislocation line is captured and annihilated, thereby reducing the dislocation density in the gallium nitride layer, improving the crystal quality of the gallium nitride layer, and enhancing the performance and reliability of the semiconductor structure, thus improving the performance of the semiconductor device using this structure.

[0009] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0010] Figure 1 A schematic diagram of the layer structure of GaN thin films provided for related technologies;

[0011] Figure 2 A flowchart illustrating a semiconductor structure fabrication method provided in an embodiment of this application;

[0012] Figure 3 A schematic diagram illustrating the generation of stacking fault blocking dislocations in a mixed defect suppression layer provided as an example of this application;

[0013] Figure 4 A partial atomic structure diagram of a cubic and hexagonal mixed phase in a YAlN mixed defect suppression layer provided as an example of this application;

[0014] Figure 5 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0015] Figure 6 A schematic diagram illustrating the fabrication of a semiconductor structure provided as an example in this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0017] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0018] In the description of the embodiments of this application, unless otherwise expressly limited, terms such as setting, installing, and connecting should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in the embodiments of this application in combination with the specific content of the technical solution.

[0019] In this application, the terms "furthermore," "exemplarily," or "optionally" are used as examples, illustrations, or descriptions and should not be construed as being more preferred or advantageous than other embodiments or designs. The use of terms such as "furthermore," "exemplarily," or "optionally" is intended to present the relevant concepts in a specific manner.

[0020] In related technologies, heteroepitaxial growth of nitride materials relies on methods due to the lack of suitable homogeneous substrates. However, lattice and thermal mismatches between the substrate and the epitaxial layer during heteroepitaxial growth result in high defect densities in the epitaxial layer, primarily consisting of high-density dislocations and various point defects. These defects not only affect the performance of nitride-based optoelectronic and power electronic devices but also severely restrict further applications of the materials and the reliability of the devices.

[0021] Currently, to suppress these defects, academia and industry mainly employ advanced defect suppression methods, such as epitaxial lateral overgrowth (ELOG) technology. ELOG technology, by growing an epitaxial layer defined at the substrate edge, can effectively reduce dislocation density and improve the crystal quality of the material. However, these methods typically require additional steps, increasing process complexity and cost. Furthermore, methods like ELOG may introduce impurities during growth, which can further affect the electrical and optical properties of the material, hindering the growth of high-quality materials.

[0022] In related technologies, a method for epitaxially growing gallium nitride (GaN) thin films on silicon carbide (SiC) substrates using an aluminum nitride (AlN) nucleation layer is employed, such as... Figure 1As shown, the main purpose of growing an AlN nucleation layer is to achieve GaN thin film growth through a two-step growth method using AlN nucleation layers. This can alleviate the lattice mismatch problem between the substrate and the GaN layer. Simultaneously, the AlN nucleation layer provides high-quality nucleation islands for GaN nucleation. These nucleation islands gradually merge during subsequent high-temperature growth, forming a flat GaN epitaxial layer. However, the above-mentioned nucleation layer technology generally has a limited effect on preventing dislocation lines from extending upwards, resulting in a high dislocation density in the GaN thin film, which affects the performance and reliability of the semiconductor structure. Furthermore, excessively high dislocation density in the GaN thin film also leads to low crystal quality, limiting the frequency characteristics and electron mobility of the device. How to improve the performance and reliability of semiconductor structures is a problem that urgently needs to be discussed and solved.

[0023] To address the aforementioned issues, this application provides a semiconductor structure fabrication method, a semiconductor structure, and an electronic device. A mixed defect suppression layer with a cubic and hexagonal mixed-phase structure is disposed between a substrate and a gallium nitride (GaN) layer. This mixed defect suppression layer replaces the AlN nucleation layer in related technologies. During the fabrication process, the atomic stacking sequence in the mixed defect suppression layer leads to a mismatch in the lattice parameters between the cubic and hexagonal phases, resulting in stacking faults at the phase interface. These stacking faults are perpendicular to the dislocation line growth direction. By utilizing these stacking faults to form a physical barrier, when a dislocation line encounters a stacking fault, the dislocation line is captured and annihilated, thereby reducing the dislocation density in the GaN layer, improving the crystal quality of the GaN layer, and enhancing the performance and reliability of the semiconductor structure.

[0024] The semiconductor structure of this application embodiment, or the device fabricated using the semiconductor structure fabrication method provided in this application embodiment, can be applied to the following scenarios:

[0025] High-frequency communication devices: such as high-frequency radio frequency power amplifiers, used in 5G base stations and satellite communications; low-noise amplifiers, used in receiver front-ends.

[0026] Power electronics: such as high-efficiency power converters for data centers, electric vehicles and renewable energy systems; high-power-density power electronic modules for industrial motor drives and grid regulation.

[0027] Optoelectronic devices: such as high-brightness LED lighting for general and special lighting applications; ultraviolet detectors and emitters for medical disinfection, environmental monitoring and security systems.

[0028] High-temperature electronic devices: such as high-temperature sensors, used in aerospace and industrial process control; high-temperature stable electronic devices, used in automotive engine management systems.

[0029] Military and avionics: such as high-frequency devices in radar and electronic warfare systems; high-temperature and radiation-resistant devices in avionics equipment.

[0030] Medical devices: such as high-frequency ultrasound transducers for medical imaging; miniaturized medical sensors for in vivo diagnosis and treatment.

[0031] Wearable devices: such as miniature sensors integrated into smartwatches and health monitoring devices; flexible electronics for health monitoring and human-computer interaction.

[0032] Internet of Things (IoT): such as sensors and communication modules for smart cities and smart homes; wireless sensor networks for environmental monitoring and data collection.

[0033] Quantum computing and communication: such as high-frequency qubit control and readout devices; single-photon detectors in quantum communication systems.

[0034] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0035] Figure 2 This is a flowchart illustrating a semiconductor structure fabrication method according to an embodiment of this application. Figure 2 As shown, the method for fabricating this semiconductor structure includes at least the following:

[0036] Step 210: A mixed defect suppression layer is formed above the substrate, wherein the mixed defect suppression layer is a mixed phase structure of cubic and hexagonal phases, and stacking faults are formed at the phase interface of cubic and hexagonal phases.

[0037] Step 220: Form a gallium nitride layer above the mixed defect suppression layer.

[0038] In step 210, the substrate refers to the basic material that supports the growth of the epitaxial layer in the fabrication of the semiconductor structure. Exemplarily, substrate materials include, but are not limited to, sapphire, Si (silicon), SiC (silicon carbide), diamond, etc.

[0039] The mixed defect suppression layer is formed by mixing cubic and hexagonal transition metal nitrides, resulting in a mixed cubic and hexagonal phase structure with stacking faults at the phase interface between the cubic and hexagonal phases. The mixed defect suppression layer serves as a crucial starting layer for epitaxial growth, providing the foundation for subsequent gallium nitride layer growth. Here, cubic phase refers to a crystal structure in which atoms are arranged in a cubic lattice; hexagonal phase refers to a crystal structure in which atoms are arranged in a hexagonal lattice; and stacking faults are line defects in a crystal involving the misalignment of atomic layers. Examples of transition metal nitrides include, but are not limited to, yttrium aluminum nitride (YAlN), scandium aluminum nitride (ScAlN), and aluminum phosphorus nitride (AlPN).

[0040] Gallium nitride (GaN) layer is the core functional layer that determines the performance of semiconductor structures. Its material properties, growth process, and structural design directly affect the efficiency and reliability of high-frequency and high-power devices.

[0041] For example, Figure 3 This is a schematic diagram illustrating the generation of stacking fault blocking dislocations in a mixed defect suppression layer provided as an example of this application, using cubic and hexagonal phases. Figure 3 As shown, in this example, the substrate is assumed to be a SiC substrate, and the mixed defect suppression layer is a transition metal nitride defect suppression layer. By controlling the growth conditions, cubic transition metal nitrides are incorporated into hexagonal transition metals, resulting in phase deformation into a mixed phase structure of cubic and hexagonal phases. This alters the atomic packing order during crystal growth, leading to a mismatch in the lattice parameters between the cubic and hexagonal phases, thereby generating stacking faults (such as...) at the phase interface. Figure 3 As shown in the diagram, when the dislocation line extends upwards, it will encounter a stacking fault perpendicular to its growth direction, be captured and annihilated by the stacking fault (as shown in the diagram). Figure 3 (As shown).

[0042] The above embodiments provide a mixed defect suppression layer with a mixed cubic and hexagonal phase structure between the substrate and the gallium nitride layer. Replacing the AlN nucleation layer in related technologies with this mixed defect suppression layer, the atomic stacking sequence during the fabrication process leads to a mismatch in the lattice parameters between the cubic and hexagonal phases, resulting in stacking faults at the phase interface. These stacking faults are perpendicular to the dislocation line growth direction, forming a physical barrier. When a dislocation line encounters a stacking fault, it is captured and annihilated, thereby reducing the dislocation density in the gallium nitride layer. Furthermore, the use of the mixed defect suppression layer can reduce the surface roughness of the GaN film, further improving the crystal quality of the gallium nitride layer and enhancing the performance and reliability of the semiconductor structure. Moreover, compared to related technologies such as ELOG, which require additional processes and impurities, the semiconductor structure fabrication method provided in this application does not introduce additional processes or other materials that could cause impurities.

[0043] In some scenarios, defects (dislocations) in semiconductor materials can become the core of secondary defects generated by irradiation, accelerating material performance degradation. Defects can also trap electron-hole pairs generated by irradiation, leading to non-radiative recombination and reducing device response speed or the light output efficiency of optoelectronic devices. By utilizing the hybrid defect suppression layer provided in the embodiments of this application to reduce dislocation density, the radiation resistance of devices can be effectively improved.

[0044] In some scenarios, defects such as dislocations can scatter phonons, reducing the thermal conductivity of materials (e.g., GaN's theoretical thermal conductivity is as high as 2.1 W / cm·K, but defects can significantly reduce its actual value), leading to poorer heat dissipation capabilities of devices. Defective regions can also form localized hot spots inside the device, causing thermal breakdown and accelerating device aging. By utilizing the hybrid defect suppression layer provided in this application, internal material defects can be reduced, thereby improving the device's heat dissipation capabilities and enhancing its reliability.

[0045] In some scenarios, defects such as dislocations act as scattering centers, increasing carrier scattering and thus reducing carrier mobility. Simultaneously, defects can trap carriers, reducing carrier concentration and consequently lowering device current density. By utilizing the hybrid defect suppression layer provided in this application embodiment, internal material defects can be reduced, thereby improving device current density.

[0046] In some applications, such as optoelectronic devices, defects like dislocations can increase recombination centers for charge carriers, promoting electron-hole recombination and reducing the device's photoelectric conversion efficiency. By utilizing the hybrid defect suppression layer provided in this application, internal material defects can be reduced, thereby enhancing the device's photoelectric conversion efficiency.

[0047] As can be seen, the semiconductor structure fabrication method provided in this application achieves efficient annihilation of dislocation lines by controlling the mixing of cubic and hexagonal phases in the mixed defect suppression layer to form stacking faults. This is something that is difficult to achieve through simple material stacking or process adjustments in related technologies. The specific phase transition mechanism and stacking fault formation in this application significantly optimize the crystal quality of GaN thin films, thereby improving device performance.

[0048] The above is a general description of steps 210 and 220. The following is a detailed description of the specific implementation process of steps 210 and 220.

[0049] In one embodiment, step 210 includes:

[0050] A mixed defect suppression layer is formed on the substrate using aluminum, yttrium, and nitrogen sources.

[0051] In this embodiment, the aluminum source refers to a precursor compound used to provide aluminum, the yttrium source refers to a precursor compound used to provide yttrium, and the nitrogen source refers to a precursor compound used to provide nitrogen. During the fabrication of the semiconductor structure, the aluminum source, yttrium source, and nitrogen source are all in a gaseous state.

[0052] For example, the aluminum source is trimethylaluminum (TMAl), the yttrium source is tris(methylcyclopentadienyl)yttrium ((MCp)3Y), and the nitrogen source is ammonia (NH3).

[0053] In the embodiments, an aluminum source, a yttrium source, and a nitrogen source are used to generate a YAlN mixed defect suppression layer, which is formed by the incorporation of cubic yttrium nitride (YN) into hexagonal YAlN. For example... Figure 4 As shown, Figure 4 This is a top view along the [11-20] direction, where gray spheres represent nitrogen (N) atoms, green spheres represent aluminum (Al) atoms, and blue spheres represent yttrium (Y) atoms. The orange and blue dashed lines represent the generated stacking fault boundaries. Due to the significant difference in lattice constants between the cubic YN phase and the wurtzite phase (i.e., the hexagonal phase), lattice slip and distortion occur along the [-1100] and

[0001] directions, respectively, resulting in the formation of stacking fault boundaries along the [11-20] and [-1100] directions at the interface. The generation of stacking faults in the mixed defect suppression layer effectively blocks upward-extending through dislocations, thereby effectively reducing the defect density inside the GaN layer.

[0054] The AlN nucleation layer used in related technologies has certain limitations in heteroepitaxial processes. The above embodiments overcome these limitations by introducing a transition metal nitride mixed defect suppression layer. For example, the YAlN mixed defect suppression layer provides better lattice matching and stress control compared to traditional AlN nucleation layers. The 11% YAlN composition in the mixed defect suppression layer allows for lattice matching with GaN, contributing to improved GaN film quality. By precisely controlling the growth conditions of the YAlN mixed defect suppression layer, a mixture of cubic and hexagonal phases can be achieved, resulting in stacking faults at the phase interface. Stacking faults are used to block dislocations, annihilating upward-extending dislocation lines and reducing dislocation density in the GaN film. Furthermore, the application of the transition metal nitride mixed defect suppression layer can significantly reduce the surface roughness of the GaN film, further improving its crystal quality.

[0055] In one embodiment, a mixed defect suppression layer is formed above a substrate using an aluminum source, a yttrium source, and a nitrogen source, comprising:

[0056] An aluminum source is introduced into the reaction chamber, and an aluminum film is formed on the substrate inside the reaction chamber using a metal-organic chemical vapor deposition process.

[0057] Adjust the flow rate of the aluminum source and simultaneously introduce the yttrium source and nitrogen source so that the yttrium source and nitrogen source react with the aluminum film to generate a mixed defect suppression layer;

[0058] Adjusting the periodic step changes in temperature and pressure controls the formation of stacking faults at the phase interface in the mixed defect suppression layer.

[0059] In this embodiment, Metal-Organic Chemical Vapor Deposition (MOCVD) refers to a technique that deposits high-quality semiconductor thin films on a substrate surface by decomposing a metal-organic precursor at high temperature and reacting it with a reactive gas. It offers high flexibility, large-area uniformity, and atomic-level thickness control. Temperature refers to the growth temperature at which the mixed defect suppression layer is formed; pressure refers to the pressure within the reaction chamber.

[0060] The above embodiments control growth conditions such as temperature, pressure, and flow rates of each element source, and adjust the growth temperature and reaction chamber pressure of the mixed defect suppression layer by periodic step changes, so that stacking faults are generated in the mixed defect suppression layer to form a physical barrier for capturing and annihilating dislocations, thereby reducing the dislocation density of the GaN layer and improving the crystal quality.

[0061] In one embodiment, a mixed defect suppression layer is formed above a substrate using an aluminum source, a yttrium source, and a nitrogen source. The method further includes adjusting the flow rate and temperature of the yttrium source to control the mixing ratio of cubic and hexagonal phases in the mixed defect suppression layer. By controlling the flow rate of the yttrium source and the growth temperature, the Y composition in the YAlN mixed defect suppression layer is adjusted, while simultaneously adjusting the mixing ratio of the hexagonal and cubic phases in the mixed defect suppression layer, thereby generating dislocation lines within the mixed defect suppression layer that block stacking faults from extending into the GaN layer.

[0062] In one embodiment, during the reaction to generate the mixed defect suppression layer, the flow rates of the aluminum source and the nitrogen source are determined based on the V / III ratio during the growth of the mixed defect suppression layer.

[0063] In this embodiment, the V / III ratio, or 5 / 3 ratio, refers to the ratio of Group V precursor to Group III precursor during the epitaxial growth of a Group III-V compound semiconductor. Increasing or decreasing the V / III ratio alters the proportions of the components in the mixed defect suppression layer, introducing excess defects and reducing crystal quality. By precisely controlling the V / III ratio during the growth of the mixed defect suppression layer, the flow rates of the aluminum and nitrogen sources are precisely controlled, ensuring that the V / III ratio remains within a preset range during growth, thereby improving the growth quality of the mixed defect suppression layer.

[0064] In one embodiment, during the reaction to generate the mixed defect suppression layer, the flow rate of the aluminum source is 300 to 320 sccm, and the flow rate of the nitrogen source is 8000 sccm.

[0065] In one embodiment, step 220 includes:

[0066] Trimethylgallium and a nitrogen source are introduced into the reaction chamber to epitaxially generate a gallium nitride layer above the mixed defect suppression layer.

[0067] In this embodiment, trimethylgallium (TMGa) is used to provide gallium (Ga) for the growth of the GaN layer. During the GaN layer fabrication process, the introduced trimethylgallium is in a gaseous state. It should be noted that in other embodiments, in addition to using trimethylgallium as the source of Ga, other compounds capable of providing Ga can also be used as the source when fabricating the gallium nitride layer.

[0068] In one embodiment, during the epitaxial growth of a gallium nitride (GaN) layer, the flow rates of trimethylgallium (TMG) and the nitrogen source are determined based on the V / III ratio during GaN layer growth. By precisely controlling the V / III ratio during GaN layer growth, the flow rates of TMG and the nitrogen source are ensured to remain within a preset range, thereby improving the growth quality of the GaN layer.

[0069] In one embodiment, during the epitaxial formation of the gallium nitride layer, the flow rate of trimethylgallium is 200 sccm and the flow rate of the nitrogen source is 9000 sccm.

[0070] Figure 5 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application. Figure 5 As shown, the semiconductor structure includes, but is not limited to:

[0071] Substrate;

[0072] A mixed defect suppression layer is disposed above a substrate, wherein the mixed defect suppression layer has a mixed phase structure of cubic and hexagonal phases, and stacking faults are formed at the phase interface between the cubic and hexagonal phases;

[0073] A gallium nitride layer is disposed above the mixed defect suppression layer.

[0074] In this embodiment, the hybrid defect suppression layer not only reduces dislocation density but also significantly improves the crystal quality of the GaN thin film. High-quality crystal materials are crucial for improving the performance of electronic devices, especially in high-frequency communication technologies. For example, GaN-based high electron mobility transistors (HEMTs) utilize an AlGaN / GaN heterojunction structure to form a two-dimensional electron gas (2DEG) at the interface through polarization effects, thereby achieving high electron mobility (up to 2000 cm⁻¹). 2 The GaN thin film exhibits a high dislocation field strength (3.5 MV / cm), far exceeding that of silicon (Si) and silicon carbide (SiC), thus improving switching frequency and efficiency. Furthermore, high-quality GaN thin films also possess high breakdown field strength (3.5 MV / cm) and high switching performance, characteristics that make GaN devices perform exceptionally well in high-frequency, high-voltage applications. Therefore, this embodiment employs a semiconductor structure with a hybrid defect suppression layer, whose gallium nitride layer has low dislocation density and high crystal quality, significantly improving the performance of electronic devices.

[0075] In one embodiment, the thickness of the hybrid defect suppression layer is a first thickness, such that the dislocation density in the gallium nitride layer is below a preset threshold. Exemplarily, the first thickness is 50 to 200 nm.

[0076] In this embodiment, if the thickness of the hybrid defect suppression layer is less than 50 nm, its dislocation blocking performance will decrease, resulting in a dislocation density in the gallium nitride layer exceeding a preset threshold, thus failing to meet device quality requirements. Conversely, if the thickness of the hybrid defect suppression layer is greater than 200 nm, the overall device will be too thick, hindering heat dissipation. This embodiment sets the thickness of the hybrid defect suppression layer within the range of 50-200 nm, adjusting it according to the dislocation density in the gallium nitride layer, thus achieving a hybrid defect suppression layer that is as thin as possible while still meeting dislocation blocking requirements.

[0077] In one embodiment, the thickness of the gallium nitride layer is 1–2 μm.

[0078] It should be noted that the semiconductor structure of this application embodiment is fabricated based on the semiconductor fabrication method provided in the above embodiments. That is, the specific implementation details and beneficial effects of the semiconductor structure of this application embodiment correspond to any or a combination of the above embodiments, and will not be repeated here.

[0079] This application also provides a semiconductor device, which includes at least the semiconductor structure provided in the above embodiments, or a semiconductor structure fabricated using the semiconductor structure fabrication method provided in the above embodiments.

[0080] It should be noted that the semiconductor device in this application includes the semiconductor structure provided in the above embodiments, or includes the semiconductor structure fabricated using the semiconductor fabrication method provided in the above embodiments. That is, the specific implementation details and beneficial effects of the semiconductor device in this application correspond to any or a combination of the above embodiments, and will not be repeated here.

[0081] This application also provides an electronic device, which includes at least the semiconductor structure provided in the above embodiments, or a device fabricated using the semiconductor structure fabrication method provided in the above embodiments.

[0082] It should be noted that the electronic devices in the embodiments of this application include the semiconductor structures provided in the above embodiments, or include devices fabricated using the semiconductor fabrication methods provided in the above embodiments. That is, the specific implementation details and beneficial effects of the electronic devices in the embodiments of this application correspond to any or a combination of the above embodiments, and will not be repeated here.

[0083] The semiconductor structure fabrication method of this application will be described in detail below through an example. It should be understood that the following embodiments are for better illustrative purposes of the semiconductor structure fabrication method of this application and are not intended to limit the scope of the application.

[0084] Figure 6 This is a schematic diagram illustrating the fabrication of a semiconductor structure provided as an example in this application. For example... Figure 6 As shown, this example uses a YAlN hybrid defect suppression layer:

[0085] Step 1: In the low-pressure environment of MOCVD, the double-polished 4H-SiC substrate is first placed in the reaction chamber, then hydrogen gas is introduced and the temperature of the reaction chamber is gradually increased to 1100 degrees Celsius. During this process, the pressure of the reaction chamber is maintained at 40-50 Torr for 1 minute to clean the substrate surface.

[0086] In some examples, surface cleaning of the substrate is required before step 1. The method for surface cleaning of the SiC substrate is as follows: first, the substrate is placed in an acetone solution, followed by ultrasonic cleaning of the substrate in the acetone solution for 5 minutes; then, the substrate is placed in anhydrous ethanol solution, followed by ultrasonic cleaning of the substrate in the anhydrous ethanol solution for 5 minutes; finally, the substrate is placed in deionized water, followed by ultrasonic cleaning of the substrate in the deionized water for 5 minutes. The purpose of surface cleaning of the substrate is to remove inorganic compounds from the substrate surface to avoid adverse effects on the growth process.

[0087] Step 2: Epitaxially grow a YAlN mixed defect suppression layer on a SiC substrate. TMAl and (MCp)3Y are used as the aluminum and yttrium sources, respectively, with ammonia as the nitrogen source and hydrogen as the carrier gas. The reaction chamber temperature is controlled at 900-1100℃, and the valves for TMAl, (MCp)3Y, and ammonia are opened. The TMAl source flow rate is controlled at 300-320 sccm, and the ammonia flow rate is set to 8000 sccm. This forms a YAlN mixed defect suppression layer with a thickness of 50-200 nm on the SiC substrate. By controlling the yttrium source flow rate and growth temperature, the Y composition in the YAlN mixed defect suppression layer is adjusted, and the mixing ratio of hexagonal and cubic phases in the defect suppression layer is also adjusted, thereby generating stacking faults within the mixed defect suppression layer to block dislocation lines extending into GaN.

[0088] In some examples, the process of growing the YAlN hybrid defect suppression layer in step 2 includes:

[0089] Step 2.1: Under a TMAl atmosphere, an aluminum thin film is pre-deposited on the SiC substrate using the MOCVD process. Specifically, the SiC substrate is placed in the MOCVD reaction chamber, and the temperature is raised to 1085-1120℃. The TMAl gas path is opened, and the TMAl flow rate is adjusted to 20 sccm to form an aluminum thin film on the SiC substrate.

[0090] Step 2.2: After forming an aluminum film on the SiC substrate, the TMAl flow rate is adjusted, and (MCp)3Y is introduced simultaneously with NH3 to react with the aluminum film, thereby generating a YAlN mixed defect suppression layer above the SiC substrate. Subsequently, by periodically adjusting the growth temperature and reaction chamber pressure, stacking faults are generated in the YAlN mixed defect suppression layer through precise control of the growth conditions. Specifically, the reaction chamber temperature is lowered to 900-920℃, while the TMAl, (MCp)3Y, and NH3 gas paths are opened. The TMAl flow rate is adjusted to 300-320 sccm, and the NH3 flow rate is 8000 sccm. TMAl is introduced to grow the YAlN defect suppression layer, and then the reaction chamber temperature and pressure are increased, with the temperature rising to 1050℃ and the pressure increasing from 50 mbar to 70 mbar. To avoid irreversible phase transitions in the YAlN mixed defect suppression layer, the adjustment time for the reaction chamber temperature and pressure is short, controlled within 30 seconds. Subsequently, the temperature and pressure of the reaction chamber were reduced to their original levels, and the temperature and pressure were continuously adjusted until the YAlN mixed defect suppression layer was fully grown. The temperature increase from 900℃ to 1050℃ constituted one cyclical step change.

[0091] Step 3: Epitaxially grow a GaN layer above the YAlN defect suppression layer. The GaN growth temperature is 1150℃ and the thickness is 2μm.

[0092] In some examples, step 3, the epitaxial growth of the GaN layer, includes:

[0093] The reaction chamber temperature was raised to 1150℃, the TMAl source and (MCp)3Y source were turned off, and the flow rates of TMGa and NH3 were adjusted to 200 sccm and 9000 sccm, respectively, to form a GaN layer epitaxially with a thickness of 1-2 μm on the YAlN mixed defect suppression layer.

[0094] The above example incorporates a mixed defect suppression layer with a cubic and hexagonal phase structure between the substrate and the gallium nitride (GaN) layer. Replacing the AlN nucleation layer in related technologies with this mixed defect suppression layer addresses the issue that during the fabrication process, the atomic stacking order leads to a mismatch in the lattice parameters between the cubic and hexagonal phases, resulting in stacking faults at the phase interface. These stacking faults are perpendicular to the dislocation line growth direction, forming a physical barrier. When a dislocation line encounters a stacking fault, it is captured and annihilated, reducing the dislocation density in the GaN layer. Furthermore, the mixed defect suppression layer reduces the surface roughness of the GaN film, further improving the crystal quality of the GaN layer and enhancing the performance and reliability of the semiconductor structure. Moreover, compared to related technologies such as ELOG, which require additional processes and impurities, the semiconductor structure fabrication method provided in this application does not introduce additional processes or other materials that could cause impurities.

[0095] Furthermore, the addition of a hybrid defect suppression layer not only reduces dislocation density but also significantly improves the crystal quality of GaN thin films. High-quality crystal materials are crucial for enhancing the performance of electronic devices, especially in high-frequency communication technologies. For example, GaN-based high electron mobility transistors (HEMTs) utilize an AlGaN / GaN heterojunction structure to form a two-dimensional electron gas (2DEG) at the interface through polarization effects, thereby achieving high electron mobility (up to 2000 cm⁻¹). 2 The GaN film exhibits a high dislocation density (3.5 MV / cm) far exceeding that of silicon (Si) and silicon carbide (SiC), thus improving switching frequency and efficiency. Furthermore, high-quality GaN films also possess high breakdown field strength (3.5 MV / cm) and high switching performance, making GaN devices perform exceptionally well in high-frequency, high-voltage applications. Therefore, the above example utilizes a hybrid defect suppression layer to optimize the growth of the gallium nitride (GaN) layer, reducing the dislocation density and improving the crystal quality of the GaN layer, thereby significantly enhancing the performance of electronic devices.

[0096] The above description, with reference to the accompanying drawings, illustrates some embodiments of this application, but does not limit the scope of this application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of this application shall be within the scope of this application.

Claims

1. A method for fabricating a semiconductor structure, the method comprising: A mixed defect suppression layer is formed above the substrate, wherein the mixed defect suppression layer is a mixed phase structure of cubic and hexagonal phases, and stacking faults are formed at the phase interface between the cubic phase and the hexagonal phase; A gallium nitride layer is formed above the hybrid defect suppression layer.

2. The semiconductor structure fabrication method according to claim 1, characterized in that, The formation of the mixed defect suppression layer above the substrate includes: The mixed defect suppression layer is formed on the substrate using an aluminum source, a yttrium source, and a nitrogen source.

3. The semiconductor structure fabrication method according to claim 2, characterized in that, The method of forming the mixed defect suppression layer on the substrate using an aluminum source, a yttrium source, and a nitrogen source includes: The aluminum source is introduced into the reaction chamber, and an aluminum film is formed on the substrate located in the reaction chamber using a metal-organic chemical vapor deposition process; The flow rate of the aluminum source is adjusted, and the yttrium source and nitrogen source are simultaneously introduced, so that the yttrium source and the nitrogen source react with the aluminum film to generate the mixed defect suppression layer; Adjusting the periodic step changes in temperature and pressure controls the formation of stacking faults in the hybrid defect suppression layer at the phase interface.

4. The semiconductor structure fabrication method according to claim 3, characterized in that, The method of forming the mixed defect suppression layer on the substrate using an aluminum source, a yttrium source, and a nitrogen source further includes: Adjust the flow rate and temperature of the yttrium source to control the mixing ratio of the cubic and hexagonal phases in the mixed defect suppression layer.

5. The semiconductor structure fabrication method according to claim 3, characterized in that, During the reaction to generate the mixed defect suppression layer, the flow rates of the aluminum source and the nitrogen source are determined based on the V / III ratio during the growth of the mixed defect suppression layer.

6. In the semiconductor structure fabrication method according to claim 5, when the mixed defect suppression layer is generated by reaction, the flow rate of the aluminum source is 300 to 320 sccm, and the flow rate of the nitrogen source is 8000 sccm.

7. The method for fabricating a semiconductor structure according to any one of claims 2 to 6, characterized in that, The aluminum source is trimethylaluminum, the yttrium source is tris(methylcyclopentadienyl)yttrium, and the nitrogen source is ammonia.

8. The semiconductor structure fabrication method according to claim 2, characterized in that, The formation of a gallium nitride layer above the hybrid defect suppression layer includes: Trimethylgallium and the nitrogen source are introduced into the reaction chamber to epitaxially generate the gallium nitride layer above the mixed defect suppression layer.

9. The semiconductor structure fabrication method according to claim 8, characterized in that, During the epitaxial formation of the gallium nitride layer, the flow rate of the trimethylgallium and the flow rate of the nitrogen source are determined based on the V / III ratio during the growth of the gallium nitride layer.

10. The semiconductor structure fabrication method according to claim 9, characterized in that, During the epitaxial formation of the gallium nitride layer, the flow rate of the trimethylgallium source is 200 sccm, and the flow rate of the nitrogen source is 9000 sccm.

11. A semiconductor structure, characterized in that, include: Substrate; A mixed defect suppression layer is disposed above the substrate, wherein the mixed defect suppression layer has a mixed phase structure of cubic and hexagonal phases, and stacking faults are formed at the phase interface between the cubic phase and the hexagonal phase; A gallium nitride layer is disposed above the hybrid defect suppression layer.

12. The semiconductor structure according to claim 11, characterized in that, The thickness of the hybrid defect suppression layer is a first thickness, so that the dislocation density in the gallium nitride layer is lower than a preset threshold.

13. The semiconductor structure according to claim 12, characterized in that, The first thickness is 50 to 200 nm.

14. The semiconductor structure according to claim 11, characterized in that, The thickness of the gallium nitride layer is 1–2 μm.

15. An electronic device, characterized in that, include: The semiconductor structure as described in any one of claims 11 to 14.

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