reduction of interface resistance between silicon nanosheets and highly doped source / drain regions

Abstract

Methods and systems are disclosed for silicon nanosheet etch-back using epitaxial deposition methods in the same reaction chamber under the same process conditions to reduce source / drain and silicon nanosheet interface resistance. The etch-back can be a Cl2 thermal etch-back.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor processing methods and systems, and to the field of device and integrated circuit manufacturing. More specifically, this disclosure generally relates to reducing the interface resistance between silicon nanosheets and highly doped source / drain regions in nanosheet devices. Background Technology

[0002] Scaling of semiconductor devices has led to significant improvements in the speed and density of integrated circuits. However, current fabrication methods for stacked nanosheets can exhibit interfacial resistance in the region between the silicon nanosheets and the highly doped source / drain regions of nanosheet devices. This interfacial resistance can degrade performance and reduce the maximum drive current, which in turn reduces the overall power efficiency in the finished nanosheet devices.

[0003] For example, Figure 1 A silicon nanosheet structure 105 is shown. The silicon nanosheet regions 107 between the spacers 109 within the silicon nanosheets experience minimal (if any) field effects in the finished transistor device. This creates a potential resistance bottleneck between the highly doped source / drain regions 111 and the gate control region 113.

[0004] Current methods for reducing interface resistance in nanosheet devices (such as PMOS devices) require high-temperature spike annealing, which increases the number of process steps required to fabricate logic devices. Therefore, there is a need for improved methods and systems for reducing interface resistance in the region between the silicon nanosheet and the highly doped source / drain regions of nanosheet devices.

[0005] Any discussion set forth in this section (including discussions of problems and solutions) is included in this disclosure for the purpose of providing background information and should not be construed as an admission that any or all of the discussions were known at the time of making this invention or otherwise constitute prior art. Summary of the Invention

[0006] This invention provides a simplified overview of some concepts, which will be described in further detail below. This invention is not intended to require the identification of key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] Various embodiments of this disclosure relate to silicon nanosheet etching back to reduce source / drain and silicon nanosheet interface resistance using an epitaxial deposition method under the same process conditions in the same reaction chamber. Embodiments of this disclosure relate to structures and devices formed using this method, and to apparatus for performing the method and / or for forming the structures and / or devices.

[0008] According to an example of this disclosure, a method for reducing the interfacial resistance between a silicon nanosheet layer of a substrate and doped source / drain regions is provided. An exemplary method includes providing a substrate in a reaction chamber, performing an etching process in the reaction chamber to form silicon nanosheet recesses in the silicon nanosheet layer, and performing first and second vapor deposition processes in the reaction chamber to deposit a first dopant into the formed recesses and a second dopant into the source / drain regions of the nanosheet device. The second dopant may be in contact with the first dopant. The substrate may include a stack comprising a silicon nanosheet layer and a SiGe layer.

[0009] According to examples of this disclosure, the formed silicon nanosheet recess can be between about 0 and 10 nm, or between about 1 and 7 nm. The width of the deposited first doped material can be between about 1 and 10 nm. The width of the deposited first doped material can be larger than the formed silicon nanosheet recess.

[0010] According to another example of this disclosure, the temperature inside the reaction chamber may be less than 600°C or between about 200°C and 450°C or between about 275°C and 400°C. The pressure inside the reaction chamber may be between 1 and 100 Torr or between about 10 Torr and about 70 Torr or between about 30 Torr and about 60 Torr.

[0011] In another embodiment of this disclosure, the etching process may include an etchant selected from Cl2, HCl, Br2, HI, HF, F2, and I2. In one example, the etchant flow rate of Cl2 may be between 1 and 2000 sccm, or between about 1 and 460 sccm, or between 1 and 75 sccm. In embodiments, the deposited first doped material may include Si:B, Si:P, or SiGe:B.

[0012] This disclosure further describes a device that can be fabricated by: providing a substrate in a reaction chamber, performing an etching process in the reaction chamber to form silicon nanosheet recesses in a silicon nanosheet layer, and performing first and second vapor depositions in the reaction chamber to deposit a first dopant into the formed recesses and a second dopant into the source / drain regions of the nanosheet device. The second dopant may be in contact with the first dopant. The substrate may comprise a stack comprising a silicon nanosheet layer and a SiGe layer.

[0013] According to other embodiments of this disclosure, the reaction chamber may be adapted to perform the methods according to this disclosure.

[0014] For the purpose of summarizing the invention and its advantages relative to the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all of these objects or advantages may necessarily be achieved according to any particular embodiment of the invention. Therefore, for example, those skilled in the art will recognize that the invention may be embodied or implemented in a manner that achieves or optimizes one or more advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0015] All these embodiments are intended to fall within the scope of the invention disclosed herein. Those skilled in the art will readily appreciate these and other embodiments from the following detailed description of certain embodiments with reference to the accompanying drawings; however, the invention is not limited to any particular embodiment disclosed. Attached Figure Description

[0016] To facilitate identification of any particular element or action being discussed, one or more of the most significant digits in the reference numerals refer to the drawing number in which the element was first introduced.

[0017] Embodiments of this disclosure can be more fully understood when considered in conjunction with the following illustrative drawings, which illustrate source / drain formation with reduced interface resistance during the epitaxial step, by referring to the detailed description and claims.

[0018] Figure 1 A silicon nanosheet structure during a source / drain epitaxial step is shown according to one or more embodiments of the present disclosure.

[0019] Figure 2 A controlled etch-back and deposition process according to one or more embodiments of the present disclosure is illustrated.

[0020] Figures 3A to 3D Source / drain deposition profiles according to one or more embodiments of the present disclosure are shown.

[0021] Figures 4A to 4C A gate-all-around device structure according to one or more embodiments of the present disclosure is shown.

[0022] Figures 5A to 5C A complementary field-effect transistor (CFET) device structure according to one or more embodiments of the present disclosure is shown.

[0023] Figure 6 A method for reducing interface resistance according to one or more embodiments of the present disclosure is shown.

[0024] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements to aid in understanding the embodiments shown in this disclosure. Detailed Implementation

[0025] The following description of exemplary embodiments of the methods and compositions is merely illustrative and for purposes of explanation only. The following description is not intended to limit the scope of this disclosure or the claims. Furthermore, the description of multiple embodiments having indicated features or steps is not intended to exclude other embodiments having additional features or steps or other embodiments including different combinations of said features or steps.

[0026] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or films can be formed according to the methods of embodiments of this disclosure. A substrate may comprise a bulk material, such as silicon (e.g., single-crystal silicon), other group IV materials (e.g., germanium), or other semiconductor materials (e.g., group II-VI or III-V semiconductor materials), and may comprise one or more layers overlying or underlying the bulk material. A substrate may include various topologies, such as gaps, including spaces between recesses, lines, trenches, or protrusions (e.g., fins) formed within or on at least a portion of the layers of the substrate. For example, a substrate may comprise a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material. Furthermore, the term "substrate" can refer to any one or more underlying materials on which devices, circuits, or films can be used or on which they can be formed. A "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous. A "substrate" can be in any form, such as powder, plate, or workpiece. Plate-type substrates can include wafers of various shapes and sizes. The substrate can be made of materials such as silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide.

[0027] The continuous substrate may extend beyond the boundary of the processing chamber where the deposition process takes place and may move through the processing chamber, allowing the process to continue until the end of the substrate is reached. The continuous substrate can be supplied from a continuous substrate supply system that allows the continuous substrate to be manufactured and output in any suitable form. Non-limiting examples of continuous substrates may include sheets, nonwoven films, rolls, foils, fiber webs, flexible materials, bundles of continuous filaments or fibers (i.e., ceramic fibers or polymer fibers). The continuous substrate may also include a carrier or sheet on which a non-continuous substrate is mounted.

[0028] As used herein, the term "layer" can refer to any continuous or discontinuous structure and material. For example, a layer can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers or partial or complete atomic layers or atomic and / or molecular clusters. A layer can include a material or layer with pinholes, which can be at least partially continuous.

[0029] The term “atomic layer deposition” can refer to a vapor-phase deposition process in which deposition cycles, typically multiple consecutive, are performed in a processing chamber. As used herein, the term atomic layer deposition is also intended to include processes specified by related terms such as chemical vapor deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy when performed using alternating pulses of precursor / reactive gases and purge gases (e.g., inert carrier gases).

[0030] Typically, for an ALD process, during each deposition cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the deposition surface (e.g., a substrate surface that may include previously deposited material from a previous ALD cycle or other materials) and forms a monolayer or sub-monolayer of material that is not readily reactive with additional precursors (i.e., a self-limiting reaction). Subsequently, in some cases, a reactant (e.g., another precursor or reactive gas) may be introduced into the processing chamber to convert the chemisorbed precursor into the desired material on the deposition surface. The reactant is capable of further reacting with the precursor. During one or more deposition cycles, such as during each step of each cycle, a purging step may be used to remove any excess precursor from the processing chamber and / or any excess reactant and / or reaction byproducts from the reaction chamber.

[0031] In one aspect of this disclosure, the precursor may include silane, silane, propane, butane, dichlorosilane, pentachlorosilane, monoiodosilane, diiodosilane, tetrabromosilane, any other halosilane, or higher silane molecules. In one embodiment, boron halide and boron hydride precursors may also be used. In one embodiment, the DCS flow rate may be in the range of 20 to 1000 sccm, the silane flow rate may be in the range of 1 to 1600 sccm, the 1% B₂H₆ / H₂ flow rate may be in the range of 1 to 1000 sccm, the x% Si₂Cl₅H₁ / H₂ flow rate may be in the range of 20 to 1000 sccm, and the Si₂Cl₅H₁ container temperature may be in the range of 5 to 60 degrees Celsius. In another embodiment, the silane flow rate may be about 18 sccm, the 1% B₂H₆ / H₂ flow rate may be about 12 sccm, and the Si₂Cl₅H₁ container temperature may be about 45 degrees Celsius.

[0032] As used herein, the term “chemical vapor deposition” can refer to any process in which a substrate is exposed to one or more volatile precursors that react and / or decompose on the substrate surface to produce the desired deposition.

[0033] As used herein, the term "gate-all-around device" can refer to a device comprising conductive material surrounding a semiconductor channel region. As used herein, the term "gate-all-around device" can also refer to various device architectures such as nanosheet devices, fork-plate devices, vertical FETs, CFETs, etc.

[0034] Furthermore, in this disclosure, any two numbers of a variable may constitute a feasible range of the variable, and any range indicated may include or exclude endpoints. Additionally, any value of the indicated variable (whether or not it is indicated by “about”) may refer to an exact value or an approximate value and include equivalents, and may refer to an average, median, representative value, multi-value, etc. Furthermore, in this disclosure, the terms “comprising,” “consisting of,” and “having” independently mean “generally or broadly comprising,” “comprising,” “substantially composed of,” or “consisting of” in some embodiments. It should be understood that when a composition, method, device, etc., is referred to as comprising certain features, it means that it includes those features, and it does not necessarily exclude the presence of other features, provided they do not render the claims unfeasible. Nevertheless, the word “comprising” includes the meaning of “consisting of,” i.e., when the composition, method, device, etc., in question comprises only the listed features, components, and / or steps, and does not contain any other features, components, steps, etc. According to another aspect, substantially identical may mean within ±5%, ±1%, ±0.5%, for example, atoms, volume, length, etc., depending on the context.

[0035] In this disclosure, the meaning of any definition does not necessarily exclude the common and customary meaning in some embodiments.

[0036] As used herein, the term "carrier gas" can refer to a gas supplied to the reaction chamber along with one or more precursors and / or etchants. For example, a carrier gas may be supplied to the reaction chamber along with one or more precursors and / or etchants as used herein. Exemplary carrier gases include N2, H2, and rare gases such as He, Ne, Kr, Ar, and Xe. As a specific example, the carrier gas may include one or more of nitrogen (N2), argon (Ar), and helium (He) in any combination. For example, in various embodiments of this disclosure, an N2 carrier gas with a flow rate ranging from 5 to 30 slm may be utilized.

[0037] Unlike carrier gases, purge gases can be supplied to the reaction chamber alone (i.e., not with one or more precursors). Nevertheless, gases commonly used as carrier gases can also be used as purge gases, even within the same process. For example, in a cyclic deposition-etch process, N2 used as a carrier gas can be supplied with one or more precursors during the deposition pulse, and N2 used as a purge gas can be used to separate the deposition and etching pulses. Of course, N2 can be replaced by another suitable inert gas (e.g., H2) or rare gases (e.g., He, Ne, Kr, Ar, and Xe). Therefore, the manner in which a gas is supplied to the reaction chamber determines whether it is used as a purge gas or a carrier gas in a given situation. Thus, as used herein, the term "purge" can refer to the process of supplying an inert or substantially inert gas to the reaction chamber between two potentially reactive gas pulses. For example, a purge, for example using nitrogen, can be provided between a precursor pulse and an etchant pulse to avoid or at least minimize gas-phase reactions between the precursor and the etchant. It should be understood that purging can be affected temporally, spatially, or both. For example, in the case of time-purge, a purge step can be used, for instance, in the order of providing a first precursor to the reaction chamber, providing a purge gas to the reaction chamber, and providing an etchant to the reaction chamber, wherein the substrate on which the deposited layer is deposited does not move. In the case of spatial purge, the purge step can take the form of, for instance, moving the substrate from a first position (e.g., continuously) supplying the first precursor through a purge gas curtain to a second position (e.g., continuously) supplying the second precursor or etchant.

[0038] As described in more detail below, the various steps of the exemplary methods described herein can be performed in the same reaction chamber. In one embodiment, the reaction chamber may include an epitaxial reactor.

[0039] In this disclosure, any two numbers of a variable may constitute a feasible range of the variable, and any range indicated may include or exclude endpoints. Furthermore, any value of the indicated variable (whether or not it is indicated by “about”) may refer to an exact value or an approximate value and includes equivalents, and in some embodiments may refer to an average, median, representative value, multi-value, etc. Additionally, in this disclosure, the terms “comprising,” “consisting of,” and “having” may, in some embodiments, independently mean “generally or broadly comprising,” “including,” “substantially consisting of,” or “consisting of.” The meaning of any definition in this disclosure does not necessarily exclude the common and customary meaning in some embodiments. In some cases, percentages indicated herein may be relative or absolute percentages.

[0040] Numerous example materials are given throughout the embodiments of this disclosure. It should be noted that the chemical formulas given for each example material should not be interpreted as limiting, and the non-limiting example materials given should not be limited by the given example stoichiometry.

[0041] In this specification, it will be understood that the terms "on" or "above" may be used to describe relative positional relationships. Another element, film, or layer may be directly on the mentioned layer, or another layer (intermediate layer) or element may be inserted between them, or a layer may be disposed on the mentioned layer but not completely cover the surface of the mentioned layer. Therefore, unless the term "directly" is used alone, the terms "on" or "above" will be interpreted as relative concepts. Similarly, it will be understood that the terms "below," "under," or "beneath" will be interpreted as relative concepts.

[0042] A method and system for etching back silicon nanosheets using an epitaxial deposition method in the same reaction chamber under the same process conditions to reduce the source / drain and silicon nanosheet interface resistance are disclosed. Turning now to the accompanying drawings, Figure 2 Controlled etchback of silicon nanosheets is illustrated to reduce the interfacial resistance between the silicon nanosheets and the doped source / drain regions of the nanosheet device. In one embodiment, the etchback can be Cl2 thermal etchback.

[0043] exist Figure 2 In this embodiment, a substrate 202 is provided within a reaction chamber. In embodiments of this disclosure, the reaction chamber can be brought to the desired temperature and / or pressure to perform all steps of the etch-back and deposition processes. For example, during the etch-back and deposition processes, the reaction chamber can be maintained at a temperature below 600°F, or between about 200°F and 450°F, or between about 275°F and 400°F. During the etch-back and deposition processes, the reaction chamber pressure can be maintained between 1 and 100 Torr, or between about 10 Torr and about 70 Torr, or between about 30 Torr and about 60 Torr.

[0044] The substrate can be pre-cleaned to remove oxides and carbon from the substrate surface. The substrate 202 may include at least one silicon (Si) and silicon-germanium (SiGe) stack 204. The Si and SiGe stack 204 may include a number of silicon nanosheet layers and SiGe layers.

[0045] The Si, SiGe stack 204 may include spacers 206 formed within the silicon nanosheets. The outer walls of the stack 204 may include a silicon nitride layer 208, which may potentially improve stack integrity and facilitate later downstream removal of the sacrificial SiGe layer, allowing replacement with a metal gate stack. The regions between the silicon nanosheet spacers 206 can experience minimal field effects in the finished nanosheet device. The high potential resistance between the silicon spacers 206 may prevent the gate from acceptably controlling the resulting nanosheet device.

[0046] like Figure 2As shown, an etching process 210 is performed in a reaction chamber. The etching process is performed on at least a portion of the silicon nanosheets to form silicon nanosheet recesses in the silicon nanosheet layer. According to various embodiments of this disclosure, the etching process 210 can use an etchant selected from Cl2, HCl, Br2, HI, HF, F2, and I2. In some exemplary embodiments, any etchant capable of thermally etching silicon can be used. The etchant may preferably be a halogen-based etchant.

[0047] exist Figure 2 In this process, a Cl2 etchant can be used to form the recesses 212 of the silicon nanosheets. The Cl2 etchant flow rate can be between 1 and 2000 sccm, or between approximately 1 and 460 sccm, or between 1 and 75 sccm.

[0048] The formed nanosheet recess 212 may have a length 214 and a width 216, where the length 214 is defined by the thickness of the nanosheet layer, and the width 216 may be between about 0 and 10 nm or between about 1 and 7 nm. In embodiments of this disclosure, the width 216 of the formed nanosheet recess 212 may be a fraction of a nanometer, based on the etching of the nanosheet layer performed. The formed nanosheet recess 212 may include a sidewall surface 218, a top surface 220, and a bottom surface 222.

[0049] like Figure 2 As shown, a first vapor deposition process 223 can be performed in a reaction chamber to selectively deposit a material with a first dopant into the formed silicon nanosheet recess 212. The deposited first dopant 224 may include a SiB deposition layer, which may be highly conductive and provide improved valence state matching. Alternatively, a SiGe:B layer with a low Ge content may be selected for the deposited first dopant 224 in a PMOS device. For NMOS devices, the first dopant 224 may include SiP.

[0050] In embodiments of this disclosure, the first doping can be 1×10 19 and 5×10 21 atoms / cm 3 Between, preferably 1×10 19 Up to 3×10 21 atoms / cm 3 Between, or even more preferably at 1×10 20 Up to 2×10 21 atoms / cm 3 The width of the deposited first doped material can be between approximately 1 and 10 nm. In another exemplary embodiment, the width of the deposited first doped material can be 1 nm. In yet another exemplary embodiment, the width of the first doped material can be greater than the formed silicon nanosheet recess 212.

[0051] Return to Figure 2 A second vapor deposition process 225 can be performed in the reaction chamber to selectively deposit a material having a second dopant 226 to fill the source / drain regions of the substrate, the second doped material being in contact with the first doped material. The second doped material may include SiGe:B, which may be in contact with the first doped material comprising SiB. In some embodiments, the first and second doped materials may be the same material or different materials having the same or different doping. In embodiments of this disclosure, the second doping may be 1 × 10⁻⁶. 17 and 9×10 21 atoms / cm 3 Between, preferably 5×10 20 Up to 6×10 21 atoms / cm 3 Between, or even more preferably at 1×10 21 Up to 5×10 21 atoms / cm 3 .

[0052] Figures 3A to 3D Source / drain deposition profiles according to various embodiments of this disclosure are shown. Figure 3A In this process, a second vapor deposition using a second doped material 304 is used to fill the source / drain region of the substrate 302, with the second doped material in contact with the first doped material. Figure 3A In this process, the second doped material may include SiGe:B, which may contact the first doped material, including SiB3O6. In some embodiments, the first and second doped materials may be the same material or different materials with the same or different doping. In some embodiments, such as for CFET and GAA devices, the source / drain may also be contacted from the back side of the wafer.

[0053] Figure 3B The selective deposition of both 1) a high-content SiGe:B Ge layer and 2) a low-content SiGe:B Ge layer is shown to fill the source / drain regions of substrate 310. For example, as Figure 3B As shown, the first region 312 of the source / drain region may include a low-Ge content SiGe:B layer for filling the first region 312 of the source / drain region. The low Ge content may be between 0% and 80%, more preferably between 0% and 50%, and most preferably between 0% and 35%.

[0054] The second region 314 of the source / drain region may include a high-Ge-content SiGe:B layer for filling the second region 314 of the source / drain region. The high Ge content may be between 0% and 100%, more preferably between 20% and 90%, and most preferably between 60% and 90%.

[0055] Figure 3C A continuously graded Ge content of SiGe:B for the source / drain material used in selective deposition of substrate 322 is shown. In embodiments of this disclosure, the Ge content can be continuously and gradually reduced to the Ge content level of silicon nanosheets. The continuously graded Ge content 324 of SiGe:B can help overcome any energy barriers caused by valence band differences.

[0056] Figure 3D The diagram shows a continuously gradient Ge content 324 in SiGe:B and a SiB cap 332 for the source / drain material used in the selective deposition of the substrate 334.

[0057] Figures 4A to 4C A gate-all-around (GAA) device structure according to one or more embodiments of the present disclosure is illustrated. Figure 4A In the reaction chamber, a substrate 402 is provided. The substrate may be pre-cleaned to remove oxides and carbon from its surface. The substrate 402 may include at least one silicon (Si) or silicon-germanium (SiGe) stack 404. The Si or SiGe stack 404 may include square SiN internal spacers 406. In one embodiment, the internal spacers 406 may include SiCN, SiOCN, and / or other dielectric materials.

[0058] Figure 4B This illustrates the addition of dielectric 414 in the sub-fin region to prevent damage from Cl2 etching. The dielectric may include SiO2. x SiN, AlO x Materials such as TiN can be used. In another embodiment, other protective dielectric or non-dielectric materials, such as Si and SiGe, can also be used. In one embodiment, substrate 412 may be reverse-doped to prevent parasitic current leakage paths in the finished device, which may degrade performance. In one embodiment, for NMOS devices, the Si substrate may be p-type doped, and for PMOS devices, the substrate sub-fins may be n-type doped.

[0059] Figure 4C Additional silicon nanosheets, SiGe layers 420, are shown that can be used in a variety of gate-all-around devices.

[0060] Figures 5A to 5C A complementary field-effect transistor (CFET) device structure according to one or more embodiments of the present disclosure is shown. Figure 5A In the middle, the bottom silicon nanosheet 502 is exposed, while the top silicon nanosheet 504 is covered. Figure 5B In this process, dielectric 510 has been added to the sub-fin region of substrate 512. Figure 5C In the middle, the top silicon nanosheet 520 is exposed, and source / drain deposition has occurred in the bottom silicon nanosheet region 525.

[0061] Figure 6 A method for reducing interface resistance according to embodiments of the present disclosure is illustrated. In one aspect of the disclosure, the method and system use a single reaction chamber to reduce the interface resistance between the source / drain of a nanosheet device and the silicon nanosheet channel during an epitaxial process (EPI).

[0062] In step 602, a substrate is provided in the reaction chamber. The substrate comprises at least one stack, which includes a silicon nanosheet layer and a SiGe layer.

[0063] An etching process is performed in a reaction chamber on at least a portion of the silicon nanosheet layer to form silicon nanosheet recesses in the silicon nanosheet layer, as shown in step 604. In step 606, a first vapor deposition process is performed in the reaction chamber to selectively deposit a material having a first dopant into the formed silicon nanosheet recesses. In step 608, a second vapor deposition process is performed in the reaction chamber to selectively deposit a material having a second dopant to fill the source / drain regions of the substrate, the second dopant contacting the first dopant. In embodiments of this disclosure, each of process steps 602 through 608 may be performed in the same reaction chamber under the same process conditions.

[0064] In embodiments of this disclosure, when using Figure 6 After reducing the interface resistance as outlined in the steps described, a graph of the maximum drive current (ID, SAT) versus gate voltage (VG) of the finished device can be generated. The generated graph illustrates that if silicon nanosheets can be etched beneath the silicon nitride spacers to form silicon nanosheet recesses, and these recesses can be doped with a SiB layer, the maximum drive current can be increased. The graph also shows that the width of the formed recessed channel should not be too large because the doped material deposited in the recess should not contact the gate of the finished nanosheet device; otherwise, a short-channel effect may occur, potentially preventing the finished nanosheet device from turning off.

[0065] For the purpose of summarizing the invention and its advantages over the prior art, certain objects and advantages of the invention have been described above. However, it should be understood that not all of these objects or advantages must be achieved according to any particular embodiment of the invention. Therefore, for example, those skilled in the art will recognize that the invention may be embodied or performed in a manner that achieves or optimizes one or more advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0066] All these embodiments are intended to fall within the scope of the invention disclosed herein. Those skilled in the art will readily appreciate these and other embodiments from the following detailed description of certain embodiments with reference to the accompanying drawings; however, the invention is not limited to any particular embodiment disclosed.

Claims

1. A method for reducing the interface resistance between a silicon nanosheet layer on a substrate and a doped source / drain region, the method comprising: A substrate is provided in the reaction chamber, the substrate comprising a stack of silicon nanosheet layers and SiGe layers; An etching process is performed on at least a portion of a silicon nanosheet layer in a reaction chamber to form silicon nanosheet recesses in the silicon nanosheet layer; A first vapor deposition process is performed in the reaction chamber to selectively deposit the material with the first doping onto the formed silicon nanosheet recesses; as well as A second vapor deposition process is performed in the reaction chamber to selectively deposit a material with a second dopant to fill the source / drain region of the substrate, the second doped material being in contact with the first doped material.

2. The method according to claim 1, wherein, The resulting silicon nanosheet recesses are between approximately 0 and 10 nm or between approximately 1 and 7 nm.

3. The method according to claim 1, wherein, The width of the first doped material deposited is between approximately 1 and 10 nm.

4. The method according to claim 1, wherein, The width of the first doped material deposited is 1 nm.

5. The method according to claim 2, wherein, The width of the first doped material deposited is greater than the recess of the formed silicon nanosheet.

6. The method according to claim 1, wherein, The temperature inside the reaction chamber is less than 600°C or between about 200°C and 450°C, or between about 275°C and 400°C.

7. The method according to claim 1, wherein, The pressure in the reaction chamber is between 1 and 100 Torr, or between about 10 Torr and about 70 Torr, or between about 30 Torr and about 60 Torr.

8. The method according to claim 1, wherein, The steps involved in performing the etching process include providing an etchant selected from Cl2, HCl, Br2, HI, HF, F2, and I2.

9. The method according to claim 8, wherein, The etchant contains Cl2.

10. The method according to claim 9, wherein, The etchant flow rate of Cl2 is between 1 and 2000 sccm, or between approximately 1 and 460 sccm, or between 1 and 75 sccm.

11. The method according to claim 1, wherein, The first doped material deposited includes SiB, SiP, or SiGe:B.

12. The method according to claim 1, wherein, The second doped material deposited to fill the source / drain region includes any doped material consisting of Si or SiGe (Si1Ge1-x), wherein the dopant may include P-type (hole) (B, Ga, Al) or N-type (electron donor) (P, Ab, As, Sb).

13. The method according to claim 1, wherein, The second doped material used to fill the source / drain regions includes SiGe:B.

14. The method according to claim 1, wherein, The source / drain region includes a first region and a second region.

15. The method according to claim 14, wherein, The first region of the source / drain region includes SiGe:B with a low Ge content used to fill the first region of the source / drain region.

16. The method of claim 14, wherein, The second region of the source / drain region includes SiGe:B with a high Ge content used to fill the second region of the source / drain region.

17. The method of claim 14, wherein, The Ge content of SiGe:B used to fill the first and second source / drain regions includes a continuously varying Ge content of SiGe:B in the first and second source / drain regions.

18. The method according to claim 17, wherein, The source / drain region includes a SiB layer on top of the source / drain region to terminate growth.

19. A device manufactured by performing the following steps: A substrate is provided in the reaction chamber, the substrate comprising a stack of silicon nanosheet layers and SiGe layers; An etching process is performed on at least a portion of a silicon nanosheet layer in a reaction chamber to form silicon nanosheet recesses in the silicon nanosheet layer; A first vapor deposition process is performed in the reaction chamber to selectively deposit highly doped material into the recesses of the formed silicon nanosheets; as well as A second vapor deposition process is performed in the reaction chamber to selectively deposit doped material to fill the source / drain regions of the substrate, with the doped material in contact with the highly doped material.

20. The device according to claim 19, wherein, The device includes a gate-all-around device or a complementary field-effect transistor device.

21. A reaction chamber adapted to perform the following steps: A substrate is provided in the reaction chamber, the substrate comprising a stack of silicon nanosheet layers and SiGe layers; An etching process is performed on at least a portion of a silicon nanosheet layer in a reaction chamber to form silicon nanosheet recesses in the silicon nanosheet layer; A first vapor deposition process is performed in the reaction chamber to selectively deposit the material with the first doping onto the formed silicon nanosheet recesses; as well as A second vapor deposition process is performed in the reaction chamber to selectively deposit a second-doped material to fill the source / drain regions of the substrate, with the doped material in contact with the highly doped material.

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