Methods of forming semiconductor structures, semiconductor structures, and semiconductor processing systems

Abstract

A method of forming a semiconductor structure is provided, including depositing a material on a sidewall of a recess in a processing chamber. The method includes providing an etching gas into the processing chamber. The method includes providing a dilution gas into the processing chamber. The method includes providing a plasma into the processing chamber.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor structure, and more particularly to a method for forming a semiconductor structure having uniform recesses on the entire substrate. Background Technology

[0002] Next-generation semiconductor devices require more integrated patterning; therefore, as feature sizes shrink, more gap-filling techniques are needed. Various profile-setting methods exist within gap-filling techniques. Common gap-filling techniques include CVD and ALD processes, and additional suppression and etching techniques are required for feature sizes that are difficult to achieve.

[0003] Among these techniques, etching encompasses both physical etching methods and chemical etching techniques. Chemical etching primarily utilizes etching gases, but the extent of improvement achievable through etching is limited. Applying too much etching gas will not yield the desired profile, as the gas may even etch into deep regions of the pattern. Similarly, applying too little etching gas can achieve an improved profile, but it may degrade etching uniformity within the wafer. This disclosure includes an etching pattern profile and a method for improving uniform etching within a wafer by applying a diluting gas to an existing etching gas.

[0004] Therefore, a method is needed to form a semiconductor structure with uniform recesses throughout the substrate. Summary of the Invention

[0005] Embodiments of this disclosure provide a method for forming a semiconductor structure, comprising: depositing material on the sidewalls of a recess in a processing chamber. The method includes providing an etching gas into the processing chamber. The method includes providing a dilution gas into the processing chamber. The method includes providing plasma into the processing chamber.

[0006] In some embodiments, the etching gas comprises fluorine. In some embodiments, the etching gas comprises at least one of the following: NF3, SF6, F2, ClF3, and CF4. In some embodiments, the etching gas is NF3. In some embodiments, the dilution gas comprises nitrogen. In some embodiments, the dilution gas comprises at least one of the following: N2, NH3, N2H4, and N2O. In some embodiments, the dilution gas is N2.

[0007] In some embodiments, the flow of etching gas and the flow of dilution gas at least overlap. In some embodiments, the flow of etching gas, the flow of dilution gas, and plasma at least overlap. In some embodiments, the duration of the step of providing etching gas to the processing chamber is longer than the duration of the step of providing plasma to the processing chamber. In some embodiments, the duration of the step of providing dilution gas to the processing chamber is longer than the duration of the step of providing plasma to the processing chamber. In some embodiments, the flow rate of dilution gas is greater than or equal to 5000 sccm. In some embodiments, the flow rate of dilution gas is greater than or equal to 7000 sccm. In some embodiments, the method further includes the steps of repeatedly depositing material, providing etching gas, providing dilution gas, and providing plasma.

[0008] In some embodiments, the recess has an aspect ratio greater than or equal to 5:1. In some embodiments, the method further includes providing an inert gas into the processing chamber. In some embodiments, the recess is formed on a substrate.

[0009] Embodiments of this disclosure provide a semiconductor structure formed on a substrate using this method.

[0010] In some embodiments, the lateral conformal properties of the remaining material are uniform across the entire substrate.

[0011] Embodiments of this disclosure provide a semiconductor processing system including a processing chamber, a substrate, an etching gas source, a dilution gas source, a plasma source, and a controller. The substrate is disposed within the processing chamber and supports a substrate. The etching gas source is configured and arranged to provide etching gas into the processing chamber. The dilution gas source is configured and arranged to provide dilution gas into the processing chamber. The plasma source is configured and arranged to provide plasma into the processing chamber. The controller is configured to control the flow of dilution gas into the processing chamber to perform the method. Attached Figure Description

[0012] A more complete understanding of this disclosure can be obtained by reading the following detailed description and examples and referring to the accompanying drawings, in which:

[0013] Figure 1 This is a schematic diagram of a part of a semiconductor structure;

[0014] Figure 2 This is a schematic diagram of a method for forming a semiconductor structure according to some embodiments of the present disclosure;

[0015] Figure 3 This is a timing diagram according to some embodiments of the present disclosure;

[0016] Figure 4A This is a schematic diagram of the outline of the concave portion of the semiconductor structure at the center of the substrate;

[0017] Figure 4B This is a schematic diagram of the outline of the recessed portion of the semiconductor structure at the edge of the substrate;

[0018] Figure 4C This is a schematic diagram of the outline of the concave portion of the semiconductor structure at the center of the substrate;

[0019] Figure 4D This is a schematic diagram of the outline of the recessed portion of the semiconductor structure at the edge of the substrate;

[0020] Figure 5 This is a schematic diagram of a semiconductor structure 500 according to some embodiments of the present disclosure; and

[0021] Figure 6 A semiconductor processing system illustrated according to an exemplary embodiment of the present disclosure is shown. Detailed Implementation

[0022] Although certain embodiments and examples are disclosed below, those skilled in the art will understand that this disclosure extends beyond the specific embodiments and / or uses disclosed herein, as well as their obvious modifications and equivalents. Therefore, it is intended that the scope of this disclosure should not be limited to the specific disclosed embodiments described below.

[0023] As used herein, the term "substrate" can refer to any one or more underlying materials, including any one or more underlying materials that can be modified or on which devices, circuits, or films can be formed. A "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous; and combinations thereof. A substrate can be in any form, such as powder, plate, or workpiece. Plate-type substrates can include wafers of various shapes and sizes. Substrates can be made of semiconductor materials, including, for example, silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide. In some embodiments, the substrate may have OH capping. OH capping can occur naturally, for example, through atmospheric oxidation, or OH capping can be intentionally provided, for example, by subjecting the substrate to plasma treatment.

[0024] As an example, the substrate in powder form can have applications for pharmaceutical manufacturing. Porous substrates can contain polymers. Examples of workpieces may include medical devices (e.g., stents and syringes), jewelry, tooling devices, components for battery manufacturing (e.g., anodes, cathodes, or separators), or components for photovoltaic cells, etc.

[0025] The continuous substrate can extend beyond the boundary of the processing chamber where the deposition process takes place. In some processes, the continuous substrate can move through the processing chamber, allowing the process to continue until the end of the substrate is reached. The continuous substrate can be supplied from a continuous substrate supply system to allow the continuous substrate to be manufactured and output in any suitable form.

[0026] Non-limiting examples of continuous substrates may include sheets, nonwoven films, rolls, foils, fiber webs, flexible materials, bundles of continuous filaments or fibers (e.g., ceramic fibers or polymer fibers). Continuous substrates may also include carriers or sheets on which non-continuous substrates are mounted.

[0027] The specific embodiments shown and described are illustrative of this disclosure and its best mode, and are not intended to limit the scope of aspects and embodiments in any way. In fact, for brevity, conventional manufacturing, connection, fabrication, and other functional aspects of the system may not be described in detail. Furthermore, the connecting lines shown in the figures are intended to represent exemplary functional relationships and / or physical connections between various elements. Many alternative or additional functional relationships or physical connections may exist in the actual system, and / or may not exist in some embodiments.

[0028] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples herein should not be considered limiting, as many variations are possible. The particular routines or methods described herein may represent one or more of any number of processing strategies. Therefore, the various actions shown may be performed in the order shown, in another order, or in some cases omitted.

[0029] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of various processes, systems and configurations, as well as other features, functions, actions and / or properties disclosed herein, and any and all equivalents thereof.

[0030] Exposing the substrate to the precursor can result in one or more of the physical and chemisorption of at least one of the precursor and precursor fragments on the substrate. Reactant pulses from multiple reactant pulses can result in one or more of the physical and chemisorption of at least one of the reactant and reactant fragments on the substrate.

[0031] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms. These terms do not refer to a particular order, vertical relationship, or preference, and are used only to distinguish one component, region, or part from another. Therefore, without departing from the teachings of this disclosure, the first component, region, or part described below may refer to the second component, region, or part.

[0032] As used herein, "basic" or "approximately equivalent" means ±5%, ±2%, ±1%, or ±0.5% of another value or shape (e.g., one or more cross-sectional dimensions of a shape). Percentages can be absolute or relative.

[0033] In the accompanying drawings, the shapes illustrated may vary due to manufacturing techniques and / or tolerances. Therefore, embodiments should not be construed as limited to a specific shape within the areas shown herein, but may include shape variations, for example, due to manufacturing processes. Furthermore, the drawings may be used to illustrate various features, which may not be drawn to scale.

[0034] When a phrase such as "at least one of..." follows a column of elements, it modifies the entire column of elements, rather than a single element within that column.

[0035] As used herein, "atomic layer deposition," abbreviated as "ALD," refers to a method of depositing a film on a substrate by sequentially exposing the substrate surface to alternating gaseous reactants. Unlike chemical vapor deposition, the different reactants are not present simultaneously in the reactor, but are introduced as a series of sequential, non-overlapping pulses. In each of these pulses, the reactant reacts with the surface in a self-limiting or substantially self-limiting manner. Furthermore, as used herein, ALD may also be intended to include processes specified by related terms such as chemical vapor deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas-sourced MBE, or organometallic MBE, and chemical beam epitaxy when performed with alternating pulses of reactants. Plasma-enhanced atomic layer deposition (PEALD) refers to an ALD process in which plasma is applied during one or more ALD steps or sub-steps.

[0036] As used herein, "chemical vapor deposition," abbreviated as "CVD," refers to a method of depositing a film on a substrate by exposing the substrate surface to one or more gaseous reactants, which react and / or decompose on the substrate surface to produce the desired film. Typically, CVD is performed by co-introducing the reactants into a reactor. Plasma-enhanced chemical vapor deposition (PECVD) refers to a CVD process in which plasma is applied during one or more CVD steps or sub-steps.

[0037] As used herein, “chemisorption” refers to an adsorption process caused by a reaction on an exposed surface, which creates, for example, covalent or ionic bonds between the surface and the adsorbate.

[0038] As used herein, a “film” refers to a continuous, substantially continuous, or discontinuous material that extends in a direction perpendicular to its thickness direction to cover at least a portion of a surface. Films can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers, partial or complete atomic layers, or atomic and / or molecular clusters. Films can consist of one or more indistinguishable layers (e.g., monolayers or submonolayers) to produce a homogeneous or substantially homogeneous material, wherein the number of layers affects the thickness of the material.

[0039] As used herein, the terms “layer,” “film,” and / or “thin film” can refer to any continuous or discontinuous structure and material deposited by the methods disclosed herein. For example, a “layer,” “film,” and / or “thin film” can include 2D materials, nanorods, nanotubes, or nanoparticles, or even partial or complete molecular layers, partial or complete atomic layers, or atomic and / or molecular clusters. A “layer,” “film,” and / or “thin film” can include a material or layer with pinholes, but still at least partially continuous.

[0040] As used herein, “gas” refers to a state of matter consisting of atoms or molecules that have neither a defined volume nor a defined shape. Gases include evaporated solids and / or liquids, and may, depending on the circumstances, consist of a single gas or a mixture of gases.

[0041] As used herein, “plasma” refers to an ionized gas containing approximately equal numbers of negatively and positively charged matter (typically electrons and ions). Excitation and reactive matter are also included in plasma, such as atoms and free radicals, metastable atoms and molecules, and photons. Plasma discharge requires an externally applied electric or magnetic field to ionize the gas. Plasma generation schemes and geometries include, but are not limited to, capacitively coupled plasma (CCP), inductively coupled plasma (ICP), and RF hollow cathode (HC) plasma, which differ in the generation of excitation and reactive matter and therefore can provide very different fluxes of various substances.

[0042] As used herein, a "precursor" refers to a compound that participates in a chemical reaction to form another compound or element, wherein a portion of the precursor (an element or group within the precursor) is incorporated into the compound or element produced by the chemical reaction. The compound or element produced by the chemical reaction can be a layer and / or film formed on a substrate surface.

[0043] As used herein, "reactant" refers to a compound that participates in a chemical reaction to form another compound or element. In some cases, a reactant is a precursor. In other cases, the compound or element produced by a chemical reaction does not contain any part of the reactant (the element or group within the reactant), and therefore the reactant is not a precursor.

[0044] As used herein, "self-limiting" refers to a process that proceeds along a finite path and terminates once that finite path is completed. For example, a self-limiting surface reaction terminates when the surface becomes saturated and all available and / or accessible surface reactive sites are exhausted. At most, a single monolayer can form on a surface.

[0045] As used herein, a "substituent" refers to an atom or group of atoms that replaces one or more atoms (e.g., hydrogen atoms) or groups of atoms in a parent compound, thereby producing a new compound. A substituent replaces an original atom or group of atoms in a parent molecule. For simplicity, a substituent may be represented in a chemical formula as an "R" group, and each "R" group in the compound may be chosen independently unless otherwise specifically stated otherwise. Examples of substituents include, but are not limited to: hydrogen atoms (H); "alkyl", such as saturated straight-chain or branched C1-C10 hydrocarbons, preferably C1-C6 hydrocarbons (e.g., methyl, ethyl, propyl, isopropyl, butyl, isobutyl, sec-butyl, tert-butyl, pentyl, 3-pentyl, neopentyl, and hexyl); "cycloalkyl", such as C3 to C6 cyclic hydrocarbons (e.g., cyclopropyl, cyclobutyl, cyclopentyl, and cyclohexyl); "alkenyl", such as C2 to C6 straight-chain or branched unsaturated hydrocarbons (e.g., vinyl, allyl, propylene). "Aryl", such as phenyl, benzyl, tolyl, xylyl, naphthyl, cyclopentadienyl and methyl, dimethyl or ethylcyclopentadienyl; hydroxyl (OH); "alkoxy", such as straight-chain or branched C1 to C10 alkoxy, usually C1 to C4 alkoxy (e.g. methoxy, ethoxy, n-propoxy, isopropoxy, butoxy, isobutoxy, sec-butoxy). "Alkyl and tert-butoxy"; hydroxyalkyl, such as straight-chain or branched C1 to C10 hydroxyalkyl, typically straight-chain or branched C1 to C4 hydroxyalkyl (e.g., hydroxymethyl, hydroxyethyl, hydroxypropyl, hydroxybutyl, hydroxypentyl, and hydroxyhexyl); "alkoxycarbonyl", such as straight-chain or branched C1-C6 carbonyl hydrocarbons (e.g., methoxycarbonyl, ethoxycarbonyl, propoxycarbonyl, isopropoxycarbonyl, butoxycarbonyl, pentoxycarbonyl, and hexoxycarbonyl); thiol (SH); "alkylthiol group", such as straight-chain or branched C1 The substituents are C6 thiols (e.g., thiomethyl, thioethyl, thiopropyl, thiobutyl, thiopentyl, and thiohexyl); halides (X), such as fluorides (F), chlorides (Cl), bromides (Br), and iodides (I); and "haloalkyl", such as straight-chain or branched C1-C6 alkyl halides having one or more halogen atoms (e.g., iodomethyl, bromomethyl, chloromethyl, fluoromethyl, trifluoromethyl, 2-chloroethyl, 2-fluoroethyl, 2,2,2-trifluoroethyl, and pentafluoroethyl). The substituent itself can be substituted. For example, hydroxyalkyl is a substituted alkyl group in which the H atom on the alkyl group is replaced by an OH group.

[0046] Depending on the context, the article “a” or “one” refers to a species or a genus comprising multiple species. Therefore, the terms “a,” “one or more,” and “at least one” are used interchangeably in this text. It should also be noted that the terms “comprising,” “including,” and “having” are used interchangeably.

[0047] The term "approximately" typically refers to a range of numbers that are considered equivalent to the value (e.g., having the same function or result). In some cases, the term "approximately" may include a numerical value rounded to the nearest significant figure.

[0048] The term "basic" when applied to compositions, methods, or systems generally means that the addition of components does not substantially alter the properties and / or function of the composition, method, or system.

[0049] The term "basic" applied to compositions, methods, or systems generally refers to a proportion of a value, property, characteristic, etc., or conversely, to the absence of such a value, i.e., at least about 70%, at least about 80%, at least about 90%, at least about 95%, at least about 97%, at least about 98%, at least about 99%, at least about 99.5%, at least about 99.9% or more, or any proportion between about 70% and about 100%. In some embodiments, the term "basic" means a proportion of about 90%, about 95%, about 97%, about 98%, about 99%, about 99.5%, or about 99.9%.

[0050] "At least one," "one or more," and "and / or" are open-ended expressions that are both conjunction and disjunctive in operation. For example, each of the expressions "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," and "A, B, and / or C" means a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together. When each of A, B, and C in the above expressions refers to an element (such as X, Y, and Z) or a category of elements (such as X1-Xn, Y1-Ym, and Z1-Zo), the phrase is intended to refer to a single element selected from X, Y, and Z, a combination of elements selected from the same category (such as X1 and X2), and a combination of elements selected from two or more categories (such as Y1 and Zo).

[0051] It should be understood that every numerical range given in this disclosure is considered to include both an upper and lower endpoint, as well as every narrower numerical range falling within such a wider range, as such narrower numerical ranges are explicitly stated herein. For example, the phrase “about 2 to about 4” or “2 to 4” includes 2 and 4, and the range of integers and / or integers from about 2 to about 3, about 3 to about 4, and every possible range based on real numbers (e.g., irrational and / or rational numbers), such as about 2.1 to about 3.9, about 2.1 to about 3.4, etc.

[0052] This disclosure generally relates to methods for forming an underlayer over a substrate using CVD (e.g., PECVD) or ALD (e.g., PEALD), semiconductor structures having an underlayer, and reactor systems for performing the methods, and particularly to using a precursor gas having at least one carbon-carbon double bond to form an underlayer having carbon-carbon double bonds to provide dose reduction for EUV lithography. Various aspects of the methods and systems, and the benefits derived therefrom, will now be described.

[0053] This disclosure allows for uniform etching of high aspect ratio (HAR) features across the substrate. In some examples, one layer of material is deposited per deposition cycle. After multiple deposition cycles are performed, an etching cycle is performed to etch back the top of the feature.

[0054] Processes including deposition, etching, and deposition-extraction (DED) can be performed to increase the effectiveness of gap filling in a feature. In other words, the feature is partially filled with material, and then etching is performed. Etching removes some material closer to the top of the feature than to the bottom. As a result, the recess remains open for a longer period, and more material is deposited at the lower part of the feature.

[0055] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a portion of a semiconductor structure 100. The semiconductor structure 100 includes a substrate 110 and a material 120. The material 120 covers the substrate 110. A recess 130 is formed on the substrate 110. The recess 130 includes sidewalls 131 and a bottom 132. The material 120 covers the sidewalls 131 and the bottom 132.

[0056] In some embodiments, material 120 may be a dielectric layer. In some embodiments, the dielectric layer may include silicon or metal. For example, the dielectric layer may include one or more of SiN, SiON, SiC, SiCN, SiCO, SiCOH, or SiCON. For example, the dielectric layer may include one or more of TiN, TiC, HfN, HfC, WC, WN, MoC, MoN, AlN, AlC, ZrO, or ZrC.

[0057] In some embodiments, the recess may include a trench with a width between 10 nm and 100 nm. For example, the recess may include trenches with widths of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, or greater. The recess may include trenches with a width less than 10 nm. The recess may also include trenches with a width greater than 100 nm. In some embodiments, the recess may have an aspect ratio between 1 and 10. For example, the recess may have an aspect ratio of 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10. In some embodiments, the recess has an aspect ratio greater than or equal to 5:1. In some embodiments, the width and aspect ratio depend on the application area. For example, widths ranging from 5 nm to 100 nm and aspect ratios from 2 to 100 correspond to nanoscale logic and memory devices, while widths ranging from 100 to 1000 nm and aspect ratios from 1 to 100 correspond to TSVs (Through Silicon Vias) used for three-dimensional interconnection of nanoscale devices.

[0058] Back Figure 1 The sidewall 131 is inclined relative to the bottom, and the width of the bottom 132 is less than the width of the opening 135 of the recess 130. Typically, a recess with a wide opening and a narrow bottom results in a "positive slope" recess. Positive slope recesses can be easily filled without creating voids.

[0059] Back Figure 1 The upper portion 133 of the recess 130 is closer to the opening 135 of the recess 130 and the flat portion 111 of the substrate 110. The lower portion 134 of the recess 130 is closer to the bottom 132 of the recess 130. The material 120 has a thickness 121 at the upper portion 133 and a thickness 122 at the lower portion 134. To maintain a recess with a wide opening and a narrow bottom, it is desirable that the thickness 122 at the lower portion 134 is greater than the thickness 121 at the upper portion 133. Furthermore, the conformability of the side surface of the material 120 is defined as:

[0060] .

[0061] Since the thickness 122 at the lower part 134 is greater than the thickness 121 at the upper part 133, the side conformity of material 120 is greater than 100% (side conformity of material 120 > 100%).

[0062] Ideally, the lateral conformability of material 120 is high enough to achieve void-free gap filling in the recess. In some embodiments, the lateral conformability of material 120 over the entire substrate 110 is greater than 105%. In some embodiments, the lateral conformability of material 120 over the entire substrate 110 is close to 110%.

[0063] Ideally, the lateral conformability of the material 120 across the entire substrate 110 remains substantially consistent, and the variation in lateral conformability across the entire substrate 110 is ideally small in order to obtain a uniform substrate. That is, the lateral conformability of the material 120 near the central axis of the substrate 110 is ideally close to the lateral conformability of the material 120 near the edge of the substrate 110.

[0064] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a method 200 for forming a semiconductor structure according to some embodiments of the present disclosure.

[0065] In step 210, material is deposited on the sidewalls of the recess. Step 210 is performed in a processing chamber having a substrate including the recess.

[0066] In some embodiments, the material may be a dielectric layer. In some embodiments, the dielectric layer may include silicon or metal. For example, the dielectric layer may include one or more of SiN, SiON, SiC, SiCN, SiCO, SiCOH, or SiCON. For example, the dielectric layer may include one or more of TiN, TiC, HfN, HfC, WC, WN, MoC, MoN, AlN, AlC, ZrO, or ZrC.

[0067] Next, step 220 involves providing an inert gas into the processing chamber. The inert gas may be a rare gas. For example, the inert gas may be helium (He) or argon (Ar). Step 220 is optional. In some embodiments, step 220 is performed. In some embodiments, step 220 is omitted.

[0068] Next, step 230 involves supplying etching gas into the processing chamber.

[0069] In some embodiments, the etching gas comprises fluorine (F). In some embodiments, the etching gas comprises at least one of the following: NF3, SF6, F2, ClF3, and CF4. In some embodiments, the etching gas is NF3.

[0070] In some embodiments, the flow rate of the etching gas is maintained in any intermediate range between about 0 sccm, about 1 sccm or greater, typically about 1 sccm to about 100,000 sccm, more typically about 1 sccm to about 10,000 sccm, more typically about 1 sccm to about 5,000 sccm, more typically about 1 sccm to about 1,000 sccm, more typically about 1 sccm to about 500 sccm, more typically about 1 sccm to about 200 sccm, more typically about 1 sccm to about 100 sccm, more typically about 1 sccm to about 50 sccm, more typically about 1 sccm to about 10 sccm, or about 1 sccm to about 100,000 sccm. In some embodiments, the flow rate of the etching gas may be maintained in any intermediate range between 1 sccm or greater, 10 sccm or greater, 50 sccm or greater, 100 sccm or greater, 200 sccm or greater, 500 sccm or greater, 1,000 sccm or greater, 5,000 sccm or greater, or 10,000 sccm or greater. In some embodiments, the flow rate of the etching gas can be maintained at about 1 sccm, about 10 sccm, about 50 sccm, about 100 sccm, about 200 sccm, about 500 sccm, about 1000 sccm, about 5000 sccm, about 10000 sccm, or about 100000 sccm.

[0071] In a specific embodiment, the flow rate of the dilution gas is greater than or equal to 5000 sccm. In another specific embodiment, the flow rate of the dilution gas is greater than or equal to 7000 sccm.

[0072] Next, step 240 involves providing a dilution gas into the processing chamber. In some embodiments, steps 230 and 240 are performed simultaneously. In some embodiments, step 230 is performed before step 240. In some embodiments, step 240 is performed before step 230.

[0073] Diluting the gas helps distribute the etching gas across the entire substrate, thus ensuring uniform etching gas distribution within the processing chamber. For example, the concentration of the etching gas is substantially uniform across the substrate. That is, the etching gas concentration above the center of the substrate is substantially the same as the etching gas concentration above the edges of the substrate.

[0074] In some embodiments, the diluent gas includes nitrogen (N). In some embodiments, the diluent gas includes at least one of the following: N2, NH3, N2H4, and N2O. In some embodiments, the diluent gas is N2.

[0075] In some embodiments, the flow rate of the dilution gas is greater than the flow rate of the etching gas. In some embodiments, the flow rate of the dilution gas is less than the flow rate of the etching gas. In some embodiments, the flow rate of the dilution gas is the same as the flow rate of the etching gas.

[0076] In some embodiments, the flow rate of the diluent gas is maintained in any intermediate flow rate range between about 0 sccm or greater, about 1 sccm or greater, typically about 1 sccm to about 100,000 sccm, more typically about 1 sccm to about 10,000 sccm, more typically about 1 sccm to about 5,000 sccm, more typically about 1 sccm to about 1,000 sccm, more typically about 1 sccm to about 500 sccm, more typically about 1 sccm to about 200 sccm, more typically about 1 sccm to about 100 sccm, more typically about 1 sccm to about 50 sccm, more typically about 1 sccm to about 10 sccm, or about 1 sccm to about 100,000 sccm. In some embodiments, the flow rate of the diluent gas may be maintained in any intermediate flow rate range between 1 sccm or greater, 10 sccm or greater, 50 sccm or greater, 100 sccm or greater, 200 sccm or greater, 500 sccm or greater, 1,000 sccm or greater, 5,000 sccm or greater, or 10,000 sccm or greater. In some embodiments, the flow rate of the diluent gas may be maintained at about 1 sccm, about 10 sccm, about 50 sccm, about 100 sccm, about 200 sccm, about 500 sccm, about 1000 sccm, about 5000 sccm, about 10000 sccm, or about 100000 sccm.

[0077] Next, step 250 involves supplying plasma into the processing chamber.

[0078] The etching gas forms free radicals under plasma. In some embodiments, the etching gas forms F radicals (F*) under plasma. With the help of the diluting gas, the F radicals are well distributed on the substrate, and the concentration of F radicals at the center of the substrate and at the edge of the substrate is uniform.

[0079] Furthermore, in the presence of a dilution gas, the etching gas forms NF2. For example, in an embodiment where the etching gas is NF3 and the dilution gas is N2, the reduction formula is: NF3 + N2 → NF2. This reduces F radicals and allows for the formation of a positive slope concave portion.

[0080] Therefore, the substrate is uniform, and the recess has a positive slope profile.

[0081] In some embodiments, the RF power used to generate plasma is maintained in any intermediate flow range between about 0 W or more, about 0.1 W or more, typically about 0.1 W to about 100,000 W, more typically about 1 W to about 10,000 W, more typically about 1 W to about 5,000 W, more typically about 1 W to about 1,000 W, more typically about 1 W to about 500 W, more typically about 1 W to about 200 W, more typically about 1 W to about 100 W, more typically about 1 W to about 50 W, more typically about 1 W to about 10 W, or about 1 W to about 100,000 W. In some embodiments, the flow rate of the dilution gas may be maintained in any intermediate flow range between 0.1 W or more, 1 W or more, 10 W or more, 50 W or more, 100 W or more, 200 W or more, 500 W or more, 1,000 W or more, 5,000 W or more, or 10,000 W or more. In some embodiments, the flow rate of the diluent gas may be maintained at about 0.1W, about 1W, about 10W, about 50W, about 100W, about 200W, about 500W, about 1000W, about 5000W, about 10000W, or about 100000W.

[0082] In some embodiments, the duration of the plasma is about 100 seconds or less, typically about 0.01 seconds to about 100 seconds, more typically about 0.01 seconds to about 50 seconds, more typically about 0.01 seconds to about 10 seconds, more typically about 0.01 seconds to about 5 seconds, more typically about 0.01 seconds to about 1 second, more typically about 0.01 seconds to about 0.5 seconds, more typically about 0.01 seconds to about 0.1 seconds, more typically about 0.1 seconds to about 100 seconds, more typically about 1 second to about 50 seconds, more typically about 0.1 seconds to about 10 seconds, more typically about 0.1 seconds to about 5 seconds, more typically about 0.1 seconds to about 10 ...01 seconds to about 100 seconds, more typically about 0.01 seconds to about 100 seconds, more typically about 0.01 seconds to about 100 seconds, more typically about 0.01 seconds to about 100 seconds, more typically about 0.01 seconds to about 100 seconds, more typically about 0.01 seconds to about 100 seconds, more typically about 0.01 seconds to about 100 seconds, more typically about 0.01 seconds to about The RF power may be maintained within any intermediate time range between 1 second, more typically about 0.1 seconds to about 0.5 seconds, more typically about 0.5 seconds to about 100 seconds, more typically about 0.5 seconds to about 50 seconds, more typically about 0.5 seconds to about 10 seconds, more typically about 0.5 seconds to about 5 seconds, more typically about 0.5 seconds to about 1 second, more typically about 1 second to about 100 seconds, more typically about 1 second to about 50 seconds, more typically about 1 second to about 10 seconds, more typically about 1 second to about 5 seconds, more typically about 5 seconds to about 100 seconds, more typically about 5 seconds to about 50 seconds, more typically about 5 seconds to about 10 seconds, or about 0.01 seconds to about 100 seconds. In some embodiments, the RF power may be maintained within any intermediate time range between about 100 seconds or less, about 50 seconds or less, about 10 seconds or less, about 5 seconds or less, about 1 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. In some embodiments, the RF power may be maintained for about 0.01 seconds, about 0.1 seconds, about 0.5 seconds, about 1 second, about 5 seconds, about 10 seconds, about 50 seconds, or about 100 seconds.

[0083] Method 200 also includes a sub-loop 260. Sub-loop 260 includes steps 230, 240, and 250. Sub-loop 260 is also referred to as an etch loop. In some embodiments, sub-loop 260 may be repeated multiple times until the desired etch depth is reached.

[0084] According to some embodiments, the etching cycle can be performed at temperatures ranging from about 20 to about 1200°C, about 50 to about 800°C, about 75 to about 600°C, about 300°C to about 500°C, or about 350°C to about 450°C. In some embodiments, the temperature is greater than about 20, 50, or 100°C, but less than about 1000, 800, 600, or 500°C. In some embodiments, the cycle is performed at a temperature of about 450°C.

[0085] In some embodiments, the pressure in the processing chamber for the etching cycle is typically from about 10E-9 Torr to about 760 Torr, or from about 0.001 Torr to about 100 Torr. However, in some cases, the pressure will be higher or lower than this range, which can be determined by those skilled in the art based on the specific circumstances. In some embodiments, a pressure of less than 2 Torr is used. In some cases, the reactor can operate under isothermal (e.g., hot-wall) or non-isothermal (e.g., cold-wall) conditions. In some embodiments, the reactor itself does not interact with the etching chemicals and may also not interact with the substrate. In some cases, the reactor may comprise a processing chamber of the hot-wall, cold-wall, or warm-wall type.

[0086] In some embodiments, the etching cycle has an average etching rate of about 0.01 to about 5 Å / cycle. The etching rate is defined as the amount of material or film thickness removed after each cycle. In some embodiments, the average etching rate is about 0.01 to 0.1 Å / cycle or 0.1 to about 2 Å / cycle, or in some cases even higher than 2 Å / cycle. In some embodiments, the average etching rate is greater than about 0.1 Å / cycle, greater than about 0.5 Å / cycle, greater than about 1.0 Å / cycle, greater than about 2.0 Å / cycle, greater than about 3.0 Å / cycle, greater than about 5.0 Å / cycle, greater than about 10 Å / cycle, or greater than about 20 Å / cycle, and in some cases, if a continuous flow with flow rate modification is applied or the exposure time is sufficiently long, the etching rate can be greater than about 30 Å / cycle, greater than about 50 Å / cycle, or about 100 Å / cycle. The pre-cleaning process of the present invention is not limited to any particular form of cyclic etching. In some embodiments, the plasma etching cycle may have an etching rate of about 50 Å / cycle. In some embodiments, the modification depends on the ion implantation depth of the process. For H2, this can be a few nm. In some embodiments, EPC can be increased by increasing the substrate bias. In some embodiments, an etch rate of 100 Å / cycle can be obtained. In thermal etch cycles (e.g., ALE), the etch rate can be in the range of 0.1-3 Å / cycle, as this is more dependent on the surface reaction.

[0087] In some embodiments, the etching selectivity, i.e., the ratio of material (thickness, mass, or amount of atoms / molecules) removed from the desired surface / material to the material removed from the undesired surface / material or surface / material, is greater than about 2:1, greater than about 3:1, greater than about 5:1, greater than about 7:1, greater than about 10:1, greater than about 15:1, greater than about 20:1, greater than about 30:1, greater than about 50:1, greater than about 100:1, greater than about 1000:1, greater than about 10000:1, or greater than 10000:1. In some embodiments, no significant amount of material is removed from the undesired surface / material. In some embodiments, this ratio depends on the cyclic etching process.

[0088] Method 200 also includes an optional supercycle 270. Supercycle 270 includes steps 210, 220, 230, 240, and 250. Supercycle 270 includes deposition, etching, and deposition (DED), thus supercycle 270 can be performed to increase the effectiveness of gap filling in the recess. Supercycle 270 can also achieve void-free gap filling in the recess. In some embodiments, supercycle 270 can be repeated multiple times until the recess is filled.

[0089] Please refer to Figure 3 , Figure 3This is a schematic diagram of timing 300 according to some embodiments of the present disclosure.

[0090] An inert gas, an etching gas, and a dilution gas are provided at time 310; that is, the flow of the etching gas and the flow of the dilution gas at least overlap. At time 310, the plasma is not ignited.

[0091] Pulsed plasma at time 320, while still providing inert gas, etching gas and dilution gas; that is, the flow of etching gas, the flow of dilution gas and plasma at least overlap.

[0092] The plasma is shut off at time 330, while inert gas, etching gas, and dilution gas are still supplied; that is, the duration of the step of supplying etching gas to the processing chamber is longer than the duration of the step of supplying plasma to the processing chamber; and the duration of the step of supplying dilution gas to the processing chamber is longer than the duration of the step of supplying plasma to the processing chamber.

[0093] In some embodiments, timings 310, 320 and 330 may be repeated multiple times until the desired etching depth is reached.

[0094] Please refer to Figure 4A and Figure 4B , Figure 4A and Figure 4B The image shows a recess etched under a low flow rate of diluting gas; wherein... Figure 4A This is a schematic diagram of the outline of the recess 430A of the semiconductor structure 400A at the center of the substrate 410A; and Figure 4B This is a schematic diagram of the outline of the recess 430B of the semiconductor structure 400B at the edge of the substrate 410B.

[0095] It can be seen that the thickness of material 420A at the upper part 433A is generally greater than the thickness of material 420B at the upper part 433B; the thickness of material 420B at the lower part 434B is generally greater than the thickness of material 420A at the lower part 434A. Therefore, the lateral conformability of material 420A ((thickness 422A at the lower part 434A) / (thickness 421A at the upper part 433A)) and the lateral conformability of material 420B ((thickness 422B at the lower part 434B) / (thickness 421B at the upper part 433B)) are not uniform.

[0096] Please refer to Figure 4C and Figure 4D , Figure 4C and Figure 4D The image shows a recess etched under a high flow rate of diluting gas; wherein... Figure 4C This is a schematic diagram of the outline of the recess 430C of the semiconductor structure 400C at the center of the substrate 410C; and Figure 4D This is a schematic diagram of the outline of the recess 430D of the semiconductor structure 400D at the edge of the substrate 410D.

[0097] It can be seen that the thickness of material 420C at the upper part 433C is similar to the thickness of material 420D at the upper part 433D; the thickness of material 420C at the lower part 434C is similar to the thickness of material 420D at the lower part 434D. Therefore, the lateral conformability of material 420C ((thickness 422C at the lower part 434C) / (thickness 421C at the upper part 433C)) and the lateral conformability of material 420D ((thickness 422D at the lower part 434D) / (thickness 421D at the upper part 433D)) are uniform.

[0098] Figure 5 This is a schematic diagram of a semiconductor structure 500 according to some embodiments of the present disclosure.

[0099] Semiconductor structure 500 includes a substrate 510 and a material 520 covering the substrate 510. A recess 530A is formed on the substrate 510, located near the central axis 501 of the substrate 510. A recess 530B is formed on the substrate 510 and located near the edge 502 of the substrate 510. Recesses 530A and 530B have positive slopes. The lateral conformability of the material 520 in recess 530A is similar to that of the material 520 in recess 530B; that is, the lateral conformability is uniform across the entire substrate 510. Furthermore, the substrate 510 is also uniform across the entire substrate.

[0100] In some embodiments, method 200 is used to form semiconductor structure 500. In some embodiments, timing 300 is used to form semiconductor structure 500.

[0101] Now go to Figure 6 A semiconductor processing system 600 is illustrated according to exemplary embodiments of the present disclosure. The semiconductor processing system 600 can be used to perform one or more steps or sub-steps as described herein and / or form one or more structures or portions thereof as described herein.

[0102] The semiconductor processing system 600 includes a pair of parallel and facing conductive plate electrodes 604, 602 within a processing chamber 603, inside a interior 611 (reaction zone). Although shown as having one processing chamber, the semiconductor processing system 600 may include two or more processing chambers. Plasma can be excited within the processing chamber 603 by applying HRF power (e.g., 100 kHz, 13.56 MHz, 27 MHz, 2.45 GHz, or any value between) from a plasma source 630 to one electrode (e.g., upper electrode 604) and electrically grounding the other electrode (e.g., lower electrode 602). A temperature regulator may be provided in the lower platform 602 (lower electrode), and the temperature of the substrate 601 placed thereon can be maintained at a desired temperature, such as the substrate temperature described above. The upper electrode 604 may be used as a gas distribution device, such as a spray plate or spray head. Etching gas, dilution gas, and / or inert gas (if any) can be introduced into the processing chamber 603 from a first source 621, a second source 622, a third source 620, and a fourth source 626 via a spray plate 604 using one or more of the first gas line 623, the second gas line 624, the third gas line 625, and the fourth gas line 627. Although illustrated with four gas lines, the semiconductor processing system 600 may include any suitable number of gas lines. For example, the first source 621 may correspond to an etching gas source, the second source 622 may correspond to a dilution gas source, the third source 620 may correspond to a purge gas source, and the fourth source 626 may correspond to an inert gas source.

[0103] In the processing chamber 603, a circular pipe 613 with an exhaust line 607 can be provided, through which gas in the interior 611 of the processing chamber 603 can be discharged. Additionally, a transfer chamber 605 located below the processing chamber 603 can be provided with a sealing gas line 629 to introduce sealing gas into the interior 611 of the processing chamber 603 via the interior 616 (transfer zone) of the transfer chamber 605, through which a separation plate 614 for separating the reaction zone and the transfer zone can be provided (a gate valve is omitted from this figure; the substrate is transferred in and out of the transfer chamber 605 through this gate valve). The transfer chamber can also be provided with an exhaust line 606 connected to an exhaust source 632. In some embodiments, two or more (e.g., all) steps of method 200 and / or timing 300 can be performed without exposing the substrate to air or other oxygen-containing atmospheres.

[0104] Semiconductor processing system 600 may include one or more controllers 628 programmed or otherwise configured to perform one or more method steps as described herein. As those skilled in the art will understand, controller 628 is connected to valves of various power supplies, heating systems, pumps, robots, and airflow controllers or reactors. For example, controller 628 may be configured to control the flow of etching gas, dilution gas, and inert gas into at least one of one or more processing chambers to etch material on a substrate. The controller may similarly be configured to perform additional steps as described herein.

[0105] In some embodiments, the semiconductor processing system 600 is used to perform method 200. In some embodiments, the semiconductor processing system 600 is used to perform timing 300. In some embodiments, the semiconductor processing system 600 is used to form a semiconductor structure 500.

[0106] The methods and systems disclosed herein can provide several benefits, including forming positive slope profile recesses and substrates with uniformity, which facilitates subsequent processes (such as DED processes).

[0107] Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, those skilled in the art will readily understand that many features, functions, processes, and materials described herein may vary while still remaining within the scope of the present disclosure. Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, apparatuses, methods, and steps described in the specification. Those skilled in the art will readily understand from the disclosure of this publication that, according to this disclosure, existing or later-developed processes, machines, manufactures, compositions of matter, apparatuses, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be utilized. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, apparatuses, methods, or steps within their scope. Additionally, the scope of this disclosure is defined by the scope of the appended claims. Furthermore, each scope of the claims is constructed as a separate embodiment, and various combinations of claims and combinations of embodiments are within the scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: In the processing chamber, material is deposited on the sidewalls of the recess; Etching gas is supplied to the processing chamber; Diluent gas is supplied to the processing chamber; as well as The plasma is supplied to the processing chamber.

2. The method as described in claim 1, wherein, The etching gas includes fluorine.

3. The method as described in claim 2, wherein, The etching gas includes at least one of the following: NF3, SF6, F2, ClF3, and CF4.

4. The method of claim 2, wherein, The etching gas is NF3.

5. The method of claim 1, wherein, The diluting gas includes nitrogen.

6. The method of claim 5, wherein, The diluting gas includes at least one of the following: N2, NH3, N2H4, and N2O.

7. The method of claim 5, wherein, The diluting gas is N2.

8. The method of claim 1, wherein, The flow of the etching gas and the flow of the dilution gas overlap at least.

9. The method of claim 1, wherein, The flow of the etching gas, the flow of the dilution gas, and the plasma at least overlap.

10. The method of claim 1, wherein, The step of providing the etching gas to the processing chamber lasts longer than the step of providing the plasma to the processing chamber.

11. The method of claim 1, wherein, The step of providing the dilution gas into the processing chamber lasts longer than the step of providing the plasma into the processing chamber.

12. The method of claim 1, wherein, The flow rate of the diluent gas is greater than or equal to 5000 sccm.

13. The method of claim 1, wherein, The flow rate of the diluent gas is greater than or equal to 7000 sccm.

14. The method of claim 1, further comprising the steps of repeatedly depositing the material, providing the etching gas, providing the dilution gas, and providing the plasma.

15. The method of claim 1, wherein, The recess has an aspect ratio greater than or equal to 5:

1.

16. The method of claim 1, further comprising providing an inert gas into the processing chamber.

17. The method of claim 1, wherein, The recess is formed on the substrate.

18. A semiconductor structure formed on a substrate using the method of claim 1.

19. The semiconductor structure of claim 18, wherein, The lateral conformal properties of the remaining material are uniform across the entire substrate.

20. A semiconductor processing system, comprising: Processing room; A base, which is set in the processing chamber and supports the substrate; An etching gas source, configured and arranged to supply etching gas to the processing chamber; A dilution gas source, configured and arranged to supply dilution gas to the processing chamber; A plasma source, configured and arranged to supply plasma to the processing chamber; as well as A controller configured to control the flow of dilution gas into the processing chamber in order to perform the method as described in claim 1.

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