Etching method of stack structure, forming method and semiconductor process equipment

Abstract

The application provides an etching method of a stack structure, a forming method and a semiconductor process equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: providing a stack structure, wherein the stack structure comprises alternately stacked multiple layers of sacrificial layers and multiple layers of functional layers, the functional layers and the sacrificial layers are different material film layers, the material of the sacrificial layers comprises a target element, the stack structure is divided into a first region and a second region located on the first region in a vertical direction, the number of layers of the sacrificial layers in the second region is greater than or equal to 1 and less than 30% of the total number of layers of the sacrificial layers, the concentration difference of the target element in any two sacrificial layers in the first region is less than a predetermined threshold, and the concentration of the target element in the sacrificial layers in the second region is greater than the concentration of the target element in the sacrificial layers in the first region; and laterally etching the sacrificial layers along the sidewalls of the stack structure. By increasing the concentration of the target element in the sacrificial layers in the second region, the etching rate of the top of the stack structure is compensated, and the etching uniformity is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to an etching method, a formation method, and semiconductor process equipment for a stacked structure. Background Technology

[0002] In the fabrication process of 3D DRAM or gate-all-around (GAA) devices, a stacked structure consisting of tens to hundreds of alternating germanium-silicon layers and silicon layers is typically required. The germanium-silicon layers are then etched laterally along the sidewalls of the stacked structure using vapor phase etching. With the continuous improvement of device integration, maintaining a high selectivity while achieving uniform etching depth across the entire germanium-silicon layer in the vertical direction has become a core process requirement in this field.

[0003] To achieve these goals, the industry has attempted to globally and layer-by-layer decrease the concentration of target elements in the germanium-silicon layer during the growth of the stacked structure, aiming to compensate for potential etching rate differences along the vertical direction. However, due to its inherent principle, this approach requires precise control of the concentration of target elements in each layer of the epitaxial growth process. This not only significantly increases the complexity and control difficulty of the process and prolongs the production cycle, but also easily introduces additional lattice mismatch risks due to large-scale concentration variations, potentially affecting the electrical performance and thermal stability of the device. Therefore, it is difficult to achieve an effective balance between process simplicity, structural stability, and etching uniformity. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide an etching method, a formation method and a semiconductor process equipment for stacked structures, so as to solve the problems of difficulty in achieving both etching uniformity and process simplicity in the etching of stacked structures in the prior art.

[0005] This application provides an etching method for stacked structures, including: A stacked structure is provided, comprising alternating stacked multiple sacrificial layers and multiple functional layers, wherein the functional layers and the sacrificial layers are film layers of different materials, the material of the sacrificial layers includes a target element, the stacked structure is vertically divided into a first region and a second region located on the first region, wherein the number of sacrificial layers in the second region is greater than or equal to 1 and less than 30% of the total number of sacrificial layers, the concentration difference of the target element in any two sacrificial layers in the first region is less than a predetermined threshold, and the concentration of the target element in the sacrificial layers in the second region is greater than the concentration of the target element in the sacrificial layers in the first region; and, The sacrificial layer is etched laterally along the sidewall of the stacked structure.

[0006] This application also provides a method for forming a stacked structure, including: Alternating layers of sacrificial layers and functional layers are formed to create a stacked structure, wherein the functional layers and the sacrificial layers are made of different material films, and the material of the sacrificial layers includes the target element. The stacked structure is vertically divided into a first region and a second region located on the first region. The number of sacrificial layers in the second region is greater than or equal to 1 and less than 30% of the total number of sacrificial layers. When forming the sacrificial layer in the first region, the flow rate of the process gas containing the target element is always the first flow rate, so that the concentration difference of the target element in any two sacrificial layers in the first region is less than a predetermined threshold. When forming the sacrificial layer in the second region, the flow rate of the process gas containing the target element is a second flow rate greater than the first flow rate, so that the concentration of the target element in the sacrificial layer in the second region is greater than the concentration of the target element in the sacrificial layer in the first region.

[0007] This application also provides a semiconductor process apparatus, including: a process chamber, an inlet assembly, an exhaust assembly, and a controller. The controller includes at least one processor and at least one memory, the memory storing a computer program. When the computer program is executed by the processor, it implements the etching method of the stacked structure or the formation method of the stacked structure.

[0008] This application provides an etching method, formation method, and semiconductor process equipment for a stacked structure. By dividing the stacked structure into a first region and a second region above it in the vertical direction, and setting the concentration of the target element in the sacrificial layer in the second region to be greater than that in the first region, the second region has a faster intrinsic etching rate due to the higher concentration of the target element when the sacrificial layer is etched laterally along the sidewall of the stacked structure. This compensates for the problem of the low etching rate of the sacrificial layer at the top of the stacked structure, significantly improves the etching uniformity of the stacked structure in the vertical direction, effectively eliminates the trapezoidal morphology at the top of the stacked structure, and avoids the high process complexity and mass production difficulties caused by the global germanium gradient scheme. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the stacked structure after the germanium-silicon layer has been etched using a vapor phase etching process.

[0010] Figure 2 A flowchart of an etching method for a stacked structure provided in an embodiment of this application.

[0011] Figure 3 A flowchart illustrating a method for forming a stacked structure according to an embodiment of this application.

[0012] Figure 4 This is a schematic diagram of a method for forming a stacked structure according to an embodiment of this application.

[0013] Figures 5-6 This is a schematic diagram of the corresponding steps of the etching method for a stacked structure provided in an embodiment of this application.

[0014] Figure 7 This is a schematic diagram of lateral etching when the concentration of the target element in the sacrificial layer in the second region is 1.1 times the concentration of the target element in the sacrificial layer in the first region, according to an embodiment of this application.

[0015] Figure 8 This is a schematic diagram of lateral etching when the concentration of the target element in the sacrificial layer in the second region is 1.3 times the concentration of the target element in the sacrificial layer in the first region, according to an embodiment of this application.

[0016] Figure 9 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of this application.

[0017] Figure 10 This is a schematic diagram of another semiconductor process equipment provided in an embodiment of this application.

[0018] The attached figures are labeled as follows: 100 - Substrate; 200 - Stacked structure; 200a - Second region; 200b - First region; 201 - Sacrificial layer; 202 - Functional layer; 300 - Mask layer; 301 - First oxide layer; 302 - Nitride layer; 303 - Second oxide layer; 400 - Isolation trench; 500 - Extension trench; 20-Process chamber; 20A-Inlet assembly; 20C-Evacuation assembly; 21-Flow equalization disk; 22-Wafer carrier module; 201-Upper dome; 202-Lower dome; 203-First thermometer; 204-Second thermometer; 205-Base; 206-Heating lamp; 207-Inlet; 208-Exhaust port. Detailed Implementation

[0019] In semiconductor manufacturing, to create cavity structures in three-dimensional dynamic random access memory (3D DRAM) or gate-all-around (GAA) devices, the relevant techniques involve forming a stacked structure on a substrate, consisting of alternating germanium-silicon layers and silicon layers. Subsequently, a vapor phase etching process is used to laterally etch the germanium-silicon layers along the sidewalls of the stacked structure. This process utilizes a fluorine-containing gas as the primary etchant, which reacts with the germanium-silicon layers to generate volatile products, achieving selective removal of the germanium-silicon layers. The initial design principle is that a pure vapor phase etching process can avoid the physical damage caused by plasma bombardment, thus achieving a balance between etch selectivity and process simplification.

[0020] However, when this method is applied to stacked structures with many layers (tens or even hundreds of layers) and a large aspect ratio, the etching uniformity in the vertical direction becomes less than ideal. Figure 1 This is a schematic diagram of the stacked structure after partial etching of the germanium-silicon layer using vapor phase etching, as shown. Figure 1 As shown, due to the concentration distribution differences of the products generated by the vapor phase etching process at different depths of the stacked structure, while the concentration of germanium in each germanium-silicon layer is consistent, it is difficult to keep the etching rate of the top region of the stacked structure consistent with that of the first region. The etching rate of the germanium-silicon layer in the top region is slower, often resulting in a smaller etching amount. For example, the average etching amount of the germanium-silicon layer in the top region is only about 50% of that in the first region. The germanium-silicon layer in the top region exhibits a trapezoidal morphology, and the etching non-uniformity (NU%) of the entire stacked structure exceeds 20%, where etching non-uniformity = (maximum etching amount - minimum etching amount) / (2 Average etching amount 100%. The industry standard for acceptable etching non-uniformity is usually within 5%.

[0021] In-depth analysis revealed that the aforementioned problem stems from the fact that in pure vapor-phase etching processes using fluorine-containing gases (pure chemical etching processes without radio frequency bias) or low-RF power etching processes, the determining factor for the local etching rate is not solely controlled by the concentration of the main etching gas. Taking F2 as the main etching gas as an example, the etching reaction generates volatile SiF4 and GeF4. GeF4 exhibits autocatalytic activity, forming fluorine-rich complexes (GeF5) with fluorine molecules. - / GeF6 2-The fluorine-rich complex (e.g., F2 molecules) more readily transfers fluorine atoms to the SiGe surface, thereby lowering the activation energy, accelerating the etching of SiGe, generating more GeF4, and further increasing the concentration of GeF4 to enhance the transfer efficiency of F2 molecules, forming a positive cycle. Simultaneously, the etching reaction also generates non-volatile SiF2, which tends to adsorb onto the material surface, forming a physical barrier that inhibits subsequent reactions. Furthermore, the SiF2 coating on the silicon layer improves the etching selectivity. Therefore, the etching of SiGe primarily relies on the fluorine-rich complex. Due to its larger molecular weight, GeF4 tends to deposit towards the bottom in the high aspect ratio gaps of the stack, leading to enhanced bottom catalysis, faster and more stable etching rates, resulting in better etching uniformity in the bottom region. It is this uneven distribution of reaction products in the vertical space, combined with the weak catalysis and strong barrier formed in the top region, that causes the etching rate difference between the top and first regions, and this difference becomes increasingly significant with increasing layer count.

[0022] Currently, there are also schemes to improve etching rate consistency by progressively reducing the germanium concentration within the germanium-silicon layer. However, to achieve progressively decreasing germanium concentration within the germanium-silicon layer, the germanium concentration of each layer needs to be precisely controlled during the growth or deposition of the germanium-silicon layer. This places higher demands on epitaxial growth, atomic layer deposition, and other processes, increasing the complexity and control difficulty of the process. Moreover, the growth and processing of each germanium-silicon layer takes time, and progressively reducing the concentration will significantly extend the overall process time and reduce production efficiency. In addition, even within the same germanium-silicon layer, the uniformity of germanium concentration needs to be ensured. If there is uneven concentration, it will also lead to uneven etching rate, affecting etching consistency and thus affecting device performance. This places extremely high demands on the process.

[0023] Based on this, this application divides the stacked structure vertically into a first region and a second region above the first region. The concentration of the target element in the sacrificial layer in the second region is set to be greater than that in the sacrificial layer in the first region. The number of layers in the second region is not less than one and less than 30% of the total number of sacrificial layers. Lateral etching is then performed using a vapor phase etching process. By increasing the concentration of the target element in the top few sacrificial layers of the stacked structure, and utilizing the correlation between the concentration of the target element and the halogen-containing vapor phase etching rate, the intrinsic etching rate of the top few sacrificial layers is improved. This offsets the decrease in effective etching rate caused by insufficient autocatalytic intermediates and reaction barrier intermediates. Thus, without changing the concentration of the target element in the first region to meet the requirements of device electrical performance, stress, thermal budget, and process complexity, the etching uniformity of the entire stacked structure in the vertical direction is achieved by adjusting the concentration of the target element in only a few sacrificial layers at the top.

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] This application provides an etching method for a stacked structure, which can be performed during the formation of devices such as DRAM, 3D DRAM, capacitor structures, gate all-around structures, etc. Figure 2 A flowchart illustrating an etching method for a stacked structure provided in an embodiment of this application. Figure 2 As shown, the etching methods for stacked structures include: Step S100: Provide a stacked structure, the stacked structure including alternating stacked multiple sacrificial layers and multiple functional layers, the functional layers and sacrificial layers being different material films, the material of the sacrificial layers including the target element, the stacked structure being vertically divided into a first region and a second region located on the first region, the number of sacrificial layers in the second region being greater than or equal to 1 and less than 30% of the total number of sacrificial layers, the concentration difference of the target element in any two sacrificial layers in the first region being less than a predetermined threshold, and the concentration of the target element in the sacrificial layers in the second region being greater than the concentration of the target element in the sacrificial layers in the first region; and, Step S200: Etch the sacrificial layer laterally along the sidewall of the stacked structure.

[0026] Furthermore, this application also provides a method for forming a stacked structure, which can be performed when forming devices such as DRAM, 3D DRAM, capacitor structures, gate-all-around structures, etc. Figure 3 This is a flowchart illustrating a method for forming a stacked structure according to an embodiment of this application. Figure 3 As shown, the method for forming the stacked structure includes: Step S300: Alternately form multiple sacrificial layers and multiple functional layers to form a stacked structure. The functional layers and sacrificial layers are different material films. The material of the sacrificial layers includes the target element. The stacked structure is divided into a first region and a second region located on the first region in the vertical direction. The number of sacrificial layers in the second region is greater than or equal to 1 and less than 30% of the total number of sacrificial layers. When forming the sacrificial layer in the first region, the flow rate of the process gas containing the target element is the first flow rate, so that the concentration difference of the target element in any two sacrificial layers in the first region is less than a predetermined threshold. When forming the sacrificial layer in the second region, the flow rate of the process gas containing the target element is a second flow rate that is greater than the first flow rate, so that the concentration of the target element in the sacrificial layer in the second region is greater than the concentration of the target element in the sacrificial layer in the first region.

[0027] Figure 4 This is a schematic diagram of a method for forming a stacked structure according to an embodiment of this application. Figures 5-6 This is a schematic diagram of the corresponding steps of the etching method for a stacked structure provided in an embodiment of this application. Next, we will combine... Figures 4-6 The method for forming and etching the stacked structure provided in this application is described in detail.

[0028] like Figure 4 As shown, a substrate 100 is provided. The material of the substrate 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc., or it can be an organic semiconductor material or other semiconductor materials known in the art. Device structures such as doped regions, trench isolation structures, and embedded epitaxial layers can also be formed on and / or within the substrate 100, which will not be explained in detail here.

[0029] Please continue reading. Figure 4 In step S300, multiple sacrificial layers 201 and multiple functional layers 202 are formed on the substrate 100 to form a stacked structure 200. The sacrificial layers 201 and functional layers 202 can be stacked alternately from bottom to top. Figure 4 The example demonstrates 8 sacrificial layers 201 and 8 functional layers 202, but this is not a limitation. The sacrificial layers 201 and functional layers 202 may be less than 8 layers or more than 8 layers, for example, 3 layers, 5 layers, 10 layers, 20 layers, 50 layers, and 100 layers. In some embodiments, to meet thickness requirements, the number of sacrificial layers 201 and functional layers 202 may be greater than or equal to 20 layers, for example, the number of sacrificial layers 201 and functional layers 202 may be 20 to 108. The formation process of the sacrificial layers 201 and functional layers 202 includes, but is not limited to, epitaxial growth processes, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0030] In some embodiments, the thicknesses of the sacrificial layer 201 and the functional layer 202 may be equal or unequal, which does not affect the implementation of this application. The thicknesses of the sacrificial layer 201 and the functional layer 202 can be designed according to actual needs.

[0031] In some embodiments, the sacrificial layer 201 and the functional layer 202 are different material films. The material of the sacrificial layer 201 includes the target element, and both are preferably materials with high etching selectivity, thereby enabling selective subsequent lateral etching processes. For example, the sacrificial layer 201 can be made of germanium-silicon, with germanium as the target element, and the functional layer 202 can be made of silicon, but this is not a limitation; the sacrificial layer 201 and the functional layer 202 can also be made of other materials with high etching selectivity. Figure 4 In this process, the sacrificial layer 201 is made of silicon, the functional layer 202 is made of germanium-silicon, and the target element is germanium. Thus, the functional layer 202 can be selectively and directionally grown epitaxially on the surface of the sacrificial layer 201, and the process is simple and controllable.

[0032] Furthermore, the stacked structure 200 is vertically divided into a first region 200b and a second region 200a located on the first region 200b. The number of sacrificial layers 201 in the second region 200a is greater than or equal to 1 and less than 30% of the total number of sacrificial layers 201.

[0033] When forming the sacrificial layer 201 of the first region 200b, the flow rate of the process gas containing the target element (such as germane GeH4) can be an equal first flow rate to ensure that the concentration of the target element in the sacrificial layer 201 of the first region 200b is equal (or substantially equal). Alternatively, when forming the sacrificial layer 201 of the first region 200b, the flow rate of the process gas containing the target element (such as germane GeH4) can be a slightly different first flow rate to ensure that the concentration difference of the target element in any two sacrificial layers 201 of the first region 200b is less than a predetermined threshold, which can be less than 1%, such as 0.5%, 0.3%, or 0.1%.

[0034] When forming the sacrificial layer 201 of the second region 200a, the flow rate of the process gas containing the target element (such as germane GeH4) is a second flow rate greater than the first flow rate, so that the concentration of the target element in the sacrificial layer 201 of the second region 200a is greater than the concentration of the target element in the sacrificial layer 201 of the first region 200b. That is to say, when forming the sacrificial layer 201 of the second region 200a, this application does not change the epitaxial conditions of the sacrificial layer 201 of the first region 200b. It only needs to fine-tune the flow rate of the process gas containing the target element (such as germane GeH4) when growing the sacrificial layer 201 of the second region 200a, which is fully compatible with existing production lines and avoids the risk of lattice mismatch and dislocation caused by global concentration gradient. Thus, it achieves a significant improvement in the etching uniformity of the entire stacked structure 200 with minimal process modification.

[0035] In some embodiments, the number of sacrificial layers 201 in the second region 200a is less than 10% of the total number of sacrificial layers 201; and / or, the concentration of the target element in the sacrificial layer 201 in the second region 200a can be 1.1 to 1.3 times the concentration of the target element in the sacrificial layer 201 in the first region 200b, or the concentration difference of the target element in the sacrificial layer 201 in the second region 200a and the first region 200b is 1% to 5%. The technical effects of this numerical range will be described below.

[0036] In some embodiments, the concentration of the target element in the sacrificial layer 201 of the first region 200b can be 15% to 25%. This concentration range provides a basis for stable etching and device performance of the first region 200b and provides a clear reference for the concentration configuration of the second region 200a. For example, taking the concentration of the target element in the sacrificial layer 201 of the second region 200a as 1.1 to 1.3 times that of the target element in the sacrificial layer 201 of the first region 200b as an example, when the concentration of the target element in the sacrificial layer 201 of the first region 200b is 15%, the concentration of the target element in the sacrificial layer 201 of the second region 200a can be 16.5% to 19.5%.

[0037] Furthermore, in some embodiments, when forming the sacrificial layer 201 of the second region 200a, the flow rate of the process gas containing the target element can be uniformly equal, so that the concentration of the target element in each sacrificial layer 201 of the second region 200a can be equal. That is, each sacrificial layer 201 of the second region 200a has the exact same concentration of the target element.

[0038] In another embodiment, when forming the sacrificial layer 201 of the second region 200a, the flow rate of the process gas containing the target element can be increased layer by layer, so that the concentration of the target element in the sacrificial layer 201 closer to the substrate 100 in the second region 200a is lower. That is, within the second region 200a, along the direction toward the substrate 100, the concentration of the target element in each sacrificial layer 201 is set to decrease layer by layer. This means that in the second region 200a, the top layer has the highest concentration of the target element, the bottom layer has the lowest concentration of the target element, and the concentration of the target element in the bottom layer is still greater than the concentration of the target element in the first region 200b.

[0039] Please continue reading. Figure 4 A mask layer 300 is formed on the topmost functional layer 202. The mask layer 300 can act as a mask in subsequent etching processes, protecting the areas of the sacrificial layer 201 and the functional layer 202 that do not need to be etched. In some embodiments, the mask layer 300 includes a first oxide layer 301, a nitride layer 302, and a second oxide layer 303 stacked sequentially. The thicknesses of the first oxide layer 301 and the second oxide layer 303 can be equal, and the thicknesses of both the first oxide layer 301 and the second oxide layer 303 can be less than the thickness of the nitride layer 302. The nitride layer 302, as the core of the mask layer 300, has high resistance to etching with fluorine-containing gases. The first oxide layer 301 and the second oxide layer 303, as symmetrically arranged films, have equal and thin thicknesses, which can provide a symmetrical stress state and prevent the mask layer 300 from warping or peeling due to stress mismatch during the etching process. At the same time, the first oxide layer 301 and the second oxide layer 303 enhance the interfacial bonding force between the nitride layer 302 and the lower film layer. This symmetrical "oxide-nitride-oxide" three-layer structure together ensures the reliability of the mask function and the accuracy of the etching position.

[0040] In some embodiments, the thickness of the first oxide layer 301 and the second oxide layer 303 can be 5 nm to 10 nm, and the thickness of the nitride layer 302 can be 25 nm to 35 nm.

[0041] like Figure 5 As shown, step S100 is first performed, in which a pattern is formed on the mask layer 300 using photolithography and etching processes. Then, the patterned mask layer 300 is used as a mask to etch the sacrificial layer 201 and the functional layer 202 to form at least one isolation trench 400 in the stacked structure 200. The isolation trench 400 can penetrate all sacrificial layers 201 and all functional layers 202.

[0042] In some embodiments, when etching the functional layer 202 and the sacrificial layer 201, a portion of the depth of the substrate 100 may also be etched, so that the isolation trench 400 extends into the substrate 100. Subsequently, the portion of the isolation trench 400 located in the substrate 100 may be filled with isolation material to form a trench isolation structure.

[0043] Furthermore, as mentioned above, the number of sacrificial layers 201 and functional layers 202 may be relatively large, resulting in a large aspect ratio of the isolation trench 400. For example, the aspect ratio of the isolation trench 400 may be greater than or equal to 50, which drastically increases the etching difficulty. In order to achieve a better morphology on the sidewalls of the isolation trench 400, in some embodiments, the Bosch process can be used to etch the sacrificial layers 201 and functional layers 202. The core of the Bosch process is to achieve etching and edge passivation by alternating the etching gas and passivation gas. The passivation gas deposits a polymer on the sidewalls to suppress lateral etching, while ion bombardment maintains continuous vertical etching, thereby achieving a high aspect ratio vertical etching structure. After etching, an isolation trench 400 with nearly vertical sidewalls can be formed.

[0044] Furthermore, during the etching of the sacrificial layer 201 and functional layer 202 using the Bosch process, a polymer is formed on the inner wall of the isolation trench 400. This polymer can adversely affect subsequent lateral etching processes. Therefore, after forming the stacked structure 200, a cleaning agent is typically used to clean the area. Figure 4 The semiconductor structure in the stack 200 is wet-cleaned to remove the polymer on the sidewalls. However, the acidic components in the cleaning agent may break the chemical bonds on the sidewalls of the stack 200 while removing the polymer, resulting in bond breakage. At the same time, the polymer may not be completely removed, leaving some impurity particles on the sidewalls of the stack 200, which may affect the subsequent lateral etching process. These impurity particles typically contain carbon, nitrogen, and oxygen.

[0045] Based on this, after forming the isolation trench 400, the free radicals of the treatment gas can be used to perform surface treatment on the sidewalls of the stacked structure 200. The free radicals of the treatment gas can combine with the broken bonds on the sidewalls of the stacked structure 200 to generate gas, thereby removing the broken bonds on the sidewalls of the stacked structure 200. At the same time, the free radicals of the treatment gas can also react with the impurity particles on the sidewalls of the stacked structure 200 to generate gas, thereby removing the impurity particles on the sidewalls of the stacked structure 200.

[0046] Furthermore, the processing gas can be an inert gas or a gas that does not react with the sacrificial layer 201 and the functional layer 202, thereby avoiding damage to the sacrificial layer 201 and the functional layer 202 by surface treatment of the sidewalls of the stacked structure 200. In some embodiments, the processing gas includes at least one of hydrogen, nitrogen, and oxygen. For example, the processing gas may include at least one of hydrogen, nitrogen, oxygen, argon, helium, neon, ammonia, nitric oxide, and water vapor. The processing gas may also carry free radicals of the processing gas. Taking hydrogen as an example, the reaction energy of hydrogen free radicals (hydrogen free radical H·) is about 2.26 eV, which is much greater than the bond energy of various Si-Ge bonds (about 0.61 eV). When hydrogen free radicals come into contact with the sidewalls of the stacked structure 200, their unpaired electrons attract the broken bonds or impurity particles on the sidewalls of the stacked structure 200, causing a layer of hydrogen free radicals to be adsorbed on the sidewalls of the stacked structure 200. Then, relying on the reaction energy, covalent bonds are generated, forming a gas that is carried away.

[0047] It should be noted that free radicals mainly participate in the reaction through the activity of unpaired electrons, and their energy comes from the activity energy. Free radicals themselves have a high energy state, making them prone to adsorbing broken bonds or impurity particles on the sidewalls of the stacked structure 200. Furthermore, the energy adsorption is relatively strong and not easily dissociated. Utilizing their high reactivity, they can effectively remove broken bonds or impurity particles from the sidewalls of the stacked structure 200, ensuring that the sidewalls of the stacked structure 200 are in a relatively clean state. Compared to directly using the processing gas to surface-treat the sidewalls of the stacked structure 200, using the free radicals of the processing gas to surface-treat the sidewalls of the stacked structure 200 is more effective.

[0048] Please continue reading. Figure 5As explained above, the stacked structure 200 is vertically divided into a first region 200b and a second region 200a located on the first region 200b. The number of sacrificial layers 201 in the second region 200a is greater than or equal to 1 and less than 30% of the total number of sacrificial layers 201. The concentration of the target element in the sacrificial layer 201 in the second region 200a is greater than the concentration of the target element in the sacrificial layer 201 in the first region 200b. It is understood that the first region 200b occupies the majority of the thickness of the stacked structure 200, and the concentration of the target element in its sacrificial layer 201 can be considered a baseline concentration, which typically determines the core electrical performance, stress state, and thermal stability of the device. The second region 200a, located above the first region 200b and closer to the top of the stacked structure 200, has its target element concentration in the sacrificial layer 201 intentionally increased to be greater than the baseline concentration. By setting the concentration of the target element in the sacrificial layer 201 of the second region 200a to be greater than that in the sacrificial layer 201 of the first region 200b, and utilizing the intrinsic relationship that the etching rate increases exponentially with the concentration of the target element, the intrinsic etching rate of the sacrificial layer 201 in the top region is improved. This solves the problem of low top etching rate caused by insufficient concentration of autocatalytic intermediates in the top region and the relatively significant effect of reaction barrier intermediates. This results in a more uniform lateral etching amount in the vertical direction of the entire stacked structure 200 when the sacrificial layer 201 is subsequently etched laterally using a vapor phase etching process, improving etching uniformity, eliminating the trapezoidal morphology caused by insufficient etching in the top region, and avoiding the high process complexity and mass production challenges associated with the global germanium gradient scheme.

[0049] In some embodiments, the number of sacrificial layers 201 in the second region 200a is less than 10% of the total number of sacrificial layers 201. That is, by increasing the concentration of a small number of sacrificial layers 201, the etching uniformity of the subsequent vapor phase etching process can be improved, minimizing changes to the epitaxial growth process conditions of the first region 200b. This avoids the risk of increased cumulative stress and dislocation defects that may result from increasing the concentration of the target element over a large thickness range, maintaining the uniformity and stability of the large-scale lattice structure, thereby achieving high compatibility with existing production line manufacturing processes.

[0050] In some embodiments, the concentration of the target element in the sacrificial layer 201 of the second region 200a can be 1.1 to 1.3 times the concentration of the target element in the sacrificial layer 201 of the first region 200b, or the concentration difference of the target element in the sacrificial layer 201 of the second region 200a and the first region 200b can be 1% to 5%. Within this range, the etching rate of the sacrificial layer 201 of the second region 200a can be precisely compensated to match the etching rate of the sacrificial layer 201 of the first region 200b, avoiding undercompensation or overcompensation. If the multiple is less than 1.1 or the concentration difference is less than 1%, the effect of improving the etching rate of the sacrificial layer 201 of the second region 200a is too weak to overcome the problem of the low etching rate caused by the lack of autocatalytic species in the second region 200a, and the improvement effect on the trapezoidal morphology is not significant. If the multiple is greater than 1.3 times or the concentration difference is greater than 5%, the intrinsic etching rate of the sacrificial layer 201 in the second region 200a becomes too fast, causing the etching amount of the sacrificial layer 201 in the second region 200a to exceed that in the first region 200b, forming a reverse etching non-uniform morphology; at the same time, the excessively high concentration of the target element will exacerbate lattice mismatch and increase the risk of defect generation.

[0051] Typically, the concentration of the target element in the sacrificial layer 201 of the first region 200b can be 15% to 25%. This concentration range provides a basis for stable etching and device performance in the first region 200b, and provides a clear reference for the concentration configuration of the second region 200a. For example, if the concentration of the target element in the sacrificial layer 201 of the second region 200a can be 1.1 to 1.3 times that of the sacrificial layer 201 of the first region 200b, then when the concentration of the target element in the sacrificial layer 201 of the first region 200b is 15%, the concentration of the target element in the sacrificial layer 201 of the second region 200a can be 16.5% to 19.5%.

[0052] Furthermore, in some embodiments, the concentration of the target element in each sacrificial layer 201 within the second region 200a can be equal. That is, each sacrificial layer 201 in the second region 200a has the exact same concentration of the target element. At a uniformly high concentration of the target element, each sacrificial layer 201 generates a large amount of autocatalytic intermediates during etching. This process causes the autocatalytic effect to rapidly reach saturation at a very shallow depth within the second region 200a. Once saturated, subtle differences in the concentration of autocatalytic intermediates no longer cause further gradient changes in the etching rate, thus making the etching rate of each layer within the second region 200a more consistent and eliminating the gradual etching depth variations that might occur due to the layer-by-layer accumulation of autocatalytic intermediates within the second region 200a. Simultaneously, this single concentration setting scheme also simplifies the control requirements for the germanium source flow rate during epitaxial growth to the greatest extent possible.

[0053] In another embodiment, the concentration of the target element in the sacrificial layer 201 closer to the substrate 100 in the second region 200a is lower. That is, within the second region 200a, along the direction towards the substrate 100, the concentration of the target element in each sacrificial layer 201 is set to decrease layer by layer. This means that in the second region 200a, the top layer has the highest concentration of the target element, the bottom layer has the lowest concentration of the target element, and the concentration of the target element in the bottom layer is still greater than that in the first region 200b. This smooth concentration transition design makes the lateral etching rate present a gentle gradient process from the higher level of the second region 200a to the reference level of the first region 200b. It avoids the abrupt change in the etching profile of a certain layer due to the concentration step change at the junction of the second region 200a and the first region 200b, further improving the continuity of the etching morphology in the vertical direction and the overall uniformity of the entire stacked structure 200.

[0054] Furthermore, the number of sacrificial layers 201 and functional layers 202 in the stacked structure 200 can be 20 to 108. That is, there are a total of 20 to 108 pairs of sacrificial layers 201 and functional layers 202, and the total number of layers in the stacked structure 200 is 40 to 216. When the total number of layers in the stacked structure 200 is in the range of 20 to 108 pairs, the depth-to-width ratio of the stacked structure 200 is large, and the top trapezoidal morphology problem caused by the uneven distribution of etching products has become significant and affects the device yield. If the number of layers is too small, for example, less than 20 pairs, the high depth-to-width ratio and product accumulation effect of the stacked structure 200 are not obvious, and the etching non-uniformity problem itself is not prominent, reducing the necessity of adopting the solution of this application; if the number of layers is too large, for example, more than 108 pairs, although the solution of this application is still effective, the complexity of process control will systematically increase due to the increase in the total number of layers. The range of 20 to 108 layers precisely covers the mainstream needs of current and foreseeable future 3D DRAM and GAA device manufacturing, enabling the local density compensation scheme of this application to achieve significant uniformity improvement in practical applications. Of course, this application can also be applied to scenarios where the number of sacrificial layers 201 and functional layers 202 in the stacked structure 200 is less than 20 or greater than 108.

[0055] like Figure 4 and Figure 5 As shown, in step S200, using the mask layer 300 as a mask, a vapor phase etching process (vapor phase etching without RF bias) is used to laterally etch the sacrificial layer 201 along the sidewall of the stacked structure 200, thereby forming at least one extension trench 500. The extension trench 500 connects to the isolation trench 400 and extends laterally. The extension trench 500 is generated by etching the sacrificial layer 201. Therefore, from a planar perspective, the extension trench 500 surrounds the isolation trench 400, and each sacrificial layer 201 corresponds to one row of extension trenches 500. Figure 4 Eight rows of extension slots 500 are spaced apart in the vertical direction of the stacked structure 200, with a functional layer 202 separating adjacent rows of extension slots 500. Figure 5 As can be seen, the depth of the extension trench 500 is D. When the semiconductor device is a 3D DRAM, the exposed width of the functional layer 202 will serve as the channel of the transistor. The length of the capacitor and the transistor in the memory cell can be precisely defined by laterally etching the sacrificial layer 201.

[0056] In some embodiments, when the sacrificial layer 201 is etched laterally along the sidewall of the stacked structure 200, a biased etching process may not be required.

[0057] It should be noted that if there are two or more isolation trenches 400, when the sacrificial layer is etched laterally along the sidewall of the stacked structure 200, the sacrificial layer 201 between two adjacent isolation trenches 400 is not completely removed. After the lateral etching is completed, the two adjacent isolation trenches 400 are not connected and remain isolated from each other.

[0058] In some embodiments, a halogen-containing gas can be used to etch the sacrificial layer 201 laterally along the sidewall of the stacked structure 200. Taking the sacrificial layer 201 as a germanium-silicon material and the functional layer 202 as a silicon material as an example, the etching rate of the halogen-containing gas for germanium-silicon can reach 4000 nm / min, while the etching rate for silicon is only 40 nm / min, resulting in a selectivity ratio as high as 100:1. It can be considered that during the etching of the sacrificial layer 201, the functional layer 202 is basically not etched, thereby achieving the purpose of selective etching of the sacrificial layer 201 on the sidewall of the stacked structure 200. The halogen-containing gas can be CF4, HCl, HBr, NF3, SF6, XeF2, F2, C4F8, C3F6, CHF3, CH2F2, CH3F, etc., which will not be listed here.

[0059] Furthermore, taking the sacrificial layer 201 as a germanium-silicon material and F2 as the halogen gas as an example, the actual etching rate of a certain sacrificial layer 201 in the stacked structure 200 is determined by the superposition of the etching ability of F2, the catalytic ability of GeF4, and the barrier ability of SiF2. In the conventional 64-pair scheme with a germanium concentration of 15%, the GeF4 concentration at the top is low and the GeF4 concentration at the bottom is high, resulting in a significantly slower etching rate at the top than at the bottom, and leaving a distinct inverted trapezoidal morphology in the top 3-5 layers (e.g., Figure 1 (As shown). GeF4 has a large molecular weight and is easy to deposit downwards. However, deposition is not infinitely cumulative. In high aspect ratio stacks, GeF4 molecules continuously collide, adsorb, and desorb with the sidewalls during downward diffusion. When the depth exceeds a certain critical value, the concentration of GeF4 reaches a dynamic equilibrium (the downward transport of GeF4 flux equals the rate of reaction consumption), rather than increasing indefinitely. As a self-catalyst, GeF4 exhibits a saturation effect. When the GeF4 concentration is sufficiently high, the catalytic reaction rate no longer increases linearly with concentration but approaches an upper limit (limited by F2 supply or surface reaction sites). Therefore, the etching rate at the bottom does not increase indefinitely but tends to stabilize. The relatively uniform etching rate at the bottom reflects the saturation effect. The top GeF4 concentration accumulates from zero and has not yet reached saturation, thus exhibiting a gradual etching rate. Based on measured data, under vapor phase etching, the average etching amount of the top 10% of the layers is approximately 50% of the etching amount at the bottom. To address the difference in etching amounts between the top and bottom, increasing the germanium concentration at the top by 1% to 3% can bring the top etching rate to the same level as the bottom.

[0060] Therefore, by uniformly increasing the concentration of the target element in the sacrificial layer 201 of the second region 200a (e.g., by 10% to 30%), the intrinsic etching rate of these sacrificial layers 201 is significantly increased, far exceeding the range of etching rate variations caused by differences in GeF4 concentration in the original structure, since the concentration of the target element has an exponential relationship with the etching rate (each 1% increase in the target element concentration increases the etching rate by approximately 26%). At high target element concentrations, the amount of GeF4 generated increases significantly, and its catalytic effect quickly reaches saturation at a very shallow depth. Once saturated, the catalytic effect at subsequent depths no longer increases, thus making the etching rate of the sacrificial layer 201 in the second region 200a more uniform. Therefore, without the need to progressively decrease the concentration of the target element, simply increasing the concentration of the target element in the top few sacrificial layers 201 is sufficient to utilize the relationship between the etching rate and the target element concentration, as well as the catalytic saturation mechanism, to make the etching rate of these few sacrificial layers 201 more uniform, eliminating the progressively deeper morphology.

[0061] Furthermore, when the sacrificial layer 201 is etched laterally along the sidewall of the stacked structure 200, the etching rate of the sacrificial layer 201 in the second region 200a is the same, and the etching rate of the sacrificial layer 201 in the first region 200b is the same (or substantially the same), and the difference in etching rate between the sacrificial layer 201 in the second region 200a and the first region 200b does not change with time. In this way, the etching reaches a steady state, the etching rate of all sacrificial layers 201 is relatively consistent, the conical morphology of the sacrificial layer 201 in the second region 200a is eliminated, the etching amount of the sacrificial layer 201 increases linearly with time, and the difference in etching amount between the sacrificial layer 201 in the second region 200a and the first region 200b is less than 5%.

[0062] Figure 7 This is a schematic diagram of lateral etching when the concentration of the target element in the sacrificial layer 201 of the second region 200a is 1.1 times the concentration of the target element in the sacrificial layer 201 of the first region 200b, according to an embodiment of this application. Figure 8 This is a schematic diagram showing the lateral etching process when the concentration of the target element in the sacrificial layer 201 of the second region 200a is 1.3 times the concentration of the target element in the sacrificial layer 201 of the first region 200b, according to an embodiment of this application. Figure 7 and Figure 8 As shown, regardless of whether the concentration of the target element in the sacrificial layer 201 of the second region 200a is 1.1 times or 1.3 times the concentration of the target element in the sacrificial layer 201 of the first region 200b, compared to Figure 1 In this application, the etching uniformity has been significantly improved, among which, Figure 7 The etching non-uniformity (NU%) was optimized to approximately 5%. Figure 8The etching non-uniformity NU% was optimized to approximately 2.5%.

[0063] To demonstrate that the proposed solution can optimize etching uniformity, the following comparative experiment was designed: Sample A: The germanium concentration in all germanium-containing sacrificial layers is C. Sample B: The germanium concentration in the germanium-containing sacrificial layers in the first region is C, and the germanium concentration in the germanium-containing sacrificial layers in the second region is 1.1C. Sample C: The germanium concentration in the germanium-containing sacrificial layers in the first region is C, and the germanium concentration in the germanium-containing sacrificial layers in the second region 200a is 1.3C.

[0064] Each sample was etched using a vapor phase etching process, and the etching rate was measured at 30s, 60s, and 90s. After etching, the sample cross-section was inspected. In each cross-section, one measurement point was selected in the second region to calculate the etching amount, and two measurement points were selected in the first region to calculate the etching amount.

[0065] By observing the change in etching amount with etching time, the average etching rate of each measurement point at different time periods can be calculated. The following three sets of data show the changes in etching rate (ER) over time for the second region (hereinafter referred to as top), the upper part of the first region (hereinafter referred to as middle), and the lower part of the first region (hereinafter referred to as bottom).

[0066] Sample A: From 0 to 30 seconds, the top ER was 0.80 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. From 0 to 60 seconds, the top ER was 0.73 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. From 0 to 90 seconds, the top ER was 0.56 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. It can be seen that the etching rate of the upper and lower parts of the first region of sample A is constant (both are 1.20 nm / s): this proves that the GeF4 concentration in the first region is saturated, the catalytic effect no longer increases with etching time, and the etching rate is determined only by the F2 supply, that is, the catalytic saturation effect exists.

[0067] Sample B: From 0 to 30 seconds, the top ER was 1.10 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. From 0 to 60 seconds, the top ER was 1.10 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. From 0 to 90 seconds, the top ER was 1.10 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. It can be seen that the etching rate of the second region of sample B is 1.1 nm / s, while the etching rates of the upper and lower parts of the first region are both constant at 1.2 nm / s. This indicates that increasing the concentration in the second region to 1.1C significantly increases the amount of GeF4 generated, rapidly reaching catalytic saturation in the second region. The SiF2 barrier is effectively overcome, the etching enters a steady state, the etching rate is relatively consistent across all depths, the conical morphology is eliminated, and the etching rate deviation between the second and first regions does not increase over time. The etching amount increases linearly with time, and the etching non-uniformity is less than 5%.

[0068] Sample C: From 0 to 30 seconds, the top ER was 1.40 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. From 0 to 60 seconds, the top ER was 1.40 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. From 0 to 90 seconds, the top ER was 1.40 nm / s, the middle ER was 1.20 nm / s, and the bottom ER was 1.20 nm / s. As can be seen, the etching rate of the second region of sample C is 1.4 nm / s, while the etching rates of the upper and lower parts of the first region are both constant at 1.2 nm / s. This indicates that further increasing the germanium concentration in the second region to 1.3C does not result in catalytic saturation (the etching rate does not change with time), but the intrinsic etching rate is higher, leading to the second region being faster overall than the first region (slight overcompensation). However, the difference in etching rates between the second and first regions does not increase with time, indicating that etching uniformity does not deteriorate under saturation conditions.

[0069] The above data also indicate that 1.1C to 1.3C are all effective compensation windows.

[0070] Based on this, one embodiment of this application also provides a semiconductor process apparatus. Figure 9 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of this application, as shown below. Figure 9 As shown, semiconductor process equipment may include a process chamber 20, an inlet assembly 20A, an exhaust assembly 20C, and a controller. Figure 9 (Not shown in the image), the air intake assembly 20A may include a gas passage that connects to the process chamber 20, and an air intake valve is provided on the gas passage. Figure 9The black rectangular block on the gas channel. For example, the controller can be a host computer or a slave computer. The controller can control the intake valve of the intake assembly 20A and the exhaust valve of the exhaust assembly 20C. Figure 9 The controller controls the opening and closing of the black rectangular block between the extraction assembly 20C and the process chamber 20 to introduce and extract the corresponding gas into the process chamber 20. The controller can also control the opening and closing degree of the intake valve of the intake assembly 20A to control the intake flow rate, and control the opening and closing degree of the extraction valve of the extraction assembly 20C to control the exhaust flow rate. The controller can also control the extraction assembly 20C to extract gas from the process chamber 20, for example, by controlling the opening degree of the extraction valve or the speed of the extraction pump, to control the pressure inside the process chamber 20 and remove reaction byproducts. Furthermore, the semiconductor process equipment may also include a flow equalization disk 21, a wafer carrier module 22, etc. A flow equalization space is formed between the flow equalization disk 21 and the top of the process chamber 20 to uniformly flow the process gas into the process chamber 20. The wafer carrier module 22 is used to carry the wafer; the wafer carrier module 22 can be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum adsorption chuck.

[0071] In some embodiments, the semiconductor process equipment may include an ion source, such as an RPS, CCP, or ICP ion source. When process gas is introduced into the process chamber 20, some of the process gas can be ionized to generate free radicals. Compared to simply introducing process gas directly, the free radicals of the process gas have higher activity. Utilizing the free radicals of the process gas for deposition or etching can improve efficiency and uniformity. Of course, the ion source can be omitted. In this case, when process gas is introduced into the process chamber 20, the process gas may not be ionized, and therefore no free radicals will be generated. Etching can then be performed using a purely chemical etching process.

[0072] Furthermore, the controller includes at least one processor and at least one memory, in which a computer program is stored, which, when executed by the processor, implements the etching method for the stacked structure described above.

[0073] Figure 10 This is a schematic diagram of the structure of another semiconductor process equipment provided in an embodiment of this application, as shown below. Figure 10As shown, the semiconductor process equipment may further include a process chamber, which may include an upper dome 201, a lower dome 202, a first thermometer 203, a second thermometer 204, a base 205, heating lamps 206, an air inlet 207, and an exhaust outlet 208. The first thermometer 203 may be located above the upper dome, and the second thermometer 204 may be located below the lower dome. Multiple heating lamps 206 may be present, respectively positioned above the upper dome 201 and below the lower dome 202. During epitaxial processing, the wafer may be placed on the base 205. The heating lamps 206 radiate energy to the base 205 through the upper and lower transparent domes, rapidly heating the base 205 to provide the process temperature required for the epitaxial reaction.

[0074] Furthermore, the controller includes at least one processor and at least one memory, in which a computer program is stored, which, when executed by the processor, implements the method for forming the stacked structure described above.

[0075] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0076] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0077] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0078] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. An etching method for a stacked structure, characterized in that, include: A stacked structure is provided, comprising alternating stacked multiple sacrificial layers and multiple functional layers, wherein the functional layers and the sacrificial layers are film layers of different materials, the material of the sacrificial layers includes a target element, the stacked structure is vertically divided into a first region and a second region located on the first region, wherein the number of sacrificial layers in the second region is greater than or equal to 1 and less than 30% of the total number of sacrificial layers, the concentration difference of the target element in any two sacrificial layers in the first region is less than a predetermined threshold, and the concentration of the target element in the sacrificial layers in the second region is greater than the concentration of the target element in the sacrificial layers in the first region; and, The sacrificial layer is etched laterally along the sidewall of the stacked structure.

2. The etching method for the stacked structure according to claim 1, characterized in that, When the sacrificial layer is etched laterally along the sidewall of the stacked structure, the etching rate of the sacrificial layer in the second region is equal, the etching rate of the sacrificial layer in the first region is equal, and the deviation of the etching rate of the sacrificial layer in the second region and the first region does not change substantially with time.

3. The etching method for the stacked structure according to claim 2, characterized in that, The etching rate deviation between the second region and the sacrificial layer in the first region is less than 0.2 nm / s.

4. The etching method for the stacked structure according to claim 1, characterized in that, The number of sacrificial layers in the second region is less than 10% of the total number of sacrificial layers.

5. The etching method for the stacked structure according to claim 1, characterized in that, The concentration of the target element in the sacrificial layer of the second region is 1.1 to 1.3 times the concentration of the target element in the sacrificial layer of the first region; or, The concentration difference of the target element in the sacrificial layer in the second region and the first region is 1% to 5%.

6. The etching method for the stacked structure according to any one of claims 1 to 5, characterized in that, The concentration of the target element in the sacrificial layer in the first region is 15% to 25%.

7. The etching method for a stacked structure according to any one of claims 1 to 5, characterized in that, The concentration of the target element in each of the sacrificial layers in the second region is equal; or the concentration of the target element in the sacrificial layer in the second region is lower the closer it is to the substrate.

8. A method for forming a stacked structure, characterized in that, include: Alternating layers of sacrificial layers and functional layers are formed to create a stacked structure, wherein the functional layers and the sacrificial layers are made of different material films, and the material of the sacrificial layers includes the target element. The stacked structure is vertically divided into a first region and a second region located on the first region. The number of sacrificial layers in the second region is greater than or equal to 1 and less than 30% of the total number of sacrificial layers. When forming the sacrificial layer in the first region, the flow rate of the process gas containing the target element is a first flow rate, so that the concentration difference of the target element in any two sacrificial layers in the first region is less than a predetermined threshold. When forming the sacrificial layer in the second region, the flow rate of the process gas containing the target element is a second flow rate greater than the first flow rate, so that the concentration of the target element in the sacrificial layer in the second region is greater than the concentration of the target element in the sacrificial layer in the first region.

9. The method for forming a stacked structure according to claim 8, characterized in that, The number of sacrificial layers in the second region is less than 10% of the total number of sacrificial layers.

10. The method for forming a stacked structure according to claim 8, characterized in that, The concentration of the target element in the sacrificial layer of the second region is 1.1 to 1.3 times the concentration of the target element in the sacrificial layer of the first region; or, The concentration difference of the target element in the sacrificial layer in the second region and the first region is 1% to 5%.

11. The method for forming a stacked structure according to any one of claims 8 to 10, characterized in that, The concentration of the target element in the sacrificial layer in the first region is 15% to 25%.

12. The method for forming a stacked structure according to any one of claims 8 to 10, characterized in that, When forming the sacrificial layer in the second region, the flow rates of the process gas containing the target element are all equal, so that the concentration of the target element in each sacrificial layer in the second region is equal; or, During the formation of the sacrificial layer in the second region, the flow rate of the process gas containing the target element is increased layer by layer so that the concentration of the target element in the sacrificial layer closer to the substrate in the second region is lower.

13. A semiconductor process apparatus, characterized in that, include: The process chamber, air intake assembly, air extraction assembly, and controller, wherein the controller includes at least one processor and at least one memory, the memory storing a computer program, which, when executed by the processor, implements the etching method for the stacked structure as described in any one of claims 1 to 7 or the method for forming the stacked structure as described in any one of claims 8 to 12.

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