A semiconductor device, a manufacturing method thereof, and an electronic apparatus
Patent Information
- Application Number
- CN202510416523.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2026-10-16
AI Technical Summary
[0003]然而，通过对栅极材料层进行刻蚀以形成栅极的方法对于栅极整体形貌(profile)的控制较为困难，其中，对于立体残留(3D Corner Residue，简称3DR)(在栅极侧壁、鳍片侧壁以及衬底三面组成的角落处的栅极材料层残留)的控制尤为困难
[0026]本申请实施例的半导体器件及其制造方法、电子装置，在栅极的侧壁形成保护层，暴露在栅极的侧壁、鳍片的侧壁和衬底组成的交界区域存在的栅极材料层的残留部，再以保护层为掩膜，去除残留部，能够有效改善3DR，进而能够避免因3DR存在导致外延晶体生长受限的问题和S2G short缺陷，同时能够减小寄生电容，提高了器件性能和可靠性，同时不会影响其他核心结构参数与后续工艺。
Smart Images
Figure CN122935145A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] Currently, for semiconductor devices such as 3D transistors, fins and gates (pseudo-gates) are sequentially formed on a substrate. When forming the gate, a gate material layer is generally deposited first, and then the gate material layer is etched to form the gate.
[0003] However, the method of forming the gate by etching the gate material layer is difficult to control the overall gate profile. In particular, the control of 3D Corner Residue (3DR) (the gate material layer residue at the corner formed by the gate sidewall, fin sidewall and substrate) is especially difficult.
[0004] 3DR restricts epitaxial crystal growth (source and drain epitaxial growth) and increases parasitic capacitance, affecting device performance. In addition, a large 3DR can also cause severe source-to-gate short (S2Gshort) defects, leading to device failure.
[0005] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention
[0006] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0007] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising:
[0008] A substrate is provided on which fins and a gate spanning the fins are formed, wherein a residual portion of the gate material layer exists in the interface region formed by the sidewall of the gate, the sidewall of the fins, and the substrate;
[0009] A protective layer is formed on the sidewall of the gate to expose the residual portion;
[0010] Using the protective layer as a mask, the residual portion is removed.
[0011] Exemplarily, the protective layer is formed on the sidewall of the gate to expose the residual portion, including:
[0012] A protective material layer is deposited, the protective material layer covering the gate and the residual portion;
[0013] The protective material layer is processed to form the protective layer on the sidewall of the gate and at least expose the residual portion.
[0014] Exemplarily, processing the protective material layer to form the protective layer on the sidewall of the gate and at least expose the residual portion includes:
[0015] An etch-back process is used to remove the protective material layer on the top surface of the gate and the residual portion to form the protective layer on the sidewall of the gate and expose the residual portion and the top surface of the gate.
[0016] Exemplarily, the gate spanning the fin is formed on the substrate by the following steps:
[0017] Forming the gate material layer covering the fins and the substrate;
[0018] A patterned hard mask layer is formed on the gate material layer;
[0019] Using the hard mask layer as a mask, the gate material layer is etched to form the gate spanning the fin, wherein a residual portion of the gate material layer exists in the interface region formed by the sidewall of the gate, the sidewall of the fin, and the substrate.
[0020] For example, a wet etching process is used to remove the residual portion.
[0021] For example, the etching solution in the wet etching process includes diluted hydrofluoric acid and ozone-containing deionized water.
[0022] For example, after removing the residue, the method further includes the step of forming a sidewall layer on the sidewall of the gate, the sidewall layer covering the protective layer.
[0023] For example, the protective layer has the same material as the sidewall layer.
[0024] This application also provides a semiconductor device, which is manufactured using the method described above.
[0025] In another aspect, this application provides an electronic device, which includes the semiconductor device described above.
[0026] The semiconductor device and its manufacturing method, and electronic device of the present application embodiment form a protective layer on the sidewall of the gate, expose the residual portion of the gate material layer in the junction region composed of the sidewall of the gate, the sidewall of the fin, and the substrate, and then remove the residual portion using the protective layer as a mask. This can effectively improve 3DR, thereby avoiding the problem of limited epitaxial crystal growth and S2G short defects caused by the presence of 3DR. At the same time, it can reduce parasitic capacitance, improve device performance and reliability, and does not affect other core structural parameters and subsequent processes. Attached Figure Description
[0027] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0028] In the attached image:
[0029] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown;
[0030] Figures 2A-2E The diagram shows a projection schematic of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application;
[0031] Figures 3A-3E The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.
[0032] Explanation of reference numerals in the attached figures:
[0033] 200-Substrate, 201-Well region, 202-Shallow trench isolation structure, 203-Gate material layer, 2031-Residue, 204-Nitride layer, 205-Oxide layer, 206-Fin, 207-Gate, 208-Protective material layer, 209-Protective layer. Detailed Implementation
[0034] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0038] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.
[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0040] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0041] In related technologies, a gate material layer is typically deposited first, and then etched to form the gate (pseudo-gate). During this process, due to limitations in spatial structure and process technology, residual gate material layers may occur at the corners formed by the gate sidewalls, fin sidewalls, and substrate (i.e., 3DR), which affects device performance and reliability.
[0042] In related technologies, 3DR is generally improved by over-etching, but over-etching has a significant impact on the overall gate morphology. Therefore, a trade-off must be made between 3DR and other core structural parameters, making it difficult to achieve a balance.
[0043] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 1 As shown, it mainly includes the following steps:
[0044] Step S1: Provide a substrate on which fins and a gate spanning the fins are formed, wherein a residual portion of the gate material layer exists in the junction region formed by the sidewall of the gate, the sidewall of the fins, and the substrate.
[0045] Step S2: A protective layer is formed on the sidewall of the gate to expose the residual portion;
[0046] Step S3: Using the protective layer as a mask, remove the residual parts.
[0047] The semiconductor device manufacturing method of this application forms a protective layer on the sidewall of the gate, exposes the residual portion of the gate material layer in the interface region composed of the sidewall of the gate, the sidewall of the fin, and the substrate, and then removes the residual portion using the protective layer as a mask. This can effectively improve 3DR, thereby avoiding the problem of limited epitaxial crystal growth and S2Gshort defects caused by the presence of 3DR. At the same time, it can reduce parasitic capacitance, improve device performance and reliability, and does not affect other core structural parameters and subsequent processes.
[0048] Below, for reference Figure 1 , Figures 2A-2E as well as Figures 3A-3E The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Figures 2A-2E The diagram shows a projected schematic of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Figures 3A-3E The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.
[0049] For example, the method for manufacturing the semiconductor device of this application includes the following steps:
[0050] First, execute step S1, as follows: Figure 2B and Figure 3B As shown, a substrate 200 is provided, on which a gate 207 is formed along and across a fin 206. A residual portion 2031 of the gate material layer exists in the interface region formed by the sidewall of the gate 207, the sidewall of the fin 206, and the substrate 200. Exemplarily, the gate 207 is obtained by etching the gate material layer.
[0051] The semiconductor device in this application can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of this application is explained and illustrated mainly by taking the case of a three-dimensional transistor as the semiconductor device.
[0052] In one example, substrate 200 is a silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, substrate 200 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form substrate 200 have been described herein, any material that can serve as substrate 200 falls within the spirit and scope of this application.
[0053] In one example, the method for forming fin 206 includes the following steps: forming a patterned mask layer on the surface of substrate 200, the patterned mask layer defining the pattern of fin 206, including the width, length, and position of fin 206; etching substrate 200 using the patterned mask layer as a mask to form fin 206; and then removing the mask layer. It should be noted that the method for forming fin 206 is merely exemplary and is not limited to the methods described above.
[0054] In one example, fin 206 extends along a first direction, and gate 207 extends along a second direction intersecting the first direction. Exemplarily, the second direction is perpendicular to the first direction. Exemplarily, Figures 2A-2E The diagram shown is a projection along a direction perpendicular to the extension direction of the fin 206 (i.e., perpendicular to the first direction). When the second direction is perpendicular to the first direction, Figures 2A-2E The diagram shown is a projection along the second direction; Figures 3A-3E The diagram shown is a cross-sectional view along the first direction.
[0055] In one example, such as Figures 2A-2B as well as Figures 3A-3B As shown, a gate 207 spanning the fin 206 is formed on a substrate 200 through the following steps: forming a gate material layer 203 covering the fin 206 and the substrate 200; forming a patterned hard mask layer on the gate material layer 203; and etching the gate material layer 203 using the hard mask layer as a mask to form the gate 207 spanning the fin 206. A residual portion 2031 of the gate material layer 203 exists at the interface region formed by the sidewall of the gate 207, the sidewall of the fin 206, and the substrate 200. Exemplarily, Figure 2A In the schematic diagram shown, the fins are obscured by the gate material layer 203.
[0056] In one example, a patterned hard mask layer can be formed by the following steps: First, a hard mask layer is formed using various deposition processes commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD); then, the hard mask layer is patterned to obtain a patterned hard mask layer, for example, a patterned photoresist layer is formed on the hard mask layer using a photolithography process, and the patterned photoresist layer is used as a mask to etch the hard mask layer to obtain a patterned hard mask layer.
[0057] In one example, such as Figure 2A and Figure 3A As shown, the hard mask layer includes a nitride layer 204 and an oxide layer 205 stacked from bottom to top, wherein the nitride layer 204 is located on the gate material layer 203, and the oxide layer 205 is located on the nitride layer 204. Exemplarily, the nitride layer 204 is made of silicon nitride, and the oxide layer 205 is made of silicon oxide. In other embodiments, the hard mask layer may be a single film layer or a composite film layer of three or more layers. For example, the hard mask layer may be a single nitride layer, or it may be a three-layer composite film layer of nitride layer-oxide layer-nitride layer.
[0058] In one example, a commonly used etching process in the art (e.g., dry etching) can be used to etch the gate material layer 203 to form the gate 207. Exemplarily, the gate 207 is a dummy gate, and the material of the gate 207 includes amorphous silicon (α-Si). Exemplarily, the regions of the fins 206 located on both sides of the gate 207 are used as the source region and the drain region, respectively.
[0059] In one example, such as Figures 2A-2E as well as Figures 3A-3E As shown, a well region 201 and a shallow trench isolation (STI) structure 202 are also formed in the substrate 200. Exemplarily, the shallow trench isolation structure 202 is made of silicon oxide and serves as electrical isolation. Exemplarily, the well region 201 can be formed in the substrate 200 using an ion implantation process.
[0060] In one example, such as Figure 2B and Figure 3BAs shown, when etching the gate material layer 203 to form the gate 207, due to the limitations of the spatial structure and process, the gate material layer 203 at the junction region formed by the sidewall of the gate 207, the sidewall of the fin 206 and the substrate 200 is difficult to be completely etched, resulting in the presence of a residual portion 2031 (i.e., 3DR) of the gate material layer 203 in the junction region formed by the sidewall of the gate 207, the sidewall of the fin 206 and the well region 201, and the junction region formed by the sidewall of the gate 207, the sidewall of the fin 206 and the shallow trench isolation structure 202.
[0061] Next, proceed to step S2, as follows: Figure 2D and Figure 3D As shown, a protective layer 209 is formed on the sidewall of the gate 207, exposing the residual portion 2031.
[0062] In one example, such as Figures 2C to 2D as well as Figures 3C to 3D As shown, a protective layer 209 is formed on the sidewall of the gate 207, exposing the residual portion 2031. This includes: depositing a protective material layer 208, which covers the gate 207 and the residual portion 2031; and processing the protective material layer 208 to form the protective layer 209 on the sidewall of the gate 207 and at least expose the residual portion 2031. Specifically, the protective material layer 208 covers the top surface and sidewall of the gate 207 and the residual portion 2031. Exemplarily, the protective material layer 208 also covers a portion of the surface of the fin 206 and the substrate 200, and more specifically, the protective material layer 208 also covers the top surface and sidewall of the fin 206 and a portion of the surface of the well region 201 and the shallow trench isolation structure 202. Exemplarily, various deposition processes commonly used in the art can be used to form the protective material layer 208, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0063] In one example, such as Figure 2C As shown, in a projection along a direction perpendicular to the extension direction of the fin 206, the protective material layer 208 on the sidewall of the fin 206 will obscure the fin 206. To more clearly illustrate the relative positions of the fin 206, the gate 207, and the protective material layer 208, in Figure 2C , Figure 2D as well as Figure 2E The protective material layer 208 on the sidewall of the fin 206 is omitted in the projected schematic diagrams shown.
[0064] In one example, processing the protective material layer 208 to form a protective layer 209 on the sidewall of the gate 207 and at least expose the residual portion 2031 includes: using an etch-back process to remove the protective material layer 208 on the top surface of the gate 207 and the residual portion 2031, to form a protective layer 209 on the sidewall of the gate 207 and expose the residual portion 2031 and the top surface of the gate 207. Exemplarily, when a hard mask layer is formed on the top surface of the gate 207, exposing the top surface of the gate 207 here refers to exposing the hard mask layer on the top surface of the gate 207.
[0065] Specifically, a dry etching process can be used to etch back towards the substrate 200. During this process, the horizontal portion of the protective material layer 208 (the portion parallel to the surface of the substrate 200) is consumed faster, while the vertical portion of the protective material layer 208 (the portion perpendicular to the surface of the substrate 200) is consumed slower. The residual portion 2031 protrudes horizontally from the sidewall of the gate 207. The portion of the protective material layer 208 on the residual portion 2031 can be considered as the horizontal portion of the protective material layer 208, meaning that the protective material layer 208 on the residual portion 2031 is consumed relatively quickly. The protective material layer 208 on the top surface of the gate 207 and the residual portion 2031 is the horizontal portion of the protective material layer 208, and the protective material layer 208 on the sidewall of the gate 207 is the vertical portion of the protective material layer 208. In the etch-back process, the protective material layer 208 on the top surface of 207 and the residual portion 2031 is consumed even faster, causing the protective material layer 208 on the top surface of the gate 207 and the residual portion 2031 to be removed, while the protective material layer 208 on the sidewall of the gate 207 is retained to form the protective layer 209. That is, the remaining protective material layer 208 on the sidewall of the gate 207 serves as the protective layer 209.
[0066] In one example, when the deposited protective material layer 208 still covers part of the surface of the substrate 200 and the fin 206, the protective material layer 208 on the surface of the substrate 200 and the top surface of the fin 206 is the horizontal portion of the protective material layer 208, and the protective material layer 208 on the sidewall of the fin 206 is the vertical portion of the protective material layer 208. In the etch-back process, the protective material layer 208 on the surface of the substrate 200 and the top surface of the fin 206 is consumed faster. The protective material layer 208 on the surface of the substrate 200 and the top surface of the fin 206 is removed, while the protective material layer 208 remains on the sidewall of the fin 206.
[0067] Next, proceed to step S3, as follows: Figure 2E and Figure 3EAs shown, using the protective layer 209 as a mask, the residual portion 2031 (the residual portion 2031 is the 3DR) is removed. Exemplarily, during the removal of the residual portion 2031, the protective layer 209 on the sidewall of the gate 207 protects the sidewall of the gate 207; simultaneously, during the removal of the residual portion 2031, the hard mask layer on the top surface of the gate 207 protects the top surface of the gate 207. That is, during the removal of the residual portion 2031, the protective layer 209 on the sidewall of the gate 207 and the hard mask layer on the top surface of the gate 207 work together to protect the gate 207, preventing it from being etched.
[0068] In one example, a wet etching process is used to remove the residual portion 2031. The etching solution used in the wet etching process includes diluted hydrofluoric acid (DHF) and ozone-containing deionized water (DIO3).
[0069] In one example, this application uses the protective layer 209 as a mask to remove the residual portion 2031, which can effectively improve 3DR, thereby avoiding the problem of subsequent epitaxial crystal growth being limited due to the presence of 3DR. At the same time, it can reduce parasitic capacitance and improve device performance. Due to the improvement of 3DR, it can also effectively avoid S2G short (short circuit between epitaxial crystal and gate 207) defect.
[0070] In one example, after removing the residual portion 2031, the process further includes forming a sidewall layer on the sidewall of the gate 207, the sidewall layer covering the protective layer 209. Exemplarily, the sidewall layer also covers the fin 206. Exemplarily, the protective layer 209 and the sidewall layer have the same material (e.g., both the protective layer 209 and the sidewall layer can be made of silicon oxide), meaning the protective layer 209 can serve as part of the sidewall layer without affecting other core structures of the device and subsequent processes. Exemplarily, various deposition processes commonly used in the art can be employed to form the sidewall layer, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). For example, since the protective layer 209 exists as part of the sidewall layer, the deposition thickness of the sidewall layer should be modified accordingly when depositing to form the sidewall layer (e.g., appropriately reducing the deposition thickness of the sidewall layer on the sidewall of the gate 207) so that the other core structural parameters after the sidewall layer deposition, except for 3DR, are substantially consistent with the existing process, such as making the overall thickness of the sidewall layer substantially consistent with the prior art.
[0071] In one example, the steps of forming a protective layer 209 on the sidewall of the gate 207 and removing the residual portion 2031 (e.g., using an etch-back process to remove the protective material layer 208 on the top surface of the gate 207 and the residual portion 2031 to form a protective layer 209 on the sidewall of the gate 207, and using a wet etching process to remove the residual portion 2031) consume a hard mask layer, for example, an oxide layer 205. Therefore, when depositing the hard mask layer, the deposition thickness of the hard mask layer should be modified accordingly (e.g., appropriately increasing the deposition thickness of the hard mask layer) so that the core structural parameters after the sidewall layer deposition, except for 3DR, are substantially consistent with the existing process. For example, the remaining thickness of the hard mask layer after the step of removing the residual portion 2031 is substantially consistent with the existing process.
[0072] In one example, after forming the sidewall layer, there is a step of growing epitaxial crystal, such as growing a source-drain epitaxial layer. Since the residual portion 2031 is removed in the aforementioned step, the 3DR is effectively improved, thereby avoiding the problem of limited epitaxial crystal growth due to the presence of 3DR. At the same time, due to the improvement of 3DR, the S2G short defect can also be effectively avoided.
[0073] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The preparation of a complete semiconductor device may also include other steps, such as dummy gate removal and metal gate filling processes, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0074] In summary, the semiconductor device manufacturing method of this application forms a protective layer on the sidewall of the gate, exposes the residual portion of the gate material layer in the interface region formed by the sidewall of the gate, the sidewall of the fin, and the substrate, and then removes the residual portion using the protective layer as a mask. This can effectively improve 3DR, thereby avoiding the problem of limited epitaxial crystal growth and S2G short defects caused by the presence of 3DR. At the same time, it can reduce parasitic capacitance, improve device performance and reliability, and does not affect other core structural parameters and subsequent processes.
[0075] This application also provides a semiconductor device manufactured by the method described in Embodiment 1 above. Since the device of this application is manufactured using the aforementioned method, it has the same advantages as the aforementioned method.
[0076] The semiconductor device in this application can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of this application is explained and illustrated mainly by taking the case of a three-dimensional transistor as the semiconductor device.
[0077] The semiconductor device of this application embodiment is manufactured using the above method. A protective layer is formed on the sidewall of the gate, exposing the residual portion of the gate material layer in the junction region formed by the sidewall of the gate, the sidewall of the fin, and the substrate. The residual portion is then removed using the protective layer as a mask. This can effectively improve 3DR, thereby avoiding the problem of limited epitaxial crystal growth and S2G short defects caused by the presence of 3DR. At the same time, it can reduce parasitic capacitance, improve device performance and reliability, and does not affect other core structural parameters and subsequent processes.
[0078] In another embodiment of this application, an electronic device is provided, which includes the aforementioned semiconductor device.
[0079] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including the aforementioned semiconductor devices. The electronic device in this application embodiment has better performance because it uses the aforementioned semiconductor devices.
[0080] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided on which fins and a gate spanning the fins are formed, wherein a residual portion of the gate material layer exists in the interface region formed by the sidewall of the gate, the sidewall of the fins, and the substrate; A protective layer is formed on the sidewall of the gate to expose the residual portion; Using the protective layer as a mask, the residual portion is removed.
2. The manufacturing method according to claim 1, characterized in that, The protective layer is formed on the sidewall of the gate to expose the residual portion, including: A protective material layer is deposited, the protective material layer covering the gate and the residual portion; The protective material layer is processed to form the protective layer on the sidewall of the gate and at least expose the residual portion.
3. The manufacturing method according to claim 2, characterized in that, Processing the protective material layer to form the protective layer on the sidewall of the gate and at least expose the residual portion includes: An etch-back process is used to remove the protective material layer on the top surface of the gate and the residual portion to form the protective layer on the sidewall of the gate and expose the residual portion and the top surface of the gate.
4. The manufacturing method according to claim 1, characterized in that, The gate spanning the fin is formed on the substrate by the following steps: Forming the gate material layer covering the fins and the substrate; A patterned hard mask layer is formed on the gate material layer; Using the hard mask layer as a mask, the gate material layer is etched to form the gate spanning the fin, wherein a residual portion of the gate material layer exists in the interface region formed by the sidewall of the gate, the sidewall of the fin, and the substrate.
5. The manufacturing method according to claim 1, characterized in that, The residual portion is removed using a wet etching process.
6. The manufacturing method according to claim 5, characterized in that, The etching solution used in the wet etching process includes diluted hydrofluoric acid and ozone-containing deionized water.
7. The manufacturing method according to claim 1, characterized in that, After removing the residue, the process further includes forming a sidewall layer on the sidewall of the gate, the sidewall layer covering the protective layer.
8. The manufacturing method according to claim 7, characterized in that, The protective layer has the same material as the sidewall layer.
9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.
10. An electronic device, characterized in that, The electronic device includes the semiconductor device of claim 9.