Wafer and method of dicing the same

Abstract

The present application provides a wafer and a wafer cutting method. The wafer of the present application is designed to have a test key adjacent to one side of a cutting path. The wafer of the present application combines the existing cutting path and the empty area on both sides of the test key in the wafer design. Therefore, the wafer cutting method of the present application does not need to perform the laser slotting in the prior art, and can directly perform plasma cutting along the cutting path. The wafer cutting method of the present application reduces the process of laser slotting, reduces the cost, and does not need to perform the wafer slicing process after laser slotting, thereby reducing the risk of wafer cracking and chip unit failure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a wafer and a method for cutting the wafer. Background Technology

[0002] Semiconductor wafer manufacturing involves creating complex electronic circuits on silicon wafers and designing test keys on the dicing ridges for chip functional testing. In the semiconductor packaging stage, the entire wafer needs to be diced into chip units. Plasma etching is a relatively new wafer dicing technology that uses plasma etching to create narrow dicing grooves in the wafer dicing ridges, separating the chip units. Compared to traditional blade dicing, it can simultaneously diced all chip units on the entire wafer in one go, eliminating the need for sequential dicing of all ridges. Its dicing speed is independent of chip size, only related to wafer thickness, resulting in a significant increase in dicing speed and representing a revolution in existing dicing technologies. This technology can minimize back-side chipping and chip breakage during chip unit dicing, significantly improving chip unit strength.

[0003] However, plasma cutting technology can only be applied to semiconductor materials such as silicon or silicon nitride, and cannot be used on the metal layer of the test bond within the cutting path, such as... Figure 1 As shown, the current wafer test key 12 is designed in the middle of the dicing channel 13. For example, the width of the dicing channel 13 is 60μm, and the width of the test key 12 is 30μm. It is about 15μm away from the safety walls (SR, Sealring) of the chip units 10 on both sides (i.e. the width of the open area 11). When separating the chip units 10, symmetrical cutting is required, that is, the dicing groove is located in the middle of the dicing channel 13. Therefore, before plasma cutting, laser grooving must be performed to burn off the test key 12 in the middle of the dicing channel 13. Only then can plasma cutting technology be used to separate the chip units 10, which increases the process and cost. Moreover, after laser grooving, the wafer thinning process may crack, which may lead to the failure of the chip units 10. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer and its dicing method to solve the problems in the prior art where the wafer test bond is designed in the middle of the dicing channel. Before plasma dicing, laser grooving must be performed to burn off the test bond in the middle of the dicing channel before plasma dicing technology can be used to separate the chip unit, which increases the process and cost. Furthermore, since the wafer thinning process is after laser grooving, it is easy to cause wafer cracking, which leads to chip unit failure.

[0005] To achieve the above and other related objectives, the present invention provides a wafer comprising a plurality of chip units, wherein a dicing track and a test key are disposed between two adjacent chip units, and the test key is adjacent to one side of the dicing track.

[0006] Optionally, the width of the cutting channel is greater than 22 μm.

[0007] Optionally, a safety wall is provided on the side of the chip unit near the cutting channel, and there is an open area between the test key and the safety wall.

[0008] Furthermore, the width of the open area is not less than 5 μm.

[0009] Optionally, the width of the test key is 25μm to 35μm.

[0010] Optionally, the test key is a multilayer metal structure with two or more layers.

[0011] The present invention also provides a wafer dicing method, characterized in that the dicing method includes:

[0012] S1, providing a wafer as described in any of the above;

[0013] S2, the wafer is cut along the cutting path using a plasma cutting process.

[0014] Optionally, in step S2, before cutting the wafer along the cutting path using plasma cutting technology, a step of back-side thinning of the substrate of the wafer is further included.

[0015] Further, in step S2, the method of cutting the wafer along the cutting path using plasma cutting technology includes:

[0016] S21, apply protective tape to the upper surface of the wafer;

[0017] S22, perform back-side thinning on the substrate of the wafer;

[0018] S23, the wafer is fixed on the dicing platform using adhesive tape;

[0019] S24, the wafer is cut along the dicing track using a plasma cutting process to completely separate the dicing track.

[0020] Optionally, in step S2, when the wafer is cut along the dicing channel using plasma cutting technology, a dicing groove is formed in the dicing channel, and the width of the dicing groove is 12μm to 18μm.

[0021] As described above, the wafer and its dicing method of the present invention have the following beneficial effects: The wafer of the present invention is designed to have the test bond adjacent to one side of the dicing track, that is, to combine the empty areas on both sides of the dicing track and the test bond in the existing wafer design to form the dicing track of the present invention. Therefore, the wafer dicing method of the present invention does not require laser grooving as in the prior art, and plasma dicing can be performed directly along the dicing track, reducing the laser grooving process and lowering costs. Furthermore, the present invention does not require wafer thinning after laser grooving, reducing the risk of wafer cleaving and chip cell failure. Attached Figure Description

[0022] Figure 1 The diagram shows a schematic representation of the surface structure of a wafer in the prior art.

[0023] Figure 2 The diagram shown is a schematic representation of the surface structure of the wafer of this invention.

[0024] Figure 3 The diagram shown is a schematic flowchart of the wafer dicing method of the present invention.

[0025] Component designation explanation

[0026] 10 and 20 chip units

[0027] 11, 21 Open areas

[0028] 12, 22 Test keys

[0029] Cutting channels 13 and 23

[0030] Steps S1 to S2 Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Please see Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] This embodiment provides a wafer, such as Figure 2As shown, the wafer includes a plurality of chip units 20, and a dicing channel 23 and a test key 22 are provided between two adjacent chip units 20, with the test key 22 adjacent to one side of the dicing channel 23.

[0034] In this embodiment, the wafer is designed to have the test key adjacent to one side of the dicing track. This combines the empty areas on both sides of the dicing track and the test key in the existing wafer design to form the dicing track in this embodiment. In subsequent wafer dicing operations, there is no need to perform laser grooving. Plasma dicing can be performed directly along the dicing track, reducing the laser grooving process and lowering costs.

[0035] As an example, considering the precision of plasma cutting and the fluctuation of the cutting groove width, the width of the cutting groove 23 is designed to be greater than 22μm to ensure sufficient space during plasma cutting and to avoid contact between the cutting tool and the internal structure of the chip unit 20, thereby reducing the risk of mechanical damage and contamination.

[0036] As an example, a safety wall (not shown) is provided on the side of the chip unit 20 near the dicing channel 23. This safety wall prevents mechanical damage to the internal structure of the chip unit 20 from subsequent processes, and also shields the chip unit 20 from external interference, prevents moisture intrusion, and provides electrostatic protection. An open area 21 is provided between the test key 22 and the safety wall. The width of the open area 21 is, for example, not less than 5 μm, to ensure that the test key 22 will not damage the safety wall, thereby maintaining the integrity and function of the safety wall.

[0037] As an example, the width of the test key 22 is 25μm to 35μm to ensure that electrical and physical characteristics can be effectively tested during the test, while avoiding unnecessary impact on the adjacent chip units 20.

[0038] As an example, the test key 22 is a multilayer metal structure with two or more layers. The specific materials include, but are not limited to, copper (Cu), aluminum (Al) or titanium (Ti), to provide sufficient conductivity and mechanical strength while meeting different testing requirements.

[0039] This embodiment also provides a wafer dicing method for dicing the aforementioned wafer, but it is not limited to this; other suitable dicing methods are also possible. The foregoing content can be quoted in its entirety here, and for the sake of brevity, it will not be repeated below. Figure 3 As shown, the cutting method includes:

[0040] S1 provides the wafer as described above;

[0041] S2, the wafer is cut along the cutting path using a plasma cutting process.

[0042] In this embodiment of the wafer dicing method, the test bond is adjacent to one side of the dicing track in the wafer design. That is, the empty areas on both sides of the dicing track and the test bond in the existing wafer design are combined to form the dicing track of this embodiment. When dicing the wafer, there is no need to perform laser grooving. Plasma dicing can be performed directly along the dicing track, reducing the laser grooving process in the prior art and reducing costs.

[0043] As an example, before the wafer is cut along the dicing track 23 using plasma cutting, a back-side thinning step is included on the substrate of the wafer. Compared with the prior art wafer thinning process after laser grooving, this reduces the risk of wafer cleaving and chip cell failure.

[0044] As a specific example, a method for cutting the wafer along the dicing track 23 using a plasma cutting process includes:

[0045] S21, apply protective tape to the upper surface of the wafer to reduce or even prevent scratches, contamination, etc. on the surface of the wafer circuit during subsequent operations.

[0046] S22, perform back-side thinning on the substrate of the wafer to grind the wafer to a thickness required by the customer.

[0047] S23, the wafer is fixed to the dicing platform by tape, for example, the wafer is fixed to the center of a metal frame by tape. During subsequent dicing, the wafer is fixed to the dicing platform by the frame, and the tape can also serve as a substrate.

[0048] S24, the wafer is cut along the dicing track 23 using a plasma cutting process to completely separate the dicing track.

[0049] When the wafer is cut along the dicing track 23 using plasma cutting technology, a dicing groove is formed in the dicing track 23. For example, the width of the dicing groove is generally 12μm to 18μm to ensure that the plasma cutting process can complete the wafer cutting task efficiently and accurately, while minimizing damage to the chip unit 20 and potential impact on the performance of the chip unit 20.

[0050] In summary, the wafer of this invention is designed to have the test bond adjacent to one side of the dicing track. This combines the empty areas on both sides of the dicing track and the test bond in existing wafer designs to form the dicing track of this invention. Therefore, the wafer dicing method of this invention eliminates the need for laser grooving as in the prior art, allowing direct plasma dicing along the dicing track. This reduces the laser grooving process, lowers costs, and eliminates the need for wafer thinning after laser grooving, reducing the risk of wafer cleaving and chip unit failure. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer, characterized in that: The wafer includes a plurality of chip units, and a dicing channel and a test key are provided between two adjacent chip units, with the test key adjacent to one side of the dicing channel.

2. The wafer according to claim 1, characterized in that: The width of the cutting channel is greater than 22 μm.

3. The wafer according to claim 1, characterized in that: A safety wall is provided on the side of the chip unit near the cutting channel, and there is an open area between the test key and the safety wall.

4. The wafer according to claim 3, characterized in that: The width of the open area is not less than 5μm.

5. The wafer according to claim 1, characterized in that: The width of the test key is 25μm to 35μm.

6. The wafer according to claim 1, characterized in that: The test key has a structure of two or more metal layers.

7. A wafer dicing method, characterized in that, The cutting method includes: S1, providing a wafer as described in any one of claims 1 to 6; S2, the wafer is cut along the cutting path using a plasma cutting process.

8. The wafer dicing method according to claim 7, characterized in that: In step S2, before cutting the wafer along the cutting path using plasma cutting technology, a back-side thinning step is also included on the substrate of the wafer.

9. The wafer dicing method according to claim 8, characterized in that, In step S2, the method of cutting the wafer along the cutting path using plasma cutting technology includes: S21, apply protective tape to the upper surface of the wafer; S22, perform back-side thinning on the substrate of the wafer; S23, the wafer is fixed on the dicing platform using adhesive tape; S24, the wafer is cut along the dicing track using a plasma cutting process to completely separate the dicing track.

10. The wafer dicing method according to claim 7, characterized in that: In step S2, when the wafer is cut along the dicing channel using plasma cutting technology, a dicing groove is formed in the dicing channel, and the width of the dicing groove is 12μm to 18μm.

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