A method and wafer dicing carrier structure for reducing post-dicing residue and particles on a chip surface

Abstract

The present application relates to chip surface particle control technical field, specifically to a kind of method for reducing chip surface residual glue and particle and wafer cutting carrier structure, wherein a kind of method for reducing chip surface residual glue and particle includes the following steps: S1, film pasting;S2, cutting;S3, UV pretreatment;S4, ladder structure preparation;S5, surface reduction;S6, cleaning.The present application provides a kind of method for reducing chip surface residual glue and particle, by increasing particle control measures before plasma activation procedure, make the exposed adhesion layer surface layer in cutting groove partially solidify, while retaining enough adhesion of the adhesion layer below chip to prevent chip offset, again quantitatively remove the solidified layer to form ladder structure, directly remove the particle that has been attached to the surface of solidified layer before plasma activation, ensure the exposed area of smaller ladder side, significantly reduce the number of newly added particles due to adhesion layer shedding when subsequent plasma activation.

Description

Technical Field

[0001] This invention relates to the field of chip surface particle control technology, and in particular to a method for reducing residual adhesive and particles on chip surfaces and a wafer dicing carrier structure. Background Technology

[0002] In an era of explosive growth in data and computing power demands, High Bandwidth Memory (HBM), with its high bandwidth and low power consumption, has become the core of new memory solutions in fields such as artificial intelligence and high-performance computing, leading to a surge in market demand. In the HBM manufacturing process, chip-to-wafer (D2W) advanced packaging is a mainstream process, and its packaging quality directly determines the functionality and reliability of the final memory device. Before packaging, a dicing (or dicing) technique is used to divide the entire wafer into multiple independent chips. The cleanliness of the chip surface directly affects the effectiveness and yield of subsequent interconnection, bonding, and other packaging processes. Therefore, reducing particulate contamination on the chip surface and improving its cleanliness are essential.

[0003] To maintain process integrity, existing chip interconnect pretreatment processes typically include the following steps: Before dicing, a UV adhesive film is pre-attached to the back of the wafer to provide temporary fixation and support; then, wafer dicing is performed. Under the fixed constraint of the UV adhesive film, the wafer will not shift or misalign during the dicing process, thus ensuring dicing accuracy; after dicing, plasma activation (e.g., spraying plasma gas onto the chip surface to improve surface energy and enhance the adhesion of subsequent materials), cleaning (using deionized water to clean the chip surface to remove some contaminants), and back-side debonding (using a UV light source to irradiate the back of the wafer, causing the UV adhesive film's adhesion layer to solidify and lose adhesion, making it easier to separate the chip from the adhesive film).

[0004] In the above process, after the wafer dicing process, dicing grooves are formed between adjacent chips. The UV film adhesion layer below the dicing groove is directly exposed because it is no longer shielded by the wafer above. During the subsequent plasma activation process, high-energy ions bombard the exposed UV film adhesion layer in the dicing groove. The UV film adhesion layer contains prepolymers such as epoxy acrylate and acrylic resin. The weak bonds (such as hydrogen bonds) between the C=O and C=N double bond groups on its molecular chain break under the bombardment of high-energy ions, causing a large number of polymer molecules to detach from the adhesion layer surface and aggregate to form particles that adhere to the surface and sides of the chip. Because these particles are sticky and in direct contact with the UV film adhesion layer in the dicing groove, there is an adhesion between the two, making the particles extremely difficult to remove. In addition, the number of particles that were already attached to the adhesion layer surface before plasma activation will further increase under the above bombardment, making the particle contamination problem on the chip surface even more serious.

[0005] Therefore, a cleaning process is required after plasma activation to remove particles. However, in the cleaning process, to avoid damaging the fine patterns on the chip surface, highly corrosive solutions such as sulfuric acid (H2SO4) are generally not used. Instead, milder cleaning media such as deionized water are mainly relied upon. This results in limited removal of the aforementioned sticky particles that are in close contact with the UV film adhesion layer. The particles remaining on the chip surface will form voids at the bonding interface during subsequent interconnect processes, affecting the reliability of the interconnect and, in severe cases, directly causing the chip to be scrapped.

[0006] In addition, existing technologies have proposed several improvement solutions to address the aforementioned particle problem. For example, a method for controlling chip surface particles in hybrid bonding (publication number CN120637222A) uses laser irradiation to modify the blue film between adjacent chips after wafer dicing, and then combines chemical wet cleaning to remove the exposed blue film adhesion layer, thereby suppressing particle generation during plasma activation. Another example is a study (ACS Applied Electronic Materials, Vol. 8, 2026, pp. 378-389) that proposes to perform UV pretreatment on the UV film from the front side of the wafer before plasma activation, so that the exposed adhesion layer is cured to improve its resistance to plasma bombardment. However, the former relies on a combination of laser modification and wet cleaning, which is a complex process. Laser irradiation and chemical cleaning can easily damage the chip surface, and the degree of removal of the adhesive layer is not quantitatively controlled, resulting in a large exposed area on the side of the adhesive layer under the chip, and the risk of new particles is still high. The latter only improves the stability of the adhesive layer by curing, which cannot remove particles that have already adhered to the surface of the adhesive layer before plasma activation, and its curing degree also lacks quantitative control methods.

[0007] Therefore, how to effectively control particles during chip processing, especially to suppress or eliminate the sticky particles that are difficult to remove formed by the shedding of the UV film adhesion layer during plasma activation, improve the cleanliness of the chip surface, and avoid the generation of interconnect voids, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0008] To address the aforementioned technical problems, embodiments of the present invention provide a method and wafer dicing carrier structure for reducing residual adhesive and particles on the chip surface, thereby removing particles already attached to the adhesion layer before plasma activation and reducing the risk of new particles during plasma activation.

[0009] According to one aspect, in order to achieve the above objective, embodiments of the present invention provide a method for reducing adhesive residue and particles on a chip surface, comprising the following steps: S1. Film application: Fix the base layer of the UV film to the frame and fix the wafer to the adhesive layer of the UV film; S2. Cutting: The wafer is cut into several chips, and a cutting groove is formed between adjacent chips; S3, UV pretreatment: Irradiate the front side of the wafer with a UV light source to cure the surface of the exposed adhesive layer in the dicing groove into a cured layer; The UV pretreatment irradiation time is predetermined by refractive index calibration: the refractive index of the adhesion layer in the unirradiated state is determined as n1, the refractive index when the refractive index stops rising is determined as n2, and the irradiation time corresponding to the point where the refractive index stops rising is determined as t2. In step S3, the irradiation time of the wafer front side is 20% to 80% of t2, so that the refractive index of the adhesion layer in the dicing groove after irradiation is in the range of n1+(n2-n1)×0.2 to n1+(n2-n1)×0.8, and is in a partially cured state, so as to control the thickness of the cured layer; while the adhesion layer under the chip still maintains a low degree of cross-linking to maintain adhesion to the chip and prevent the chip position from shifting during the processing. S4. Step structure preparation: Quantitatively remove the cured layer in the cutting groove to form a step structure with a height of 2% to 20% of the thickness of the adhesive layer between the surface of the cured layer and the surface of the adhesive layer below the wafer, so as to remove the particles that have been attached to the surface of the cured layer before plasma activation, and control the exposed area of ​​the side of the adhesive layer step in the cutting groove to reduce the number of new particles during plasma activation. S5. Surface reduction: Remove the oxide film on the surface of the chip; S6. Washing: Wash with water to remove remaining particles.

[0010] In one possible implementation, the refractive index calibration in step S3 is performed in advance in the following manner: Under calibration conditions U1 where the irradiation wavelength, irradiation range, irradiation distance, and illuminance of the UV light source are all fixed, the refractive index of the adhesive layer of the UV film is measured at different irradiation durations. The refractive index first increases and then stabilizes as the irradiation duration increases. Step S3 is performed under the calibration conditions U1, based on the irradiation conditions set by n1, n2 and t2 determined by calibration, to partially cure the adhesive layer in the dicing groove, thereby controlling the thickness of the cured layer and preventing the excessively thick cured layer from being repeatedly irradiated by the UV light source placed on the back of the wafer during subsequent debonding, which would result in an excessive difference in energy absorbed by the UV film under the chip and the UV film in the dicing groove.

[0011] In one possible implementation, the irradiation conditions of the UV light source in step S3 are: irradiation wavelength 320~405nm, irradiation distance 10~30mm, illuminance 60~200mW / cm2, and irradiation time 1~10s, so that the refractive index of the adhesion layer in the cutting groove is in the range of n1+(n2-n1)×0.2 to n1+(n2-n1)×0.8.

[0012] In one possible implementation, the method for quantitatively removing the cured layer in step S4 is one of ozone aqueous solution rinsing, oxygen plasma treatment, or low-temperature oxidation treatment in an oxidation furnace.

[0013] In one possible implementation, the rinsing conditions of the ozone aqueous solution in step S4 are: flow rate 0.5~5L / min, suction cup rotation speed 400~2000rpm, rinsing time 1~30min, followed by rinsing with deionized water and drying with nitrogen. The oxidation etching rate within the flow rate range and the reaction time within the rinsing time range work together to ensure that 75% to 90% of the hydrocarbons in the cured layer remain after rinsing, thereby forming the stepped structure with a height of 2% to 20% of the thickness of the adhesion layer. The centrifugal force within the range defined by the rotation speed of the suction cup is sufficient to remove the etched hydrocarbons and attached particles from the cutting groove, thereby reducing the risk of new particle formation during subsequent plasma activation. After rinsing, deionized water is used for rinsing and nitrogen is used for drying to prevent residual ozone solution from continuing to oxidize the metal on the chip surface and to avoid watermarks.

[0014] In one possible implementation, the rinsing conditions of step S4 are predetermined by the following calibration method: The height of the stepped structure was calibrated: Under calibration conditions C1 with a fixed flow rate of ozone aqueous solution and a fixed suction cup rotation speed, the carbon dioxide concentration in the cutting groove was measured at different rinsing times. The carbon dioxide concentration will first rise, then stabilize, and then rise again as the rinsing time increases. The rinsing time corresponding to the second rise in carbon dioxide concentration is defined as t1. Set the step structure preparation condition C2: Under the calibration condition C1, the wafer front-side rinsing time is 10%~25% of t1, so that 75%~90% of the solidified hydrocarbons in the dicing groove remain after rinsing; Step S4 is performed using the stepped structure preparation conditions C2 to form a stepped structure with a height of 2% to 20% of the thickness of the adhesive layer, in order to remove particles that have already adhered to the surface of the cured layer before plasma activation, and to control the exposed area of ​​the stepped side of the adhesive layer in the cutting groove, so as to reduce the number of new particles during plasma activation.

[0015] In one possible implementation, the oxide film removal method in step S5 is one of argon plasma treatment, hydrogen plasma treatment, or solution cleaning.

[0016] In one possible implementation, when removing the oxide film using argon plasma treatment and hydrogen plasma treatment, the power is 50~1500W, the gas flow rate is 30~1000sccm, and the treatment time is 0.5~10min. The power, gas flow rate, and processing time are coordinated to ensure effective removal of the oxide film on the chip surface while avoiding damage to the fine patterns on the chip surface and the addition of new particles.

[0017] In one possible implementation, when removing the oxide film by solution cleaning, the solution temperature is 40~100°C, the solution flow rate is 0.5~10L / min, the cleaning time is 1~30min, and after cleaning, the oxide film is rinsed with deionized water and dried with nitrogen. The solution temperature, the solution flow rate, and the cleaning time are coordinated to ensure the oxide film removal efficiency and avoid thermal damage, contaminant redeposition, and excessive corrosion to the chip surface. After cleaning, the chip is rinsed with deionized water and dried with nitrogen to prevent residual cleaning solution from continuing to corrode the metal surface of the chip and to avoid watermarks and subsequent interconnect voids caused by them.

[0018] In one possible implementation, after the oxide film is removed by solution cleaning in step S5 and before cleaning in step S6, the wafer is activated by plasma gas to improve the surface energy of the chip and enhance the adhesion of subsequent materials. The plasma gas is argon, hydrogen, or nitrogen.

[0019] In one possible implementation, the cleaning solution is an organic acid or a diluted inorganic acid, wherein the organic acid is one or more of formic acid, acetic acid, and oxalic acid, and the diluted inorganic acid is one or more of dilute hydrochloric acid, dilute sulfuric acid, and dilute phosphoric acid.

[0020] In one possible implementation, the water washing in step S6 has a megaphonic power of 10~100W, a water flow rate of 0.5~5L / min, a suction cup rotation speed of 400~2000rpm, a washing time of 0.5~10min, and is dried with nitrogen after water washing.

[0021] According to another aspect, at least one embodiment of the present invention also provides a wafer dicing carrier structure for reducing residual adhesive and particles on the chip surface, including a frame and a UV film, the UV film including a base layer and an adhesive layer, the base layer being fixed to the frame, and the adhesive layer being used to adhere to the back side of the wafer to fix the wafer. After the wafer is diced into several chips, the surface of the adhesive layer in the dicing groove between adjacent chips has a curing layer. The surface of the curing layer is lower than the surface of the uncured adhesive layer below the chip, forming a stepped structure between them. The height of the stepped structure is 2% to 20% of the thickness of the adhesive layer.

[0022] Compared with the prior art, the method and wafer dicing carrier structure for reducing residual adhesive and particles on the chip surface provided by the embodiments of the present invention have the following significant technical effects: Particle control measures were added before the plasma activation process, rather than relying solely on post-plasma activation cleaning to compensate. Specifically, after dicing, two processes were sequentially implemented: UV pretreatment and stepped structure fabrication. First, UV light source was used to irradiate the exposed surface of the adhesive layer in the dicing groove, causing partial curing to form a cured layer, while maintaining sufficient adhesion of the adhesive layer below the chip to prevent chip displacement. Then, the cured layer was quantitatively removed, making the surface of the adhesive layer in the dicing groove lower than the surface of the adhesive layer below the chip, forming a stepped structure with a height of 2% to 20% of the adhesive layer thickness.

[0023] The stepped structure effectively removes particles already adhering to the cured layer surface before plasma activation during fabrication. Furthermore, by controlling the exposed area of ​​the smaller stepped sides, it significantly reduces the number of new particles added during subsequent plasma activation due to the shedding of the adhesive layer. Following this, surface reduction, cleaning, and backside debonding yields a chip with high cleanliness and reliable interconnects.

[0024] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are merely some exemplary embodiments of this application. For those skilled in the art, other drawings can be obtained based on the content of the exemplary embodiments of this application and these drawings without any creative effort.

[0026] Figure 1 This is a flowchart of a method for reducing residual adhesive and particles on the chip surface according to one embodiment of the present invention; Figure 2 for Figure 1 Schematic diagram of the structure of the wafer and UV film; Figure 3 This is a schematic diagram of a wafer dicing carrier structure for reducing residual adhesive and particles on the chip surface in one embodiment of the present invention. Figure 4 for Figure 3 Enlarged view of point A in the middle; Figure 5 This is a schematic diagram of the wafer surface defect detection results in the comparative examples and embodiments of the present invention.

[0027] In the diagram: 100, UV film; 101, substrate layer; 200, frame; 300, wafer; 102, adhesion layer; 301, chip; 302, dicing groove; 103, curing layer; 104, stepped structure. Detailed Implementation

[0028] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0029] To keep the drawings concise, each figure only schematically shows the parts relevant to the invention, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, components with the same structure or function are shown only schematically, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0030] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] It should be noted that when an element is referred to as being "set on" another element, it can be directly set on the other element or indirectly set on the other element. It should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0032] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a number" means two or more, unless otherwise explicitly specified.

[0033] This invention is based on the complete process chain of pre-interconnection treatment of chip 301 in D2W advanced packaging. As described in the background art, in the existing process of film bonding, cutting, plasma activation, cleaning and back-side debonding, plasma activation causes the prepolymer of the exposed adhesive layer 102 in the cutting groove 302 to fall off, forming sticky particles that are tightly attached to the adhesive layer 102. Subsequent cleaning is difficult to remove these particles because strong corrosive solutions cannot be used. The residual particles form voids during interconnection, and in severe cases, chip 301 is scrapped.

[0034] This invention provides a method for reducing adhesive residue and particles on the chip surface, such as... Figure 1 and Figure 2The process includes sequential steps such as film application, cutting, UV pretreatment, stepped structure preparation, surface reduction, and cleaning, which are described in detail below.

[0035] Film application: A film application machine is used to fix the thinned and chemically mechanically polished wafer 300 onto the UV film 100 and the frame 200. After fixation, from a top view, the wafer 300, UV film 100, and frame 200 are arranged in sequence. The base layer 101 of the UV film 100 is connected to the frame 200, and its adhesive layer 102 facing the wafer 300 is used to adhere to the back of the wafer 300, providing temporary fixation and support for subsequent cutting and transportation.

[0036] Cutting: The coated wafer 300 is placed in a dicing machine for cutting into multiple independent chips 301, with dicing grooves 302 formed between adjacent chips 301. After cutting, the adhesion layer 102 of the UV film 100 below the dicing groove 302 is directly exposed inside the dicing groove 302 because it is no longer shielded by the wafer 300 above, which becomes a potential source of particle generation during subsequent plasma activation.

[0037] UV pretreatment: A UV light source is used to irradiate the front side of the wafer 300. Under UV irradiation, the prepolymers (such as epoxy acrylate, acrylic resin) in the adhesion layer 102 of the exposed UV film 100 in the dicing groove 302 undergo a cross-linking polymerization reaction, solidifying from a flowable adhesive state into a cross-linked hydrocarbon layer, i.e., forming a cured layer 103. Since the irradiation only acts on the front side and the energy is controlled, the degree of cross-linking of the adhesion layer 102 under the chip 301 can still remain low, maintaining sufficient adhesion to adhere to the chip 301, thereby preventing the chip 301 from shifting position during subsequent processing.

[0038] The preferred irradiation conditions for this step are: irradiation wavelength of 320 nm to 405 nm, irradiation distance of 10 mm to 30 mm, illuminance of 60 mW / cm² to 200 mW / cm², and irradiation time of 1 second to 10 seconds. The wavelength of 320-405 nm covers the UVA band, matching the absorption peak of the photoinitiator in the adhesion layer 102, which can fully excite the crosslinking of the prepolymer while avoiding irradiation damage to the active region or passivation layer of chip 301 by short-wavelength high-energy photons, and also avoiding incomplete curing due to insufficient long-wavelength energy. The irradiation distance and illuminance together constrain the energy density, preventing local overexposure or excessive curing penetration that could affect the adhesion layer 102 below chip 301.

[0039] To ensure controllable curing degree, this invention introduces refractive index calibration and condition setting for the adhesion layer 102 before UV pretreatment: First, the UV film 100 of the used model is calibrated (UV films of the same model 100 only need to be calibrated once). Under calibration conditions U1 with fixed wavelength, range, distance, and illuminance, the refractive index of the adhesion layer 102 is measured at different irradiation durations. As the irradiation time increases, the refractive index first increases and then tends to stabilize. This is because molecular cross-linking increases the layer density and the monomer polymerization results in a more compact structure. The refractive index in the unirradiated state is recorded as n1, the refractive index when it stops increasing is recorded as n2, and the corresponding irradiation duration at that moment is recorded as t2.

[0040] Then, UV pretreatment condition U2 is set: based on U1, the front side of wafer 300 is irradiated for 20%~80% of time t2, so that the refractive index of the adhesive layer 102 in the dicing groove 302 after irradiation is in the range of n1+(n2-n1)×0.2 to n1+(n2-n1)×0.8. By irradiating the front side of wafer 300 with U2, the adhesive layer 102 in the dicing groove 302 can be partially cured to form a cured layer 103 with a suitable thickness, the thickness of the cured layer 103 accounting for 20%~80% (preferably 40%~70%) of the thickness of the adhesive layer 102. By constraining the degree of curing with a physical quantity such as refractive index that can be measured online without damage, it is possible to ensure that the cured layer 103 can be quantitatively removed in the subsequent process, and to avoid the cured layer 103 being too thick and being repeatedly irradiated by the back UV light source during the subsequent back-side debonding, which would cause an excessive difference in energy absorption between the adhesive layer 102 under chip 301 and in the dicing groove 302, resulting in over-curing and loss of adhesion, and chip 301 falling off.

[0041] Stepped structure preparation: The cured layer 103 (hydrocarbons) within the cutting groove 302 is quantitatively removed by rinsing with an ozone aqueous solution, making the surface of the cured layer 103 lower than the surface of the adhesion layer 102 below the chip 301, thus forming a stepped structure 104 with a height of 2%~20% of the thickness of the adhesion layer 102. Ozone molecules can directly react with hydrocarbons in an oxidation reaction. Simultaneously, ozone decomposes in water to generate reactive species such as hydroxyl radicals, indirectly oxidizing and etching hydrocarbons via a free radical pathway. To accelerate the reaction rate, hydrogen peroxide, fatty alcohols, or free radical activators or promoters such as ultraviolet irradiation can be added to the ozone aqueous solution.

[0042] The preferred rinsing conditions for this step are: ozone aqueous solution flow rate of 0.5 L / min to 5 L / min, suction cup rotation speed (for fixing the frame 200 holding the wafer 300) of 400 rpm to 2000 rpm, rinsing time of 1 minute to 30 minutes, followed by rinsing with deionized water and drying with hot nitrogen. The oxidation etching rate limited by the flow rate and the reaction time limited by the rinsing time work synergistically to ensure that 75% to 90% of the hydrocarbons in the cured layer 103 remain after rinsing; the centrifugal force provided by the suction cup rotation speed is sufficient to remove the etched hydrocarbons and attached particles from the dicing groove 302, reducing the risk of particle addition during subsequent plasma activation; the deionized water rinsing and hot nitrogen drying after rinsing prevent the residual ozone aqueous solution from continuing to oxidize the surface metal of the chip 301 and avoid watermark residue.

[0043] To ensure quantifiable and reproducible control of the step height, this invention introduces step height calibration and condition setting: Under calibration condition C1 with fixed flow rate and suction cup rotation speed, the carbon dioxide concentration in the cutting groove 302 is measured at different rinsing times. As the rinsing time increases, the carbon dioxide concentration shows a pattern of first rising, then stabilizing, and then rising again. This is because the uncured UV adhesive has more active monomers and reaction sites, resulting in a faster oxidation rate. After the cured layer 103 is removed to near the lower layer, the change in the oxidized object causes a second increase in concentration. The rinsing time corresponding to the second increase in carbon dioxide concentration is recorded as t1 (it should be noted that t1 can also be determined by monitoring the number of hydroxyl radicals in the solution after rinsing, which can replace the carbon dioxide concentration method; both reflect the progress of oxidation etching).

[0044] Then, the step structure preparation condition C2 is set: under the condition of C1, the front side of the wafer 300 is rinsed for 10%~25% of the t1 time, so that 75%~90% of the hydrocarbons solidified in the dicing groove 302 remain after rinsing, forming a step structure 104 with a height of 2%~20% of the thickness of the adhesion layer 102. This ensures that the particles that were attached to the surface of the solidified layer 103 before activation are removed, and the exposed area of ​​the step side is controlled to a small range, reducing the new particles in the exposed area of ​​the step side during plasma activation.

[0045] As an alternative implementation of this step, the step structure 104 can also be prepared by oxygen plasma treatment or by applying low-temperature oxidation treatment in an oxidation furnace. The essence of both is to quantitatively remove the surface layer of the cured layer 103 through an oxidation reaction to form the step structure 104.

[0046] In this step, the metal on the surface of chip 301 may be oxidized, which needs to be removed in the subsequent surface reduction process to ensure the interconnection effect.

[0047] Surface reduction: The oxide film on the surface of chip 301 is removed by one of argon plasma treatment, hydrogen plasma treatment or solution cleaning to improve surface energy and prepare for subsequent interconnection or bonding.

[0048] When using argon or hydrogen plasma for treatment, the preferred process conditions are: power of 50 watts to 1500 watts, gas flow rate of 30 standard cubic centimeters per minute to 1000 standard cubic centimeters per minute, and treatment time of 0.5 minutes to 10 minutes. Other gases, such as nitrogen, can be added to adjust the treatment uniformity. If the power is too low, the yield of active particles will be insufficient, and the oxide film will not be completely removed; if the power is too high, the ion bombardment energy will be too strong, easily damaging the fine pattern on the surface of the 301 chip. The constraint mechanism of flow rate and treatment time is as described above, aiming to maintain reaction kinetic balance and avoid over-etching.

[0049] When using solution cleaning, the cleaning solution should be an organic acid or a diluted inorganic acid. The organic acid can be one or more combinations of formic acid, acetic acid, and oxalic acid, while the diluted inorganic acid can be one or more combinations of dilute hydrochloric acid, dilute sulfuric acid, and dilute phosphoric acid. The preferred process conditions are: solution temperature of 40°C to 100°C (increasing the temperature accelerates the chemical reaction); solution flow rate of 0.5 L / min to 10 L / min to ensure timely removal of dissolved contaminants; cleaning time of 1 minute to 30 minutes; rinsing with deionized water and drying with hot nitrogen after cleaning to prevent residual acidic solution from corroding the metal and to avoid interconnect voids caused by watermarks or stains.

[0050] If solution cleaning is used for surface reduction, a plasma activation step needs to be added between surface reduction and subsequent cleaning. Argon, hydrogen, or nitrogen can be used as the plasma gas to enhance the surface energy of chip 301 and strengthen the adhesion of subsequent materials.

[0051] Cleaning: Use water to remove residual particles and other contaminants. Preferred process conditions are: megohm power 10 to 100 watts, water flow rate 0.5 to 5 liters / minute, suction cup (for fixing the frame 200 holding the wafer 300) rotation speed 400 to 2000 rpm, cleaning time 0.5 to 10 minutes, followed by drying with hot nitrogen.

[0052] This invention also provides a wafer dicing carrier structure compatible with the above method, such as... Figure 3 and Figure 4The system includes a frame 200 and a UV film 100. The UV film 100 includes a substrate layer 101 and an adhesive layer 102. The substrate layer 101 is fixed to the frame 200, and the adhesive layer 102 is used to adhere the back side of the wafer 300 to fix the wafer 300. A dicing groove 302 is provided between adjacent chips 301, and the surface of the adhesive layer 102 within the dicing groove 302 has a curing layer 103. The surface of the curing layer 103 is lower than the surface of the portion of the adhesive layer 102 below the chip 301 that has not been removed, thereby forming a stepped structure 104 between the two. The height of the stepped structure 104 is 2% to 20% of the thickness of the adhesive layer 102. This stepped structure 104 can remove particles already attached to the surface of the adhesive layer 102 before plasma activation and control the area of ​​the stepped side of the adhesive layer 102 to a small size, thereby reducing the risk of new particles on the stepped side of the adhesive layer 102 during plasma activation. This carrier structure can be obtained after performing the UV pretreatment and step structure 104 preparation of the aforementioned method, and is the embodiment of the carrier morphology of the method of the present invention.

[0053] The following comparative examples and three embodiments are provided to verify the technical effects of the present invention. Each example uses a 12-inch wafer 300, a 12-inch frame 200, and a 12-inch UV film 100.

[0054] Comparative Example 1. Use a laminator to attach the wafer 300 to the UV film 100 and fix it to the frame 200; 2. The dicing machine uses blades for cutting, with an X and Y stroke of 300 mm, a spindle speed of 23,000 rpm, a cutting speed of 45 mm / s, and is rinsed with deionized water. The chipping area after cutting is controlled within 50 micrometers. 3. Activate under nitrogen plasma generated by CCP equipment, power 200 watts, nitrogen flow rate 50 standard cubic centimeters / minute, processing time 1.5 minutes; 4. Single-piece washer water washing, megohm power 40 watts, flow rate 1 liter / minute, suction cup speed 1000 rpm, cleaning time 2 minutes, followed by hot nitrogen drying; 5. Inspect the surface defects of the wafer 300 after cleaning.

[0055] Example 1 Steps 1 and 2 are the same as the comparative example.

[0056] 3. Based on the calibration of UV film 100, obtain U1 and t2, and set U2 as follows: wavelength 365 nm, irradiation range diameter 320 mm, distance 20 mm, illuminance 60 mW / cm², irradiation time 4 seconds. Use this to irradiate the front side of wafer 300, so that the adhesion layer 102 in the dicing groove 302 is partially cured. 4. Based on the step height calibration, obtain C1 and t1, and set C2: ozone water flow rate 1.5 liters / minute, suction cup rotation speed 800 rpm, rinsing time 1.5 minutes, rinse the front side of the wafer 300, rinse with deionized water and dry with hot nitrogen to form an adhesion layer 102 and a step structure 104. 5. Place the surface under the argon plasma generated by the CCP device for reduction, with a power of 300 watts, an argon flow rate of 100 standard cubic centimeters / minute, and a processing time of 3 minutes; 6~7. Repeat steps 4~5 of the comparative example.

[0057] Example 2 Based on Example 1, the surface reduction in step 5 is performed using a mixed gas plasma treatment of hydrogen and nitrogen, with a power of 300 watts, a hydrogen flow rate of 80 standard cubic centimeters / minute, a nitrogen flow rate of 20 standard cubic centimeters / minute, and a treatment time of 3 minutes; the rest is the same as in Example 1.

[0058] Example 3 Based on Example 1, the surface reduction in step 5 is carried out by solution cleaning: the solution is formic acid, the temperature is 50 degrees Celsius, the flow rate is 1.8 liters / minute, the cleaning time is 2 minutes, and the surface is rinsed with deionized water and dried with hot nitrogen; and a plasma activation step is added between surface reduction and cleaning (under the same conditions as comparative example step 3); the rest is the same as in Example 1.

[0059] The surface defects of wafer 300 in the above comparative examples and embodiments of the present invention were detected, and the results are as follows: Figure 5 As shown: the total number of defects in the comparative example is 541, of which 49 are defects with a particle size of not less than 0.5 micrometers; Example 1 has a total of 70 defects (1 of which is not less than 0.5 micrometers), Example 2 has a total of 79 defects (3 of which are not less than 0.5 micrometers), and Example 3 has a total of 58 defects (0 of which are not less than 0.5 micrometers). It can be seen that by using the method and structure of the present invention, the number of particles on the surface of chip 301 is significantly reduced compared to existing processes. Large particles (not less than 0.5 micrometers) are almost completely eliminated, there is no obvious particle aggregation in the defect distribution map, and the total number of surface particles can be controlled to within 80 with no large particle aggregation.

[0060] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention applied herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary technical means not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0061] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, but various modifications can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for reducing adhesive residue and particles on the surface of a chip, characterized in that, Includes the following steps: S1, Film application: Fix the base layer (101) of the UV film (100) onto the frame (200), and fix the wafer (300) onto the adhesive layer (102) of the UV film (100); S2. Cutting: The wafer (300) is cut into a plurality of chips (301), and a cutting groove (302) is formed between adjacent chips (301). S3, UV pretreatment: The front side of the wafer (300) is irradiated with a UV light source to cure the surface of the exposed adhesive layer (102) in the dicing groove (302) into a cured layer (103). The UV pretreatment irradiation time is predetermined by refractive index calibration: the refractive index of the adhesion layer (102) in the unirradiated state is determined as n1, the refractive index when the refractive index stops rising is determined as n2, and the irradiation time corresponding to the stop rising refractive index is determined as t2. The irradiation time of the front side of the wafer (300) in step S3 is 20% to 80% of t2, so that the refractive index of the adhesion layer (102) in the dicing groove (302) after irradiation is in the range of n1+(n2-n1)×0.2 to n1+(n2-n1)×0.8 and is in a partially cured state, so as to control the thickness of the cured layer (103); while the adhesion layer (102) under the chip (301) still maintains a low degree of cross-linking to maintain adhesion to the chip (301) and prevent the chip (301) from shifting position during the processing. S4. Step structure preparation: The solidified layer (103) in the dicing groove (302) is quantitatively removed to form a step structure (104) with a height of 2% to 20% of the thickness of the adhesive layer (102) between the surface of the solidified layer (103) and the surface of the adhesive layer (102) below the wafer (300). This removes particles that have been attached to the surface of the solidified layer (103) before plasma activation and controls the exposed area of ​​the stepped side of the adhesive layer (102) in the dicing groove (302) to reduce the number of new particles added during plasma activation. S5. Surface reduction: Remove the oxide film on the surface of the chip (301); S6. Washing: Wash with water to remove remaining particles.

2. The method for reducing adhesive residue and particles on the chip surface according to claim 1, characterized in that, The refractive index calibration in step S3 is performed in advance in the following manner: Under calibration conditions U1 where the irradiation wavelength, irradiation range, irradiation distance and illuminance of the UV light source are all fixed, the refractive index of the adhesion layer (102) of the UV film (100) is measured at different irradiation durations. The refractive index first increases and then stabilizes as the irradiation duration increases. Step S3 is performed under the irradiation conditions set according to the calibrated n1, n2 and t2 under the calibration conditions U1, so as to partially cure the adhesive layer (102) in the dicing groove (302) to control the thickness of the cured layer (103) and avoid the excessively thick cured layer (103) being repeatedly irradiated by the UV light source placed on the back of the wafer (300) during the subsequent de-adhesion process, which would result in an excessive difference in the energy absorbed by the UV film (100) under the chip (301) and the UV film (100) in the dicing groove (302).

3. The method for reducing residual adhesive and particles on the chip surface according to claim 2, characterized in that, The irradiation conditions of the UV light source in step S3 are: irradiation wavelength 320~405nm, irradiation distance 10~30mm, illuminance 60~200mW / cm2, and irradiation time 1~10s, so that the refractive index of the adhesion layer (102) in the cutting groove (302) is in the range of n1+(n2-n1)×0.2 to n1+(n2-n1)×0.

8.

4. The method for reducing residual adhesive and particles on the chip surface according to claim 1, characterized in that, The method for quantitatively removing the cured layer (103) in step S4 is one of ozone aqueous solution rinsing, oxygen plasma treatment, or low-temperature oxidation treatment in an oxidation furnace.

5. The method for reducing adhesive residue and particles on the chip surface according to claim 4, characterized in that, The rinsing conditions for the ozone aqueous solution in step S4 are: flow rate 0.5~5L / min, suction cup rotation speed 400~2000rpm, rinsing time 1~30min, and after rinsing, deionized water is used for rinsing and nitrogen is used for drying. The oxidation etching rate within the flow rate range and the reaction time within the rinsing time range work together to ensure that 75% to 90% of the hydrocarbons in the cured layer (103) remain after rinsing, thereby forming the stepped structure (104) with a height of 2% to 20% of the thickness of the adhesion layer (102). The centrifugal force within the range defined by the rotation speed of the suction cup is sufficient to remove the etched hydrocarbons and attached particles from the cutting groove (302), thereby reducing the risk of particle addition during subsequent plasma activation. After rinsing, deionized water is used for rinsing and nitrogen is used for drying to prevent residual ozone solution from continuing to oxidize the metal on the surface of the chip (301) and to avoid watermarks.

6. The method for reducing adhesive residue and particles on the chip surface according to claim 5, characterized in that, The rinsing conditions in step S4 are predetermined by the following calibration method: The height of the stepped structure was calibrated: Under calibration conditions C1 with a fixed flow rate of ozone aqueous solution and a fixed suction cup rotation speed, the carbon dioxide concentration in the cutting groove (302) was measured at different rinsing times; The carbon dioxide concentration will first rise, then stabilize, and then rise again as the rinsing time increases. The rinsing time corresponding to the second rise in carbon dioxide concentration is defined as t1. Set the step structure preparation condition C2: Under the calibration condition C1, the front washing time of the wafer (300) is 10%~25% of t1, so that 75%~90% of the hydrocarbons solidified in the dicing groove (302) remain after washing; Step S4 is performed using the stepped structure preparation conditions C2 to form the stepped structure (104) with a height of 2% to 20% of the thickness of the adhesion layer (102) in order to remove particles that have already adhered to the surface of the cured layer (103) before plasma activation, and to control the exposed area of ​​the stepped side of the adhesion layer (102) in the cutting groove (302) to reduce the number of new particles added during plasma activation.

7. The method for reducing adhesive residue and particles on the chip surface according to claim 1, characterized in that, In step S5, the oxide film is removed by one of the following methods: argon plasma treatment, hydrogen plasma treatment, or solution cleaning.

8. The method for reducing adhesive residue and particles on the chip surface according to claim 7, characterized in that, When removing oxide films using argon plasma treatment and hydrogen plasma treatment, the power is 50~1500W, the gas flow rate is 30~1000sccm, and the treatment time is 0.5~10min. The power, the gas flow rate, and the processing time are coordinated to ensure that the oxide film on the surface of the chip (301) is effectively removed while avoiding damage to the fine pattern on the surface of the chip (301) and the addition of particles.

9. The method for reducing adhesive residue and particles on the chip surface according to claim 7, characterized in that, When removing the oxide film by solution cleaning, the solution temperature is 40~100°C, the solution flow rate is 0.5~10L / min, the cleaning time is 1~30min, and after cleaning, it is rinsed with deionized water and dried with nitrogen. The solution temperature, the solution flow rate, and the cleaning time are coordinated to ensure the oxide film removal efficiency and avoid thermal damage, contaminant redeposition, and excessive corrosion on the chip (301) surface. After cleaning, the chip is rinsed with deionized water and dried with nitrogen to prevent residual cleaning solution from continuing to corrode the surface metal of the chip (301) and to avoid water marks and subsequent interconnect voids caused by them.

10. The method for reducing adhesive residue and particles on the chip surface according to claim 9, characterized in that, After the oxide film is removed by solution cleaning in step S5 and before cleaning in step S6, the wafer (300) is activated by plasma gas to improve the surface energy of the chip (301) and enhance the bonding force of subsequent materials. The plasma gas is argon, hydrogen or nitrogen.

11. The method for reducing residual adhesive and particles on the chip surface according to claim 9, characterized in that, The cleaning solution is an organic acid or a diluted inorganic acid. The organic acid is one or more of formic acid, acetic acid, and oxalic acid, and the diluted inorganic acid is one or more of dilute hydrochloric acid, dilute sulfuric acid, and dilute phosphoric acid.

12. The method for reducing adhesive residue and particles on the chip surface according to claim 1, characterized in that, In step S6, the water washing power is 10~100W, the water flow rate is 0.5~5L / min, the suction cup speed is 400~2000rpm, the washing time is 0.5~10min, and nitrogen is used to dry the water after washing.

13. A wafer dicing carrier structure for reducing adhesive residue and particles on the chip surface, characterized in that, The device includes a frame (200) and a UV film (100). The UV film (100) includes a base layer (101) and an adhesive layer (102). The base layer (101) is fixed to the frame (200), and the adhesive layer (102) is used to adhere to the back side of the wafer (300) to fix the wafer (300). After the wafer (300) is cut into a plurality of chips (301), the surface of the adhesive layer (102) in the dicing groove (302) between adjacent chips (301) has a curing layer (103). The surface of the curing layer (103) is lower than the surface of the uncured adhesive layer (102) below the chip (301), and a stepped structure (104) is formed between them. The height of the stepped structure (104) is 2% to 20% of the thickness of the adhesive layer (102).

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