Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure, and belongs to the technical field of semiconductor manufacturing. The preparation method comprises a P-type base region annealing process. In the P-type base region annealing process, a silicon boat is used to support a wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the radius of the wafer. In the semiconductor structure preparation method, the silicon boat is used to support the wafer in the P-type base region annealing process. The silicon boat has the same physical properties as the wafer, so that the lattice dislocation caused by the difference in the thermal expansion coefficient and the thermal conductivity coefficient can be avoided. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the radius of the wafer. The support point of the silicon boat is close to the center of the wafer, the influence of the gravity stress on the whole wafer is small in the high-temperature process, the situation that the contact hole overetching precision is large due to the influence of high temperature in the P-type base region annealing process can be improved, and the product yield is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and more specifically, relates to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Overlay accuracy (OVL) refers to the alignment precision between one pattern layer and the previous pattern layer. In chip manufacturing, overlay accuracy is crucial to the performance and reliability of integrated circuits, and the requirements for overlay accuracy become increasingly stringent as feature sizes shrink.

[0003] Existing Insulated-Gate Bipolar Transistors (IGBTs) have evolved from planar gates to trench gates through vertical structures such as punch-through (PT), non-punch-through (NPT), and field-stop (FS) types, becoming the most widely used semiconductor devices in high-voltage, high-current, and high-frequency electronic equipment. Compared to planar gate IGBTs, trench gate IGBTs offer advantages such as lower on-resistance, smaller cell size, increased channel current density, and increased current capacity. Current trench gate IGBTs generally use FZ-type wafer substrates. Compared to CZ-type wafers, FZ-type wafers have extremely low oxygen and carbon content. The low oxygen content results in weaker mechanical strength, making them more susceptible to high-temperature processing, leading to larger on-state volume (OVL) of the contact holes. This affects production line yield and can even cause device parameter failure. Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing a semiconductor structure and a semiconductor structure. This method can improve the situation where the contact hole overlay accuracy is too large due to the influence of high temperature process during semiconductor preparation, thereby improving product yield.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The first aspect of the present invention provides a method for preparing a semiconductor structure, comprising: The P-type base region annealing process uses a silicon boat to support the wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

[0006] In one embodiment, the spacing between two adjacent wafers on the silicon boat is doubled during the P-type base region annealing process.

[0007] In one embodiment, the process further includes the following steps before the P-type base region annealing process: The sacrificial oxidation process uses a silicon boat to support the wafers, and the spacing between two adjacent wafers on the silicon boat is double. The gate oxidation process uses a silicon boat to support the wafer, and the spacing between two adjacent wafers on the silicon boat is double.

[0008] In one embodiment, the process further includes the following steps prior to the sacrificial oxidation process: In the P-type field ring annealing process, a silicon boat is used to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The carrier storage layer annealing process uses a silicon boat to support the wafer, wherein the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

[0009] In one embodiment, the spacing between two adjacent wafers on the silicon boat in the P-type field ring annealing process is a single spacing. In the carrier storage layer annealing process, the spacing between two adjacent wafers on the silicon boat is a single unit; in the P-type base region annealing process, the spacing between two adjacent wafers on the silicon boat is a single unit.

[0010] In one embodiment, the distance from the support point of the silicon boat used to support the wafer in the sacrificial oxidation process and the gate oxidation process to the center of the wafer is less than or equal to 85% of the wafer radius.

[0011] A second aspect of the present invention provides a method for preparing a semiconductor structure, comprising: Acquire images of the semiconductor structure before and after each high-temperature fabrication process during the semiconductor fabrication process; The overlay accuracy after the high-temperature preparation process is obtained from the image. The high-temperature preparation process with the largest overlay accuracy deviation is taken as the target high temperature; In the target high-temperature fabrication process, a silicon boat is used to support the wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

[0012] In one embodiment, the preparation method further includes: In the target high-temperature fabrication process, the spacing between two adjacent wafers on the silicon boat is double.

[0013] In one embodiment, the high-temperature fabrication process is a P-type field ring annealing process, a carrier storage layer annealing process, a sacrificial oxidation process, a gate oxidation process, or a P-type base region annealing process.

[0014] In one embodiment, the temperature conditions for the P-type field ring annealing process, the carrier storage layer annealing process, the sacrificial oxidation process, the gate oxidation process, and the P-type base region annealing process are all 900℃~1200℃.

[0015] A second aspect of the present invention provides a semiconductor structure, wherein the semiconductor structure is fabricated using the semiconductor structure fabrication method described above.

[0016] In one embodiment, the semiconductor structure is an insulated gate bipolar transistor.

[0017] The semiconductor structure fabrication method provided by this invention includes a P-type base region annealing process. In this process, a silicon boat is used to support the wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. In this semiconductor structure fabrication method, the silicon boat, having the same physical properties as the wafer, avoids lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity, thus improving contact hole overlay accuracy. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point is close to the center of the wafer, minimizing the impact of gravitational stress on the entire wafer during high-temperature processes. This improves the situation where contact hole overlay accuracy is too high due to high temperatures in the P-type base region annealing process, thereby increasing product yield.

[0018] The semiconductor structure fabrication method provided by this invention includes acquiring images of the semiconductor structure before and after each high-temperature fabrication process; obtaining the overlay accuracy after each high-temperature fabrication process based on the images; identifying the high-temperature fabrication process with the largest overlay accuracy deviation as the target high temperature; and using a silicon boat to support the wafer in the target high-temperature fabrication process, wherein the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. This semiconductor structure fabrication method can improve the situation where the contact hole overlay accuracy is too large due to the influence of high temperature during semiconductor structure fabrication, thereby improving product yield. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1These are schematic photographs illustrating the following conditions: after gate etching, after gate oxide removal, after P-type base region annealing, after N-type source region annealing, and after dielectric layer reflow, as provided in embodiments of the present invention. Figure 2 This is a schematic diagram of the OVL average plus 3 times the standard deviation provided in the embodiments of the present invention, where the vertical axis represents the uncompensated value of OVL; Figure 3 This is a schematic diagram of the structure after placing a wafer on the silicon boat support provided in an embodiment of the present invention; Figure 4 The box plots of the average OVL plus 3 times the standard deviation before and after using the silicon carbide boat and the box plots of the average OVL plus 3 times the standard deviation before and after using the silicon boat are provided for the P-type base region annealing process of the present invention. Figure 5 Box plots of OVL average value plus 3 times standard deviation for wafer arrangement in silicon boat of P-type base region annealing process provided in embodiments of the present invention and box plots of OVL average value plus 3 times standard deviation for wafer arrangement with double spacing. Figure 6 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 7 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] In the description of this invention, it should be understood that the terms “comprising” and “having” as used herein, and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0023] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. It should be understood that the term "and / or" as used herein is merely a description of the relationship between related objects, indicating that three relationships may exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0025] OVL (Organizational Value Lift) refers to the alignment accuracy between consecutive patterned layers. In chip manufacturing, OVL is crucial to the performance and reliability of integrated circuits. As feature sizes decrease, the requirements for OVL become increasingly stringent. Many steps in semiconductor fabrication processes are performed at high temperatures, where semiconductor materials undergo thermal expansion. Due to the different coefficients of thermal expansion of different materials, the degree of thermal expansion between contact holes and surrounding materials varies. This difference causes changes in the relative position of the contact hole to its surrounding structure, thus affecting OVL. For example, if the contact hole material has a higher coefficient of thermal expansion than the surrounding material, the contact hole may move towards the surrounding material at high temperatures, leading to a larger OVL. High temperatures also generate thermal stress within the material. When materials are heated unevenly, internal stress is generated, causing material deformation or cracking. This stress affects the shape and position of contact holes, thus affecting overlay accuracy. Especially in multilayer structures, where the coefficients of thermal expansion of each layer are different, thermal stress is more easily generated at high temperatures, leading to a larger OVL.

[0026] The inventors analyzed the thermal process closest to the contact hole OVL in the manufacturing process of trench gate IGBT products, and gradually collected OVL data. They found that the high-temperature annealing process of the P-type base region would worsen the OVL. Figure 1 These are schematic photographs illustrating the following steps in the semiconductor structure fabrication method provided in this embodiment of the invention: after gate etching, after gate oxide removal, after P-type base region annealing, after N-type source region annealing, and after dielectric layer reflow. Figure 2This diagram illustrates the OVL average plus three times the standard deviation provided in an embodiment of the invention. The vertical axis represents the uncompensated value of OVL, with the blue histogram representing the uncompensated OVL value in the X-direction and the orange histogram representing the uncompensated OVL value in the Y-direction. Please refer to [link / reference]. Figure 1 , 2 Specifically, the process following P-type base region annealing includes N-type source region annealing and dielectric layer reflow. The process preceding P-type base region annealing includes gate photolithography, gate etching, gate re-oxidation, and gate oxide layer removal. By acquiring images sequentially after gate photolithography, gate etching, gate re-oxidation, gate oxide layer removal, P-type base region annealing, N-type source region annealing, and dielectric layer reflow, and statistically analyzing the uncompensated OVL values ​​in the X and Y directions, it can be seen that the contact hole OVL significantly increases after P-type base region annealing. Subsequent N-type source region annealing and dielectric layer reflow have almost no impact on the contact hole OVL. Therefore, it is concluded that the high-temperature process in P-type base region annealing deteriorates the contact hole OVL. Based on the above findings, this application provides a method for fabricating a semiconductor structure and a semiconductor structure.

[0027] The preparation method and semiconductor structure of the present invention will be described in detail below with reference to specific embodiments.

[0028] The semiconductor structure fabrication method provided in the first aspect of this embodiment includes a P-type base region annealing process, wherein a silicon boat is used to support the wafer in the P-type base region annealing process, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

[0029] The semiconductor structure fabrication method in this embodiment is illustrated using a trench gate IGBT as an example. The P-type base region annealing process in this embodiment refers to the technique of annealing the P-type base region during semiconductor device manufacturing. Its main purpose is to activate doped P-type impurities and repair lattice damage caused during ion implantation, thereby optimizing device performance.

[0030] In this embodiment, the substrate for fabricating the trench gate IGBT is a silicon wafer. During the P-type base region annealing process, a silicon boat is used to support the wafer. The silicon boat has the same physical properties as the silicon wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity, and improving the overlay accuracy of contact holes. The use of a silicon boat to support the wafer during the P-type base region annealing process in this embodiment is significantly more effective in improving the OVL (Out-of-Voltage) effect compared to existing silicon carbide boat-supported wafers.

[0031] In existing P-type base region annealing processes, the wafer is located on a silicon carbide boat. The wafer groove of the silicon carbide boat is generally supported by three support points. The distance from the three support points in contact with the silicon carbide boat to the center of the wafer is greater than 85% of the wafer radius. The distance from the three support points in contact with the silicon carbide boat to the center of the wafer is generally 85%-90%. Due to the large distance from the three support points in contact with the silicon carbide boat to the center of the wafer, the gravitational stress has a significant impact on the entire wafer during high-temperature processes, which further leads to a larger OVL of the contact holes in the P-type base region annealing process due to the influence of high temperature. Figure 3 Please refer to the schematic diagram of the structure after placing the wafer on the silicon boat support provided in the embodiment of the present invention. Figure 3 In this embodiment, when the wafer is placed on the silicon boat, the distance D from the wafer support point to the wafer center is less than or equal to 85% of the wafer radius, and the support point of the silicon boat is closer to the wafer center. In this embodiment, the distances D from all three support points to the wafer center are less than or equal to 85% of the wafer radius. This minimizes the impact of wafer gravity stress on the entire wafer during high-temperature processes, reducing the possibility of excessively large contact hole open volume (OVL) due to high temperatures during the P-type base region annealing process. Figure 4 The box plots for the P-type base region annealing process provided in this embodiment of the invention use the average OVL plus 3 times the standard deviation before and after using a silicon carbide boat, and the box plots for the average OVL plus 3 times the standard deviation before and after using a silicon boat, combined with... Figure 4 It can be seen that the average OVL of the P-type base region annealing process using a silicon boat plus 3 times the standard deviation is more convergent, and the OVL of the P-type base region annealing process using a silicon boat is less than that using a silicon carbide boat.

[0032] The semiconductor structure fabrication method provided by this invention includes a P-type base region annealing process. This process uses a silicon boat to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. In this semiconductor structure fabrication method, the silicon boat supports the wafer during the P-type base region annealing process. The silicon boat has the same physical properties as the silicon wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point of the silicon boat is closer to the center of the wafer, resulting in less impact of gravitational stress on the entire wafer during high-temperature processes. This semiconductor structure fabrication method can improve the situation where the contact hole overlay accuracy is too high due to high temperature in the P-type base region annealing process, thereby improving product yield.

[0033] Optionally, in one specific embodiment, the spacing between adjacent wafers on the silicon boat in the P-type base region annealing process is double. In this embodiment, the spacing refers to the distance between adjacent wafer slots on the silicon boat. Double spacing means that adjacent wafers are separated by one wafer slot in the silicon boat. In existing furnace tubes, each wafer slot on the silicon carbide boat has a wafer, and the spacing between adjacent wafers on the silicon boat is single. In the P-type base region annealing process of this embodiment, a silicon boat is used inside the furnace tube, and the spacing between adjacent wafers on the silicon boat is double. The increased distance between adjacent wafers improves airflow within the furnace tube during the annealing process compared to single spacing, reducing thermal radiation between wafers during high-temperature thermal processes, improving the situation of excessively large OVL (Output Vulnerability Level) of contact holes due to high temperatures, and increasing product yield. Figure 5 Box plots of the OVL average value plus 3 times the standard deviation for wafer arrangement in a silicon boat during P-type base region annealing process provided in this embodiment of the invention, and box plots of the OVL average value plus 3 times the standard deviation for wafer arrangement with double spacing, are presented. Figure 5 It can be seen that the OVL (Out-of-Vehicle Lid) spacing on the silicon boat using the double-pitch method in the P-type base region annealing process is smaller than the OVL spacing using the single-pitch method.

[0034] In one specific embodiment, the P-type base region annealing process further includes a sacrificial oxidation process and a gate oxidation process. In the sacrificial oxidation process, a silicon boat is used to support the wafer, and the spacing between two adjacent wafers is doubled. In the gate oxidation process, a silicon boat is used to support the wafer, and the spacing between two adjacent wafers is doubled.

[0035] The gate oxidation process in this embodiment refers to the process of forming a thin silicon oxide film on the wafer surface during the fabrication of the semiconductor structure. The role of gate oxidation in IGBTs is to protect the wafer surface, prevent the intrusion of external contaminants, and isolate different circuit components, thereby improving the stability and reliability of the device. The sacrificial oxidation process in this embodiment is a process that removes the damage layer generated after trench etching using a high-temperature process before gate oxidation, preparing for subsequent gate oxidation. Sacrificial oxidation typically employs a high-temperature process to remove trench sidewall defects and loss layers, ensuring the integrity and quality of the gate oxide layer. In this embodiment, a silicon boat is used to support the wafer during both the sacrificial oxidation and gate oxidation processes in the semiconductor structure fabrication process. The silicon boat has the same physical properties as the silicon wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity, and improving the on-vessel volume (OVL) of the contact holes. In sacrificial oxidation and gate oxidation processes, the spacing between two adjacent wafers on the silicon boat is double, resulting in a larger distance between adjacent wafers. This improves the airflow within the furnace tube during sacrificial oxidation and gate oxidation processes compared to single-spacing processes. It can reduce thermal radiation between wafers during high-temperature thermal processes, improve the situation where the contact hole open volume (OVL) is too large due to high temperature, and increase product yield.

[0036] This embodiment improves the large OVL of the contact hole by improving the P-type base region annealing process, sacrificial oxidation process, and gate oxidation process in the semiconductor structure fabrication method, thereby increasing the production line yield.

[0037] In one specific embodiment, the sacrificial oxidation process further includes a P-type field ring annealing process and a carrier storage layer annealing process before the sacrificial oxidation process. The P-type field ring annealing process uses a silicon boat to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The carrier storage layer annealing process also uses a silicon boat to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

[0038] The main purpose of the carrier storage layer annealing process in this embodiment is to repair lattice defects, activate dopants, and improve the electrical and mechanical properties of the material. For example, during ion implantation, high-energy particles can disrupt the lattice structure, leading to defects and damage. Annealing can repair these defects, allowing atoms to rearrange back to their correct positions in the lattice, thereby restoring the electrical properties of the material. The purpose of the P-type field ring annealing process is to repair the damage to the wafer surface caused during ion implantation through heat treatment and to activate dopant ions, enabling them to move to appropriate positions in the lattice, thereby optimizing the conductivity of the semiconductor. The P-type field ring annealing process involves heating the wafer to a certain temperature and holding it for a period of time, followed by cooling, to restore the lattice structure and ensure the correct activation of dopant ions. In the P-type field ring annealing process and the carrier storage layer annealing process of this embodiment, a silicon boat is used to support the wafer. The silicon boat has the same physical properties as the wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity, and improving the accuracy of contact hole overlay.

[0039] In existing P-type field ring annealing processes, the wafer is placed on a silicon carbide boat. The wafer groove of the silicon carbide boat supports the wafer through three support points. The distance from the three support points where the wafer contacts the silicon carbide boat to the center of the wafer is generally greater than 85% of the wafer radius. During high-temperature processes, gravitational stress has a significant impact on the entire wafer, further leading to a situation where the contact hole overlay accuracy is too high due to the high temperature in the P-type field ring annealing process. In this embodiment, please refer to... Figure 3When the wafer is placed on the silicon boat, the distance D from the wafer support point to the wafer center is less than or equal to 85% of the wafer radius, and the wafer support points on the silicon boat are closer to the wafer center. In this embodiment, the distances from the three support points to the wafer center are less than or equal to 85% of the wafer radius. During the high-temperature process of P-type field ring annealing, the impact of wafer gravity stress on the entire wafer is small, which can reduce the possibility of an excessively large OVL (Output Value L) of the contact holes due to high temperatures in the P-type field ring annealing process. Similarly, in the carrier storage layer annealing process of this embodiment, the distance from the support points of the silicon boat used to support the wafer to the wafer center is less than or equal to 85% of the wafer radius, which can reduce the possibility of an excessively large OVL of the contact holes due to high temperatures in the carrier storage layer annealing process.

[0040] Furthermore, in the P-type field ring annealing process, the spacing between two adjacent wafers on the silicon boat is a single unit; in the carrier storage layer annealing process, the spacing between two adjacent wafers on the silicon boat is a single unit; and in the P-type base region annealing process, the spacing between two adjacent wafers on the silicon boat is a single unit.

[0041] In this embodiment, the spacing between adjacent wafers on the silicon boat is single in the P-type field ring annealing process and the carrier storage layer annealing process. In semiconductor structure fabrication methods, if the spacing between adjacent wafers on the silicon boat is double in the P-type field ring annealing process, the carrier storage layer annealing process, the sacrificial oxidation process, and the gate oxidation process, it will affect production capacity. For example, in this embodiment, the spacing between adjacent wafers on the silicon boat is single in the P-type field ring annealing process and the carrier storage layer annealing process, while the spacing between adjacent wafers on the silicon boat is double in the sacrificial oxidation process, the gate oxidation process, and the P-type base region annealing process, which balances production capacity. Table 1 is a comparison table of the proportion of OVL exceeding specifications after the combination of single and double spacing between adjacent wafers on the silicon boat in the five high-temperature processes of semiconductor structure fabrication. As shown in Example 1 of Table 1, among the semiconductor structure fabrication methods, the P-type field ring annealing process and the carrier storage layer annealing process have a single-layer spacing between adjacent wafers on the silicon boat, while the sacrificial oxidation process, the gate oxidation process, and the P-type base region annealing process have a double-layer spacing between adjacent wafers on the silicon boat, resulting in the semiconductor structure with the smallest OVL (Out-of-Volume Liability) exceeding specifications. In Example 2, compared to Example 1, the P-type base region annealing process has a single-layer spacing between adjacent wafers on the silicon boat, and the OVL exceeding specifications is 0.1%, which is also within an acceptable range.

[0042]

[0043] Table 1: Comparison of OVL (Out-of-Voltage) Exceedance Ratios After Single and Double Spacing Combinations Between Adjacent Wafers on the Silicon Boat in Five High-Temperature Processes of Semiconductor Structure Fabrication Methods. In the P-type field ring annealing process, carrier storage layer annealing process, and P-type base region annealing process of this embodiment, the spacing between two adjacent wafers on the silicon boat is single, while the spacing between two adjacent wafers on the silicon boat is double in the sacrificial oxidation process and gate oxidation process. This can improve the situation where the contact hole OVL is too large due to the influence of high temperature, improve product yield, and balance production capacity.

[0044] In the above embodiments, the temperature conditions for the P-type field ring annealing process, the carrier storage layer annealing process, the sacrificial oxidation process, the gate oxidation process, and the P-type base region annealing process are 900℃~1200℃. Exemplarily, the P-type field ring annealing process, the carrier storage layer annealing process, the sacrificial oxidation process, the gate oxidation process, and the P-type base region annealing process all employ a high-temperature process of 1150℃.

[0045] The semiconductor structure fabrication method provided in this invention includes a P-type base region annealing process. This process uses a silicon boat to support the wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. In this semiconductor structure fabrication method, the silicon boat supports the wafer during the P-type base region annealing process. The silicon boat has the same physical properties as the wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point of the silicon boat is close to the center of the wafer, minimizing the impact of gravitational stress on the entire wafer during high-temperature processing. This semiconductor structure fabrication method can improve the situation where the contact hole overlay accuracy is too high due to high temperature in the P-type base region annealing process, thereby improving product yield.

[0046] Figure 6 For a flowchart of the method for fabricating the semiconductor structure provided in the embodiments of the present invention, please refer to [link / reference]. Figure 6 The method for preparing a semiconductor structure provided in the second aspect of this embodiment includes: S101. Obtain images of the semiconductor structure before and after each high-temperature fabrication process during the semiconductor structure fabrication process; Specifically, the high-temperature fabrication process of semiconductor structures generally includes P-type field ring annealing, carrier storage layer annealing, sacrificial oxidation, gate oxidation, and P-type base region annealing. This embodiment obtains images of the semiconductor structure before and after the five high-temperature fabrication processes: P-type field ring annealing, carrier storage layer annealing, sacrificial oxidation, gate oxidation, and P-type base region annealing. The images of the semiconductor structure in this embodiment are photographs of the semiconductor structure.

[0047] S102. Obtain the overlay accuracy after each high-temperature preparation process based on the image; Specifically, this embodiment uses existing technology to obtain the overlay accuracy through images. For example, the overlay accuracy of this embodiment can be obtained by the method disclosed in patent CN102749815A. Of course, this embodiment can also use existing known methods to obtain the overlay accuracy.

[0048] S103. The high-temperature preparation process with the largest overlay accuracy deviation is selected as the target high-temperature preparation process. Specifically, after obtaining the overlay accuracy of each high-temperature preparation process, the high-temperature preparation process with the largest overlay accuracy deviation is selected as the target high-temperature preparation process for improvement.

[0049] S104. In the target high-temperature fabrication process, a silicon boat is used to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

[0050] Specifically, in this embodiment, the target high-temperature fabrication process uses a silicon boat to support the wafer. The silicon boat has the same physical properties as the silicon wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point of the silicon boat and the wafer is closer to the center of the wafer, so the gravitational stress has little impact on the entire wafer during the high-temperature process. This semiconductor structure fabrication method can improve the situation where the contact hole overlay accuracy is too large due to the influence of high temperature in the high-temperature fabrication process, thereby improving the product yield.

[0051] In one specific embodiment, in the target high-temperature fabrication process, the spacing between two adjacent wafers on the silicon boat is double. In this embodiment, the spacing between two adjacent wafers on the silicon boat is double. The spacing in this embodiment refers to the distance between adjacent wafer slots on the silicon boat. Double spacing means that adjacent wafers are separated by one wafer slot in the silicon boat. In existing furnace tubes, each wafer slot on the silicon carbide boat has a wafer, and the spacing between two adjacent wafers on the silicon boat is single. In this embodiment, the target high-temperature fabrication process uses a silicon boat inside the furnace tube, and the spacing between two adjacent wafers on the silicon boat is double. This increased distance between adjacent wafers improves airflow within the furnace tube during the annealing process compared to single spacing, reducing heat radiation between wafers during high-temperature thermal processes and mitigating the issue of excessively large OVL (Output Vulnerability Level) contact holes caused by high temperatures.

[0052] In the above embodiments, the high-temperature preparation process is a P-type field ring annealing process, a carrier storage layer annealing process, a sacrificial oxidation process, a gate oxidation process, or a P-type base region annealing process. The temperature conditions for the P-type field ring annealing process, the carrier storage layer annealing process, the sacrificial oxidation process, the gate oxidation process, and the P-type base region annealing process are all 900℃~1200℃.

[0053] The semiconductor structure fabrication method provided in this invention includes acquiring images of the semiconductor structure before and after each high-temperature fabrication process, obtaining the overlay accuracy after each high-temperature fabrication process based on the images, identifying the high-temperature fabrication process with the largest overlay accuracy deviation as the target high temperature, and using a silicon boat to support the wafer in the target high-temperature fabrication process. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. This semiconductor structure fabrication method can improve the situation where the contact hole overlay accuracy is too large due to the influence of high temperature during semiconductor structure fabrication, thereby improving product yield.

[0054] A third aspect of this embodiment provides a semiconductor structure fabricated using the semiconductor structure fabrication method described in the above embodiments. The semiconductor structure can be a planar gate IGBT, a trench gate IGBT, or other semiconductor devices.

[0055] For example, please refer to Figure 6 The semiconductor structure in this embodiment is fabricated using the following semiconductor structure fabrication method, which includes: S201, P-type field ring annealing process, wherein the P-type field ring annealing process uses a silicon boat to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius; Specifically, in this embodiment, the P-type field ring annealing process adopts a high-temperature process of 1150°C. In the semiconductor structure fabrication method, a silicon boat is used to support the wafer during the P-type field ring annealing process. The silicon boat has the same physical properties as the wafer, so it can avoid lattice misalignment caused by the difference in thermal expansion coefficient and thermal conductivity, and improve the contact hole OVL. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point of the silicon boat to the wafer is close to the center of the wafer. In the high-temperature process, the gravitational stress has little effect on the entire wafer, which can improve the situation of large contact hole OVL caused by high temperature in the P-type base region annealing process and improve product yield.

[0056] S202, Carrier storage layer annealing process, wherein the carrier storage layer annealing process uses a silicon boat to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the radius of the wafer; Specifically, in this embodiment, the carrier storage layer annealing process adopts a high-temperature process of 1150°C. In the semiconductor structure fabrication method, a silicon boat is used to support the wafer during the carrier storage layer annealing process. The silicon boat has the same physical properties as the wafer, so it can avoid lattice misalignment caused by the difference in thermal expansion coefficient and thermal conductivity, and improve the contact hole OVL. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point of the silicon boat to the wafer is close to the center of the wafer. In the high-temperature process, the gravitational stress has little effect on the entire wafer, which can improve the situation of large contact hole OVL caused by high temperature in the P-type base region annealing process and improve product yield.

[0057] S203, Sacrificial oxidation process, wherein a silicon boat is used to support the wafer in the sacrificial oxidation process, and the spacing between two adjacent wafers on the silicon boat is double; Specifically, in this embodiment, the sacrificial oxidation process adopts a high-temperature process of 1150°C. In the semiconductor structure fabrication method, a silicon boat is used to support the wafer during the sacrificial oxidation process. The silicon boat has the same physical properties as the wafer, so it can avoid lattice misalignment caused by the difference in thermal expansion coefficient and thermal conductivity, and improve the OVL of the contact hole. In the sacrificial oxidation process, the spacing between two adjacent wafers on the silicon boat is double. The distance between adjacent wafers is larger, and the airflow in the furnace tube during the sacrificial oxidation process is better than that of a single spacing. This can reduce the thermal radiation between wafers in the high-temperature thermal process, improve the situation of large OVL of the contact hole due to the influence of high temperature, and improve the product yield.

[0058] S204, Gate oxidation process, wherein a silicon boat is used to support the wafer in the gate oxidation process, and the spacing between two adjacent wafers on the silicon boat is double; Specifically, in this embodiment, the gate oxidation process adopts a high-temperature process of 1150°C. In the semiconductor structure fabrication method, a silicon boat is used to support the wafer during the gate oxidation process. The silicon boat has the same physical properties as the wafer, so it can avoid lattice misalignment caused by the difference in thermal expansion coefficient and thermal conductivity, and improve the OVL of the contact hole. In the gate oxidation process, the spacing between two adjacent wafers on the silicon boat is double. The distance between adjacent wafers is larger, and the airflow in the furnace tube during the gate oxidation process is better than that of a single spacing. This can reduce the thermal radiation between wafers in the high-temperature thermal process, improve the situation of large OVL of the contact hole due to the influence of high temperature, and improve the product yield.

[0059] S205, P-type base region annealing process, wherein the P-type base region annealing process uses a silicon boat to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

[0060] Specifically, in the semiconductor structure fabrication method, a silicon boat is used to support the wafer during the P-type base region annealing process. The silicon boat has the same physical properties as the wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity, and improving the OVL of the contact holes. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point of the silicon boat to the wafer is close to the center of the wafer, so the gravitational stress has little impact on the entire wafer during the high-temperature process. This can improve the situation where the OVL of the contact holes is too large due to the high temperature in the P-type base region annealing process, and improve the product yield.

[0061] The semiconductor structure fabrication method provided in this invention includes a P-type base region annealing process. This process uses a silicon boat to support the wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. In this semiconductor structure fabrication method, the silicon boat supports the wafer during the P-type base region annealing process. The silicon boat has the same physical properties as the wafer, thus avoiding lattice misalignment caused by differences in thermal expansion coefficients and thermal conductivity. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The support point of the silicon boat is close to the center of the wafer, minimizing the impact of gravitational stress on the entire wafer during high-temperature processes. This semiconductor structure fabrication method can improve the situation where the contact hole overlay accuracy is too high due to high temperature in the P-type base region annealing process, thereby improving product yield.

[0062] The semiconductor fabrication method described above can improve the accuracy of contact hole overlay, thereby ensuring the effectiveness of semiconductor structure component parameters and improving semiconductor yield.

[0063] In the above description, the terms "an embodiment," "some embodiments," "example," "specific example," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: The P-type base region annealing process uses a silicon boat to support the wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the P-type base region annealing process, the spacing between two adjacent wafers on the silicon boat is double.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process preceding the P-type base region annealing includes: The sacrificial oxidation process uses a silicon boat to support the wafers, and the spacing between two adjacent wafers on the silicon boat is double. The gate oxidation process uses a silicon boat to support the wafer, and the spacing between two adjacent wafers on the silicon boat is double.

4. The method for preparing a semiconductor structure according to claim 1 or 3, characterized in that, The process preceding the sacrificial oxidation process also includes: In the P-type field ring annealing process, a silicon boat is used to support the wafer, and the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius. The carrier storage layer annealing process uses a silicon boat to support the wafer, wherein the distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, In the P-type field ring annealing process, the spacing between two adjacent wafers on the silicon boat is a single spacing. In the carrier storage layer annealing process, the spacing between two adjacent wafers on the silicon boat is a single unit. In the P-type base region annealing process, the spacing between two adjacent wafers on the silicon boat is a single unit.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, In the sacrificial oxidation process and the gate oxidation process, the distance from the support point of the silicon boat used to support the wafer to the center of the wafer is less than or equal to 85% of the wafer radius.

7. A method for fabricating a semiconductor structure, characterized in that, include: Acquire images of the semiconductor structure before and after each high-temperature fabrication process during the semiconductor fabrication process; The overlay accuracy after each high-temperature preparation process is obtained from the image; The high-temperature preparation process with the largest overlay accuracy deviation is selected as the target high-temperature preparation process. In the target high-temperature fabrication process, a silicon boat is used to support the wafer. The distance from the support point of the silicon boat to the center of the wafer is less than or equal to 85% of the wafer radius.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The preparation method further includes: In the target high-temperature fabrication process, the spacing between two adjacent wafers on the silicon boat is double.

9. The method for preparing a semiconductor structure according to claim 7 or 8, characterized in that, The high-temperature preparation process is a P-type field ring annealing process, a carrier storage layer annealing process, a sacrificial oxidation process, a gate oxidation process, or a P-type base region annealing process.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The temperature conditions for the P-type field ring annealing process, carrier storage layer annealing process, sacrificial oxidation process, gate oxidation process, and P-type base region annealing process are all 900℃~1200℃.

11. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the semiconductor structure fabrication method according to any one of claims 1-10.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure is an insulated gate bipolar transistor.

Images