LED chip testing method and system

Abstract

The application provides an LED chip testing method and system, the method comprising: collecting a full-domain high-definition image when a wafer is attached to a blue film; identifying all single dies in the wafer and extracting core physical parameters to generate a wafer coordinate file; archiving the wafer coordinate file and transmitting it to a testing machine; calling a corresponding coordinate file in the wafer coordinate file, collecting real-time coordinate data of several feature points of the wafer; comparing and operating the real-time coordinate data with corresponding reference data; generating offset compensation data based on deviation data and dynamically correcting the wafer coordinate file based on the offset compensation data to generate on-site accurate positioning coordinates, and testing parameters of the dies through the accurate positioning coordinates and probes of the testing machine. The application effectively meets the high-efficiency testing demand of large batches of LED chips by canceling the pre-scanning step, and reduces the unit chip testing cost.

Description

Technical Field

[0001] This invention belongs to the technical field of LED chip manufacturing, and specifically relates to an LED chip testing method and system. Background Technology

[0002] In the back-end testing stage of LED chip manufacturing, the traditional process flow is as follows: after the wafer is diced and the blue film is flipped, it is loaded onto a spot testing machine. The machine's camera performs a full-area pre-scan of the entire wafer before electrical parameter testing is carried out. This process relies on pre-scanning to achieve chip positioning, which is a fundamental step to ensure testing accuracy.

[0003] In existing technologies, the pre-scanning of the entire area of ​​each wafer accounts for about 10% of the total testing time of a single wafer. The larger the chip size, the higher the proportion of pre-scanning time, which directly reduces the overall production capacity of the line. Manual pin adjustment by personnel affects efficiency. For chips of different sizes, and with scanning loss, the pre-scanning parameters need to be adjusted frequently, which increases the complexity of process switching and the risk of errors. Manual pin adjustment by personnel increases the risk of anomalies. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an LED chip testing method and system to overcome the shortcomings of the prior art.

[0005] In a first aspect, the present invention provides an LED chip testing method, the method comprising: Capture full-area high-definition images of the wafer and blue film during bonding; Based on the core reference data of the wafer and the full-domain high-definition image, all individual dies within the wafer are identified, and the core physical parameters of all individual dies are extracted to generate a wafer coordinate file. The wafer coordinate file is archived and stored using the unique wafer number as an identifier, and the archived wafer coordinate file is then transmitted to the testing equipment. The test equipment scans the barcode of the wafer, retrieves the corresponding coordinate file from the wafer coordinate file, and scans the wafer to collect real-time coordinate data of several feature points of the wafer. The real-time coordinate data is compared with the corresponding reference data in the wafer coordinate file to calculate the deviation data of the wafer on the stage. Offset compensation data is generated based on the deviation data, and the wafer coordinate file is dynamically corrected based on the offset compensation data to generate precise on-site positioning coordinates. The parameters of the die are then tested using the precise positioning coordinates and the probes of the testing equipment.

[0006] Compared with existing technologies, the beneficial effects of this invention are as follows: By eliminating the pre-scanning step, the time spent on positioning, screening, and process connection corresponding to pre-scanning is directly eliminated, reducing the total testing time for a single batch of LED chips by more than 10%. Simultaneously, through dynamic coordinate adjustment and integrated testing and screening functions, it is ensured that testing accuracy is not reduced and there is no rework or repair after eliminating pre-scanning, avoiding wasted production capacity due to repeated testing. Furthermore, the optimized testing process is compact and coherent, increasing the effective working time of the testing equipment, allowing for the testing of more batches and quantities of LED chips per unit time. Actual verification shows that testing capacity can be increased by 10%, effectively meeting the high-efficiency testing needs of large-volume LED chips and reducing the unit chip testing cost.

[0007] Furthermore, the step of acquiring a full-area high-definition image when the wafer and the blue film are bonded includes: The industrial camera was calibrated, its focal length was calibrated, and its pixel accuracy was calibrated in sequence. Acquire full-area high-definition images of the wafer and blue film during bonding, obtained by an industrial area array camera based on a ring shadowless supplementary light source.

[0008] Furthermore, the step of identifying all individual dies within the wafer based on the core reference data of the wafer and the full-domain high-definition image, and extracting the core physical parameters of all individual dies to generate a wafer coordinate file includes: Identify the wafer layout array rules, and combine the layout array rules, wafer dicing texture features, and standard wafer expansion ratio parameters to identify and sort all individual dies within the wafer; Obtain the physical center coordinates, grain outline, and grain angle deflection of all individual grains to generate a wafer coordinate file containing a unique grain ID, XY plane coordinates, angle offset value, and row and column arrangement number.

[0009] Furthermore, the step of archiving and storing the wafer coordinate file using a unique wafer number as an identifier includes: A unified wafer number is used as an identifier to classify, archive, and store the wafer coordinate files, distinguishing them by batch, specification, and production period to establish a hierarchical data directory.

[0010] Furthermore, the step of scanning the wafer to acquire real-time coordinate data of several feature points of the wafer includes: The vision system of the test equipment performs local scanning of the upper edge, lower edge, left edge, right edge and center of the wafer to obtain a scanned image. Real-time coordinate data of five feature points are acquired based on the scanned image.

[0011] Furthermore, the deviation data includes planar translation deviation, circumferential rotation angle deviation, and minute position offset.

[0012] Furthermore, after the step of performing parameter testing on the die using the precise positioning coordinates and the probes of the testing machine, the method further includes: The test data after parameter testing are summarized, and the test data corresponding to each individual die is bound and archived to establish a full life cycle electronic data archive for a single wafer.

[0013] Secondly, the present invention also provides an LED chip testing system, the system comprising: The acquisition module is used to acquire full-area high-definition images of the wafer and the blue film during bonding. The identification module is used to identify all individual dies within the wafer based on the core reference data of the wafer and the full-domain high-definition image, and to extract the core physical parameters of all individual dies to generate a wafer coordinate file. The storage module is used to archive and store the wafer coordinate file using a unique wafer number as an identifier, and to transmit the archived wafer coordinate file to the testing equipment. The retrieval module is used to scan the barcode of the wafer based on the test equipment, retrieve the corresponding coordinate file in the wafer coordinate file, and scan the wafer to collect real-time coordinate data of several feature points of the wafer; The comparison module is used to compare the real-time coordinate data with the corresponding reference data in the wafer coordinate file to calculate the deviation data of the wafer on the stage. The generation module is used to generate offset compensation data based on the deviation data, and to dynamically correct the wafer coordinate file based on the offset compensation data to generate precise on-site positioning coordinates, and to perform parameter testing on the die using the precise positioning coordinates and the probes of the testing machine.

[0014] Thirdly, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described LED chip testing method.

[0015] Fourthly, the present invention also provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described LED chip testing method. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the LED chip testing method in the first embodiment of the present invention; Figure 2 This is a structural block diagram of the LED chip testing system in the second embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the electronic device in the third embodiment of the present invention.

[0018] Explanation of key component symbols: 10. Acquisition Module; 20. Identification Module; 30. Storage Module; 40. Retrieval Module; 50. Comparison Module; 60. Generation Module; 70. Bus; 71. Processor; 72. Memory; 73. Communication interface.

[0019] The embodiments of the present invention will be further described below with reference to the accompanying drawings. Detailed Implementation

[0020] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0021] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] Example 1 Please see Figure 1 The image shows an LED chip testing method according to the first embodiment of the present invention, the method comprising steps S1 to S6: S1, acquires full-area high-definition images of the wafer and blue film during bonding; Specifically, step S1 includes steps S11 to S12: S11 sequentially performs focal length calibration, adjustment, and pixel accuracy calibration on the industrial camera; S12, acquire full-area high-definition images of the wafer and blue film bonding when the industrial area array camera is based on the ring shadowless supplementary light source; It should be noted that the blue film flipping station is equipped with a high-definition, high-frame-rate industrial area array camera, a ring-shaped shadowless supplementary light source, and an independent AI vision computing and processing unit. The entire vision component completes precise focus calibration, pixel accuracy calibration, and other processes. After the wafer and blue film are bonded together and the entire flipping and shaping process is completed, the equipment automatically triggers full-area high-definition image acquisition, completing full-area imaging of the entire wafer without blind spots in one go. This ensures the clarity and consistency of the chip array imaging and avoids imaging errors caused by wafer warping, material color differences, and uneven lighting.

[0024] S2, based on the core reference data of the wafer and the full-domain high-definition image, identify all individual dies in the wafer and extract the core physical parameters of all individual dies to generate a wafer coordinate file; Specifically, step S2 includes steps S21 to S22: S21, identify the wafer arrangement array rules, and combine the arrangement array rules, wafer dicing texture features, and standard wafer expansion ratio parameters to identify and sort all individual dies in the wafer; S22, obtain the physical center coordinates, grain outline, and grain angle deflection of all the individual grains to generate a wafer coordinate file containing a unique grain ID, XY plane coordinates, angle offset value, and row and column arrangement number. It should be noted that, relying on mature wafer array recognition AI deep learning algorithms, and combining three core benchmark data—the array rules for wafer chips of different sizes, the texture features of wafer dicing channels, and standard wafer expansion ratio parameters—the system autonomously completes the intelligent sorting and identification of all individual dies within the entire wafer. It accurately captures core physical parameters such as the physical center coordinates, die outline, and die angle deflection of each die, automatically assigns a unique die code, and generates standardized, structured wafer-wide die coordinate archives in batches. Each archive contains a unique die ID, precise XY plane coordinates, angle offset value, and row / column arrangement sequence number.

[0025] S3, using the unique wafer number as an identifier, archive and store the wafer coordinate file, and then transmit the archived wafer coordinate file to the testing equipment; Specifically, step S3 includes step S31: S31, using the unique wafer number as an identifier, classify and archive the wafer coordinate files, distinguish batches and specifications, and establish a hierarchical data directory based on production time period; It should be noted that, 3. All generated wafer die coordinate files are uniformly classified and archived using the unique wafer number as the core identifier. A hierarchical data directory is established by batch, specification, and production period. At the same time, a two-way data connection channel is reserved between the MES production execution system and the factory cloud data platform, which can realize high-speed data synchronization of coordinate files across workstations, equipment, and production lines, and complete the data link between the flip-flop workstation and the back-end testing workstation, providing the original and accurate coordinate data source for the subsequent end-point testing process.

[0026] S4, based on the barcode of the wafer scanned by the test equipment, the corresponding coordinate file is retrieved from the wafer coordinate file, and the wafer is scanned to collect real-time coordinate data of several feature points of the wafer; Specifically, step S4 includes steps S41 to S42: S41, based on the vision system of the test equipment, the upper edge, lower edge, left edge, right edge and center position of the wafer are partially scanned to obtain a scanned image; S42, acquire real-time coordinate data of five feature points based on the scanned image; It should be noted that the point probe testing machine has undergone a software upgrade, adding a dedicated data reading and parsing interface for standardized coordinate files, compatible with both local database retrieval and cloud batch download data acquisition modes. After the automatic wafer feeding mechanism completes the wafer placement and positioning, it retrieves the pre-generated full-domain die coordinate files for the corresponding batch of wafers with one click through two triggering methods: material barcode scanning and recognition, and automatic wafer number matching. This eliminates the need for manual coordinate input and alignment calibration, significantly simplifying the pre-processing workflow. The machine's vision system only performs local scanning on five preset feature points of the wafer (top, middle, bottom, left, and right edge chips). By comparing the feature point coordinates with the file data, it calculates the minute offsets (translation and rotation) of the wafer on the machine platform.

[0027] S5, compare the real-time coordinate data with the corresponding reference data in the wafer coordinate file to calculate the deviation data of the wafer on the stage; In this embodiment, the deviation data includes planar translation deviation, circumferential rotation angle deviation, and minute position offset.

[0028] It should be noted that, 5. The traditional two-stage full-area scanning positioning mode for the entire wafer is abandoned, significantly reducing the time required for visual alignment. The point-testing machine's vision system selects only five edge reference features on the wafer (top, bottom, left, right, and center) as positioning reference points. It performs rapid, localized visual scanning imaging on only these five reference points, quickly acquiring real-time coordinate data of the actual reference points on site. The system intelligently compares and calculates the coordinates of the measured feature points with pre-stored standard coordinate archive reference data, quickly and accurately determining the three core offset parameters: planar translational deviation, circumferential rotation angle deviation, and minute positional offset caused by the wafer being placed on the stage.

[0029] S6. Based on the deviation data, offset compensation data is generated, and the wafer coordinate file is dynamically corrected based on the offset compensation data to generate precise on-site positioning coordinates. The parameters of the die are tested using the precise positioning coordinates and the probes of the test equipment. It should be noted that, 6. The main motion control system of the equipment receives wafer offset compensation data calculated by vision in real time, performs global dynamic deviation correction and coordinate adaptive conversion on the original global die coordinate file, and quickly generates accurate on-site positioning coordinates that fit the actual placement state of the current test platform. The system directly sends the corrected accurate coordinate data to the probe motion actuator, driving the high-precision probe station to complete automatic die positioning, precise electrode alignment, and fixed-point probe testing. The entire process does not require manual fine-tuning of the alignment origin, effectively reducing manual alignment errors and improving test consistency and yield. The test platform software has added file reading and correction calculation functions, which can automatically adjust the 5-point scanning path and offset calculation model according to the wafer size and magnification.

[0030] Specifically, step S6 includes step S61: S61, summarize the test data after parameter testing, and bind and archive the test data corresponding to a single die to establish a full life cycle electronic data archive for a single wafer. It should be noted that the system automatically aggregates wafer front-end wafer enlargement and flipping imaging data, global die coordinate data, point measurement alignment correction data, and probe test result data, completing the binding and archiving of data for the entire process of a single die. This establishes a full lifecycle electronic data archive for each wafer, enabling queryable, traceable, and reproducible data throughout the entire process from die arrangement and positioning to electrical performance testing. This facilitates subsequent production line process optimization, defective die source analysis, and equipment alignment accuracy calibration and debugging, comprehensively improving the efficiency of automated operation throughout the entire back-end semiconductor testing process. In summary, the LED chip testing method in the above embodiments of the present invention, by eliminating the pre-scanning step, directly eliminates the time-consuming positioning, screening, and process connection associated with pre-scanning, reducing the total testing time for a single batch of LED chips by more than 10%. Simultaneously, through the integration of a coordinate adaptive calibration mechanism and test screening function, it ensures that the testing accuracy is not reduced and there is no rework or repair after eliminating pre-scanning, avoiding the waste of production capacity caused by repeated testing. Furthermore, the optimized testing process is compact and coherent, increasing the effective working time of the testing equipment, allowing for the testing of more batches and a greater number of LED chips per unit time. Actual verification shows that testing capacity can be increased by 10%, effectively adapting to the high-efficiency testing needs of large-volume LED chips and reducing the unit chip testing cost.

[0031] Example 2 Please see Figure 2 The image shows an LED chip testing system according to a second embodiment of the present invention, the system comprising: Acquisition module 10 is used to acquire full-area high-definition images of the wafer and blue film during bonding; The identification module 20 is used to identify all individual dies in the wafer based on the core reference data of the wafer and the full-domain high-definition image, and extract the core physical parameters of all individual dies to generate a wafer coordinate file. Storage module 30 is used to archive and store the wafer coordinate file using a unique wafer number as an identifier, and to transmit the archived wafer coordinate file to the testing equipment. The retrieval module 40 is used to scan the barcode of the wafer based on the test equipment, retrieve the corresponding coordinate file in the wafer coordinate file, and scan the wafer to collect real-time coordinate data of several feature points of the wafer; The comparison module 50 is used to compare the real-time coordinate data with the corresponding reference data in the wafer coordinate file to calculate the deviation data of the wafer on the stage. The generation module 60 is used to generate offset compensation data based on the deviation data, and to dynamically correct the wafer coordinate file based on the offset compensation data to generate precise on-site positioning coordinates, and to perform parameter testing on the die using the precise positioning coordinates and the probes of the testing machine.

[0032] In some alternative embodiments, the acquisition module 10 includes: The calibration unit is used to sequentially calibrate the focal length, perform calibration, and calibrate the pixel accuracy of the industrial camera. The first acquisition unit is used to acquire full-area high-definition images of the wafer and blue film bonding when the wafer is bonded, collected by an industrial area array camera based on a ring shadowless supplementary light source.

[0033] In some alternative embodiments, the identification module 20 includes: The identification unit is used to identify the arrangement array rules of the wafer, and to identify and sort all individual dies in the wafer by combining the arrangement array rules, wafer dicing texture features, and standard wafer expansion ratio parameters. The second acquisition unit is used to acquire the physical center coordinates, grain shape boundary contours, and grain angle deflection of all the individual grains, so as to generate a wafer coordinate file containing a unique grain ID, XY plane coordinates, angle offset value, and row and column arrangement number.

[0034] In some alternative embodiments, the storage module 30 includes: The storage unit is used to classify and archive the wafer coordinate files using a unified wafer number as an identifier, and to establish a hierarchical data directory that distinguishes batches, specifications, and production periods.

[0035] In some alternative embodiments, the retrieval module 40 includes: The scanning unit is used to perform local scanning of the upper edge, lower edge, left edge, right edge and center position of the wafer based on the vision system of the test machine to obtain a scanned image; The acquisition unit is used to acquire real-time coordinate data of five feature points based on the scanned image.

[0036] In some alternative embodiments, the generation module 60 includes: The aggregation unit is used to aggregate the test data after parameter testing and to bind and archive the test data corresponding to each individual die to establish a full lifecycle electronic data archive for a single wafer. The functions or operation steps implemented by the above modules and units are largely the same as those in the above method embodiments, and will not be repeated here.

[0037] The LED chip testing system provided in this embodiment of the invention has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0038] Example 3 The third embodiment of the present invention also proposes an electronic device, please refer to [link / reference]. Figure 3 The image shows an electronic device according to a third embodiment of the present invention.

[0039] The electronic device may include a processor 71 and a memory 72 storing computer program instructions.

[0040] Specifically, the processor 71 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement this application.

[0041] The memory 72 may include a mass storage device for data or instructions. For example, and not limitingly, the memory 72 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), flash memory, an optical disk drive, a magneto-optical disk drive, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 72 may include removable or non-removable (or fixed) media. Where appropriate, the memory 72 may be internal or external to a data processing device. In a particular embodiment, the memory 72 is non-volatile memory. In a particular embodiment, the memory 72 includes read-only memory (ROM) and random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), an electrically alterable read-only memory (EAROM), or flash memory, or a combination of two or more of these. Where appropriate, the RAM can be Static Random-Access Memory (SRAM) or Dynamic Random-Access Memory (DRAM). DRAM can be Fast Page Mode Dynamic Random-Access Memory (FPMDRAM), Extended Data Out Dynamic Random-Access Memory (EDODRAM), Synchronous Dynamic Random-Access Memory (SDRAM), etc.

[0042] The memory 72 can be used to store or cache various data files that need to be processed and / or communicated, as well as possible computer program instructions executed by the processor 71.

[0043] The processor 71 reads and executes the computer program instructions stored in the memory 72 to implement the LED chip testing method of the above embodiment 1.

[0044] In some embodiments, the electronic device may further include a communication interface 73 and a bus 70. For example, Figure 3 As shown, the processor 71, memory 72, and communication interface 73 are connected through bus 70 and complete communication with each other.

[0045] The communication interface 73 is used to enable communication between the various modules, devices, units, and / or equipment in this application. The communication interface 73 can also enable data communication with other components such as external devices, image / data acquisition devices, databases, external storage, and image / data processing workstations.

[0046] Bus 70 includes hardware, software, or both, that couples the components of a device together. Bus 70 includes, but is not limited to, at least one of the following: data bus, address bus, control bus, expansion bus, and local bus. For example, and not as a limitation, bus 70 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 70 may include one or more buses. Although this application describes and illustrates a specific bus, this application considers any suitable bus or interconnection.

[0047] The electronic device can acquire an LED chip testing system and execute the LED chip testing method of this embodiment.

[0048] In addition, in conjunction with the LED chip testing method in Embodiment 1 above, this application can provide a storage medium for implementation. This storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement the LED chip testing method of Embodiment 1 above.

[0049] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0050] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for testing LED chips, characterized in that, The method includes: Capture full-area high-definition images of the wafer and blue film during bonding; Based on the core reference data of the wafer and the full-domain high-definition image, all individual dies within the wafer are identified, and the core physical parameters of all individual dies are extracted to generate a wafer coordinate file. The wafer coordinate file is archived and stored using the unique wafer number as an identifier, and the archived wafer coordinate file is then transmitted to the testing equipment. The test equipment scans the barcode of the wafer, retrieves the corresponding coordinate file from the wafer coordinate file, and scans the wafer to collect real-time coordinate data of several feature points of the wafer. The real-time coordinate data is compared with the corresponding reference data in the wafer coordinate file to calculate the deviation data of the wafer on the stage. Offset compensation data is generated based on the deviation data, and the wafer coordinate file is dynamically corrected based on the offset compensation data to generate precise on-site positioning coordinates. The parameters of the die are then tested using the precise positioning coordinates and the probes of the testing equipment.

2. The LED chip testing method according to claim 1, characterized in that, The steps for acquiring full-area high-definition images of the wafer when it is bonded to the blue film include: The industrial camera was calibrated, its focal length was calibrated, and its pixel accuracy was calibrated in sequence. Acquire full-area high-definition images of the wafer and blue film during bonding, obtained by an industrial area array camera based on a ring shadowless supplementary light source.

3. The LED chip testing method according to claim 1, characterized in that, The step of identifying all individual dies within the wafer based on the core reference data of the wafer and the full-domain high-definition image, and extracting the core physical parameters of all individual dies to generate a wafer coordinate file includes: Identify the wafer layout array rules, and combine the layout array rules, wafer dicing texture features, and standard wafer expansion ratio parameters to identify and sort all individual dies within the wafer; Obtain the physical center coordinates, grain outline, and grain angle deflection of all individual grains to generate a wafer coordinate file containing a unique grain ID, XY plane coordinates, angle offset value, and row and column arrangement number.

4. The LED chip testing method according to claim 1, characterized in that, The step of archiving and storing the wafer coordinate file using a unique wafer number as an identifier includes: A unified wafer number is used as an identifier to classify, archive, and store the wafer coordinate files, distinguishing them by batch, specification, and production period to establish a hierarchical data directory.

5. The LED chip testing method according to claim 1, characterized in that, The step of scanning the wafer to collect real-time coordinate data of several feature points of the wafer includes: The vision system of the test equipment performs local scanning of the upper edge, lower edge, left edge, right edge and center of the wafer to obtain a scanned image. Real-time coordinate data of five feature points are acquired based on the scanned image.

6. The LED chip testing method according to claim 1, characterized in that, The deviation data includes planar translation deviation, circumferential rotation angle deviation, and minute position offset.

7. The LED chip testing method according to claim 1, characterized in that, After the step of performing parameter testing on the grain using the precise positioning coordinates and the probes of the testing machine, the method further includes: The test data after parameter testing are summarized, and the test data corresponding to each individual die is bound and archived to establish a full life cycle electronic data archive for a single wafer.

8. An LED chip testing system, characterized in that, The system includes: The acquisition module is used to acquire full-area high-definition images of the wafer and the blue film during bonding. The identification module is used to identify all individual dies within the wafer based on the core reference data of the wafer and the full-domain high-definition image, and to extract the core physical parameters of all individual dies to generate a wafer coordinate file. The storage module is used to archive and store the wafer coordinate file using a unique wafer number as an identifier, and to transmit the archived wafer coordinate file to the testing equipment. The retrieval module is used to scan the barcode of the wafer based on the test equipment, retrieve the corresponding coordinate file in the wafer coordinate file, and scan the wafer to collect real-time coordinate data of several feature points of the wafer; The comparison module is used to compare the real-time coordinate data with the corresponding reference data in the wafer coordinate file to calculate the deviation data of the wafer on the stage. The generation module is used to generate offset compensation data based on the deviation data, and to dynamically correct the wafer coordinate file based on the offset compensation data to generate precise on-site positioning coordinates, and to perform parameter testing on the die using the precise positioning coordinates and the probes of the testing machine.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the LED chip testing method as described in any one of claims 1 to 7.

10. A storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the LED chip testing method as described in any one of claims 1 to 7.

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