Trench isolation and method of fabricating semiconductor devices

Abstract

The application provides a trench isolation and semiconductor device manufacturing method. In the trench manufacturing method, a first pad oxide layer, a nitride layer, a second pad oxide layer and an organic dielectric layer are used as a mask stack structure, the mask stack structure has high etching selectivity, can ensure high-precision transfer of the pattern, and can generate oxide byproducts close to the material of the oxide layer during etching of the semiconductor substrate. The oxide byproducts will gather at the top surface of the active region and up and down with the first pad oxide layer as the gathering point, and will generate basically consistent gathering modes regardless of the pattern density. The oxide byproducts have a relatively thin gathering thickness and are difficult to etch, so that the reduction of the critical dimension of the active region becomes slow during etching of the semiconductor substrate, thereby reducing the difference of the critical dimension of the active region in different pattern density areas, eliminating the double slop in the sparse pattern area, and reducing the CD Bias of the active region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating trench isolation and semiconductor devices. Background Technology

[0002] With the continuous development of semiconductor manufacturing processes, the requirements for device isolation performance are becoming increasingly stringent, leading to the development of Shallow Trench Isolation (STI) technology. This involves creating shallow trench isolation structures within isolation devices to achieve isolation, filling these structures with insulating materials to insulate the devices to be isolated. In essence, shallow trench isolation isolates the active area (AA) of the device being fabricated. In current semiconductor chip fabrication processes, shallow trench isolation structures play a crucial role. Due to their ability to achieve high-density isolation, they are widely used in high-density semiconductor devices such as deep submicron devices and memory. Especially as semiconductor manufacturing processes reach 20nm and below, the requirements for isolation between devices become even more stringent, further highlighting the importance of shallow trench isolation technology.

[0003] As manufacturing processes become more refined and complex, the precision requirements for critical dimension offset (CD bias, i.e., the offset between the actual CD and the designed CD) of the wafer surface are also increasing. Specifically, the CD bias of the AA must be small in both densely patterned (dense) and sparsely patterned (isolated) regions of the wafer surface, while also requiring a small difference between the CD bias in the dense region and the CD bias in the isolated region. This poses a severe challenge to the photolithography etching process. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench isolation and semiconductor device fabrication method to solve the problem that when the active region is isolated by trench isolation in the prior art, the actual critical size of the active region formed on the wafer surface deviates significantly from the designed critical size, and the deviation of the critical size of the active region in the dense region differs significantly from that in the sparse region.

[0005] To achieve the above and other related objectives, the present invention provides a method for preparing trench isolation, including a method for preparing trenches, the method comprising the following steps:

[0006] Provide semiconductor substrates;

[0007] A first pad oxide layer, a nitride layer, a second pad oxide layer, an organic dielectric layer, and a photoresist layer are formed sequentially covering the surface of the semiconductor substrate;

[0008] The photoresist layer is patterned, and the organic dielectric layer is etched based on the patterned photoresist layer to obtain the patterned organic dielectric layer, and then the patterned photoresist layer is removed.

[0009] Based on the patterned organic dielectric layer, the second pad oxide layer, the nitride layer and the first pad oxide layer are etched to obtain the patterned second pad oxide layer, the nitride layer and the first pad oxide layer, and then the patterned organic dielectric layer is removed.

[0010] The semiconductor substrate is etched using the patterned second pad oxide layer as a barrier layer to form trenches in the semiconductor substrate; wherein the etching gas used for etching includes hydrogen bromide gas and oxygen.

[0011] Optionally, the semiconductor substrate is a silicon substrate, the first pad oxide layer is a silicon oxide layer, the nitride layer is a silicon nitride layer, and the second pad oxide layer is a silicon oxide layer.

[0012] Furthermore, the first pad oxide layer is prepared using a thermo-oxidative process, the second pad oxide layer is prepared using a CVD process, and the organic dielectric layer and the photoresist layer are prepared using a spin-coating process.

[0013] Optionally, a SiARC layer may be formed between the organic dielectric layer and the photoresist layer; or a DARC layer and a BARC layer may be formed between the organic dielectric layer and the photoresist layer.

[0014] Furthermore, when the SiARC layer is formed between the organic dielectric layer and the photoresist layer, the method of etching the organic dielectric layer based on the patterned photoresist layer includes: etching the SiARC layer based on the patterned photoresist layer to obtain the patterned SiARC layer; then etching the organic dielectric layer based on the patterned photoresist layer and the SiARC layer to obtain the patterned organic dielectric layer; and finally removing the patterned SiARC layer and the photoresist layer. When the DARC layer and the BARC layer are formed between the organic dielectric layer and the photoresist layer, the method of etching the organic dielectric layer based on the patterned photoresist layer includes: etching the BARC layer and the DARC layer based on the patterned photoresist layer to obtain the patterned BARC layer and the DARC layer; then removing the patterned photoresist layer and the BARC layer; next, etching the organic dielectric layer based on the patterned DARC layer to obtain the patterned organic dielectric layer; and finally removing the patterned DARC layer.

[0015] Optionally, the semiconductor substrate includes a patterned dense region and a patterned sparse region.

[0016] Optionally, the thickness of the first pad oxide layer is The thickness of the nitride layer is The thickness of the second pad oxide layer is The thickness of the organic dielectric layer is

[0017] Optionally, after forming the trench, the method further includes the step of filling the trench with insulating material.

[0018] Furthermore, the method for filling the trench with insulating material includes: firstly, wet cleaning the obtained structure; then filling the surface of the obtained structure and the trench with the insulating material; next, grinding the insulating material with a grinding process until the surface of the nitride layer is exposed; and finally removing the nitride layer.

[0019] The present invention also provides a method for fabricating a semiconductor device, comprising fabricating a trench isolation using any one of the trench isolation fabrication methods described above, and fabricating a semiconductor device in the active region isolated by the trench isolation.

[0020] As described above, the present invention provides a method for fabricating trench isolation and semiconductor devices. In the trench fabrication method, a first pad oxide layer, a nitride layer, a second pad oxide layer, and an organic dielectric layer are used as a mask stack structure for the photolithography process. The organic dielectric layer has a high etching selectivity with the second pad oxide layer, the nitride layer, and the first pad oxide layer, which can ensure high-precision pattern transfer. Based on this, when etching the semiconductor substrate, the patterned second pad oxide layer is used as a barrier layer, and hydrogen bromide gas and oxygen are used as the main etching gases. During the etching process, oxide byproducts are generated, and these oxide byproducts react with the oxide layer. Because the materials are similar, the oxide layer on the first pad will act as an attachment point to aggregate on the top and bottom surfaces of the active region. This aggregation pattern is consistent regardless of the density of the pattern. The oxide byproducts are thin and difficult to etch. Since the active region CD is defined with high precision when etching the second pad oxide layer, nitride layer and first pad oxide layer, the shrinkage of the critical dimension of the active region becomes slower when etching the semiconductor substrate to form trenches. This reduces the difference in critical dimension offset of the active region in areas with different pattern densities and eliminates the double slop in sparse areas, reducing the CD bias of the active region and facilitating the increase of the photolithography process window. Attached Figure Description

[0021] Figures 1 to 6 The diagram shows cross-sectional structural schematics of each step in the trench fabrication process for a trench isolation system, presented as a scaled-down model.

[0022] Figure 7 The image shown is a TEM image of grooves formed in sparse areas of the graphic, presented as a comparative example.

[0023] Figure 8 The image shown is a TEM image of grooves formed in densely patterned areas, presented as a comparative example.

[0024] Figures 9 to 16 The diagram shows the cross-sectional structure of each step in the trench preparation process of the trench isolation according to the present invention.

[0025] Figure 17 The image shown is a TEM image of the formation of trenches in a sparse region of a pattern during the trench fabrication process of this invention.

[0026] Figure 18 The image shown is a TEM image of the formation of trenches in a densely patterned area during the trench fabrication process of this invention.

[0027] Figures 19 to 24 The diagram shows a cross-sectional view of each step in the process of filling the trench with insulating material in the trench isolation of the present invention. Figures 19 to 23 It means Figure 16 The subsequent process steps of local structure A.

[0028] Component designation explanation

[0029] 10 Semiconductor substrate

[0030] 100 First Pad Oxide Layer

[0031] 101 Nitride layer

[0032] 102 Second Pad Oxide Layer

[0033] 103 Organic dielectric layer

[0034] 104 Photoresist layer

[0035] 105 SiARC layer

[0036] 106 DARC layers

[0037] 107 BARC layer

[0038] 11. Trench

[0039] 12 Insulation materials

[0040] 13 Oxide Byproducts

[0041] 14 Active Region

[0042] 20 Semiconductor substrates

[0043] 200 hard mask layers

[0044] 201 APF layer

[0045] 202 DARC layer

[0046] 203 BARC layer

[0047] 204 photoresist layer

[0048] 205 C-rich byproducts

[0049] 21. Trench

[0050] 22 Active Region

[0051] 23 Key Dimensions Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] Please see Figures 1 to 24 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] like Figures 1 to 6 The diagram illustrates the trench fabrication process in an example of trench isolation. For example... Figure 1 As shown, a hard mask layer 200, an APF layer 210 (Advanced Patterning Film), a DARC layer 202 (Dielectric Anti-Reflective Coating), a BARC layer 203 (Bottom Anti-Reflective Coating), and a photoresist layer 204 are sequentially deposited on the surface of the semiconductor substrate 20, and the photoresist layer 204 is then patterned; as shown... Figure 2 As shown, based on the patterned photoresist layer 204, the BARC layer 203 and DARC layer 202 are etched, and the pattern is transferred to the DARC layer 202; as Figure 2 and Figure 3 As shown, the APF layer 201 is etched based on the graphical DARC layer 202, transferring the pattern to the APF layer 201; as Figure 4 As shown, the hard mask layer 200 is etched based on the patterned APF layer 201, transferring the pattern to the hard mask layer 200; as Figure 5 and Figure 6 As shown, the semiconductor substrate 20 is etched based on a patterned hard mask layer 200 and a patterned APF layer 201 as an etch barrier layer, and then the patterned APF layer 201 is removed to form the desired trench 21 in a predetermined area of ​​the semiconductor substrate 20. The trench 21 prepared using this example has two problems. First, the critical size offset of the active area defined by the densely patterned region and the sparsely patterned region on the semiconductor substrate 20 is different. In the densely patterned region, the critical size offset of the active area is positive, meaning that the critical size CD of the active area after development inspection (ADI) in the densely patterned region is greater than the critical size CD of the active area after etching inspection (AEI), ADI-AELCD = +x. This means that the CD of the active area after etching can be smaller than the CD of the active area after exposure and development, which is equivalent to further reducing the CD of the active area. This has a positive impact on the photolithography process window and can expand the photolithography process window. In the sparsely patterned region, the critical size offset of the active area is negative, meaning that the critical size CD of the active area after ADI in the densely patterned region is smaller than the critical size CD of the active area after AEI, ADI-AEL CD = -x. This means that the CD of the active area after etching is larger than the CD of the active area after exposure and development. It is often desirable for the AEI CD of the active area after etching to be close to the ADI CD, but in this example, AEI often appears in the sparsely patterned region. The significant offset of CD > ADI CD + 10nm means that even if the lithographic ADI CD can be further reduced using OPC methods to shrink the post-etched AEI CD, this will result in insufficient lithography process window, sometimes even failing to meet process requirements. Secondly, the trenches 21 formed in the sparse patterned areas after etching will exhibit double sloping patterns, such as... Figure 7 The outline of trench 21 is shown in the red dashed box. The presence of double slop makes it difficult to control the uniformity of the active region CD, and the double slop occurs in the active region 22, causing instability in the CD of the active region 22. The inventors found that the reason for the above problems is that during the etching of the semiconductor substrate 20 using the APF layer 201 as a barrier layer, the main etching gas used is CHF3. During the etching of the semiconductor substrate 20, the APF layer 201 is also consumed, forming C-rich byproducts 205. These C-rich byproducts 205 are more likely to adsorb and accumulate on the top surface of the active region in sparsely patterned areas. Since these C-rich byproducts 205 are more difficult to etch than the semiconductor substrate, the etching rate in this area is slowed down, making it difficult to reduce the size of the active region CD and causing double slop. In densely patterned areas, these C-rich byproducts 205 are less likely to adsorb and accumulate on the top surface of the active region (e.g., Figure 8As shown in the figure, the CD of the active region will shrink at a rate larger than that of the active region in the sparse region of the figure, which ultimately leads to a large difference in CDBias between the dense region and the sparse region of the figure, and the CDBias in the sparse region of the figure is also larger.

[0055] Based on the above research, the inventors, focusing on the aspect of ensuring that the byproducts generated during the etching of the semiconductor substrate are thinly adsorbed and aggregated, and insensitive to the density of the pattern (i.e., when the byproducts are thinly adsorbed and aggregated, regardless of the density of the pattern, the byproducts exhibit a consistent adsorption and aggregation), propose a method for preparing trench isolation, including a trench preparation method, wherein the trench preparation method includes the following steps:

[0056] S1 provides a semiconductor substrate;

[0057] S2, forming a first pad oxide layer, a nitride layer, a second pad oxide layer, an organic dielectric layer, and a photoresist layer that sequentially cover the surface of the semiconductor substrate;

[0058] S3, pattern the photoresist layer, and etch the organic dielectric layer based on the patterned photoresist layer to obtain the patterned organic dielectric layer, and then remove the patterned photoresist layer;

[0059] S4, based on the patterned organic dielectric layer, the second pad oxide layer, the nitride layer and the first pad oxide layer are etched to obtain the patterned second pad oxide layer, the nitride layer and the first pad oxide layer, and then the patterned organic dielectric layer is removed;

[0060] S5, using the patterned second pad oxide layer as a barrier layer, the semiconductor substrate is etched to form trenches in the semiconductor substrate; wherein the etching gas used for etching includes hydrogen bromide gas and oxygen.

[0061] In the trench isolation trench fabrication method of this embodiment, a first pad oxide layer, a nitride layer, a second pad oxide layer, and an organic dielectric layer are used as the mask stack structure for the photolithography process. The organic dielectric layer has a high etching selectivity with the second pad oxide layer, the nitride layer, and the first pad oxide layer, which can ensure high-precision pattern transfer. Based on this, when etching the semiconductor substrate, the patterned second pad oxide layer is used as a barrier layer, and hydrogen bromide gas and oxygen are used as the main etching gases. During the etching process, oxide byproducts are generated. These oxide byproducts are similar in material to the oxide layer, thereby allowing the first pad oxide layer to be used as the etching layer. The first-pad oxide layer aggregates at the top and bottom of the active region, depending on the aggregation points. Regardless of the pattern density, it produces a basically consistent aggregation pattern. At the same time, the oxide by-product aggregation is thin and difficult to etch. Since the active region CD is defined with high precision when etching the second pad oxide layer, nitride layer and the first pad oxide layer, the shrinkage of the critical dimension of the active region becomes slower when etching the semiconductor substrate to form trenches. This reduces the difference in critical dimension offset of the active region in areas with different pattern densities. It can also eliminate the double slop in sparse areas of the pattern, reduce the CDBias of the active region, and help to increase the photolithography process window.

[0062] The preparation method of the trench isolation in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0063] like Figure 9 As shown, step S1 is performed first, providing a semiconductor substrate 10.

[0064] As an example, the semiconductor substrate 10 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This embodiment does not limit the specific material and thickness of the semiconductor substrate 10, and the semiconductor substrate 10 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate. The doping type and concentration of the impurities can be flexibly set according to the desired semiconductor structure. In this embodiment, the semiconductor substrate 10 is selected as a silicon substrate.

[0065] As an example, the semiconductor substrate 10 includes a patterned dense region and a patterned sparse region.

[0066] like Figure 10 As shown, step S2 is then performed to form a first pad oxide layer 100, a nitride layer 101, a second pad oxide layer 102, an organic dielectric layer 103, and a photoresist layer 104 that sequentially cover the surface of the semiconductor substrate 10.

[0067] The first pad oxide layer 100 can serve as a protective layer for the semiconductor substrate 10, protecting the semiconductor substrate 10 it covers during subsequent processes and preventing unnecessary damage. It can also buffer the stress of the nitride layer 101, preventing dislocations from forming on the semiconductor substrate 10. The first pad oxide layer 100 can be prepared using a thermo-oxidative process, such as dry oxidation, wet oxidation, or in-situ steam generation (ISSG). In this embodiment, when the semiconductor substrate 10 is a silicon substrate, the first pad oxide layer 100 is a silicon oxide layer. A dry oxidation method is chosen to form the first pad oxide layer 100. Specifically, the semiconductor substrate 10 is placed in a furnace tube, oxygen is introduced, and the surface of the semiconductor substrate 10 reacts with the oxygen at high temperature to generate a dense silicon oxide material, forming the first pad oxide layer 100. The thickness of the first pad oxide layer 100 is selected as follows: Between, including endpoint values.

[0068] After forming the first pad oxide layer 100, the nitride layer 101 is formed on the first pad oxide layer 100. The material of the nitride layer 101 can be silicon nitride or silicon oxynitride; in this embodiment, silicon nitride is selected. The nitride layer 101 can be prepared using existing common and suitable deposition processes, such as CVD processes. For example, when the nitride layer 101 is prepared using an LPCVD process, silicon nitride can be generated by reacting ammonia with dichlorosilane. The thickness of the nitride layer 101 is selected as follows: Between, including endpoint values.

[0069] The second pad oxide layer 102 subsequently serves as a surface barrier layer during the etching of the semiconductor substrate 10 and can be prepared using existing common and suitable deposition processes. In this embodiment, the second pad oxide layer 102 is selected as a silicon oxide layer, and TEOS is used as the deposition source to prepare the second pad oxide layer 102 using a CVD process. For example, when preparing the second pad oxide layer 102 of silicon oxide material using a CVD process, it is obtained by decomposing TEOS at high temperature and reacting it with oxygen to generate a silicon oxide thin film. The thickness of the second pad oxide layer 102 is selected as follows: Between, including endpoint values.

[0070] The organic dielectric layer 103 (OLD) is a dielectric layer made of organic polymers or small molecule materials. During photolithography, the organic dielectric layer 103 can act as an anti-reflective coating. By optimizing the thickness and refractive index of the organic dielectric layer 103, the intensity of reflected light can be reduced, significantly decreasing its influence and improving photolithography resolution and pattern quality. In this embodiment, the organic dielectric layer 103 is preferably prepared using a spin-coating method. A solution of the organic dielectric material is uniformly coated onto the semiconductor substrate 10, and the solution is uniformly distributed and formed into a thin film by rotation. The thickness of the organic dielectric layer 103 is selected as follows: Between, including endpoint values.

[0071] As an example, an anti-reflective coating can also be formed between the organic dielectric layer 103 and the photoresist layer 104 to improve exposure accuracy, such as... Figure 10 As shown, a SiARC layer 105 (containing a silicon antireflective coating, the main component of which is an organosiloxane) is formed between the organic dielectric layer 103 and the photoresist layer 104; as Figure 10a As shown, a DARC layer 106 and a BARC layer 107 are formed between the organic dielectric layer 103 and the photoresist layer 104. In this embodiment, a SiARC layer 105 is preferably formed between the organic dielectric layer 103 and the photoresist layer 104. Since the organic dielectric layer 103, the SiARC layer 105, and the photoresist layer 104 can all be prepared using a spin-coating process, the ease of the process can be effectively improved. For example, the thickness of the SiARC layer 105 is selected as follows: Between, including endpoint values.

[0072] The photoresist layer 104 is prepared using a spin-coating process, and its thickness is selected as [thickness value missing]. Between, including endpoint values.

[0073] like Figure 11 and Figure 13 As shown, step S3 is then performed, whereby the photoresist layer 104 is patterned, and the organic dielectric layer 103 is etched based on the patterned photoresist layer 104 to obtain the patterned organic dielectric layer 103, and then the patterned photoresist layer 104 is removed.

[0074] As a specific example, when the SiARC layer 105 is also formed between the organic dielectric layer 103 and the photoresist layer 104, the method for etching the organic dielectric layer 103 based on the patterned photoresist layer 104 includes: as follows Figure 12As shown, the SiARC layer 105 is etched based on the patterned photoresist layer 104 to obtain the patterned SiARC layer 105; then, the organic dielectric layer 103 is etched based on the patterned photoresist layer 104 and the SiARC layer 105 to obtain the patterned organic dielectric layer 103; as shown Figure 13 As shown, the patterned SiARC layer 105 and the photoresist layer 104 are finally removed.

[0075] As another specific example, when a DARC layer 106 and a BARC layer 107 are formed between the organic dielectric layer 103 and the photoresist layer 104, the method of etching the organic dielectric layer 103 based on the patterned photoresist layer 104 includes: etching the BARC layer 107 and the DARC layer 106 based on the patterned photoresist layer 104 to obtain the patterned BARC layer 107 and the DARC layer 106, and then removing the patterned photoresist layer 104 and the BARC layer 107; then etching the organic dielectric layer 103 based on the patterned DARC layer 106 to obtain the patterned organic dielectric layer 103, and finally removing the patterned DARC layer 106.

[0076] like Figure 14 and Figure 15 As shown, step S4 is then performed, where the second pad oxide layer 102, the nitride layer 101, and the first pad oxide layer 100 are etched based on the patterned organic dielectric layer 103 to obtain the patterned second pad oxide layer 102, nitride layer 101, and first pad oxide layer 100 (e.g., Figure 14 (as shown), and then remove the patterned organic dielectric layer 103 (as shown). Figure 15 (As shown).

[0077] The second pad oxide layer 102, the nitride layer 101, and the first pad oxide layer 100 are etched using a conventional dry etching process. Appropriate etching gases are selected based on the materials of the organic dielectric layer 103, the second pad oxide layer 102, the nitride layer 101, and the first pad oxide layer 100. This is a common application in the art. For example, when the materials of the first pad oxide layer 100 and the second pad oxide layer 102 are silicon oxide, and the material of the nitride layer 101 is silicon nitride, the etching gases selected for dry etching are CF4 and CHF3.

[0078] like Figure 16 As shown, step S5 is performed last, using the patterned second pad oxide layer 102 as a barrier layer to etch the semiconductor substrate 10 to form a trench 11 in the semiconductor substrate 10; wherein the etching gas used for etching includes hydrogen bromide gas and oxygen.

[0079] The method does not excessively limit the number, location, depth, and width of the trenches 11; the parameters can be set according to actual needs. The trench 11 fabrication method of this embodiment is particularly suitable for fabricating unevenly distributed trenches on a semiconductor substrate 10 to form densely patterned and sparsely patterned regions on the semiconductor substrate 10.

[0080] like Figure 17 and Figure 18 As shown, in this step, since the second pad oxide layer 102 is used as an etching barrier layer, when hydrogen bromide gas and oxygen are used as the main etching gases to etch the semiconductor substrate 10, oxide byproducts 13 will be generated. Because these oxide byproducts 13 are close to the oxide layer material, they will accumulate at the top and bottom of the active region, using the first pad oxide layer 100 as the attachment point. Since this accumulation method uses the first pad oxide layer 100 as the attachment point, the degree of accumulation of oxide byproducts 13 is basically the same regardless of whether the pattern is dense or sparse. Simultaneously, this oxide byproduct... The thickness of the aggregated product 13 is also relatively thin. In addition, since the active region CD has been defined with high precision when etching the second pad oxide layer 102, nitride layer 101 and first pad oxide layer 100, the shrinkage of the key dimension CD of the active region becomes slow when etching the semiconductor substrate 10 to form the trench 11. Moreover, the shrinkage rate of the key dimension CD of the active region is small regardless of whether the pattern is dense or sparse. Therefore, the final offset of the key dimension CD of the active region is not much different regardless of the density of the pattern. At the same time, since the thickness of the aggregated oxide byproduct 13 is also relatively thin, the double slop in the sparse pattern region can also be eliminated.

[0081] The parameters for the use of etching gases, including hydrogen bromide and oxygen, can be adjusted according to actual needs, and no excessive restrictions are imposed here.

[0082] In a specific example, for the same design requirements, the trench fabricated using the method described in this embodiment has a CD bias of -0.5 nm in the active region of the patterned dense region and a CD bias of -2.6 nm in the active region of the patterned sparse region; using... Figures 1 to 6 The trench fabrication method shown in the comparative example has a CD bias of +3.1 nm in the active region of the patterned dense region and -7.6 nm in the active region of the patterned sparse region. Therefore, compared to the comparative example, the trench fabrication method of this embodiment can reduce the difference between the CD bias in the patterned dense region and the CD bias in the patterned sparse region by 3.1 nm - (-7.6 nm) - [-0.5 nm - (-2.6 nm)] = 8.6 nm. This can significantly increase the lithography process window.

[0083] After forming the trench 11, the method further includes filling the trench 11 with insulating material 12 to form an isolation trench.

[0084] As a specific example, the method of filling the insulating material 12 includes: Figure 19 for Figure 16 A magnified view of the area at point A within the dashed box. Figure 19 This is a schematic diagram of the cross-sectional structure after the formation of the trench 11. After the trench 11 is formed, there will still be residue of the second pad oxide layer 102. First, the obtained structure is wet-cleaned to remove impurities on the surface of the obtained structure. In addition, the residual second pad oxide layer 102 can also be cleaned and removed during this process (e.g., Figure 20 As shown), the second pad oxide layer 102 material can be removed by adding an etching solution specifically for it to the wet cleaning solution. For example, when the second pad oxide layer 102 is silicon oxide, it can be removed by adding DHF to the wet cleaning solution. Figure 21 and Figure 22 As shown, the insulating material 12, such as silicon oxide insulating material, is then filled into the surface of the resulting structure and the trench 11. Figure 21 This is a schematic diagram showing the formation of the insulating material 12 during the wet cleaning process when the oxide layer 102 of the second pad is not removed. Figure 22 This is a schematic diagram showing the formation of the insulating material 12 during the removal of the second pad oxide layer 102 in a wet cleaning process; as shown. Figure 23 As shown, the insulating material 12 is then ground using a grinding process until the surface of the nitride layer 101 is exposed. For example, a CMP grinding process is used. If the second pad oxide layer 102 is not removed, the second pad oxide layer 102 is also ground and removed during the grinding process while the insulating material 12 is being ground. Figure 24 As shown, the nitride layer 101 is finally removed, preferably by a wet etching process.

[0085] This embodiment also provides a method for fabricating a semiconductor device, which includes fabricating a trench isolation using the trench isolation fabrication method of this embodiment, and fabricating a semiconductor device in the active region isolated by the trench isolation.

[0086] In summary, the trench isolation trench fabrication method of the present invention uses a first pad oxide layer, a nitride layer, a second pad oxide layer, and an organic dielectric layer as a mask stack structure for the photolithography process. The organic dielectric layer has a high etching selectivity with the second pad oxide layer, the nitride layer, and the first pad oxide layer, ensuring high-precision pattern transfer. Furthermore, when etching the semiconductor substrate, the patterned second pad oxide layer is used as a barrier layer, and hydrogen bromide and oxygen are used as the main etching gases. During the etching process, oxide byproducts are generated. These oxide byproducts are similar in material to the oxide layer, thereby... Aggregates at the top and bottom surfaces of the active region, using the first pad oxide layer as attachment points. This aggregation pattern remains largely consistent regardless of pattern density. Furthermore, the oxide byproducts are thin and difficult to etch. Since the active region CD (critical dimension) is precisely defined during the etching of the second pad oxide layer, nitride layer, and first pad oxide layer, the shrinkage of the active region's critical dimension during trench etching on the semiconductor substrate becomes slower. This reduces the difference in critical dimension offset between regions with varying pattern density and eliminates double slop in sparse areas, lowering the active region CD bias and facilitating a larger lithography window. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0087] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing trench isolation, characterized in that, The method includes a method for preparing a trench, the method comprising the following steps: Provide semiconductor substrates; A first pad oxide layer, a nitride layer, a second pad oxide layer, an organic dielectric layer, and a photoresist layer are formed sequentially covering the surface of the semiconductor substrate; The photoresist layer is patterned, and the organic dielectric layer is etched based on the patterned photoresist layer to obtain the patterned organic dielectric layer, and then the patterned photoresist layer is removed. Based on the patterned organic dielectric layer, the second pad oxide layer, the nitride layer and the first pad oxide layer are etched to obtain the patterned second pad oxide layer, the nitride layer and the first pad oxide layer, and then the patterned organic dielectric layer is removed. The semiconductor substrate is etched using the patterned second pad oxide layer as a barrier layer to form trenches in the semiconductor substrate; wherein the etching gas used for etching includes hydrogen bromide gas and oxygen.

2. The method for preparing trench isolation according to claim 1, characterized in that: The semiconductor substrate is a silicon substrate, the first pad oxide layer is a silicon oxide layer, the nitride layer is a silicon nitride layer, and the second pad oxide layer is a silicon oxide layer.

3. The method for preparing trench isolation according to claim 1 or 2, characterized in that: The first pad oxide layer is prepared by a thermo-oxidative process, the second pad oxide layer is prepared by a CVD process, and the organic dielectric layer and the photoresist layer are prepared by a spin-coating process.

4. The method for preparing trench isolation according to claim 1, characterized in that: A SiARC layer is also formed between the organic dielectric layer and the photoresist layer; or a DARC layer and a BARC layer are also formed between the organic dielectric layer and the photoresist layer.

5. The method for preparing trench isolation according to claim 4, characterized in that: When a SiARC layer is formed between the organic dielectric layer and the photoresist layer, the method of etching the organic dielectric layer based on the patterned photoresist layer includes: etching the SiARC layer based on the patterned photoresist layer to obtain a patterned SiARC layer; then etching the organic dielectric layer based on the patterned photoresist layer and the SiARC layer to obtain a patterned organic dielectric layer; and finally removing the patterned SiARC layer and the photoresist layer. When a DARC layer and a BARC layer are formed between the organic dielectric layer and the photoresist layer, the method of etching the organic dielectric layer based on the patterned photoresist layer includes: etching the BARC layer and the DARC layer based on the patterned photoresist layer to obtain a patterned BARC layer and the DARC layer; then removing the patterned photoresist layer and the BARC layer; next, etching the organic dielectric layer based on the patterned DARC layer to obtain a patterned organic dielectric layer; and finally removing the patterned DARC layer.

6. The method for preparing trench isolation according to claim 1, characterized in that: The semiconductor substrate includes a patterned dense region and a patterned sparse region.

7. The method for preparing trench isolation according to claim 1, characterized in that: The thickness of the first pad oxide layer is The thickness of the nitride layer is The thickness of the second pad oxide layer is The thickness of the organic dielectric layer is 8. The method for preparing trench isolation according to claim 1, characterized in that: After the trench is formed, the method further includes the step of filling the trench with insulating material.

9. The method for preparing trench isolation according to claim 8, characterized in that, The method for filling the trench with insulating material includes: firstly, wet cleaning the obtained structure; then filling the surface of the obtained structure and the trench with the insulating material; next, grinding the insulating material with a grinding process until the surface of the nitride layer is exposed; and finally removing the nitride layer.

10. A method for fabricating a semiconductor device, characterized in that, This includes fabricating trench isolation using the trench isolation fabrication method described in any one of claims 1 to 9, and fabricating a semiconductor device in the active region isolated by the trench isolation.

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