Semiconductor device and method of manufacturing the same
Patent Information
- Application Number
- CN202611093214.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-22
- Publication Date
- 2026-10-16
AI Technical Summary
其中，在对衬底背面进行刻蚀形成深沟槽时，会导致衬底产生大量的缺陷，而由于后续无法再引入高温退火制程来对这些缺陷进行修复（引入的高温退火制程会损伤正面制程形成的掺杂层和金属互连结构等），导致暗计数率增大
[0029]1、本发明的半导体器件的制造方法，由于包括：提供预处理基板，所述预处理基板包括第一表面，所述第一表面开设有第一开口；在所述第一开口内形成牺牲层；在所述第一表面一侧形成掺杂层；从所述预处理基板远离所述第一表面一侧减薄所述预处理基板，直至暴露所述牺牲层，其中，减薄后的所述预处理基板为基板；去除所述牺牲层；形成填充层，所述填充层位于所述第一开口内。使得不仅能够形成所需的深沟槽隔离结构，还能降低暗计数率。
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Figure CN122935228A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] Currently, after completing the front-side fabrication processes for devices, deep trench isolation structures are fabricated on the back side of the substrate. However, etching the back side of the substrate to form deep trenches results in a large number of defects. Since these defects cannot be repaired by subsequent high-temperature annealing processes (which would damage the doped layers and metal interconnect structures formed by the front-side processes), the dark count rate increases. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which not only enables the formation of the desired deep trench isolation structure but also reduces the dark count rate.
[0004] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0005] A pre-processing substrate is provided, the pre-processing substrate including a first surface, the first surface having a first opening;
[0006] The sacrificial layer is formed within the first opening;
[0007] A doped layer is formed on one side of the first surface;
[0008] The pre-treated substrate is thinned from the side away from the first surface until the sacrificial layer is exposed, wherein the thinned pre-treated substrate is a substrate;
[0009] Remove the sacrificial layer;
[0010] A filling layer is formed, which is located within the first opening.
[0011] Optionally, forming a sacrificial layer within the first opening includes:
[0012] A sacrificial layer material is formed within the first opening, wherein a protective layer is formed on the first surface of the pre-treated substrate, the first opening also penetrates the protective layer, and the sacrificial layer material also covers the protective layer;
[0013] Planarize the sacrificial layer material down to the protective layer;
[0014] The sacrificial layer material located in the first opening of the protective layer is removed by etching, and the remaining sacrificial layer material serves as the sacrificial layer.
[0015] Remove the protective layer.
[0016] Optionally, after forming the doped layer on one side of the first surface and before thinning the pretreated substrate, the method further includes:
[0017] Perform the annealing process.
[0018] Optionally, the annealing process is performed at a temperature of 1000℃~1100℃.
[0019] Optionally, after forming the doped layer and before thinning the pretreated substrate, the method for manufacturing the semiconductor device further includes:
[0020] An interlayer dielectric layer is formed on the first surface of the pretreated substrate, and a metal interconnect structure is formed in the interlayer dielectric layer. The interlayer dielectric layer covers the sacrificial layer and the doped layer, and the metal interconnect structure is electrically connected to the doped layer.
[0021] Optionally, before thinning the pretreated substrate, the method for manufacturing the semiconductor device further includes:
[0022] The first surface of the pretreated substrate is bonded to a carrier sheet.
[0023] Optionally, the sacrificial layer comprises polysilicon, and the sacrificial layer is removed using a wet etching process.
[0024] Optionally, the etching selectivity ratio of the sacrificial layer to the pretreated substrate is greater than or equal to 500:1.
[0025] Optionally, before forming the filling layer, the method for manufacturing the semiconductor device further includes:
[0026] A first insulating layer is formed on the sidewall of the first opening.
[0027] The present invention also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.
[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0029] 1. The semiconductor device manufacturing method of the present invention includes: providing a pre-processed substrate, the pre-processed substrate including a first surface having a first opening; forming a sacrificial layer within the first opening; forming a doped layer on one side of the first surface; thinning the pre-processed substrate from a side away from the first surface until the sacrificial layer is exposed, wherein the thinned pre-processed substrate is a substrate; removing the sacrificial layer; and forming a filler layer located within the first opening. This enables not only the formation of the desired deep trench isolation structure but also a reduction in dark count rate.
[0030] 2. The semiconductor device of the present invention, manufactured using the semiconductor device manufacturing method described above, not only enables the formation of the required deep trench isolation structure, but also reduces the dark count rate. Attached Figure Description
[0031] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0032] Figures 2a-2j yes Figure 1 A schematic diagram of the semiconductor device manufacturing method shown.
[0033] Among them, the appendix Figures 1-2j The annotations in the attached figures are explained as follows:
[0034] 11-Substrate; 11'-Pre-treated substrate; 121-First opening; 1211-Protective layer; 122-Sacrificial layer; 1221-Sacrificial layer material; 123-Filling layer; 124-First insulating layer; 13-Doped layer; 14-Interlayer dielectric layer; 15-Carrier sheet. Detailed Implementation
[0035] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0036] One embodiment of the present invention provides a method for manufacturing a semiconductor device, see reference. Figure 1 , Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method comprising:
[0037] Step S1: Provide a pre-processing substrate, the pre-processing substrate including a first surface, the first surface having a first opening;
[0038] Step S2: Form a sacrificial layer within the first opening;
[0039] Step S3: Form a doped layer on one side of the first surface;
[0040] Step S4: Thin the pre-treated substrate from the side away from the first surface until the sacrificial layer is exposed, wherein the thinned pre-treated substrate is a substrate;
[0041] Step S5: Remove the sacrificial layer;
[0042] Step S6: Form a filling layer, wherein the filling layer is located within the first opening.
[0043] See below. Figures 2a-2j The manufacturing method of the semiconductor device provided in this embodiment will be described in more detail. Figures 2a-2j This is a schematic diagram of a longitudinal cross-section.
[0044] Following step S1, as follows Figures 2a to 2b As shown, a pre-processing substrate 11' is provided, the pre-processing substrate 11' includes a first surface A1, and the first surface A1 has a first opening 121.
[0045] The pretreatment substrate 11' can be made of materials well known in the art. For example, the material of the pretreatment substrate 11' can be semiconductor materials such as Si, SiGe, SiGeC, SiC, etc.
[0046] In one embodiment, the pre-processed substrate 11' includes a substrate and an epitaxial layer formed on the substrate, wherein the side of the epitaxial layer away from the substrate is the first surface A1.
[0047] The substrate is heavily doped, and the ion doping concentration of the epitaxial layer is very low. The epitaxial layer can be an intrinsically doped layer, which can serve as a neutral region. As an example, the epitaxial layer can be unintentionally doped, i.e., it has P-type or N-type doping caused only by accidental contamination of impurities during its manufacturing.
[0048] The substrate and the epitaxial layer can have the same or opposite doping types. In one embodiment, the substrate is p-type doped, and the epitaxial layer can be n-type or p-type doped.
[0049] In one embodiment, multiple first openings 121 are provided, and the multiple first openings 121 can be arranged in an array that crosses each other.
[0050] In one embodiment, the width of the first opening 121 gradually decreases along the first surface A1 of the pre-processed substrate 11' in a direction away from the first surface A1.
[0051] like Figure 2a As shown, a protective layer 1211 is formed on the first surface A1 of the pretreated substrate 11'. In one embodiment, the protective layer 1211 includes a stacked oxide layer and a nitride layer.
[0052] like Figure 2bAs shown, a portion of the pre-processed substrate 11' is removed from its first surface A1 using a dry or wet etching process to form the first opening 121. The first opening 121 also penetrates the protective layer 1211. The first opening 121 may or may not penetrate the pre-processed substrate 11'. In this embodiment, the first opening 121 does not penetrate the pre-processed substrate 11', that is, the first opening 121 extends from the first surface A1 of the pre-processed substrate 11' into the pre-processed substrate 11'.
[0053] Following step S2, as Figures 2c to 2e As shown, a sacrificial layer 122 is formed within the first opening 121.
[0054] Forming the sacrificial layer 122 within the first opening 121 includes:
[0055] like Figure 2c As shown, a sacrificial layer material 1221 is formed within the first opening 121, wherein the sacrificial layer material 1221 also covers the protective layer 1211.
[0056] In one embodiment, before the sacrificial layer material 1221 is formed in the first opening 121, a first insulating layer 124 is formed on the inner wall of the first opening 121. The first insulating layer 124 may also be formed on the protective layer 1211, or it may not be formed on the protective layer 1211.
[0057] like Figure 2d As shown, the sacrificial layer material 1221 is planarized until the protective layer 1211 is reached.
[0058] like Figure 2e As shown, the sacrificial layer material 1221 located in the first opening 121 of the layer containing the protective layer 1211 is etched away, and the remaining sacrificial layer material 1221 serves as the sacrificial layer 122.
[0059] The sacrificial layer material 1221 located in the first opening 121 of the protective layer 1211 can be removed by wet etching to form the sacrificial layer 122.
[0060] In one embodiment, the sacrificial layer material 1221 comprises polysilicon, which may be doped or undoped, and the etching solution for the wet etching process may include a TMAH (tetramethylammonium hydroxide) solution. The etching rate for the sacrificial layer material 1221 is higher than the etching rate for the protective layer 1211 and the first insulating layer 124, to achieve maskless back etching of the sacrificial layer material 1221. The etching selectivity ratio between the sacrificial layer 122 and the first insulating layer 124, and between the sacrificial layer 122 and the substrate 11, is greater than 500:1, so that when the sacrificial layer 122 is subsequently removed from the first opening 121, etching of the first insulating layer 124 and the substrate 11 can be avoided as much as possible.
[0061] The surface of the formed sacrificial layer 122 does not exceed the first surface A1 of the pre-processed substrate 11' surrounding the first opening 121. This avoids the situation where, after the sacrificial layer 122 is subsequently removed and a filling layer 123 is formed in the first opening 121, the distance between the end of the filling layer 123 near the metal interconnect structure and the metal interconnect structure is too close, which could lead to reliability issues when voltage is applied to the device.
[0062] like Figure 2f As shown, the protective layer 1211 is removed, or the protective layer 1211 and the first insulating layer 124 located on the protective layer 1211 are removed.
[0063] Following step S3, as follows Figure 2f As shown, a doped layer 13 is formed on one side of the first surface A1.
[0064] The doped layer 13 is formed by performing an ion implantation process on the first surface A1 of the pre-treated substrate 11', the doped layer 13 being located within the pre-treated substrate 11' defined adjacent to the first opening 121. For example, a first doped layer of the doped layer 13 may be formed first, followed by a second doped layer of the doped layer 13, the doping types of the first doped layer and the second doped layer being opposite.
[0065] The first doped layer extends from the first surface A1 of the pre-treated substrate 11' into the pre-treated substrate 11'; the second doped layer extends from the side of the first doped layer away from the first surface A1 in a direction away from the first doped layer, or the second doped layer surrounds the first doped layer.
[0066] When the second doped layer extends from the side of the first doped layer away from the first surface A1 toward a direction away from the first doped layer, the width of the second doped layer in the direction parallel to the first surface A1 may be less than, equal to or greater than the width of the first doped layer in the direction parallel to the first surface A1.
[0067] The first doped layer and the second doped layer are used to form a photodiode, which can be an avalanche photodiode or a single-photon avalanche photodiode, etc.
[0068] After the doped layer 13 is formed, a third doped layer (not shown) may be further formed. The third doped layer extends from the side of the first doped layer near the first surface A1 into the first doped layer. The third doped layer has the same doping type as the first doped layer, and the doping concentration of the third doped layer is greater than that of the first doped layer.
[0069] When the pre-treated substrate 11' is subsequently thinned so that the substrate 11 only includes the epitaxial layer, in one embodiment, after forming the doped layer 13, the method of manufacturing the semiconductor device further includes: forming a fourth doped layer (not shown), the fourth doped layer extending from the first surface A1 of the periphery of the doped layer 13 into the epitaxial layer, the fourth doped layer having the same doping type as the second doped layer, and the doping concentration of the fourth doped layer being greater than the doping concentration of the epitaxial layer.
[0070] In one embodiment, the first doped layer and the third doped layer are N-type doped, and the second doped layer and the fourth doped layer are P-type doped.
[0071] Following step S4, as Figure 2h As shown, the pre-processed substrate 11' is thinned from the side away from the first surface A1 until the sacrificial layer 122 is exposed, wherein the thinned pre-processed substrate 11' is the substrate 11.
[0072] After thinning the pretreated substrate 11', the substrate 11 includes only the epitaxial layer, or the substrate 11 still includes the substrate and the epitaxial layer. The side of the substrate 11 away from the first surface A1 is the second surface A2.
[0073] In one embodiment, the thinning process may be performed using chemical mechanical polishing and / or wet etching processes.
[0074] In one embodiment, after forming the doped layer 13 on one side of the first surface A1 and before thinning the pretreated substrate 11', an annealing process is further performed. The temperature for performing the annealing process is, for example, 1000°C to 1100°C, and this application does not impose a specific limitation thereon.
[0075] Since a large number of defects are introduced during the formation of the first opening 121, for example, during the etching of the pre-processed substrate 11' using a dry etching process, defects such as lattice dislocations and vacancies caused by ion bombardment and dangling bonds on the inner surface of the first opening 121 are formed, an annealing process is performed after the formation of the doped layer 13 and before the thinning of the pre-processed substrate 11'. On the one hand, the ions in the first doped layer, the second doped layer, the third doped layer and the fourth doped layer can be activated simultaneously through the same annealing process. On the other hand, the defects introduced in the pre-processed substrate 11' during the formation of the first opening 121 can be repaired at the same time to reduce the dark count rate.
[0076] In one embodiment, after the formation of the doped layer 13 and before the thinning of the pretreated substrate 11', as... Figure 2f As shown, the method for manufacturing the semiconductor device further includes: forming an interlayer dielectric layer 14 on the first surface A1 of the pretreatment substrate 11', and forming a metal interconnect structure (not shown) in the interlayer dielectric layer 14, wherein the interlayer dielectric layer 14 covers the sacrificial layer 122 and the doped layer 13, and the metal interconnect structure is electrically connected to the doped layer 13. Further, the metal interconnect structure is formed after the annealing process and before the thinning of the pretreatment substrate 11'.
[0077] In one embodiment, the metal interconnect structure is electrically connected to the first doped layer.
[0078] In one embodiment, the metal interconnect structure is electrically connected to the third doped layer.
[0079] In one embodiment, such as Figure 2g As shown, before thinning the pre-processed substrate 11', the method for manufacturing the semiconductor device further includes bonding one side of the first surface A1 of the pre-processed substrate 11' to the carrier sheet 15. The side of the interlayer dielectric layer 14 away from the pre-processed substrate 11' can be bonded to the carrier sheet 15 via a bonding layer.
[0080] In one embodiment, the carrier sheet 15 may be a blank carrier sheet without any devices formed thereon or another substrate with devices formed thereon. The carrier sheet 15 may be made of semiconductor materials such as silicon and germanium, or glass.
[0081] Following step S5, as follows Figure 2iAs shown, the sacrificial layer 122 is removed.
[0082] In one embodiment, the sacrificial layer 122 is removed using a wet etching process.
[0083] In one embodiment, the sacrificial layer 122 is made of polycrystalline silicon, and the etching solution may include a TMAH (tetramethylammonium hydroxide) solution.
[0084] According to step S6, as Figure 2j As shown, a filling layer 123 is formed, which is located within the first opening 121.
[0085] In one embodiment, prior to forming the filling layer 123, the method of manufacturing the semiconductor device further includes: forming a second insulating layer (not shown) on the surface of the first insulating layer 124, wherein the first insulating layer 124 and the second insulating layer constitute an insulating layer, and the deep trench isolation structure includes the insulating layer and the filling layer 123. The deep trench isolation structure is used to achieve isolation between adjacent photodiodes to avoid crosstalk.
[0086] The thickness of the first insulating layer 124 on the sidewall of the first opening 121 is very thin (e.g., 45 Å to 55 Å), which allows the width of the sacrificial layer 122 formed in the first opening 121 to be increased in step S2, i.e., the aspect ratio of the sacrificial layer 122 is reduced, thereby reducing the process difficulty of removing the sacrificial layer 122 in step S5; and after removing the sacrificial layer 122 and before forming the filling layer 123, the second insulating layer is formed on the surface of the first insulating layer 124, which allows the filling layer 123 to have sufficient isolation effect between it and the substrate 11.
[0087] In one embodiment, the filling layer 123 is a conductive material, or the filling layer 123 may also be a dielectric material.
[0088] In one embodiment, the method for manufacturing the semiconductor device further includes:
[0089] A first electrode (not shown) is formed on the interlayer dielectric layer 14, and the first electrode is electrically connected to the doped layer 13 through the metal interconnect structure;
[0090] A second electrode (not shown) is formed; when the substrate 11 includes the substrate and the epitaxial layer, the second electrode is formed on the second surface A2 of the substrate 11; when the substrate 11 includes only the epitaxial layer, the second electrode is formed on the interlayer dielectric layer 14, and the second electrode is electrically connected to the fourth doped layer through another metal interconnect structure in the interlayer dielectric layer 14.
[0091] A reverse bias voltage is applied to the photodiode through the first electrode and the second electrode.
[0092] The third doped layer is used to connect the first doped layer, thereby reducing the contact resistance when a voltage is applied to the first doped layer through the first electrode; the fourth doped layer is used to connect the epitaxial layer, thereby reducing the contact resistance when a voltage is applied to the epitaxial layer through the second electrode.
[0093] When the semiconductor device includes the carrier sheet 15, the manufacturing method of the semiconductor device further includes: forming a first through-hole conductive structure (not shown) in the substrate 11, the first through-hole conductive structure penetrating the substrate 11 and being insulated from the substrate 11, the first through-hole conductive structure being electrically connected to the metal interconnect structure, so that the first electrode can be led out to the second surface A2 of the substrate 11 through the first through-hole conductive structure and the metal interconnect structure; when the semiconductor device includes the carrier sheet 15 and the substrate 11 includes only the epitaxial layer, the manufacturing method of the semiconductor device further includes: forming a second through-hole conductive structure (not shown) in the substrate 11, the second through-hole conductive structure penetrating the substrate 11 and being insulated from the substrate 11, the second through-hole conductive structure being electrically connected to the other metal interconnect structure, so that the second electrode can be led out to the second surface A2 of the substrate 11 through the second through-hole conductive structure and the other metal interconnect structure.
[0094] In one embodiment, the first electrode is connected to the positive terminal of the power supply, and the second electrode is connected to the negative terminal of the power supply.
[0095] If the photodiode is an avalanche photodiode or a single-photon avalanche photodiode, in the working state, a reverse bias voltage is applied to the photodiode through the first electrode and the second electrode, so that the working voltage is higher than the breakdown voltage of the PN junction formed between the first doped layer and the second doped layer, forming a voltage difference; under this voltage difference, a depletion layer is generated at the PN junction, and a strong electric field exists in the depletion layer. This electric field can ensure that the charge carriers in this region can obtain enough energy to generate an avalanche through the collisional ionization effect, thereby generating a large avalanche current.
[0096] As can be seen from the above, the method for manufacturing the semiconductor device provided by the present invention includes: providing a pre-processing substrate, the pre-processing substrate including a first surface and a first opening on the first surface; forming a sacrificial layer in the first opening; forming a doped layer on one side of the first surface; thinning the pre-processing substrate from the side away from the first surface until the sacrificial layer is exposed, wherein the thinned pre-processing substrate is a substrate; removing the sacrificial layer; and forming a filling layer located in the first opening. That is, before forming the doped layer on one side of the first surface of the pre-processing substrate, the first opening where the deep trench isolation structure is located is pre-formed on one side of the first surface of the pre-processing substrate. This allows the defects introduced into the pre-processing substrate during the formation of the first opening to be repaired using an annealing process after forming the doped layer, thereby enabling not only the formation of the desired deep trench isolation structure but also a reduction in dark count rate.
[0097] One embodiment of the present invention provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.
[0098] The manufacturing method of the semiconductor device is described above and will not be repeated here.
[0099] Because the semiconductor device is manufactured using the aforementioned semiconductor device manufacturing method, it is possible not only to form the required deep trench isolation structure, but also to reduce the dark count rate.
[0100] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A pre-processing substrate is provided, the pre-processing substrate including a first surface, the first surface having a first opening; A sacrificial layer is formed within the first opening; A doped layer is formed on one side of the first surface; The pre-treated substrate is thinned from the side away from the first surface until the sacrificial layer is exposed, wherein the thinned pre-treated substrate is a substrate; Remove the sacrificial layer; A filling layer is formed, which is located within the first opening.
2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Forming the sacrificial layer within the first opening includes: A sacrificial layer material is formed within the first opening, wherein a protective layer is formed on the first surface of the pre-treated substrate, the first opening also penetrates the protective layer, and the sacrificial layer material also covers the protective layer; Planarize the sacrificial layer material down to the protective layer; The sacrificial layer material located in the first opening of the protective layer is removed by etching, and the remaining sacrificial layer material serves as the sacrificial layer. Remove the protective layer.
3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After forming the doped layer on one side of the first surface and before thinning the pretreated substrate, the following steps are also included: Perform the annealing process.
4. The method for manufacturing a semiconductor device as described in claim 3, characterized in that, The annealing process is performed at a temperature of 1000℃~1100℃.
5. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The method for manufacturing the semiconductor device, after forming the doped layer and before thinning the pretreated substrate, further includes: An interlayer dielectric layer is formed on the first surface of the pretreated substrate, and a metal interconnect structure is formed in the interlayer dielectric layer. The interlayer dielectric layer covers the sacrificial layer and the doped layer, and the metal interconnect structure is electrically connected to the doped layer.
6. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Before thinning the pretreated substrate, the method for manufacturing the semiconductor device further includes: The first surface of the pretreated substrate is bonded to the carrier sheet.
7. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The sacrificial layer comprises polycrystalline silicon and is removed using a wet etching process.
8. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The etching selectivity ratio of the sacrificial layer to the pretreated substrate is greater than or equal to 500:
1.
9. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Before forming the filling layer, the method for manufacturing the semiconductor device further includes: A first insulating layer is formed on the sidewall of the first opening.
10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the manufacturing method described in any one of claims 1 to 9.