Method of forming an air gap within a semiconductor device, semiconductor device, chip, electronic device
Patent Information
- Application Number
- CN202510418007.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2026-10-16
AI Technical Summary
[0005]本申请公开了一种在半导体器件内形成气隙的方法、半导体器件、芯片、电子设备，用于解决如何在金属互联层中形成深度一致性好、且深度灵活可调的气隙结构的问题
[0021] Fourthly, this application provides an electronic device comprising a circuit board and a chip as described in the third aspect, the chip being disposed on the circuit board. The electronic device provided by this application, comprising a circuit board and a chip, effectively reduces parasitic capacitance between interconnects due to the presence of a well-consistent air gap within the chip, thereby improving signal transmission rate and overall device performance.
Smart Images
Figure CN122935231A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a method for forming an air gap in a semiconductor device, a semiconductor device, a chip, and an electronic device. Background Technology
[0002] As semiconductor devices evolve towards higher integration and higher performance, the interconnect density within chips has significantly increased, especially in 3D packaging and advanced process nodes, where the complexity of back-end metal interconnects has increased dramatically. Complex metal interconnects lead to severe resistive-capacitance (RC) delay, which has become one of the key bottleneck factors affecting device performance. Reducing RC delay is primarily achieved by decreasing the resistance of metal interconnects and reducing the parasitic capacitance between them.
[0003] One of the main technical means to reduce the parasitic capacitance between metal interconnects is to introduce an air gap structure between adjacent metal interconnects. By replacing the dielectric material between the metal interconnects with the air gap, the dielectric constant of the structure between adjacent metal interconnects is reduced.
[0004] Air gaps can be introduced by depositing dielectric material in trench structures between adjacent metal interconnects and pre-sealing the deposited dielectric material, i.e., not completely filling the trench structure. However, due to differences in geometry, surface morphology, temperature distribution, or reactant diffusion conditions in different regions of the substrate surface, the growth rate or final thickness of the dielectric material in different regions during the same deposition process is uneven. This results in poor consistency in air gap depth and the inability to flexibly adjust the air gap depth according to actual needs. Summary of the Invention
[0005] This application discloses a method for forming an air gap in a semiconductor device, a semiconductor device, a chip, and an electronic device, which is used to solve the problem of how to form an air gap structure with good depth consistency and flexible depth adjustment in a metal interconnect layer.
[0006] In a first aspect, this application provides a method for forming an air gap within a semiconductor device. The method includes: forming a first sacrificial layer on a dielectric layer; fabricating a metal interconnect layer within the dielectric layer and the first sacrificial layer, the metal interconnect layer being flush with the first sacrificial layer and the metal interconnect layer including a plurality of interconnects spaced apart along a first direction; removing the first sacrificial layer to form an isolation groove between adjacent interconnects; filling the isolation groove with a second sacrificial layer, and making the second sacrificial layer flush with the metal interconnect layer; forming a first dielectric layer on the surface of the metal interconnect layer and the second sacrificial layer, wherein the first dielectric layer allows the second sacrificial layer to pass through within a preset temperature range; adjusting the ambient temperature of the dielectric layer after the above treatment to a preset temperature range, so that the second sacrificial layer vaporizes into a gaseous substance and diffuses out through the first dielectric layer, thereby forming an air gap within the isolation groove.
[0007] Thus, by pre-forming a first sacrificial layer of uniform thickness on the dielectric layer, defining the gap depth using this first sacrificial layer, a metal interconnect layer is fabricated within the dielectric layer and the first sacrificial layer, flush with the first sacrificial layer to ensure uniform thickness and provide the prerequisite for forming a uniformly deep isolation trench. After removing the first sacrificial layer, a uniformly deep isolation trench is formed between adjacent interconnects. A second sacrificial layer is filled into the isolation trench, flush with the metal interconnect layer to ensure a uniform gap depth. A first dielectric layer is formed on the surfaces of the second sacrificial layer and the metal interconnect layer, and heated within a preset temperature range, causing the second sacrificial layer to vaporize into a gaseous substance that diffuses out through the pores of the first dielectric layer, thereby forming a uniformly deep gap at the location of the second sacrificial layer. Therefore, by adjusting the thickness of the first sacrificial layer, the gap depth can be flexibly adjusted. Simultaneously, utilizing the volatility of the second sacrificial layer, it can be removed by heating after the gap structure is formed, thus enabling the formation of a gap with good depth consistency within the semiconductor device. This effectively reduces parasitic capacitance between interconnects, improves signal transmission rate, and enhances overall device performance.
[0008] In one possible implementation, the first sacrificial layer is an inorganic material, and the second sacrificial layer is an organic material, wherein the second sacrificial layer is volatile within a preset temperature range. Thus, because the first sacrificial layer is inorganic, it possesses structural stability, allowing for precise definition of the isolation groove shape. Simultaneously, by selecting an inorganic material with a high etch selectivity, the removal of the first sacrificial layer can avoid impacting other structures of the semiconductor device. The second sacrificial layer, being a volatile organic material within a preset temperature range, allows for reliable gap formation after the formation of the first dielectric layer through its thermal decomposition characteristics, avoiding residual contaminants. This dual-sacrificial-layer design, through the structural stability of the inorganic material and the volatility of the organic material, achieves precise control and efficient formation of the gap morphology, improving process compatibility and device reliability.
[0009] In one possible implementation, the material of the second sacrificial layer is at least one selected from polymethyl methacrylate, polycarbonate, polystyrene, and polyimide. Thus, commonly used organic materials in the semiconductor field can be selected, such as at least one selected from polymethyl methacrylate, polycarbonate, polystyrene, and polyimide as the second sacrificial layer material. Through its controllable thermal decomposition temperature, high process compatibility, and precise morphology control, efficient formation and performance optimization of the air gap structure are achieved, while simultaneously improving device reliability and manufacturing efficiency.
[0010] In one possible implementation, the dielectric layer includes a second dielectric layer and a third dielectric layer, and a first sacrificial layer is formed on the dielectric layer, comprising: forming the third dielectric layer on the surface of the second dielectric layer; and forming the first sacrificial layer on the surface of the third dielectric layer. Because the third dielectric layer is formed on the surface of the second dielectric layer, by selecting an etching process with a high etch selectivity, the etching process can precisely stop at the surface of the third dielectric layer when removing the first sacrificial layer, avoiding excessive etching that could damage the second dielectric layer. Simultaneously, it prevents the second sacrificial layer from etching into the second dielectric layer.
[0011] In one possible implementation, a metal interconnect layer is fabricated within the dielectric layer and the first sacrificial layer, including: fabricating the metal interconnect layer within the second dielectric layer, the third dielectric layer, and the first sacrificial layer. Thus, by fabricating the metal interconnect layer within the second and third dielectric layers, the surface flatness and buffering effect of the third dielectric layer can be fully utilized, ensuring the sidewall perpendicularity of the metal interconnect layer, improving the controllability of air gap formation, reducing parasitic capacitance, and reducing signal transmission delay.
[0012] In one possible implementation, before filling the isolation groove with the second sacrificial layer, a fourth dielectric layer is deposited on the surface of the dielectric layer and the surface of the metal interconnect layer. Thus, during subsequent etching of the next metal layer, the fourth dielectric layer can serve as an etching stop layer, protecting the previous dielectric layer from damage and reducing the risk of short circuits between interconnects. It can also serve as a fixing material for the entire structure, enhancing the mechanical stability of the structure downstream of the air gap.
[0013] In one possible implementation, a second sacrificial layer is filled within the isolation trench, the second sacrificial layer being flush with the metal interconnect layer. This includes: depositing the second sacrificial layer within the isolation trench; planarizing the second sacrificial layer material until the surface of the metal interconnect layer is exposed; or depositing the second sacrificial layer within the isolation trench until the deposition thickness of the second sacrificial layer is consistent with the deposition thickness of the first sacrificial layer. Thus, by depositing the second sacrificial layer within the isolation trench and ensuring its flushness with the metal interconnect layer through planarization or direct monitoring of the deposition thickness, air gap morphology defects (poor depth uniformity or irregular shape) caused by insufficient or excessive filling are avoided. This optimizes the air gap structure and significantly improves device reliability.
[0014] In one possible implementation, the preset temperature range is 200°C to 400°C. When the preset temperature range is within 200°C to 400°C, the second sacrificial layer is volatile, and the structures of other dielectric layers or metal interconnect layers are stable, ensuring that the structure of the semiconductor device is not affected while forming the air gap, thereby improving the stability of the semiconductor device.
[0015] Secondly, this application provides a semiconductor device comprising: a dielectric layer, a metal interconnect layer, a first dielectric layer, and an air gap. The metal interconnect layer is formed within the dielectric layer and includes a plurality of interconnects spaced apart along a first direction, with an isolation groove formed between adjacent interconnects. The first dielectric layer is formed on one side of the metal interconnect layer in its thickness direction. The air gap is formed within the isolation groove, wherein the air gap is prepared by a method as described in any of the first aspects. Thus, by precisely defining the air gap depth using a first sacrificial layer, and combining this with a filling process where a second sacrificial layer is flush with the metal interconnect layer, the air gap depth formed within the isolation groove is ensured to be highly consistent, effectively reducing parasitic capacitance between interconnects and improving signal transmission rate and overall device performance.
[0016] In one possible implementation, the thickness of the first dielectric layer is 5 nm to 15 nm. Thus, due to the moderate thickness of the first dielectric layer (5 nm to 15 nm), within a preset temperature range (e.g., 200°C to 400°C), the vaporized second sacrificial layer can quickly diffuse and dissipate through the pores of the first dielectric layer, ensuring that the air gap formation process is efficient and residue-free.
[0017] In one possible implementation, the first dielectric layer includes pores, the size of which is larger than the size of the second sacrificial layer after it has vaporized into a gaseous substance. When the pore size is larger than the gaseous substance molecules, the vaporized second sacrificial layer substance can quickly diffuse and be discharged through the pores, ensuring the cleanliness of the gas gap interior and preventing electrical performance degradation.
[0018] In one possible implementation, the pore size ranges from 0.5 nm to 2 nm, and / or the porosity of the first dielectric layer ranges from 35% to 65%. This avoids the micropores from being too small, preventing the removal of gaseous substances after the second sacrificial layer vaporizes; it also avoids the micropores from being too large, which would affect the mechanical strength of the first dielectric layer, thus achieving a balance between efficient removal of the second sacrificial layer, clean and residue-free gas gaps, and the mechanical strength of the first dielectric layer.
[0019] In one possible implementation, both the dielectric layer and the first dielectric layer are made of at least one of silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride. Thus, by using materials such as silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride for the dielectric layer and the first dielectric layer, their excellent dielectric properties, mechanical strength, thermal stability, and process compatibility significantly improve the signal transmission rate, reliability, and manufacturing yield of semiconductor devices.
[0020] Thirdly, this application provides a chip including a packaging layer and a semiconductor device as described in any of the second aspects, wherein the packaging layer at least partially covers the semiconductor device. The chip provided by this application includes a packaging layer and the semiconductor device described in the second aspect (having a uniformly deep air gap structure). Because the semiconductor device has a uniformly deep air gap, the parasitic capacitance between interconnects is effectively reduced, improving signal transmission rate and overall device performance.
[0021] Fourthly, this application provides an electronic device comprising a circuit board and a chip as described in the third aspect, the chip being disposed on the circuit board. The electronic device provided by this application, comprising a circuit board and a chip, effectively reduces parasitic capacitance between interconnects due to the presence of a well-consistent air gap within the chip, thereby improving signal transmission rate and overall device performance. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 A structural block diagram of an electronic device provided in an embodiment of this application;
[0024] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;
[0025] Figure 3This is a schematic diagram of the structure of a semiconductor device provided in related technologies;
[0026] Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0027] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0028] Figure 6 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment;
[0029] Figure 7 This is a schematic diagram of a structure in which a first sacrificial layer is formed on a dielectric layer during the fabrication of a semiconductor device, as provided in an embodiment of this application.
[0030] Figure 8 This application provides a schematic diagram of a structure for fabricating a metal interconnect layer within a dielectric layer and a first sacrificial layer during the fabrication of a semiconductor device.
[0031] Figure 9 This is a schematic diagram of a structure for removing the first sacrificial layer during the fabrication of a semiconductor device, provided in an embodiment of this application.
[0032] Figure 10 This is a schematic diagram of a structure in which a second sacrificial layer is filled in an isolation trench during the fabrication of a semiconductor device, as provided in an embodiment of this application.
[0033] Figure 11 This is a schematic diagram of a structure in which the second sacrificial layer is flush with the metal interconnect layer during the fabrication of a semiconductor device, as provided in an embodiment of this application.
[0034] Figure 12 This application provides a schematic diagram of a structure in which a first dielectric layer is formed on the surface of a metal interconnect layer and a second sacrificial layer during the fabrication of a semiconductor device.
[0035] Figure 13 This is a schematic diagram of a structure forming an air gap in an isolation groove during the fabrication of a semiconductor device, provided by an embodiment of this application.
[0036] Figure 14 This is a schematic diagram illustrating a semiconductor device fabrication process in which a dielectric layer is formed on the side of the first dielectric layer away from the air gap during the fabrication of a semiconductor device, as provided in an embodiment of this application.
[0037] Figure 15 A schematic diagram of a fourth dielectric layer deposited on the surface of a dielectric layer and the surface of a metal interconnect layer during the fabrication of another semiconductor device provided in this application embodiment;
[0038] Figure 16 This is a schematic diagram of the structure after filling the second sacrificial layer during the fabrication process of another semiconductor device provided in this application embodiment;
[0039] Figure 17 This is a schematic diagram of another semiconductor device fabrication process for forming a first dielectric layer, provided in an embodiment of this application.
[0040] Figure 18 This is a schematic diagram of another semiconductor device fabrication process in which an air gap is formed in an isolation groove, as provided in an embodiment of this application.
[0041] Explanation of reference numerals in the attached figures:
[0042] 01-Electronic devices;
[0043] 10-Semiconductor device; 11-Air gap; 110-Isolation trench; 12-Metal interconnect layer; 121-Interconnect line; 1211-First interconnect line; 1212-Second interconnect line; 13-Dielectric layer; 132-Second dielectric layer; 133-Third dielectric layer; 14-First dielectric layer; 15-Fourth dielectric layer; 171-First sacrificial layer; 172-Mask layer; 173-Photoresist; 174-Second sacrificial layer; 191-Source; 192-Drain; 193-Gate; 194-First conductive connection component; 195-Second conductive connection component;
[0044] 20 - Circuit board;
[0045] 30 - Chip; 31 - Packaging layer;
[0046] X - First direction; D - Thickness direction. Detailed Implementation
[0047] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0048] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0049] In the embodiments of this application, unless otherwise expressly specified and limited, the term "connection" can be a direct connection or an indirect connection through an intermediate medium.
[0050] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.
[0051] In the embodiments of this application, directional indications such as up, down, left, right, front, and back used to explain the structure of different components in this application are relative. These indications are appropriate when the components are in the positions shown in the figures. However, if the description of the component positions changes, these directional indications will also change accordingly.
[0052] Please see Figure 1 , Figure 1 This is a structural block diagram of an electronic device 01 provided in an embodiment of this application. The electronic device 01 may include image sensors, flash memory, high-bandwidth memory, mobile phones, tablets, computers, televisions, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality terminal devices, augmented reality terminal devices, and other electronic products. This application does not impose any special limitations on the specific form of the aforementioned electronic device 01.
[0053] Electronic device 01 may include a circuit board 20 and a chip 30, with the chip 30 disposed on the circuit board 20. Exemplarily, the chip 30 is electrically connected to the circuit board 20. The chip 30 may include various types of chips such as computing chips, memory chips, communication chips, sensing chips, and energy management chips.
[0054] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a chip 30 provided in an embodiment of this application. The chip 30 may include a packaging layer 31 and a semiconductor device 10, with the packaging layer 31 at least partially covering the semiconductor device 10. The packaging layer 31 provides physical protection for the semiconductor device 10, preventing it from being affected by the environment during subsequent processes or use, and extending the lifespan of the semiconductor device 10. The material of the packaging layer 31 may include one or more of epoxy molding compound (EMC), polyimide (PI), ceramic materials, polypropylene, polyethylene, etc.
[0055] Understandably, as semiconductor process technology continues to advance, the size of semiconductor device 10 is also shrinking proportionally, and the distance between conductive connection components used to connect electrical components in semiconductor device 10 is also decreasing. A problem that arises is that the parasitic capacitance between conductive connection components also increases, leading to higher power consumption and greater resistive-capacitive time delay in semiconductor device 10, severely impacting its performance.
[0056] The main technical means to reduce parasitic capacitance between conductive connecting components is to introduce an air gap structure between adjacent conductive connecting components.
[0057] For example, see Figure 3 The semiconductor device 10 may include a source 191, a drain 192, and a gate 193 disposed between the source 191 and the drain 192. The gate 193 is larger in the vertical direction than the source 191 and the drain 192. A first conductive connection member 194 is disposed above the source 191, and a second conductive connection member 195 is disposed above the drain 192. A portion of the gate 193 is located between the first conductive connection member 194 and the second conductive connection member 195, and in the horizontal direction, the distance between the gate 193 and the first conductive connection member 194 is smaller, and the distance between the gate 193 and the second conductive connection member 195 is smaller. To avoid or mitigate the resulting parasitic capacitance, an air gap 11 may be provided between the gate 193 and the first conductive connection member 194, and also between the gate 193 and the second conductive connection member 195.
[0058] The air gap 11 can be formed by the material closing in advance during material deposition. Understandably, during material deposition, the deposition environment varies in different areas, such as temperature and air pressure, resulting in a large loading effect. As a result, the air gap 11 has poor uniformity, and there may be cases where the air gap 11 cannot be formed or cannot be closed and is filled by material deposited in subsequent processes.
[0059] For this purpose, please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a semiconductor device 10 provided in an embodiment of this application. The structure of the semiconductor device 10 is conducive to forming a flexible and controllable air gap 11, thereby improving the performance of the semiconductor device 10.
[0060] The semiconductor device 10 may include a dielectric layer 13, a metal interconnect layer 12, a first dielectric layer 14, and an air gap 11.
[0061] Understandably, the semiconductor device 10 may also include a substrate and electrical components (not shown) formed on the substrate. A dielectric layer 13 may be formed on the side of the electrical components away from the substrate and extend in a plane parallel to the substrate. The material of the dielectric layer 13 may be at least one of commonly used semiconductor dielectric materials such as silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride.
[0062] A metal interconnect layer 12 may be formed within the dielectric layer 13, and the metal interconnect layer 12 may be fabricated using a back-end of line (BOEL) process. Metal interconnects can be used to connect one electrical component to other electrical components to achieve a specific function. The metal interconnect layer 12 may be made of a conductive material, such as copper, aluminum, titanium, tungsten, cobalt, molybdenum, ruthenium, or an alloy containing at least one of these metals.
[0063] The metal interconnect layer 12 may include a plurality of interconnect lines 121 spaced apart along a first direction X. The first direction X is parallel to the surface of the dielectric layer 13. For example, Figure 4 A first interconnect 1211 and a second interconnect 1212 are shown arranged at intervals along a first direction X. The interconnect 121 can be used to connect electronic components to transmit electrical signals between them. For ease of description, the direction perpendicular to the surface of the dielectric layer 13 is referred to as the thickness direction D, that is, the thickness direction D is the thickness direction of the metal interconnect layer.
[0064] An isolation groove 110 can be formed in the area between adjacent interconnects 121. The isolation groove 110 can electrically isolate adjacent interconnects 121 and prevent short circuits between adjacent interconnects 121.
[0065] The first dielectric layer 14 may be formed on one side of the metal interconnect layer 12 in the thickness direction D, that is, the first dielectric layer 14 may be formed on the surface of the metal interconnect layer 12 and the isolation groove 110. The first dielectric layer 14 being formed on the surface of the isolation groove 110 means that the first dielectric layer 14 seals the isolation groove 110. The first dielectric layer 14 may be in direct contact with the interconnect line 121 in the metal interconnect layer 12, for example, in... Figure 4 In this configuration, the first dielectric layer 14 is in direct contact with the first interconnect 1211 and / or the second interconnect 1212 in the metal interconnect layer 12. Other films may also be disposed between the first dielectric layer 14 and the interconnect 121 in the metal interconnect layer 12.
[0066] The first dielectric layer 14 can be formed using semiconductor processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The first dielectric layer 14 can be at least one of commonly used semiconductor dielectric materials such as silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride. The thickness of the first dielectric layer 14 can range from 5 nm to 15 nm. For example, the thickness of the first dielectric layer 14 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm.
[0067] Within a preset temperature range, the first dielectric layer 14 allows gaseous substances (the second sacrificial layer described below) to pass through. The gaseous substances can be organic materials containing C=O, CN, or CF bonds that volatilize within the preset temperature range. For example, the organic materials can include one or more of polyether, polyester, polyamide, or polyurethane organic materials. The preset temperature range is 200°C to 400°C, for example, it can be 200°C, 220°C, 240°C, 260°C, 280°C, 300°C, 320°C, 340°C, 360°C, 380°C, or 400°C.
[0068] Understandably, the first dielectric layer 14 may include pores. Gaseous substances can volatilize through these pores; that is, the size of the pores can be larger than the size of the gaseous substances to ensure their expulsion, thereby forming air gaps. The pores may be generated by the thermal expansion of the first dielectric layer 14 within a preset temperature range. For example, within the preset temperature range, the porosity of the first dielectric layer 14 may range from 35% to 65%, such as 35%, 40%, 45%, 55%, 60%, and 65%. For example, the pore diameter may range from 0.5 nm to 2 nm, such as 0.5 nm, 0.8 nm, 1 nm, 1.5 nm, or 2 nm.
[0069] Air gap 11 may be formed in an isolation groove. Air gap 11 may be prepared by any of the methods described below. Air gap 11 may be formed between spaced interconnects 121. For example, air gap 11 may be formed between a first interconnect 1211 and a second interconnect 1212, i.e., at least a portion of the space between the first interconnect 1211 and the second interconnect 1212 is not filled. Air gap 11 may have a low dielectric constant, for example, the dielectric constant of air gap 11 is about 1.
[0070] Understandably, since the first dielectric layer 14 can be disposed on one side of the metal interconnect layer 12 in the thickness direction D, and the air gap 11 can be located between the first interconnect line 1211 and the second interconnect line 1212 in the metal interconnect layer 12, the first dielectric layer 14 can seal the air gap 11 on one side in the thickness direction D. That is, the air gap 11 can be located on one side of the first dielectric layer 14, and the first dielectric layer 14 is used to form the air gap 11.
[0071] In some embodiments, the dielectric layer 13 of the semiconductor device 10 may include a second dielectric layer 132 and a third dielectric layer 133, that is, the metal interconnect layer 12 may be disposed between the second dielectric layer 132 and the third dielectric layer 133. Specifically, the third dielectric layer 133 is disposed between the second dielectric layer 132 and the first dielectric layer 14. The second dielectric layer 132 can serve as an etch stop layer, which prevents over-etching of other portions when forming the isolation trench. Simultaneously, in subsequent processes, it also prevents gaseous substances from adversely affecting other structures of the semiconductor device 10, such as corroding other structures of the semiconductor device 10.
[0072] In some implementations, please refer to Figure 5 The semiconductor device 10 may further include a fourth dielectric layer 15, which may cover the exposed surfaces of the interconnect 121 and the dielectric layer 13. For example, a portion of the fourth dielectric layer 15 is located in the isolation recess 110 and on the opposing surfaces between the first interconnect 1211 and the second interconnect 1212 and on the exposed surface of the dielectric layer 13, thereby forming an air gap 11 together with the first dielectric layer 13.
[0073] Understandably, a portion of the fourth dielectric layer 15 may be located between the interconnect 121 and the first dielectric layer 14. For example, a portion of the fourth dielectric layer 15 may be located between the first interconnect 1211 and the first dielectric layer 14, and between the second interconnect 1212 and the first dielectric layer 14. The portion of the fourth dielectric layer 15 covering the top of the first interconnect 1211 is located between the first interconnect 1211 and the first dielectric layer 14, and the portion of the fourth dielectric layer 15 covering the top of the second interconnect 1212 is located between the second interconnect 1212 and the first dielectric layer 14. Thus, during subsequent etching of the next metal layer, the fourth dielectric layer 15 can serve as an etching stop layer, protecting the previous dielectric layer from damage and reducing the risk of short circuits between interconnects 121. It can also serve as a fixing material for the entire structure, enhancing the mechanical stability of the structure downstream of the air gap 11.
[0074] In this way, by precisely defining the depth of the air gap 11 through the first sacrificial layer 171, and combining the filling process of the second sacrificial layer 174 flush with the metal interconnect layer 12, the depth of the air gap 11 formed in the isolation groove 110 is highly consistent, which effectively reduces the parasitic capacitance between interconnects 121 and improves the signal transmission rate and overall device performance.
[0075] Similarly, the chips and electronic devices provided in this application, due to the presence of air gaps with good depth consistency within the semiconductor devices, can effectively reduce the parasitic capacitance between interconnects within the chips and electronic devices, thereby improving signal transmission rate and overall device performance.
[0076] In addition, please see Figure 6 and combined Figure 4 and / or Figure 5 , Figure 6 A flowchart illustrating a method for forming an air gap within a semiconductor device 10, as provided in this application embodiment. The method may include the following steps:
[0077] A flowchart of a method for forming an air gap 11 within a semiconductor device 10, the method may include the following steps:
[0078] S100: A first sacrificial layer is formed on the dielectric layer.
[0079] Please see Figure 7 The dielectric layer 13 can be a dielectric material with a K value less than or equal to 5. For example, the material of the dielectric layer 13 can be at least one of commonly used semiconductor dielectric materials such as silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride. The dielectric layer 13 can be formed on a substrate, on which electrical components can be formed. Multiple electrical components can be connected to realize functions such as storage, computing, and signal processing. The dielectric layer 13 can be formed using deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The dielectric layer 13 can also be formed using other mature semiconductor processes.
[0080] A first sacrificial layer 171 can be formed on the dielectric layer 13, defining the depth of the air gap. Before forming the first sacrificial layer 171, the dielectric layer 13 can be planarized. During the formation of the dielectric layer 13, it is possible to avoid the surface of the dielectric layer 13 being non-planar due to load effects, etc. The planarization process can be carried out by chemical mechanical polishing. This ensures that the surface of the first sacrificial layer 171 formed on the dielectric layer 13 is planar, thereby ensuring that the thickness of the first sacrificial layer 171 is uniform.
[0081] The material of the first sacrificial layer 171 can be an inorganic material. For example, the material of the first sacrificial layer 171 is at least one of commonly used semiconductor dielectric materials such as silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride. The first sacrificial layer 171 can have a high etch selectivity with the dielectric layer 13, meaning that the dielectric layer 13 is hardly etched during the removal of the first sacrificial layer 171. The first sacrificial layer 171 can also be formed using deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other mature semiconductor processes. For example, if the material of the first sacrificial layer 171 is silicon dioxide, the first sacrificial layer 171 can be formed by PECVD. Thus, because the first sacrificial layer 171 is an inorganic material, it has structural stability and can precisely isolate the depth and shape of the groove 110 or the air gap 11. Simultaneously, by selecting an inorganic material with a high etch selectivity, the removal of the first sacrificial layer 171 can avoid affecting other structures of the semiconductor device 10.
[0082] In some embodiments, dielectric layer 13 may include multiple sub-dielectric layers. For example, please refer to... Figure 7 The dielectric layer 13 may include a second dielectric layer 132 and a third dielectric layer 133. Therefore, forming the first sacrificial layer 171 on the dielectric layer 13 may involve first forming multiple sub-dielectric layers sequentially, and then forming the first sacrificial layer 171 on the uppermost sub-dielectric layer. For example, when the dielectric layer 13 includes a second dielectric layer 132 and a third dielectric layer 133, the third dielectric layer 133 may be formed on the surface of the second dielectric layer 132, and the first sacrificial layer 171 may be formed on the surface of the third dielectric layer 133. The methods for forming the second dielectric layer 132 and the first sacrificial layer 171 can be one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition. Since the third dielectric layer 133 is formed on the surface of the second dielectric layer 132, by selecting an etching process with a high etch selectivity, the etching process can precisely stop at the surface of the third dielectric layer 133 when removing the first sacrificial layer 171, avoiding excessive etching that could damage the second dielectric layer 132. This also prevents etching of the second dielectric layer 132 in subsequent processes. Understandably, the surface of the third dielectric layer 133 may also be planarized before the first dielectric layer 13 is formed.
[0083] S200: A metal interconnect layer is prepared within the dielectric layer and the first sacrificial layer, the metal interconnect layer being flush with the first sacrificial layer, and the metal interconnect layer including a plurality of interconnect lines spaced apart along a first direction.
[0084] Please see Figure 8 The metal interconnect layer 12 can be fabricated within the dielectric layer 13 and the first sacrificial layer 171 using a damascus process. For example, a mask can be formed using photolithography. First, a mask layer 172 and photoresist 173 are sequentially formed on the surface of the first sacrificial layer 171. Then, the photoresist 173 is patterned by exposure and development to form the desired pattern. The pattern is then transferred to the mask layer 172 to form a mask. Subsequently, the pattern on the mask can be transferred to the dielectric layer 13 using chemical or physical methods, forming trenches on the dielectric layer 13, thereby forming the preliminary structure of the metal interconnect layer 12. Exemplarily, the shapes of multiple interconnect lines 121 can be arranged at intervals along a first direction X, which is parallel to the surface of the dielectric layer 13, using photolithography.
[0085] After trenches are formed in the dielectric layer 13, metallic materials can be formed in the trenches to form interconnects 121. For example, the metallic materials can be copper, aluminum, titanium, tungsten, cobalt, molybdenum, ruthenium, or alloys containing at least one of these metals. The metallic materials can be formed using electroplating or deposition processes, with chemical vapor deposition being a suitable deposition process. Finally, removing excess metallic materials forms the metal interconnect layer 12. For example, in... Figure 8In the metal interconnect layer 12, the interconnect line 121 includes a first interconnect line 1211 and a second interconnect line 1212, which are arranged at intervals along a first direction X.
[0086] Excess metal material can be removed using a planarization process such as chemical mechanical polishing, and the removed excess metal material can be the metal material outside the trench. Understandably, after removing the excess metal material through the planarization process, the formed metal interconnect layer 12 can be flush with the first sacrificial layer 171. This ensures that the metal interconnect layer 12 has a consistent thickness, providing a prerequisite for the subsequent steps of forming isolation trenches of consistent depth.
[0087] Understandably, when the dielectric layer 13 includes a second dielectric layer 132 and a third dielectric layer 133, fabricating a metal interconnect layer within the dielectric layer 13 and the first sacrificial layer 171 may include fabricating a metal interconnect layer 12 within the second dielectric layer 132, the third dielectric layer 133, and the first sacrificial layer 171. Thus, by fabricating the metal interconnect layer 12 within the second dielectric layer 132 and the third dielectric layer 133, the surface flatness and buffering effect of the third dielectric layer 133 can be fully utilized, ensuring the perpendicularity of the sidewalls of the metal interconnect layer 12. This helps improve the controllability of air gap formation, reduce parasitic capacitance, and reduce signal transmission delay.
[0088] The fabrication of the metal interconnect layer 12 within the second dielectric layer 132, the third dielectric layer 133, and the first sacrificial layer 171 is similar to the fabrication of the metal interconnect layer 12 within the dielectric layer 13 and the first sacrificial layer 171, and will not be described in detail here.
[0089] S300: Remove the first sacrificial layer to form an isolation recess between adjacent interconnects.
[0090] Please see Figure 9 and combined Figure 8 Understandably, since the interconnects 121 can be spaced apart along the first direction X, the first sacrificial layer 171 separates adjacent interconnects 121 in the first direction X. Therefore, removing the first sacrificial layer 171 can form an isolation groove 110 between adjacent interconnects 121. Understandably, since the first sacrificial layer 171 and the dielectric layer 13 have a high etching selectivity, removing the first sacrificial layer 171 will not affect the dielectric layer 13, and the size of the formed isolation groove 110 can be precisely controlled, for example, the size of the isolation groove 110 in the thickness direction D can be precisely controlled. The first sacrificial layer 171 can be removed by wet etching or dry etching. For example, dry etching can be performed using a plasma etching process; or, for example, wet etching can be performed using a liquid including hydrogen fluoride.
[0091] In some implementations, please refer to Figure 15 and combined Figure 9 Before forming the isolation groove 110 between adjacent interconnects 121, the process may further include depositing a fourth dielectric layer 15 on the surface of the dielectric layer 13 and the surface of the metal interconnect layer 12. Understandably, when the dielectric layer 13 includes a second dielectric layer 132 and a third dielectric layer 133, the fourth dielectric layer 15 may be formed on the surfaces of the third dielectric layer 133 and the metal interconnect layer 12. Specifically, before forming the isolation groove 110 between adjacent interconnects 121, the process may further include depositing the fourth dielectric layer 15 on the surface of the third dielectric layer 133 and the surface of the metal interconnect layer 12.
[0092] The fourth dielectric layer 15 can cover the sidewalls and bottom of the isolation groove 110. Thus, the formed fourth dielectric layer 15 increases the mechanical stability of the interconnects 121, preventing adjacent interconnects 121 from collapsing and contacting each other, causing a short circuit. The material of the fourth dielectric layer 15 can be the same as or different from the material of the dielectric layer 13. Understandably, the fourth dielectric layer 15 can be formed using a deposition process, such as chemical vapor deposition or atomic layer deposition. In this way, the thickness of the fourth dielectric layer 15 can be controlled by controlling the deposition time, thereby facilitating the control of the shape of the air gap formed in subsequent process steps. Furthermore, during subsequent etching of the next metal layer, the fourth dielectric layer 15 can serve as an etching stop layer, protecting the previous dielectric layer from damage and reducing the risk of short circuits between interconnects 121. It can also serve as a fixing material for the entire structure, enhancing the mechanical stability of the structure downstream of the air gap.
[0093] For example, the fourth dielectric layer 15 may also cover the top of the interconnect 121. In this way, when other metal interconnect layers 12 are formed on the metal interconnect layer 12 including the interconnect 121, the fourth dielectric layer 15 can also serve as an etch stop layer, reducing the process of forming the etch stop layer and simplifying the process flow.
[0094] S400: Fill the isolation groove with a second sacrificial layer and make the second sacrificial layer flush with the metal interconnect layer.
[0095] Please see Figure 10 and Figure 11 and combined Figure 9 Understandably, the second sacrificial layer 174 can be formed using a suitable semiconductor process. Exemplarily, the second sacrificial layer 174 can be filled in the isolation recess 110 using processes such as deposition or spin coating. For example, the material of the second sacrificial layer 174 may include polyimide, in which case the isolation recess 110 can be filled by spin coating polyimide.
[0096] Exemplarily, the second sacrificial layer 174 may be formed outside the isolation recess 110. For example, when the material of the second sacrificial layer 174 is formed using a deposition process, the material of the second sacrificial layer 174 may be formed outside the isolation recess 110 after filling the isolation recess 110. Therefore, filling the isolation recess 110 with the second sacrificial layer 174 and making the second sacrificial layer 174 flush with the metal interconnect layer 12 may include: filling the isolation recess 110 with the second sacrificial layer 174 and planarizing the material of the second sacrificial layer 174 until the surface of the metal interconnect layer 12 is exposed. That is, the second sacrificial layer 174 can be made flush with the metal interconnect layer 12 by removing the second sacrificial layer 174 outside the isolation recess 110, such as... Figure 11 As shown.
[0097] Chemical mechanical polishing (CMP) can be used to flush the second sacrificial layer 174 with the metal interconnect layer 12. Understandably, the interface formed when removing excess second sacrificial layer 174 will affect the shape of the subsequently formed first dielectric layer 14. Understandably, the polishing pressure applied during CMP and the composition of the polishing slurry used will affect the shape of the second sacrificial layer 174 and the upper surface of the metal interconnect layer 12. Therefore, by controlling the CMP process to make the second sacrificial layer 174 flush with the metal interconnect layer 12, the consistent depth of the subsequently formed air gap can be ensured.
[0098] For example, filling the isolation recess 110 with a second sacrificial layer 174 and flush with the metal interconnect layer 12 may include: depositing the second sacrificial layer 174 within the isolation recess 110 until the deposition thickness of the second sacrificial layer 174 is consistent with the deposition thickness of the first sacrificial layer 171. That is, the thickness of the second sacrificial layer 174 can be controlled by the deposition time, thus simplifying the process. Alternatively, a white light interferometer can be used to measure the deposition thickness of the second sacrificial layer 174 to ensure consistency with the thickness of the first sacrificial layer 171.
[0099] Therefore, by depositing a second sacrificial layer 174 in the isolation groove 110, and by planarization or by directly monitoring the deposition thickness of the second sacrificial layer 174 to make the second sacrificial layer 174 flush with the metal interconnect layer 12, the air gap morphology defects (poor depth uniformity or irregular shape) caused by insufficient or excessive filling are avoided, the air gap structure is optimized, and the reliability of the device is significantly improved.
[0100] The second sacrificial layer 174 is thermally stable at a first temperature and decomposes at a second temperature to generate a gaseous substance. The gaseous substance generated after the second sacrificial layer 174 evaporates does not react with other materials in the semiconductor device. For example, the gaseous substance generated after the second sacrificial layer 174 evaporates does not react with the interconnect 121.
[0101] The second temperature can be lower than the maximum temperature required by the subsequent process. The second temperature can be a preset temperature, with a range of 200°C to 400°C. When the preset temperature range is between 200°C and 400°C, the second sacrificial layer 174 is volatile, and the structures of other dielectric layers or metal interconnect layers 12 are stable. This ensures that the structure of the semiconductor device is not affected while forming the air gap, thereby improving the stability of the semiconductor device. For example, the lowest temperature in the preset temperature range can be 200°C, 220°C, 240°C, 260°C, 280°C, 300°C, 320°C, 340°C, 360°C, or 380°C, and the highest temperature in the preset temperature range can be 220°C, 240°C, 260°C, 280°C, 300°C, 320°C, 340°C, 360°C, 380°C, or 400°C. For example, the preset temperature range is 280°C to 320°C or 340°C to 360°C.
[0102] For example, the second sacrificial layer 174 can be an organic material, and the second sacrificial layer 174 is volatile within a preset temperature range. The preset temperature range is as described above. Therefore, the volatility of the organic material can be utilized to avoid residual contamination, achieving precise control and efficient formation of the air gap morphology, thus improving process compatibility and device reliability. The second sacrificial layer 174 can be formed from a single material or a mixture of materials containing additives. For example, the material of the second sacrificial layer 174 can be one or more of polymethyl methacrylate, polycarbonate, polystyrene, and polyimide. The material of the second sacrificial layer 174 can also be one or more organic materials including C=O, CN, or CF bonds. Thus, the second sacrificial layer 174 can be controllably removed through thermal decomposition characteristics. Through its controllable thermal decomposition temperature, high process compatibility, and precise morphology control, efficient formation and performance optimization of the air gap structure are achieved, while simultaneously improving device reliability and manufacturing efficiency.
[0103] When the fourth dielectric layer 15 is formed, after filling the second sacrificial layer 174, the surface of the second sacrificial layer 174 can be flush with the surface of the fourth dielectric layer 15 at the top of the interconnect 121, such as... Figure 16 As shown.
[0104] S500: A first dielectric layer is formed on the surface of the metal interconnect layer and the second sacrificial layer, wherein the first dielectric layer allows the second sacrificial layer to pass through within a preset temperature range.
[0105] Please see Figure 12As mentioned earlier, the metal interconnect layer 12 is flush with the second sacrificial layer 174. Therefore, after the first dielectric layer 14 is formed on the surfaces of the metal interconnect layer 12 and the second sacrificial layer 174, the surface of the first dielectric layer 14 facing the metal interconnect layer 12 and the second sacrificial layer 174 is planar. The first dielectric layer 14 can be formed using semiconductor processes such as plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. The thickness of the first dielectric layer 14 can range from 5 nm to 15 nm. For example, the thickness of the first dielectric layer 14 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm. Thus, due to the moderate thickness of the first dielectric layer 14 (5 nm to 15 nm), within a preset temperature range (e.g., 200 °C to 400 °C), the vaporized second sacrificial layer 174 can quickly diffuse and dissipate through the pores of the first dielectric layer 14, ensuring that the gas gap formation process is efficient and residue-free.
[0106] Within the aforementioned preset temperature range, the first dielectric layer 14 allows gaseous substances to pass through. These gaseous substances may include those generated by the volatilization of the second sacrificial layer 174 within the preset temperature range. Understandably, the first dielectric layer 14 may include pores. Gaseous substances can volatilize through these pores; that is, the size of the pores may be larger than the size of the second sacrificial layer after it has vaporized into gaseous substances, ensuring that the gaseous substances are discharged, the resulting air gaps are clean, and preventing electrical performance degradation.
[0107] The pores can be generated by the thermal expansion of the first dielectric layer 14 within a preset temperature range. That is, at temperatures below the minimum of the preset temperature range, the first dielectric layer 14 may not contain pores or the pores may be very small. Once the temperature reaches the preset range, thermal expansion creates pores in the first dielectric layer 14, forming microchannels that penetrate the first dielectric layer 14. This avoids the pores in the first dielectric layer 14 from adversely affecting the formation of other structures on it.
[0108] For example, within the aforementioned preset temperature range, the porosity of the first dielectric layer 14 can range from 35% to 65%, such as 35%, 40%, 45%, 55%, 60%, and 65%. For example, the pore size can range from 0.5 nm to 2 nm, such as 0.5 nm, 0.8 nm, 1 nm, 1.5 nm, and 2 nm. Thus, within the preset temperature range, micropores can be formed in the first dielectric layer 14, through which the gaseous substances generated by the second sacrificial layer 174 within the preset temperature range can be diffused and eliminated. This avoids the micropores being too small, preventing the gaseous substances from being eliminated after the second sacrificial layer vaporizes; it also avoids the micropores being too large, affecting the mechanical strength of the first dielectric layer 14, achieving a balance between efficient discharge of the second sacrificial layer 174, clean and residue-free gas gaps, and the mechanical strength of the first dielectric layer.
[0109] The material of the first dielectric layer 14 can be at least one of commonly used semiconductor dielectric materials such as silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride. Thus, both the dielectric layer 13 and the first dielectric layer 14 can be made of materials such as silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride. Through their excellent dielectric properties, mechanical strength, thermal stability, and process compatibility, the signal transmission rate, reliability, and manufacturing yield of semiconductor devices are significantly improved.
[0110] Understandably, when a fourth dielectric layer 15 is formed, as previously described, the surface of the second sacrificial layer 174 can be flush with the surface of the fourth dielectric layer 15 at the top of the interconnect 121 of the metal interconnect layer 12, that is, the fourth dielectric layer 15 at the top of the interconnect 121 is not covered by the second sacrificial layer 174. Therefore, forming a first dielectric layer 14 on the surfaces of the metal interconnect layer 12 and the second sacrificial layer 174 can include forming a first dielectric layer 14 on the surfaces of the fourth dielectric layer 15 and the second sacrificial layer 174. That is, the first dielectric layer 14 can cover the upper surface of the fourth dielectric layer 15 and the second sacrificial layer 174 that is flush with it. Therefore, the surface of the first dielectric layer 14 facing the fourth dielectric layer 15 and the second sacrificial layer 174 can also be planar. A portion of the fourth dielectric layer 15 can be located between the fourth dielectric layer 15 and the interconnect 121, such as... Figure 17 As shown.
[0111] S600: Adjust the ambient temperature of the medium layer after the above treatment to a preset temperature range so that the second sacrificial layer is vaporized into a gaseous substance and diffused out through the first medium layer, thereby forming an air gap in the isolation groove.
[0112] Please see Figure 13 and combined Figure 12Understandably, within a preset temperature range, the second sacrificial layer 174 can vaporize into a gaseous substance, and micropores can be formed in the first medium layer 14. Thus, the gaseous substance after the second sacrificial layer 174 is vaporized can diffuse out of the isolation groove 110 through the micropores in the first medium layer 14, forming an air gap 11 within the isolation groove 110. In other words, an air gap 11 is formed at the location of the second sacrificial layer 174.
[0113] For example, the material of the second sacrificial layer 174 may be polyimide, and the material of the first dielectric layer 14 may be silicon nitride, with a preset temperature range including 350°C. Thus, polyimide thermally decomposes into CO2 and H2O in a nitrogen atmosphere at 350°C, and silicon nitride generates nanoscale pores due to thermal expansion at this temperature. Therefore, the first dielectric layer 14 can allow gaseous substances CO2 and H2O to diffuse out, forming an air gap 11 at the location of the second sacrificial layer 174.
[0114] With the fourth dielectric layer 15 formed, the second sacrificial layer 174 vaporizes into a gaseous substance and diffuses out through the first dielectric layer 14. A portion of the surface of the fourth dielectric layer 15 in the isolation groove 110 and a portion of the surface of the first dielectric layer 14 facing the fourth dielectric layer 15 can form an air gap 11. Figure 18 As shown.
[0115] In some implementations, please refer to Figure 14 and combined Figure 13 and Figure 4 After the air gap 11 is formed, a dielectric layer 13 and / or a metal interconnect layer 12 may be formed on the side of the first dielectric layer 14 away from the air gap 11. This application will not elaborate further.
[0116] Therefore, please combine Figures 7 to 18In the method for forming an air gap 11 within a semiconductor device, a first sacrificial layer 171 of uniform thickness is pre-formed on a dielectric layer 13, defining the depth of the air gap using the first sacrificial layer 171. A metal interconnect layer 12 is then fabricated within the dielectric layer 13 and the first sacrificial layer 171, flush with the first sacrificial layer 171 to ensure uniform thickness of the metal interconnect layer 12, providing a prerequisite for forming an isolation groove 110 of uniform depth. After removing the first sacrificial layer 171, an isolation groove 110 of uniform depth is formed between adjacent interconnects 121. A second sacrificial layer 174 is filled into the isolation groove 110, flush with the metal interconnect layer 12, ensuring uniform depth of the formed air gap 11. A first dielectric layer 14 is formed on the surfaces of the second sacrificial layer 174 and the metal interconnect layer 12, and heated within a preset temperature range, causing the second sacrificial layer 174 to vaporize into a gaseous substance, which diffuses out through the pores of the first dielectric layer 14, thereby forming an air gap 11 of uniform depth at the location of the second sacrificial layer 174. Therefore, by adjusting the thickness of the first sacrificial layer 171, the depth of the air gap 11 can be flexibly adjusted. At the same time, by utilizing the volatile properties of the second sacrificial layer 174, it can be removed by heating after the air gap 11 structure is formed. This allows for the formation of an air gap 11 with good depth consistency within the semiconductor device, effectively reducing the parasitic capacitance between interconnects 121 and improving the signal transmission rate and overall device performance.
[0117] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for forming an air gap within a semiconductor device, characterized in that, include: A first sacrificial layer is formed on the dielectric layer; A metal interconnect layer is fabricated within the dielectric layer and the first sacrificial layer, the metal interconnect layer being flush with the first sacrificial layer, and the metal interconnect layer comprising a plurality of interconnect lines spaced apart along a first direction; Remove the first sacrificial layer to form an isolation recess between adjacent interconnects; A second sacrificial layer is filled into the isolation groove and made flush with the metal interconnect layer; A first dielectric layer is formed on the surfaces of the metal interconnect layer and the second sacrificial layer, wherein the first dielectric layer allows the second sacrificial layer to pass through within a preset temperature range; The ambient temperature of the medium layer after the above treatment is adjusted to the preset temperature range so that the second sacrificial layer is vaporized into a gaseous substance and diffused out through the first medium layer, thereby forming the air gap in the isolation groove.
2. The method according to claim 1, characterized in that, The first sacrificial layer is an inorganic material, and the second sacrificial layer is an organic material. The second sacrificial layer is volatile within the preset temperature range.
3. The method according to claim 1 or 2, characterized in that, The material of the second sacrificial layer is at least one of polymethyl methacrylate, polycarbonate, polystyrene, and polyimide.
4. The method according to any one of claims 1 to 3, characterized in that, The dielectric layer includes a second dielectric layer and a third dielectric layer, and the formation of a first sacrificial layer on the dielectric layer includes: The third dielectric layer is formed on the surface of the second dielectric layer; The first sacrificial layer is formed on the surface of the third dielectric layer.
5. The method according to any one of claims 1 to 4, characterized in that, The fabrication of a metal interconnect layer within the dielectric layer and the first sacrificial layer includes: A metal interconnect layer is fabricated within the second dielectric layer, the third dielectric layer, and the first sacrificial layer.
6. The method according to any one of claims 1 to 5, characterized in that, Before filling the isolation groove with the second sacrificial layer, the process includes: A fourth dielectric layer is deposited on the surface of the dielectric layer and the surface of the metal interconnect layer.
7. The method according to any one of claims 1 to 6, characterized in that, The step of filling the isolation groove with a second sacrificial layer, the second sacrificial layer being flush with the metal interconnect layer, includes: A second sacrificial layer is deposited within the isolation groove; The second sacrificial layer material is planarized until the surface of the metal interconnect layer is exposed; or, A second sacrificial layer is deposited within the isolation groove until the deposition thickness of the second sacrificial layer is the same as that of the first sacrificial layer.
8. The method according to any one of claims 1 to 7, characterized in that, The preset temperature range is 200℃ to 400℃.
9. A semiconductor device, characterized in that, include: Dielectric layer; A metal interconnect layer is formed within the dielectric layer, the metal interconnect layer including a plurality of interconnect lines spaced apart along a first direction, and an isolation groove is formed in the region between adjacent interconnect lines; A first dielectric layer is formed on one side of the metal interconnect layer in the thickness direction; An air gap is formed within the isolation groove, wherein the air gap is prepared by the method described in any one of claims 1 to 7.
10. The semiconductor device according to claim 9, characterized in that, The thickness of the first dielectric layer is 5 nm to 15 nm.
11. The semiconductor device according to claim 9 or 10, characterized in that, The first medium layer includes pores, the size of which is larger than the size of the second sacrificial layer after it has been vaporized into a gaseous substance.
12. The semiconductor device according to claim 11, characterized in that, The pore size ranges from 0.5 nm to 2 nm, and / or the porosity of the first dielectric layer ranges from 35% to 65%.
13. The semiconductor device according to any one of claims 9 to 12, characterized in that, The materials of the dielectric layer and the first dielectric layer are at least one of silicon dioxide, silicon carbonitride, aluminum oxide, silicon carbide, silicon oxynitride, and silicon nitride.
14. A chip, characterized in that, It includes a packaging layer and a semiconductor device as claimed in any one of claims 9 to 13, wherein the packaging layer at least partially covers the semiconductor device.
15. An electronic device, characterized in that, It includes a circuit board and a chip as described in claim 14, the chip being disposed on the circuit board.