Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, a metal gate, a contact plug and a second dielectric layer arranged above them. The key is that the top of the metal gate is provided with a recess, and the recess is filled with a second conductive material; and a gate via penetrates the second dielectric layer and is electrically connected with the second conductive material. The manufacturing method comprises the following steps: etching the upper surface of the metal gate to form a recess; backfilling the recess with the second conductive material; forming a second dielectric layer and a contact plug covering the device; then forming a gate via opening exposing the second conductive material and a first via opening exposing the contact plug by one-time patterning etching; and finally filling the openings by a selective deposition process. The second conductive material in the recess is used as an in-situ seed crystal, which realizes defect-free self-bottom-up filling of the gate via and forms a low-resistance homogeneous metal contact, significantly reduces the contact resistance, and improves the device performance and yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes, the feature size of devices continues to shrink, reaching advanced technology nodes. In these advanced process nodes, to further reduce device area and increase transistor density, the industry has widely adopted Contact Over Active Gate (COAG) technology. For example... Figure 1 As shown, COAG technology significantly reduces the layout area of ​​standard cells by moving the gate contact from the traditional gate extension region to directly above the gate, typically achieving a 10% to 20% reduction in device area, which is crucial for continuing Moore's Law.

[0003] In the COAG structure, the lower metal gate (MG) needs to be electrically connected to the upper metal interconnect via a gate via (VG or VCG). Figure 2 This is a transmission electron microscope (TEM) cross-sectional image showing advanced node semiconductor devices, from which you can see that the size of various contact structures, such as gate vias (W VCGs), has entered the order of hundreds or even hundreds of angstroms.

[0004] However, at such a miniaturized size, metal filling of the gate vias presents significant challenges. Traditional filling processes typically employ chemical vapor deposition (CVD) to deposit tungsten (W). For example... Figure 3 As illustrated in the diagram, for a gate via with a critical size (CD) target value of 150 angstroms, the inherent characteristics of the CVD-W process dictate that an adhesion layer or barrier layer (adhesive layer) composed of materials such as titanium / titanium nitride (Ti / TiN) must be pre-deposited on the inner wall and bottom of the via before deposition. The thickness of this adhesive layer on one side can reach approximately 20 angstroms, and the total space occupied on both sides will be approximately 40 angstroms, thereby drastically reducing the effective aperture that actually needs to be filled with tungsten to approximately 100 angstroms.

[0005] In such narrow and high aspect ratio pores, the filling capacity of CVD-W is significantly reduced. This is due to its non-ideal bottom-up growth pattern, which leads to filling defects. Figure 4As can be observed in the TEM image of the actual device, there are obvious seams or voids in the center of the vias filled by the traditional CVD-W process. These filling defects drastically increase the contact resistance of the gate vias, severely affecting the electrical performance of the device, such as increasing RC delay, and may even lead to device failure, thereby reducing product yield. Therefore, how to achieve low-resistance, defect-free metal filling for the gate vias of COAG structures is a technical challenge that urgently needs to be solved in the current semiconductor manufacturing field. Summary of the Invention

[0006] The technical problem this invention aims to solve is that in existing semiconductor manufacturing processes, especially at advanced nodes employing COAG (Contact Over-Gate) technology, traditional CVD-W (Chemical Vapor Deposition of Tungsten) processes face bottlenecks when filling extremely small gate vias (VGs) with metal. Because an adhesion layer or barrier layer (such as Ti / TiN) needs to be pre-deposited on the inner wall of the via, this material significantly reduces the already small effective filling aperture, leading to defects such as center seams or voids during subsequent tungsten filling. These defects, along with the high resistance of the barrier layer itself, result in excessively high contact resistance of the gate via, thus affecting the electrical performance of the device and product yield. Therefore, there is an urgent need in the art for a semiconductor device and its fabrication method that can achieve low-resistance, high-quality filling of miniaturized gate vias.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor device, comprising:

[0008] A semiconductor substrate having an active region thereon;

[0009] A metal gate is disposed on a semiconductor substrate and surrounded by a first dielectric layer. The top of the metal gate has a groove filled with a second conductive material.

[0010] The contact plug is electrically connected to the active area;

[0011] The second dielectric layer covers the metal gate, the first dielectric layer, and the contact plug;

[0012] A gate via penetrates the second dielectric layer and is electrically connected to the second conductive material within the groove; and

[0013] The first through-hole penetrates the second dielectric layer and is electrically connected to the contact plug.

[0014] Preferably, the active region includes a source region and a drain region.

[0015] Preferably, it further includes: a first adhesive layer or a first barrier layer disposed on the inner surface of the groove between the metal grid and the second conductive material.

[0016] Preferably, it further includes a second barrier layer formed between the first dielectric layer and the second dielectric layer.

[0017] Preferably, the bottom critical dimension of the gate via is smaller than the top critical dimension of the groove.

[0018] Preferably, at least one of the metal gate, the second conductive material, the contact plug, the gate via, and the first through hole includes tungsten.

[0019] Preferably, both the second conductive material and the gate via comprise tungsten.

[0020] This invention also provides a method for fabricating a semiconductor device, comprising the following steps:

[0021] Step 1: Provide a semiconductor substrate, on which metal gates isolated from each other by a first dielectric layer and an active region located on the side of the metal gate are formed, wherein the upper surface of the metal gate and the upper surface of the first dielectric layer are coplanar.

[0022] Step 2: Selectively etch back the upper surface of the metal gate to form a groove in the metal gate;

[0023] Step 3: Deposit a second conductive material in the groove and perform planarization treatment;

[0024] Step 4: Form a second dielectric layer on the semiconductor substrate, and form contact holes in the second dielectric layer to expose the active region. Then fill the contact holes with a third conductive material to form contact plugs.

[0025] Step 5: Above the second dielectric layer and the contact plug, a patterned etching process is used to simultaneously form a gate via opening and a first via opening. The gate via opening exposes the second conductive material within the groove, and the first via opening exposes the contact plug.

[0026] Step 6: Using a selective deposition process, a fourth conductive material is grown in the gate via opening and the first via opening to form the gate via and the first via, respectively.

[0027] Preferably, the active region includes a source region and a drain region.

[0028] Preferably, in step three, before depositing the second conductive material, the method further includes forming a first adhesion layer or a first barrier layer on the inner surface of the groove.

[0029] Preferably, in step three, a second conductive material is deposited by chemical vapor deposition.

[0030] Preferably, in step three, the planarization process is performed by chemical mechanical polishing.

[0031] Preferably, in step four, before forming the second dielectric layer, a second barrier layer is formed over the first dielectric layer and the metal gate filled with the second conductive material.

[0032] Preferably, in step five, the critical size of the projection of the gate via opening onto the upper surface of the second conductive material is smaller than the critical size of the upper surface of the second conductive material.

[0033] Preferably, in step six, the second conductive material in the groove serves as a seed layer for the growth of the fourth conductive material in the gate via opening.

[0034] Preferably, the fourth conductive material is grown in a bottom-up manner.

[0035] Preferably, the metal grid includes a first conductive material, and at least one of the first conductive material, the second conductive material, the third conductive material, and the fourth conductive material is tungsten.

[0036] Preferably, both the second and fourth conductive materials are tungsten.

[0037] As described above, the semiconductor device and its manufacturing method of the present invention have the following beneficial effects:

[0038] This invention provides an excellent conductive substrate for subsequent gate vias by pre-etching grooves on the top of the metal gate and backfilling them with a second conductive material. During the formation of the gate vias, a selective deposition process is employed, utilizing the second conductive material within the grooves as in-situ seed crystals to achieve bottom-up, defect-free filling of the gate vias. This filling method fundamentally avoids the center seam or void problems caused by insufficient filling capacity in traditional CVD-W processes. Furthermore, since the gate vias are grown directly on the second conductive material, they can form a homogeneous metal contact without a barrier layer (e.g., tungsten-tungsten contact), effectively increasing the conductive contact area and eliminating the negative impact of high-resistance barrier layers on contact resistance in traditional processes, thereby significantly reducing the resistance of the gate vias. In addition, the gate via opening falls within a second conductive material filling area larger than its size, improving the tolerance of process alignment. Ultimately, this invention effectively improves the electrical performance, stability, and manufacturing yield of devices. Attached Figure Description

[0039] Figure 1 This is a schematic diagram illustrating the use of COAG technology to reduce device layout in existing technologies; Figure 2 The image shown is a TEM cross-sectional view of a semiconductor device in the prior art. Figure 3 This is a schematic diagram of filling vias using the CVD-W process in the prior art; Figure 4 The image shown is a TEM cross-sectional view of a prior art device filled with perforations. Figure 5 The diagram shows a flow chart of a semiconductor device fabrication method provided in an embodiment of the present invention. Figure 6 The diagram shown is a schematic representation of the structure after etching and retracting the metal gate in one embodiment of the present invention. Figure 7 This is a schematic diagram illustrating the process of depositing a second conductive material in one embodiment of the present invention; Figure 8 The diagram shown is a schematic diagram of the structure of the second conductive material after planarization treatment in one embodiment of the present invention. Figure 9 The diagram shown is a schematic representation of the structure after the contact plug is formed in one embodiment of the present invention. Figure 10 The diagram shown is a schematic representation of the final structure of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figure 10 The present invention provides a semiconductor device, comprising: A semiconductor substrate 101 has an active region 102 thereon. The semiconductor substrate 101 can be a basic semiconductor material, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or it can be a III-V compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate. The active region 102 is formed in the semiconductor substrate 101 and is the region in which carriers are turned on and off in a transistor device.

[0042] A semiconductor substrate 101 has an active region 102 thereon. The semiconductor substrate 101 can be a basic semiconductor material, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or it can be a III-V compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate. The active region 102 is formed in the semiconductor substrate 101 and is the region in which carriers are turned on and off in a transistor device.

[0043] In some embodiments, the active region 102 includes a source region and a drain region. The source region and the drain region are the two electrodes of the transistor, and current control is achieved through the channel region between them.

[0044] The semiconductor device includes a metal gate 103 disposed on a semiconductor substrate 101 and surrounded by a first dielectric layer 104. The top of the metal gate 103 has a groove filled with a second conductive material 106. The metal gate 103 is the control electrode of the transistor, and its material can be selected from conductive materials with suitable work functions, such as tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or alloys thereof. The first dielectric layer 104 is used to achieve electrical isolation between the metal gates 103, and its material can be silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), or various low-k or ultra-low-k dielectric materials. The second conductive material 106 in the groove is a key structure of the present invention, providing an excellent contact basis for the subsequent formation of low-resistance gate vias.

[0045] In some embodiments, the semiconductor device further includes a first adhesion layer or a first barrier layer 105 disposed on the inner surface of the groove between the metal gate 103 and the second conductive material 106. The first adhesion layer or the first barrier layer 105 enhances the adhesion between the second conductive material 106 and the metal gate 103 and prevents atomic interdiffusion between them. Its material may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a stacked structure thereof.

[0046] The semiconductor device includes a contact plug 109 electrically connected to the active region 102. The contact plug 109 is used to extract electrical signals from the active region 102, and its material is typically a conductive metal, such as tungsten (W), cobalt (Co), or other suitable conductive materials.

[0047] The semiconductor device includes a second dielectric layer 108 covering the metal gate 103, the first dielectric layer 104, and the contact plug 109. The second dielectric layer 108 is an interlayer dielectric (ILD) in a middle-interconnect (MOL) process, used to isolate the underlying transistor structure from the upper metal interconnect. Its material is typically similar to that of the first dielectric layer and can be silicon oxide or various low-k materials.

[0048] In some embodiments, the semiconductor device further includes a second barrier layer 107 formed between the first dielectric layer 104 and the second dielectric layer 108. The second barrier layer 107 typically serves as an etch stop layer, enabling precise control of the etching depth during subsequent etching to form the gate vias and the openings of the first vias, thus protecting the underlying device structure. The material of the second barrier layer is typically chosen to have a high etch selectivity with respect to the second dielectric layer 108, such as silicon nitride (SiN) or silicon carbonitride (SiCN).

[0049] The semiconductor device also includes a gate via and a first through-hole, both of which are filled with conductive material 110. The gate via penetrates the second dielectric layer 108, and its bottom is electrically connected to the second conductive material 106 within the groove. The first through-hole penetrates the second dielectric layer 108, and its bottom is electrically connected to the contact plug 109.

[0050] In some embodiments, the bottom critical dimension of the gate via is smaller than the top critical dimension of the recess. This structural feature provides high process tolerance for device fabrication. Even with some misalignment in photolithography, it ensures that the gate via falls completely on the underlying second conductive material 106, forming a reliable electrical connection, which is helpful in improving the manufacturing yield of large-scale integrated circuits.

[0051] The semiconductor device also includes a third dielectric layer 111 disposed above the second dielectric layer 108 and surrounding the conductive material 110 filling the gate via and the first via. In some embodiments, the upper portion of the conductive material 110 may also extend to form an upper metal interconnect (e.g., M1 layer).

[0052] In some embodiments, at least one of the metal gate 103, the second conductive material 106, the contact plug 109, and the conductive material 110 constituting the gate via and the first through-hole includes tungsten. Tungsten is widely used in semiconductor interconnects due to its good conductivity, thermal stability, and mature chemical vapor deposition process.

[0053] In some embodiments, both the second conductive material 106 and the conductive material 110 constituting the gate via comprise tungsten. This structure is key to achieving low-resistance contact by forming a homogeneous tungsten-tungsten contact interface, avoiding the introduction of a high-resistance titanium nitride (TiN) barrier layer required in conventional processes at the contact interface. This barrier-free homogeneous metal contact structure can directly reduce contact resistance, thereby improving the electrical performance of the device, such as reducing RC delay and increasing switching speed.

[0054] Please see Figure 5 It illustrates a schematic flowchart of a semiconductor device fabrication method according to an embodiment of the present invention, including the following steps:

[0055] Step 1: Provide a semiconductor substrate 101. A metal gate 103, isolated from each other by a first dielectric layer 104, and an active region 102 located on the side of the metal gate 103 are formed on the semiconductor substrate 101. The upper surface of the metal gate 103 is coplanar with the upper surface of the first dielectric layer 104. This coplanar structure is typically formed by a chemical mechanical polishing (CMP) process, providing a flat surface for subsequent patterning steps. The material forming the metal gate 103 can be tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or alloys thereof. The material forming the first dielectric layer 104 can be silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), or various low-k or ultra-low-k materials.

[0056] In some embodiments, the active region 102 includes a source region and a drain region.

[0057] Step 2: Selectively etch back the upper surface of the metal gate 103 to form a groove in the metal gate 103. This step typically employs a dry etching process, such as reactive ion etching (RIE), where the etching gas has a high etching rate on the metal gate 103 material and a low etching rate on the surrounding first dielectric layer 104 material, thus achieving selective etching. The depth of the groove can be adjusted according to design requirements, for example, 50-200 angstroms.

[0058] Please see Figure 6 It shows a cross-sectional schematic diagram of the semiconductor device after performing step two.

[0059] Step 3: Deposit the second conductive material 106 within the groove and perform planarization. (See also...) Figure 7 This illustrates a schematic diagram of the material deposition process within a groove. Please refer to... Figure 8 It shows a cross-sectional schematic diagram of the second conductive material 106 after planarization treatment.

[0060] In some embodiments, step three, before depositing the second conductive material 106, further includes forming a first adhesion layer or a first barrier layer 105 on the inner surface of the groove. The first adhesion layer or the first barrier layer 105 can be formed by thin film deposition techniques such as physical vapor deposition (PVD) and atomic layer deposition (ALD), and its material can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a stacked structure thereof.

[0061] In some embodiments, in step three, a second conductive material 106 is deposited using a chemical vapor deposition (CVD) process. Besides CVD, other deposition methods such as ALD, PVD, or electroplating may also be used, depending on the selected material. The second conductive material 106 may be the same as or different from the material of the metal gate 103; for example, it may be tungsten (W), cobalt (Co), or other suitable conductors.

[0062] In some embodiments, in step three, planarization is performed using a chemical mechanical polishing (CMP) process.

[0063] Step 4: A second dielectric layer 108 is formed on the semiconductor substrate 101, and contact holes exposing the active region 102 are formed in the second dielectric layer 108. Then, a third conductive material is filled into the contact holes to form contact plugs 109. The third conductive material forming the contact plugs 109 is typically tungsten (W) or cobalt (Co). See also... Figure 9 It shows a cross-sectional schematic diagram after the contact plug 109 is formed.

[0064] In some embodiments, step four, before forming the second dielectric layer 108, further includes forming a second barrier layer 107 over the first dielectric layer 104 and the metal gate 103 filled with the second conductive material 106. The second barrier layer 107 can be deposited by means of CVD or similar methods, and its material is typically chosen to have a high etch selectivity with the second dielectric layer 108, such as silicon nitride (SiN) or silicon carbonitride (SiCN).

[0065] Step 5: Above the second dielectric layer 108 and the contact plug 109, a patterning etching process is used to simultaneously form the gate via opening and the first via opening. For example, the third dielectric layer 111 can be deposited first. Then, a second single damascene process is used to perform patterning etching in the third dielectric layer 111 to form trenches for the upper metal interconnect, and then fill them with conductive material (i.e., Figure 10 (110) and flatten it to complete as follows Figure 10 The final device structure is shown. The gate via opening exposes the second conductive material 106 within the groove, and the first via opening exposes the contact plug 109. This method of simultaneously forming openings for different connection targets through a single patterning and etching process is a common-platform process that simplifies the process flow and reduces manufacturing costs.

[0066] In some embodiments, in step five, the critical size of the projection of the gate via opening onto the upper surface of the second conductive material 106 is smaller than the critical size of the upper surface of the second conductive material 106.

[0067] Step 6: Using a selective deposition process, a fourth conductive material is grown in the gate via opening and the first via opening to form the gate via and the first via, respectively.

[0068] Selective deposition is one of the core steps of this invention, such as selective tungsten deposition. This process is characterized by the nucleation and growth of conductive materials (such as tungsten) only on specific conductive surfaces (such as the exposed second conductive material 106 and contact plug 109), without deposition on the surrounding dielectric layer surface. This bottom-up growth approach enables void-free and seamless filling of high aspect ratio vias, especially at advanced process nodes where critical dimensions shrink to 150 angstroms or even smaller. This method effectively solves the filling difficulties and seam problems caused by the space occupied by the "adhesive layer" in traditional CVD-W processes, fundamentally reducing the contact resistance of gate vias and improving device stability and performance. The fourth conductive material can be metals such as tungsten, cobalt, or ruthenium, which can be formed through selective deposition processes.

[0069] In some embodiments, in step six, the second conductive material 106 within the groove serves as a seed layer for the growth of the fourth conductive material within the gate via opening. Since the second conductive material 106 and the fourth conductive material can be made of the same metal (such as tungsten), the second conductive material 106 serves as an ideal seed crystal for in-situ formation, ensuring that the fourth conductive material can undergo epitaxial or grain growth efficiently and with high quality.

[0070] In some embodiments, the fourth conductive material is grown preferentially from the bottom.

[0071] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate having an active region thereon; A metal gate is disposed on the semiconductor substrate and surrounded by a first dielectric layer, and the top of the metal gate has a groove filled with a second conductive material; The contact plug is electrically connected to the active area; A second dielectric layer covers the metal gate, the first dielectric layer, and the contact plug; A gate via penetrates the second dielectric layer and is electrically connected to the second conductive material within the groove; as well as The first through-hole penetrates the second dielectric layer and is electrically connected to the contact plug.

2. The semiconductor device according to claim 1, characterized in that: The active region includes a source region and a drain region.

3. The semiconductor device according to claim 1, characterized in that: Also includes: On the inner surface of the groove, a first adhesion layer or a first barrier layer is disposed between the metal grid and the second conductive material.

4. The semiconductor device according to claim 1, characterized in that: Also includes: A second barrier layer is formed between the first dielectric layer and the second dielectric layer.

5. The semiconductor device according to claim 1, characterized in that: The bottom critical dimension of the gate via is smaller than the top critical dimension of the groove.

6. The semiconductor device according to claim 1, characterized in that: At least one of the metal gate, the second conductive material, the contact plug, the gate via, and the first through hole includes tungsten.

7. The semiconductor device according to claim 6, characterized in that: Both the second conductive material and the gate via comprise tungsten.

8. A method for manufacturing a semiconductor device, characterized in that, include: Step 1: Provide a semiconductor substrate, on which a metal gate isolated from each other by a first dielectric layer and an active region located on the side of the metal gate are formed, wherein the upper surface of the metal gate is coplanar with the upper surface of the first dielectric layer. Step 2: Selectively etch back the upper surface of the metal gate to form a groove in the metal gate; Step 3: Deposit a second conductive material in the groove and perform planarization treatment; Step 4: Form a second dielectric layer on the semiconductor substrate, and form a contact hole in the second dielectric layer to expose the active region, and then fill the contact hole with a third conductive material to form a contact plug; Step 5: Above the second dielectric layer and the contact plug, a gate via opening and a first via opening are simultaneously formed by a patterning etching process. The gate via opening exposes the second conductive material in the groove, and the first via opening exposes the contact plug. Step 6: Using a selective deposition process, a fourth conductive material is grown in the gate via opening and the first via opening to form the gate via and the first via, respectively.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that: The active region includes a source region and a drain region.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that: In step three, before depositing the second conductive material, the method further includes forming a first adhesion layer or a first barrier layer on the inner surface of the groove.

11. The method for manufacturing a semiconductor device according to claim 8, characterized in that: In step three, the second conductive material is deposited using a chemical vapor deposition process.

12. The method for manufacturing a semiconductor device according to claim 8, characterized in that: In step three, the planarization process is performed using a chemical mechanical polishing process.

13. The method for manufacturing a semiconductor device according to claim 8, characterized in that: In step four, before forming the second dielectric layer, the method further includes forming a second barrier layer over the first dielectric layer and the metal gate filled with the second conductive material.

14. The method for manufacturing a semiconductor device according to claim 8, characterized in that: In step five, the critical dimension of the projection of the gate via opening onto the upper surface of the second conductive material is smaller than the critical dimension of the upper surface of the second conductive material.

15. The method for manufacturing a semiconductor device according to claim 8, characterized in that: In step six, the second conductive material within the groove serves as a seed layer for the growth of the fourth conductive material within the gate via opening.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The fourth conductive material is grown with a bottom-first growth method.

17. The method for manufacturing a semiconductor device according to claim 8, characterized in that: The metal grid includes a first conductive material, and at least one of the first conductive material, the second conductive material, the third conductive material, and the fourth conductive material is tungsten.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that: Both the second conductive material and the fourth conductive material are tungsten.

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